Lattice 7:1 VDS Video Demo Kit User's Guide

Lattice 7:1 LVDS Video Demo Kit
User’s Guide
June 2007
Technical Note TN1134
Introduction
The Lattice 7:1 LVDS Video Demo Kit is a set of boards intended to bring RGB video data into the LatticeECP2™
FPGA where it can be processed and transmitted to an output display. It is intended to be used as a reference
design and to demonstrate the capabilities of the LatticeECP2 FPGA in video processing applications.
The complete kit consists of up to five boards. The heart of the kit is the LatticeECP2 Advanced Evaluation Board,
featuring a LatticeECP2-50 FPGA device. The kit is optionally available without this board.
The other four boards feature the required I/O interfaces to complete the demonstration. These are described in
more detail below.
About This Guide
This document includes descriptions of the design of the boards, the design of the IP for the LatticeECP2™ FPGA,
the items required to run the demonstration, and how to connect the boards and the cables for the demo.
Additional Resources
Additional resources related to the Lattice 7:1 LVDS Video Demo Kit, including updated documentation, HDL
source and bitstream programming files for the LatticeECP2 FPGA, a user’s guide for the LatticeECP2 Advanced
Evaluation Board, and other related materials can be downloaded from the Lattice web site at: www.latticesemi.com/boards. Navigate to the page for the Lattice 7:1 LVDS Video Demo Kit, and see the “documents and
downloads” link on the left side of the page.
7:1 Video Demonstration Setup and Design
Figure 1 is an overview of the connection between the boards, the required cables, and a block diagram of the
demo design implemented in LatticeECP2-50. The video signals are color-coded to indicate the different I/O standards including TMDS (pink), LVCMOS/LVTTL (orange), and LVDS (yellow).
Figure 1. Block Diagram of the Lattice 7:1 LVDS Video Demo Kit Setup
Board #3
Board #1 (or #4)
LatticeECP2 Advanced Evaluation Board
60-pin
connection
LVDS 7:1 Rx
Deserializer
R
G
B
Gain
Control
Gain
Control
Gain
Control
R
G
B
TMDS signals
LVCMOS/LVTTL signals
LVDS signals
MDR-26 Channel-Link Cable
RGB to YCbCr Converter
DVI Cable
Desktop PC
DVD Player
ATSC Tuner
DVD
MDR-26 Channel-Link Cable
Y
Cb
Cr
DVI Cable
Contrast / Brightness / Hue /
Saturation Adjustments
Y
Cb
Board #1
Board #2
DVI
B
R
G
B
LVDS 7:1 Tx
Serializer
V
H
D
M
V
H
D
M
26 -p in 3 M M D R
G
OSD
D S9 0C R 28 8 A M T D
YCbCr to RGB Converter
R
LCD Display
Cr
2 6-p in 3M M D R
DVI
V
H
D
M
O n -B o ard S w itc h s
V
H
D
M
V ide o
A d jus t m en ts
2 6 -pin 3 M M D R
(TI TFP401A )
2 6 -pin 3 M M D R
TMDS
Receiver
LatticeECP2-50 Device
D S 9 0 C R 2 87 M T D
V
H
D
M
TMDS
Driver
(TI TFP410)
V
H
D
M
60-pin
connection
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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In this setup, DVI-I video signals must first be generated by a PC or an equivalent source. On Video Demo board
#3, the TMDS signals of the DVI-I interface are first converted to LVCMOS/LVTTL using the TFP401A, then converted again to LVDS using the DS90CR287MTD. These LVDS signals are then fed to the LatticeECP2-50 through
the MDR Channel Link cable and Video Demo Board #4. Video Demo Board #4 is connected to the LatticeECP2
Advanced Evaluation Board with a VHDM connector.
The demo design is implemented in the LatticeECP2-50 FPGA. This design is described in further detail later in
this guide, and is based on Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface. Source
code for this design is available in both the VHDL and Verilog languages. The LVDS video signal is de-serialized by
the LatticeECP2-50 for extracting the 8-bit R, 8-bit G, and 8-bit B pixel datum. Then the 8-bit R, G, B pixel datum
are adjusted by their own gain control block, and then the Contrast/Brightness/Hue/Saturation adjustment block,
before adding the OSD (On-Screen-Display). After the OSD is added to the video stream, the final R, G, B datum
are serialized and transmitted via the LatticeECP2-50 LVDS I/Os.
The remainder of the setup is similar to the video input side but reversed. The LVDS signals are fed via a VHDM
connector to the Video Demo board #1, then to the Video Demo board #2 via the MDR cable. The LVDS signals are
then converted to LVCMOS/LVTTL using the DS90CR288A on the Video Demo board #2. Finally the LVCMOS/LVTTL video signals are converted to the DVI / TMDS signals using the TFP410 and sent to the LCD display.
Figure 2 shows a complete Video Demo system setup, with an input source (laptop) and monitor. In this example,
power is supplied to Video Demo Boards 2 and 3 from an external source (not shown).
Figure 2. Video Demo System Setup
Prepare for the Video Demo
Before running the demo, you need the following video source and video sink.
• Video source: a desktop or a laptop PC with a DVI output port.
• Video sink: a LCD display with a DVI input port and a DVI cable.
Note: The display must be an actual DVI, digital display. Some DVI sources also include an RGB analog component, which allow the use a simple VGA -> DVI converter to supply input to an analog VGA monitor. These converters simply adapt the physical plugs to supply the RGB component signals contained in the DVI cable to a
VGA style plug. However, this video demo kit does not re-transmit any analog component signals; the output is
purely digital. As such, a simple converter will not work.
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If your PC does not have a DVI output, you may purchase a VGA-to-DVI converter (such as the CP-261D) to convert your PC’s video signal from VGA to DVI. The PC screen resolution needs to be set to any of the following to run
this demo.
• 640x480, 75Hz
• 800x600, 60Hz or 75Hz
• 1024x768, 60Hz or 75Hz
• 1152x864, 75Hz
• 1280x1024, 60Hz
The Lattice 7:1 Video Demo Kit includes the following items:
Table 1. Lattice 7:1 Video Demo Kit Contents
Item
Description
Quantity
1
1
LatticeECP2 672fpBGA Advanced Evaluation board
1
2
5V wall-mount power adapter1
1
3
Video Demo board #1
1
4
Video Demo board #42
1
5
Video Demo board #2
1
6
Video Demo board #3
1
7
DVI cable
1
8
MDR-26 Channel-Link cable
2
9
Black banana plug cable
2
10
Red banana plug cable
2
1. The Lattice 7:1 Video Demo Kit is available with or without the LatticeECP2 Advanced
Evaluation Board and 5V wall-mount power adapter.
2. Some early versions of this kit may include a modified version of “Video Demo Board #1”
as a substitute for the “Video Demo Board #4”. In these cases, Video Demo Board #4 can
be differentiated by two small wires connected to the MDR I/O. See the diagram below for
an example. In this document, this board will be referenced only as “Video Demo Board
#4”, as the function of either version is the same.
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Lattice 7:1 LVDS Video Demo Kit
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Figure 3. Lattice 7:1 Video Demo Kit Contents
LCD
Compact Flash
VIN
3.3V
GND
Video Demo Board #3
sysCONFIG
LatticeECP2 Advanced Evaluation Board
Video Demo Board #2
Video
Demo 3
NS
NS
Video
Demo 2
ADJ
USB
Type A
PAC
TI
TI
USB
Type B
1.2V
LatticeECP2-50
672 fpBGA
RS-232
OSC
Socket
1.8V
x1
G-PHY
2.5V
x1
DDR2 DIMM 0
1
DDR2 DIMM 1
RJ-45
Ethernet
RJ-45
Red Banana Plug Cable
x1
Video Demo Board #1
Video Demo Board #4 or the reworked Video Demo Board #1
or
x1
5V Wall-Mount Power Adapter
x1
DVI Cable
x1
x2
MDR-26 Channel-Link Cable
Black Banana Plug Cable
x2
x2
x1
After you verify you have the proper equipment for the video demo, make sure all the jumpers on the boards are set
correctly. The default jumper settings of Video Demo Boards #2 and #3 are shown below. The detailed functions of
these jumpers can be found in Appendix A and Appendix B at the end of this user’s guide.
• Video Demo Board #2 Default Jumper Settings:
– Install jumpers on pin1-pin2 of J3, J7, J8, J9, J11, J13 and J21.
– Install jumpers on pin2-pin3 of J10 and J12.
– Install jumpers on pin1-pin3 of J4 and J6.
– Install jumper on pin4-pin6 of J5.
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• Video Demo Board #3 Default Jumper Settings:
– Install jumpers on pin1-pin2 of J4, J5, J10 and J11.
– Install jumpers on pin2-pin3 of J6, J7, J8 and J9.
– Install jumper on pin3-pin4 of J3.
Figure 4. Block Diagram and Default Jumper Settings of Video Demo Boards #2 and #3
Board #2
3M
Board #3
10226-1210VE
3M
10226-1210VE
J2
J19
Video Demo 2
J15
J16 J14
Video Demo 3
J4
J13
J14
J15
J3
NS
NS
LED
LED
J21
DVI Molex
74320-1004
J4
TI
TFP410
J20
J5
J3
DVI Molex
74320-1004
J12
J6
J7
J8
J9
J10
J11
J5
TI
J1
TFP401A
J7
J8
J9
J10
J11
J12
J13
J6
J17
LED
3.3V
J18
J17
GND
J18
3.3V
J16
LED
GND
J19
For the I/O bank voltage setting on the LatticeECP2 Advanced Evaluation Board, bank 2 and bank 3 must be to be
set to 2.5V. Bank 0, 1, 4, 7 should all be set to 3.3V. The following table shows the proper jumper settings for the
Lattice 7:1 Video Demo.
Table 2. Jumper Settings for the LatticeECP2 Advanced Board
sysIO Bank
Jumper
0
J14
1
J39
2
J40
3
J41
4
J28
7
J27
5
6
Jumper on Pins
1-3 -> VCC_3.3V
2-4 -> VCC_2.5V
3-5 -> VCC_1.8V
4-6 -> VCC_ADJ
2.5V
Pin-6
Pin-1
Pin-5
3.3V
Tied to 1.8V
(Cannot be changed)
NA
5
ADJ
Pin-2
1.8V
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Jumpers J34 and J55 are used for the JTAG chain connection setting. Please make sure they are at their default
settings (J34: short and J55: open), which makes the LatticeECP2-50 the only device in the JTAG chain.
The OSD of this demo is controlled by a LatticeMico8™ microprocessor that requires an external clock from the
on-board oscillator. If a full size oscillator is used, make sure the oscillator on Y2 is installed on pins 1, 7, 10 and 16,
as seen in Figure 5. If a half size oscillator is used, make sure the oscillator on Y2 is installed on pins 1, 4, 13 and
16. In addition, Jumper J18 must be shorted to connect the oscillator clock output to the LatticeECP2-50 device.
The locations of these jumpers are shown below.
Figure 5. Jumper Settings on the LatticeECP2 Advanced Evaluation Board
2.5V
J55:Open
J34:Short
J18:Short
OSC installed on
Y2 pin-1,7,10,16
3.3V
If you are using the optional CP-261D VGA-to-DVI converter to convert your PC’s video signal from VGA to DVI, set
both the input switches and the output switches to “RGB”.
Boards and Cables Connections
Once you have everything needed for the demo and all the board settings are correct, you may start connecting the
boards and cables, step by step. If this is your first time to run this demo, it’s highly recommended to follow the
steps below.
• Step 1: Install Board #1 and Board #4
Boards #1 and #4 convert the LVDS signals on the MDR-26 Channel Link cable to the VHDM connector, so the
LVDS signals can be transmitted to the LatticeECP2-50 672 fpBGA device.
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Board #4 is used for the LVDS input on the Rx side and should be installed onto J36 of the LatticeECP2
Advanced Evaluation Board.
Board #1 is used for the LVDS output on the Tx side and should be installed onto J35 of the LatticeECP2
Advanced Evaluation Board.
After installation of these two boards, the boards should be perpendicular to the LatticeECP2 Advanced Evaluation Board. Figure 6 shows the proper installation of Board #1 (Tx side on the left) and Board #4 (Rx side on the
right) installed on the LatticeECP2 Advanced Evaluation Board. (Note: in this figure, the Board #4 shown is the
earlier, modified version of Board #1).
Figure 6. Proper Installation of Video Demo Boards #1 and #4 to the Lattice ECP2 Advanced Evaluation
Board
• Step 2: Connect the MDR-26 Cables
The two MDR-26 Channel Link cables are used for connecting the Rx and the Tx LVDS signals. They are used
between the following boards:
– Rx: Between Video Demo board #3 and #4
– Tx: Between Video Demo board #2 and #1
Figure 7 shows the connections between these boards.
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Lattice 7:1 LVDS Video Demo Kit
User’s Guide
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Figure 7. Proper Connection of the MDR-26 Channel Link Cables
• Step 3: Connect the DVI Cables
This demo requires two DVI cables. The video demo kit contains only one DVI cable. Therefore, you must use the
original DVI cable that comes with the LCD display as well.
If you are using a VGA-to-DVI converter to supply the DVI input, please be sure to set the converter’s input and
output switches to “RGB”, then connect the converter’s power, the VGA and DVI cables.
Before you connect the two DVI cables to the Video Demo boards #2 and #3, set the screen resolution to any of
those listed in the “Prepare for the Video Demo” section earlier in this document and check if your LCD display
can display the image properly at this resolution. Note that the DVI interface includes pins to allow the video
source getting the EDID (Extended Display Identification Data) from the video sink. These pins are not implemented on Video Demo boards #2 and #3. Some video source will not send out the video stream if it is not getting a proper EDID from the video sink. To prevent this from happening, you should first set the screen resolution
and check if the video stream is transmitting properly to the LCD display before disconnecting the DVI cable, then
reconnecting the cable to the demo system.
The DVI port of your PC should be connected to the Video Demo board #3. Video Demo board #2 should be connected to the LCD display.
• Step 4: Connect the JTAG Download Cable
The JTAG download cable is used for downloading the demo bitstream from a PC to the LatticeECP2 FPGA
device. Connect it to the J46 on the LatticeECP2 Advanced Evaluation Board. The functions of the pins of J46
are shown on the board. Be sure the cable wires are connected to the right J46 pins. You should also make sure
there is a jumper installed on J34 and no jumper installed on J55, so that the LatticeECP2-50 is the only device
in the JTAG chain. For further information, see the LatticeECP2 Advanced Evaluation Board User Manual, available from the Lattice website at www.latticesemi.com/boards.
• Step 5: Connect the Power Cables
Video Demo boards #2 and #3 require 3.3V power which can be obtained from the LatticeECP2 Advanced Evaluation Board using the red and black banana plug cables.
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Lattice 7:1 LVDS Video Demo Kit
User’s Guide
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Figure 8. Power Cable Connections for Lattice 7:1 LVDS Video Demo Kit
After connecting the banana plug cables, you should connect the 5V wall-mount power adapter to the
LatticeECP2 Advanced Evaluation Board. After completion of this step, the video demo system should look like
Figure 8.
• Step 6: Download the Video Demo Bitstream and Run the Video Demo
The DIP switch SW5 on the LatticeECP2 Advanced Evaluation Board controls several functions of this demo
design. The functions of these controls and their default settings are listed in the flowing table. When the specific
controls are selected, the push-button SW4 needs to be toggled to activate the adjustment. Note that once the
Auto-Demo is enabled, the OSD will be moving its position and bounce back when it hits the edge of the display.
This is for demonstration purpose and cannot be turned off.
Table 3. Switch for Video Color Adjustments, Demo and OSD Controls
SW5 Pin
Number
ON (Pushed Down)
OFF (Pulled Up)
Pin-1
R-gain or Contrast deselected
R-gain or Contrast selected
Pin-2
G-gain or Brightness deselected
G-gain or Brightness selected
Pin-3
B-gain or Hue deselected
B-gain or Hue selected
Pin-4
Opacity or Saturation deselected
Opacity or Saturation selected
Pin-5
OSD enabled
OSD disabled
Pin-6
Auto-Demo enabled
Auto-Demo disabled
Pin-7
Select RGBO group
Select CBHS group
Pin-8
Decrease the selected controls when SW4 is toggled
Increase the selected controls when SW4 is toggled
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Lattice 7:1 LVDS Video Demo Kit
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Now you can apply power to the demo system by turning on the SW6 of the LatticeECP2 Advanced Evaluation
Board. Then, launch ispVM® to download the demo bitstream. For full details on how to download the bitstream to
the LatticeECP2 FPGA, please refer to the LatticeECP2 Advanced Evaluation Board User Guide.
The bitstream file for this demo, as well as other resources, can be downloaded from the Lattice web site at:
www.latticesemi.com/boards. Navigate to the page for the Lattice 7:1 Video Demo Kit, and see the “documents and
downloads” link at the left of the page.
Video Demo Design Modules
This video demo design uses the Rx and Tx modules of Lattice reference design RD1030, LatticeECP2/M 7:1
LVDS Video Interface. For more information on this reference design, see the Lattice web site. Search for
“RD1030”, or navigate to the web page for the Lattice 7:1 LVDS Video Demo Kit at www.latticesemi.com/boards.
Figure 9 is a representation of the top level VHDL file of this design. The gray color blocks shown below are implemented in other VHDL files. The light green color blocks are modules generated using the IPexpress tool included
with the Lattice ispLEVER design software.
Figure 9. Video Processing Design Example
RA_in
RB_in
RC_in
reset_sync
7:1 LVDS Receiver
(LVDS_7_to_1_RX)
RD_in
RCLK_in
7
7
rx_d
7
rx_c
7
rx_b
rx_a
Rx Signal Mapping
8
8
8
3
r_R
r_G
r_B
r_Vsync
r_Hsync
r_DE
RGB_adj
Gain
Ctrl
Gain
Ctrl
8
rgb_R
Gain
Ctrl
8
rgb_G
Delay
8
rgb_B
3
rgb_Vsync
rgb_Hsync
rgb_DE
CBHS_adj
CBHS Adjustment Outputs
RGBO Adjustment Outputs
(Contrast/Brightness/Hue/Saturation
Delay
Adjustments)
8
cbhs_R
8
cbhs_G
8
cbhs_B
3
cbhs_Vsync
cbhs_Hsync
cbhs_DE
OSD
(On-Screen-Display Controlled by Mico8 uP)
Mico8 uP
Delay
8
t_G
t_B
3
t_Vsync
t_Hsync
t_DE
Tx Signal Mapping
7
tx_d
7
tx_c
7
7
tx_b
tx_a
TCLK_out
TA_out
TB_out
CBHS Adjustment Inputs
8
t_R
RGBO Adjustment Inputs
8
Adjustment
Signals
Generation
Logic
7:1 LVDS Transmitter
(LVDS_7_to_1_TX)
TC_out
TD_out
From DIP
Switch
8
From
Pushbotton
Switch
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Lattice 7:1 LVDS Video Demo Kit
User’s Guide
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In addition to the Rx and Tx modules, this design also contains the modules for the RGB gain control, the Contrast/Brightness/Hue/Saturation controls, the OSD module and the LatticeMico8 microprocessor that automatically
demonstrates the adjustments. These modules are an example design. You may implement other video applications in the LatticeECP2-50 FPGA using the video demo kit.
The Gain Control modules are 9x9 (9-bit by 9-bit) multipliers implemented using the sysDSP™ blocks of the
LatticeECP2 FPGA. The 9-bit gain value defines a positive real number between 0 and 1.99609375 with 1 bit of
integer part and 8 bits of fractional part as shown in Figure 10.
Figure 10. 18-Bit Data Value
Integer Part (1 bit)
MSB
LSB
Fractional Part (8 bits)
Gain
8
7
6
5
4
3
2
1
MSB
0
LSB
Integer Part (9 bits)
R/G/B
8
7
6
5
4
3
2
1
MSB
LSB
Integer Part (10 bits)
Product
0
Fractional Part (8 bits)
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
The R, G, B in this design are colors with 8-bit color depth. Each color is represented by 8 binary bits. Before feeding them to the multiplier’s multiplicand port, they are expanded from 8 bits to 9 bits with the most significant bit set
to “0”. The R, G, B gains are real numbers between 0 and 1 and are feeding to the multiplier port. After reset, these
gains are set to their default values 1.0. The real number 1.0 is represented by the 9-bit binary “100000000”. The
maximum value of the gains are limited to 1.0. The product of the 9x9 multiplier is an 18-bit value with 10 integer
part bits and 8 fractional part bits. However, only 8 integer part bits (bit-15 down to bit-8) are passed to the OSD
module.
Figure 11 shows the block diagram of the 7:1 LVDS receiver module. This is the same receiver module as in the
Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface. There is an auto-alignment logic in the
receiver module that utilizes the deserialized data of RCLK_in to select the proper outputs of the four data pairs.
This ensures the four data outputs are aligned at the pixel boundary. This logic will be reset whenever the PLL lock
is lost. The DDR software primitives IDDRX2B with x2 gearing ratio are used for receiving the high speed 7:1 LVDS
video stream. The 4-bit output of the IDDRX2B modules will then be sent to the 4-to-7 deserializers. Refer to reference design RD1030 for more detailed information. This can be found on the Lattice web site at: www.latticesemi.com by searching for “RD1030”.
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Lattice 7:1 LVDS Video Demo Kit
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Figure 11. 7:1 Receiver Side Block Diagram
IO DDR Registers
(2x gearing)
Auto Alignment
Module
IDDRX2B*
7
RA_in
4
4:7
Deserializer
7
4
4:7
Deserializer
7
4
4:7
Deserializer
7
4
4:7
Deserializer
7
RA_out
7
7
IDDRX2B*
7
RB_in
RB_out
7
7
IDDRX2B*
7
RC_in
RC_out
7
7
IDDRX2B*
7
O utpu t S ele c t
7
RD_in
RD_out
7
RST
IDDRX2B*
RCLK_in
4
4:7
Deserializer
RCK_out
7
7
reset_sync
SCLK
ECLK
sysclockPLL
RESET
CLKOS
CLKI x3.5, phase-shifted
CLKI
CLKOK
(CLKI x3.5)/2, 0deg
phase
DPHASE
LOCK
reset_sync
generation
logic
reset_sync_out
4
The block diagram of the 7:1 LVDS transmitter is shown in Figure 12. Four 7-to-4 serializers are used for serializing
the parallel R, G, B, VSYNC, HSYNC and DE signals. There is another serializer used for generating the LVDS output clock. The “1100011” value is feeding to this serializer so that the generated LVDS clock has a clock/data relationship that complies to the Channel Link 7:1 LVDS specification. The 4-bit outputs of the serializers are sent to
the 2x gearing ODDRX2B modules for pumping out of the LVDS I/Os. For more information about the transmitter,
please refer to Lattice reference design RD1030, LatticeECP2/M 7:1 LVDS Video Interface.
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Lattice 7:1 LVDS Video Demo Kit
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Figure 12. Block Diagram of 7:1 LVDS Transmitter Module
IO DDR Registers
(2x gearing)
ODDRX2B*
TA_in
7
TA_out
7:4
Serializer
4
ODDRX2B*
TB_in
7
TB_out
7:4
Serializer
4
ODDRX2B*
TC_in
7
TC_out
7:4
Serializer
4
ODDRX2B*
TD_in
7
TD_out
7:4
Serializer
4
“1100011”
ODDRX2B*
TCLK_out
7:4
Serializer
4
RST
SCLK
sysCLOCK PLL
RST_Tx
RESET
ECLK
CLKOP
CLKI x3.5, 0deg
CLK_Tx
CLKI
CLKOK
(CLKI x3.5)/2, 0deg
LOCK
Troubleshooting
Camera Link video camera is not supported.
Please note this kit uses the Channel-Link MDR-26 standard, not Camera-Link. These two LVDS video standards
use the same MDR-26 connector, but have different pinouts and data packet standards, and are not compatible.
Please use a standard DVI source such as a laptop or desktop computer or a Channel Link source to the LVDS.
No video output when everything is connected.
There are a number of possible causes, some of the most common include:
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Lattice 7:1 LVDS Video Demo Kit
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1. Boards #1 and #4 are not installed properly. After these boards are installed on the LatticeECP2 Advanced
Evaluation Board, the metal pieces of the VHDM connectors of Boards #1 and #4 should be touching each
other.
2. If using a computer for the DVI source, it may need to identify the monitor for initialization. Refer to the
Boards and Cable Connections section of this document, Step #3.
3. Check switches and jumpers:
Make sure that DIP switch SW1, switches 1 and 2 on the LatticeECP2 Advanced Evaluation Board, are in
the up position to correctly set the power supply options.
There are a number of other jumper and switch settings which may affect the operation of the demo. Be
sure to check the jumpers and switches on all the video demo boards, as well as the LatticeECP2
Advanced Evaluation Board.
4. The red LEDs on Boards #2 and #3 are not turned on. These LEDs indicate the 3.3V powers on these
boards are properly supplied. All of the different power supplies on the LatticeECP2 Advanced Evaluation
Board are controlled by the Lattice Power Manager II POWR1220AT8. If SW1 Pin 1 is on (pushed down),
the POWR1220AT8 device will be reset and all powers including the 3.3V will be disabled.
5. The monitor being used is a VGA monitor with a DVI -> VGA adapter. The monitor must be a DVI, digital
monitor. There is no analog component output from the Video Demo. See the Preparing for the Video
Demo section of this document for more information.
6. Make sure your monitor source is set to the supported resolutions and refresh rates listed in the “Prepare
for the Video Demo” section earlier in this document.
Testing for Board #2 and Board #3.
If you suspect that something may be wrong with Board #2 or #3, you may wish to test them independently as part
of the troubleshooting. To do this, disconnect Board #2 from the LatticeECP2 Advanced Evaluation Board and connect its LVDS cable directly into the input of Board #3. This removes the FPGA from the circuit. The video path then
goes though the DVI - LVDS - DVI conversion and should be displayed. If it is not, refer to the Boards and Cable
Connections section of this document, step #3. Figure 13 shows this arrangement.
Figure 13. Setup to Test Boards #2 and #3
LCD Display
Video
Demo 2
Video
Demo 3
Desktop PC
Note: Power connections are not shown in Figure 13, but power must be applied.
14
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Ordering Information
Ordering Part
Number
Description
LatticeECP2 7:1 Video Development Kit (Includes LatticeECP2
Advanced Evaluation Board)
LFE2-50E-VID-EV
Lattice 7:1 Video Interface Kit
HW-VID-KIT
China RoHS EnvironmentFriendly Use Period (EFUP)
10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet:www.latticesemi.com
Revision History
Date
Version
Change Summary
December 2006
01.0
Initial release.
March 2007
01.1
Added Ordering Information section.
June 2007
01.2
Updated to match RD1030 version 01.2.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
15
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Appendix A. Jumpers of the Video Demo Board #2
Table 4. Functions of the Jumpers on Video Demo Board #2
Jumper
J3
Function
Description
This is an active low control for forcing the DS90CR288A into the
/POWERDOWN powerdown mode. The DS90CR288A outputs stay low under the
powerdown mode.
Default Setting
Pin1 and Pin2 (high)
J4
CTL3
Multifunctional CTL3 input of TFP410.
Pin1 and Pin3
J5
CTL2
Multifunctional CTL2 input of TFP410.
Pin4 and Pin6
J6
CTL1
Multifunctional CTL1 input of TFP410.
Pin1 and Pin3
J7
VREF
This is the input reference voltage used to select the swing range of
the TFP410 digital inputs. High-swing 3.3V input signal level is
selected by the default setting.
Pin1 and Pin2 (high)
J8
EDGE
Edge select or hot plug input of TFP410.
Pin1 and Pin2 (high)
J9
DKEN
Data de-skew enable control of TFP410.
Pin1 and Pin2 (high)
Pin2 and Pin3 (low)
J10
ISEL/RSTn
This is an active high I2C select signal of TFP410 used for enabling
the TFP410’s I2C interface. The I2C state machine can be reset by
bringing this signal low then back high. I2C is disable by the default
setting.
J11
BSEL/SCL
Input bus select or I2C clock input of TP410.
Pin1 and Pin2 (high)
J12
DSEL/SDA
DSEL or I2C bidirectional data line of TP410.
Pin2 and Pin3 (low)
J13
PDN
This is an active low power down control of TP410. During powerdown mode, only the digital I/O buffers and I2C interface remain
active.
Pin1 and Pin2 (high)
NS_VDD
The power of the DS90CR288A is supported through this jumper’s
default setting. This jumper is used for disconnecting the
DS90CR288A power and forcing its output to the high impedance
state. Note that the powerdown mode puts the DS90CR288A outputs into low state instead of high impedance state.
Pin1 and Pin2
J21
16
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Appendix B. Jumpers of the Video Demo Board #3
Table 5. Functions of the Jumpers on Video Demo Board #3
Jumper
Function
Description
Default Setting
This jumper selects which multifunctional pins of the TFP401A
(CTL3, CTL2, or CTL1) is connected to the DS90CR287’s TxIN7 Pin3 and Pin4
input. CTL2 is selected by default.
J3
TxIN7
J4
/POWERDOWN
This is an active low control for forcing the DS90CR287 into the
powerdown mode. The DS90CR287’s LVDS outputs stay in the Pin1 and Pin2 (high)
tri-state mode under powerdown mode.
J5
OCK_INV
TFP401A’s ODCK Polarity - Selects ODCK edge on which pixel
data (QE[23:0] and QO[23:0]) and control signals (HSYNC,
Pin1 and Pin2 (high)
VSYNC, DE, CTL1-3) are latched.
J6
DFO
TFP401A’s Output clock data format - Controls the output clock
Pin2 and Pin3 (low)
(ODCK) format for either TFT or DSTN panel support.
J7
PIXS
TFP401A’s Pixel select - Selects between one or two pixels per
Pin2 and Pin3 (low)
clock output modes.
J8
STAGN
J9
ST
J10
PDN
This is an active low power down control of TP401A. During powPin1 and Pin2 (high)
erdown mode, all output buffers are in the high impedance state.
J11
PDON
This is an active low output drive power down control of TP401A.
During output drive powerdown mode, all output drivers except Pin1 and Pin2 (high)
SCDT and CTL1 are driven to a high impedance state.
Staggered pixel select of TFP401A.
Pin2 and Pin3 (low)
Output strength select of TFP401A. The default setting set the
drive strength to low drive strength.
Pin2 and Pin3 (low)
17
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Appendix C. Schematics of the Video Demo Boards #1, #2, #3 and #4
Video Demo Board #1
A
Rev
5
of
1
Sheet
5
4
3
2
Size
C
Title
Document Number
Video Demo Board #1
2
Lattice Semiconductor Corporation
1
A
A
1
4
3
2
Date:
B
C
C
B
D
D
Figure 14. Video Demo Board #1 Schematic
18
19
A
B
C
D
5
5
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
MOLEX VHDM 74031-0001
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
J1
Video Demo #1 Board
Back Side View
4
4
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
L10
A9
B9
C9
D9
E9
F9
G9
H9
J9
K9
L9
A8
B8
C8
D8
E8
F8
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
A6
B6
C6
D6
E6
F6
G6
H6
J6
K6
L6
A5
B5
C5
D5
E5
F5
G5
H5
J5
K5
L5
A4
B4
C4
D4
E4
F4
G4
H4
J4
K4
L4
Back Side View
G8
H8
J8
K8
L8
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
L3
G2
H2
J2
K2
L2
A1
B1
C1
D1
E1
F1
3
TX_OUT3_P
TX_OUT3_N
TX_CLKOUT_P
TX_CLKOUT_N
TX_OUT2_P
TX_OUT2_N
TX_OUT1_P
TX_OUT1_N
TX_OUT0_P
TX_OUT0_N
A2
B2
C2
D2
E2
F2
3
G1
H1
J1
K1
L1
27
28
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
J2
3M_Tx_10226-1210VE
Mounting_R
Mounting_L
DDC_Gnd_1
TxOut0TxOut0Gnd
TxOut0+
Sense
USB/DDC_Gnd
TxOut1TxOut1Gnd
TxOut1+
DDC/SDA
TxOut2TxOut2Gnd
TxOut2+
USB+
USB_Shield
USBDDC/SCL
TxClkOutTxClkOutGnd
TxClkOut+
USB_+5VDC
DDC_+5VDC
TxOut3TxOut3Gnd
TxOut3+
DDC_Gnd_26
13
12
2
26
25
23
24
11
22
10
9
21
20
8
19
7
18
17
16
15
14
6
5
4
3
2
1
2
Date:
Size
C
Title
1
Sheet
2
VHDM / MDR conversion
Document Number
of
2
Lattice Semiconductor Corporation
1
A
Rev
A
B
C
D
Lattice Semiconductor
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Figure 12. Video Demo Board #1 Schematic (Cont).
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Video Demo Board #2
A
Rev
5
of
1
Sheet
5
4
3
2
Size
C
Title
Document Number
Video Demo Board #2
2
Lattice Semiconductor Corporation
1
A
A
1
4
3
2
Date:
B
C
C
B
D
D
Figure 15. Video Demo Board #2 Schematic
20
A
B
C
D
27
28
26
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
3M_Rx_10226-1210VE
Mounting_R
Mounting_L
DDC_Gnd_26
RxIn0RxIn0Gnd
RxIn0+
Sense
USB/DDC_Gnd
RxIn1RxIn1Gnd
RxIn1+
DDC/SDA
RxIn2RxIn2Gnd
RxIn2+
USB+
USB_Shield
USBDDC/SCL
RxClkInRxClkInGnd
RxClkIn+
USB_+5VDC
DDC_+5VDC
RxIn3RxIn3Gnd
RxIn3+
DDC_Gnd_1
J14
HEADER 10X2
R23
100
0603
5
R24
100
0603
1
2
3
1
2
3
HEADER 3
J21
HEADER 3
J3
DVDD
R26
100
0603
J15
HEADER 10X2
R25
100
0603
NS_DVDD
DVDD
PWRDWN
R2
10K
0603
R27
100
0603
5
17
18
RX_CLKIN_N
RX_CLKIN_P
C23
0.1uF
0603
19
20
RX_IN3_N
RX_IN3_P
J16
HEADER 10X2
NS_PVCC
NS_LVCC
15
16
4
28
36
44
52
31
40
48
56
22
24
23
8
14
21
13
25
11
12
RX_IN2_N
RX_IN2_P
9
10
RX_IN1_N
RX_IN1_P
RX_IN0_N
RX_IN0_P
LVDS pairs
4
C24
0.01uF
0603
DS90CR288A
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
PLLGND
PLLGND
PLLVCC
LVDSGND
LVDSGND
LVDSGND
LVDSVCC
PWRDWN
RxCLKINN
RxCLKINP
RxIN3N
RxIN3P
RxIN2N
RxIN2P
RxIN1N
RxIN1P
RxIN0N
RxIN0P
U1
RXOUT0
RXOUT4
RXOUT8
RXOUT12
J2
RXOUT0
RXOUT1
RXOUT2
RXOUT3
RXOUT4
RXOUT5
RXOUT6
RXOUT7
RXOUT8
RXOUT9
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
C25
0.001uF
0603
RxCLKOUT
RxOUT27
RxOUT26
RxOUT25
RxOUT24
RxOUT23
RxOUT22
RxOUT21
RxOUT20
RxOUT19
RxOUT18
RxOUT17
RxOUT16
RxOUT15
RxOUT14
RxOUT13
RxOUT12
RxOUT11
RxOUT10
RxOUT9
RxOUT8
RxOUT7
RxOUT6
RxOUT5
RxOUT4
RxOUT3
RxOUT2
RxOUT1
RxOUT0
RXOUT16
RXOUT20
RXOUT24
SA1
26
7
6
5
3
2
1
55
54
53
51
50
49
47
46
45
43
42
41
39
38
37
35
34
33
32
30
29
27
6
4
2
J5
6
4
2
6
4
2
1
2
3
DVDD
HEADER 3
J7
HEADER 3X2
5
3
1
J6
HEADER 3X2
5
3
1
HEADER 3X2
5
3
1
(0.55V to 0.94V)
100
0603
100
0603
100
0603
J4
VR1
20K POT Murata PV37W101C01
PV37W
R16
20K
2
0603
R14
100K
0603
R6
DVDD
DVDD
R5
R3
DVDD
DVDD
RXCLKOUT
RXOUT27
RXOUT26
RXOUT25
RXOUT24
RXOUT23
RXOUT22
RXOUT21
RXOUT20
RXOUT19
RXOUT18
RXOUT17
RXOUT16
RXOUT15
RXOUT14
RXOUT13
RXOUT12
RXOUT11
RXOUT10
RXOUT9
RXOUT8
RXOUT7
RXOUT6
RXOUT5
RXOUT4
RXOUT3
RXOUT2
RXOUT1
RXOUT0
3
VREF
R7
10K
0603
SA1
RXOUT7
SA2
RXOUT7
SA3
RXOUT7
1
2
3
DVDD
HEADER 3
J8
PDN
BSEL
DSEL
ISEL
J9
DVDD
HEADER 3
1
2
3
10
15
14
6
7
8
13
9
35
3
5
4
2
DKEN
VREF
RXOUT15
RXOUT14
RXOUT18
57
56
50
51
52
53
54
55
58
59
60
61
62
63
36
37
38
39
40
41
42
43
44
45
46
47
EDGE
EDGE
R8
10K
0603
CTL3
CTL2
CTL1
B
G
R
4
3
DKEN
R9
10K
0603
TFP410
PDN
BSEL/SCL
DSEL/SDA
Clk Out
B/CTL3:2
G/CTL1
R/HVSync
2
DGND
DGND
DGND
DVDD
DVDD
DVDD
PGND
PVDD
TFADJ
TGND
TXCP
TXCN
TVDD
TX0P
TX0N
TGND
TX1P
TX1N
TVDD
TX2P
TX2N
TGND
S
1
VCC_3.3V
ISEL
R10
10K
0603
R22
S
1
2
BANANA JACK
J19
BANANA JACK
J18
HEADER 3
1
2
3
DVDD
DVDD
32
11
49
34
16
48
64
1
12
33
17
18
19
20
22
21
23
25
24
26
28
27
29
31
30
+
1
2
3
DVDD
C21
10uF
1206
VCC_3.3V
D2
LED_Red
R18
470
0603
+
HEADER 3
J11
4.7K
0603
MSEN/PO1
N/C
RESERVED (Tie to GND)
J10
CTL3/A3/DK3
CTL2/A2/DK2
CTL1/A1/DK1
ISEL/RSTN
DKEN
EDGE/HTPLG
VREF
VSYNC
HSYNC
DE
IDCKP
IDCKN
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
U2
J17
MOLEX VHDM 74057-1002
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RXOUT1
RXOUT5
RXOUT9
RXOUT13
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
RXOUT10
RXOUT11
RXOUT12
RXOUT13
RXOUT14
RXOUT15
RXOUT16
RXOUT17
RXOUT18
RXOUT19
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
1
3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RXOUT17
RXOUT21
RXOUT25
SA2
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
RXOUT20
RXOUT21
RXOUT22
RXOUT23
RXOUT24
RXOUT25
RXOUT26
RXOUT27
RXCLKOUT
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
RXCLKOUT
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
BSEL
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DSEL
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
RXOUT2
RXOUT6
RXOUT10
RXOUT14
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
RXOUT18
RXOUT22
RXOUT26
SA3
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
RXOUT19
RXOUT23
RXOUT27
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
RXOUT3
RXOUT7
RXOUT11
RXOUT15
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
21
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DVDD
R4
DVDD
TI_PVDD
510, 1%
0603
TI_TVDD
470
0603
0
0603
R20
C22
0.1uF
0603
C17
22uF
1206
C13
22uF
1206
C9
22uF
1206
C5
22uF
1206
C1
22uF
1206
DSEL
R12
10K
0603
Source
Drain
Source
Q1
BSS138LT1
Drain
1
2
3
DVDD
HEADER 3
J13
C18
0.1uF
0603
C14
0.1uF
0603
C10
0.1uF
0603
C6
0.1uF
0603
C2
0.1uF
0603
D1
LED_Green
C19
0.01uF
0603
C15
0.01uF
0603
C11
0.01uF
0603
C7
0.01uF
0603
C3
0.01uF
0603
PDN
R13
10K
0603
C5
C6
C4
C1
C2
C3
23
24
22
20
21
19
17
18
16
14
15
12
13
11
9
10
8
6
7
4
5
3
1
2
J20
DVI_I
C20
0.001uF
0603
NS_PVCC
C16
0.001uF
0603
NS_LVCC
C12
0.001uF
0603
TI_PVDD
C8
0.001uF
0603
DVDD
C4
0.001uF
0603
TI_TVDD
Analog_Ground_1
Analog_Ground_2
Analog_Horizontal_Sync
Analog_Red
Analog_Green
Analog_Blue
TMDS_Clock+
TMDS_Clock-
TMDS_Clock_Shield
TMDS_Data5TMDS_Data5+
TMDS_Data0/5_Shield
TMDS_Data0TMDS_Data0+
Hot_Plug_Detect
+5V_Power
GND(for +5V)
TMDS_Data3TMDS_Data3+
TMDS_Data1/3_Shield
TMDS_Data1TMDS_Data1+
Analog_Vertical_Sync
DDC_Clock
DDC_Data
TMDS_Data4TMDS_Data4+
TMDS_Data2/4_Shield
TMDS_Data2TMDS_Data2+
DVI-Integrated
1
Sheet
2
Channel Link to DVI
Document Number
of
2
Lattice Semiconductor Corporation
Date:
Size
C
Title
0
0603
0
0603
R19
0
0603
0
0603
R21
1
2
3
DVDD
HEADER 3
J12
SOT-23
Gate
Gate
R17
R15
BSEL
R11
10K
0603
MSEN
LED will be OFF when
a powered receiver is
attached to DVI.
(MSEN low)
R1
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TI_TVDD
TMDS_DATA2_P
TMDS_DATA2_N
TMDS pairs
1
A
Rev
A
B
C
D
Lattice Semiconductor
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Figure 13. Video Demo Board #2 Schematic (Cont.)
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Video Demo Board #3
A
Rev
5
of
1
Sheet
5
4
3
2
Size
C
Title
Document Number
Video Demo Board #3
2
Lattice Semiconductor Corporation
1
A
A
1
4
3
2
Date:
B
C
C
B
D
D
Figure 16. Video Demo Board #3 Schematic
22
A
B
C
D
1
2
3
DVDD
HEADER 3
J5
DVI_I
J6
DVDD
R4
10K
0603
J7
DVDD
C5
C6
C4
C1
C2
C3
23
24
22
20
21
HEADER 3
1
2
3
DFO
J14
HEADER 10X2
HEADER 3
1
2
3
PIXS
R5
10K
0603
PDN
PDON
17
18
19
OCK_INV
DFO
PIXS
STAGN
ST
5
1
2
3
R6
10K
0603
STAGN
J15
HEADER 10X2
HEADER 3
J8
DVDD
TI_PVDD
TI_OVDD
DVDD
DVDD
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
98
97
19
28
45
58
76
18
29
43
57
78
5
39
68
6
38
67
2
9
100
1
4
7
3
99
96
95
93
94
92
90
91
87
88
89
85
86
82
83
84
TI_AVDD
TMDS_DATA1_P
TMDS_DATA1_N
80
81
79
TMDS_DATA2_P
TMDS_DATA2_N
TMDS pairs
16
14
15
12
13
11
9
10
8
6
7
4
5
3
1
2
J13
HEADER 10X2
OCK_INV
R3
10K
0603
Analog_Ground_1
Analog_Ground_2
Analog_Horizontal_Sync
Analog_Red
Analog_Green
Analog_Blue
TMDS_Clock+
TMDS_Clock-
TMDS_Clock_Shield
TMDS_Data5TMDS_Data5+
TMDS_Data0/5_Shield
TMDS_Data0TMDS_Data0+
Hot_Plug_Detect
+5V_Power
GND(for +5V)
TMDS_Data3TMDS_Data3+
TMDS_Data1/3_Shield
TMDS_Data1TMDS_Data1+
Analog_Vertical_Sync
DDC_Clock
DDC_Data
TMDS_Data4TMDS_Data4+
TMDS_Data2/4_Shield
TMDS_Data2TMDS_Data2+
DVI-Integrated
5
Clk-in
B-in
G-in
R-in
1
2
3
HEADER 3
J9
DVDD
TFP401A
PGND
PVDD
OGND
OGND
OGND
OGND
OGND
OVDD
OVDD
OVDD
OVDD
OVDD
DGND
DGND
DGND
DVDD
DVDD
DVDD
PDN
PDON
OCK_INV
DFO
PIXS
STAGN
ST
ST
R7
10K
0603
RSVD (Tie high)
EXT_RES
AVDD
RxCP
RxCN
AGND
Rx0P
Rx0N
AGND
AVDD
AGND
Rx1P
Rx1N
AVDD
AGND
AVDD
Rx2P
Rx2N
AGND
U1
4
TXIN0
TXIN4
TXIN8
TXIN12
J1
TXIN0
TXIN1
TXIN2
TXIN3
TXIN4
TXIN5
TXIN6
TXIN7
TXIN8
TXIN9
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
TXIN10
TXIN11
TXIN12
TXIN13
TXIN14
TXIN15
TXIN16
TXIN17
TXIN18
TXIN19
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
TXIN20
TXIN21
TXIN22
TXIN23
TXIN24
TXIN25
TXIN26
TXIN27
TXCLKIN
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
TXIN16
TXIN20
TXIN24
R-even
R-odd
G-even
1
2
3
HEADER 3
J10
DVDD
SCDT
VSYNC
HSYNC
DE
CTL3
CTL2
CTL1
ODCK
QO7
QO6
QO5
QO4
QO3
QO2
QO1
QO0
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
QE15
QE14
QE13
QE12
QE11
QE10
QE9
QE8
QO23
QO22
QO21
QO20
QO19
QO18
QO17
QO16
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
QE7
QE6
QE5
QE4
QE3
QE2
QE1
QE0
G-odd
B-even
B-odd
TXIN1
TXIN5
TXIN9
TXIN13
R8
10K
0603
PDN
TXIN15
TXIN14
47
48
8
TXIN18
B
G
46
42
41
40
44
56
55
54
53
52
51
50
49
17
16
15
14
13
12
11
10
66
65
64
63
62
61
60
59
27
26
25
24
23
22
21
20
77
75
74
73
72
71
70
69
37
36
35
34
33
32
31
30
R
1
2
3
HEADER 3
J11
DVDD
PDON
R9
10K
0603
6
4
2
HEADER 2
1
2
HEADER 3X2
J3
J12
5
3
1
3
SCDT
R2
1
2
3
470
0603
HEADER 3
J4
SOT-23
Gate
Gate
LED will be ON
when link is
active.
(SCDT high)
DVDD
TXIN7
DVDD
Source
Drain
Source
Q1
BSS138LT1
Drain
D1
LED_Green
PWRDWN
R1
10K
0603
31
TXCLKIN
32
50
30
28
27
25
24
23
22
20
19
18
16
15
14
12
11
10
8
7
6
4
3
2
56
55
54
52
51
TXIN27
TXIN26
TXIN25
TXIN24
TXIN23
TXIN22
TXIN21
TXIN20
TXIN19
TXIN18
TXIN17
TXIN16
TXIN15
TXIN14
TXIN13
TXIN12
TXIN11
TXIN10
TXIN9
TXIN8
TXIN7
TXIN6
TXIN5
TXIN4
TXIN3
TXIN2
TXIN1
TXIN0
4
3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
DS90CR287
PWRDWN
TxCLKIN
TxIN27
TxIN26
TxIN25
TxIN24
TxIN23
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
U2
J16
MOLEX VHDM 74057-1002
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
TXIN17
TXIN21
TXIN25
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
TXCLKIN
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
TXIN2
TXIN6
TXIN10
TXIN14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
TXIN18
TXIN22
TXIN26
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
TXIN19
TXIN23
TXIN27
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
TXIN3
TXIN7
TXIN11
TXIN15
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
23
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
5
13
21
29
53
1
9
17
26
S
1
S
1
2
BANANA JACK
J18
BANANA JACK
J17
34
33
35
+
C25
10uF
1206
VCC_3.3V
D2
LED_Red
R13
470
0603
C29
0.1uF
0603
DVDD
+
NS_PVCC
NS_LVCC
36
43
49
TX_CLKOUT_N
TX_CLKOUT_P
TX_OUT3_N
TX_OUT3_P
44
TX_OUT2_N
TX_OUT2_P
38
37
40
39
TX_OUT1_N
TX_OUT1_P
42
41
0
0603
R15
C26
0.1uF
0603
C22
0.1uF
0603
C18
0.1uF
0603
C14
0.1uF
0603
C10
0.1uF
0603
C6
0.1uF
0603
C2
0.1uF
0603
1
J19
C23
0.01uF
0603
C19
0.01uF
0603
C15
0.01uF
0603
C11
0.01uF
0603
C7
0.01uF
0603
C24
0.001uF
0603
NS_PVCC
C20
0.001uF
0603
NS_LVCC
C16
0.001uF
0603
TI_PVDD
C12
0.001uF
0603
TI_OVDD
C8
0.001uF
0603
DVDD
C4
0.001uF
0603
TI_AVDD
3M_Tx_10226-1210VE
Mounting_R
Mounting_L
DDC_Gnd_1
TxOut0TxOut0Gnd
TxOut0+
Sense
USB/DDC_Gnd
TxOut1TxOut1Gnd
TxOut1+
DDC/SDA
TxOut2TxOut2Gnd
TxOut2+
USB+
USB_Shield
USBDDC/SCL
TxClkOutTxClkOutGnd
TxClkOut+
USB_+5VDC
DDC_+5VDC
TxOut3TxOut3Gnd
TxOut3+
DDC_Gnd_26
C3
0.01uF
0603
27
28
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
1
Sheet
2
DVI to Channel Link
Document Number
of
2
Lattice Semiconductor Corporation
C21
22uF
1206
C17
22uF
1206
C13
22uF
1206
C9
22uF
1206
C5
22uF
1206
C1
22uF
1206
C27
0.001uF
0603
Date:
Size
C
Title
0
0603
0
0603
R14
R16
0
0603
0
0603
R11
R12
0
0603
R10
C28
0.01uF
0603
LVDS pairs
TX_OUT0_N
TX_OUT0_P
46
45
48
47
VCC_3.3V
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
PLLGND
PLLGND
PLLVCC
LVDSGND
LVDSGND
LVDSGND
LVDSVCC
TxCLKOUTN
TxCLKOUTP
TxOUT3N
TxOUT3P
TxOUT2N
TxOUT2P
TxOUT1N
TxOUT1P
TxOUT0N
TxOUT0P
2
A
Rev
A
B
C
D
Lattice Semiconductor
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Figure 14. Video Demo Board #3 Schematic (Cont.)
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Video Demo Board #4
Rev
A1
of
1
Sheet
Video Demo Board #4
2
Lattice Semiconductor Corporation
Document Number
5
5
4
4
3
3
2
2
Size
C
Title
1
1
A
A
Date:
B
C
C
B
D
D
Figure 17. Video Demo Board #4 Schematic
24
25
A
B
C
D
5
GND_L1
GND_L2
GND_L3
GND_L4
GND_L5
GND_L6
GND_L7
GND_L8
GND_L9
GND_L10
GND_K1
GND_K2
GND_K3
GND_K4
GND_K5
GND_K6
GND_K7
GND_K8
GND_K9
GND_K10
GND_J1
GND_J2
GND_J3
GND_J4
GND_J5
GND_J6
GND_J7
GND_J8
GND_J9
GND_J10
GND_H1
GND_H2
GND_H3
GND_H4
GND_H5
GND_H6
GND_H7
GND_H8
GND_H9
GND_H10
GND_G1
GND_G2
GND_G3
GND_G4
GND_G5
GND_G6
GND_G7
GND_G8
GND_G9
GND_G10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
J1
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
MOLEX VHDM 74031-0001
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
Back Side View
5
4
4
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
L10
F9
A9
B9
C9
D9
E9
G9
H9
J9
K9
L9
F8
A8
B8
C8
D8
E8
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
A6
B6
C6
D6
E6
F6
G6
H6
J6
K6
L6
A5
B5
C5
D5
E5
F5
G5
H5
J5
K5
L5
A4
B4
C4
D4
E4
F4
G4
H4
J4
K4
L4
Back Side View
G8
H8
J8
K8
L8
F3
A3
B3
C3
D3
E3
G3
H3
J3
K3
L3
A2
B2
C2
D2
E2
F2
3
G2
H2
J2
K2
L2
3
F1
A1
B1
C1
D1
E1
RXA_IN0_N
RXA_IN0_P
RXA_IN1_N
RXA_IN1_P
RXA_IN2_N
RXA_IN4_N
RXA_IN2_P
RXA_IN4_P
RXA_CLKIN_N
RXA_CLKIN_P
RXA_IN3_N
RXA_IN3_P
RXB_IN0_N
RXB_IN0_P
RXB_IN1_N
RXB_IN1_P
RXB_IN2_N
RXB_IN4_N
RXB_IN2_P
RXB_IN4_P
RXB_CLKIN_N
RXB_CLKIN_P
RXB_IN3_N
RXB_IN3_P
G1
H1
J1
K1
L1
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
28
27
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
28
27
J3
3M_Rx_10226-1210VE
DDC_Gnd_1
RxIn3+
RxIn3Gnd
RxIn3DDC_+5VDC
USB_+5VDC
RxClkIn+
RxClkInGnd
RxClkInDDC/SCL
USBUSB_Shield
USB+
RxIn2+
RxIn2Gnd
RxIn2DDC/SDA
RxIn1+
RxIn1Gnd
RxIn1USB/DDC_Gnd
Sense
RxIn0+
RxIn0Gnd
RxIn0DDC_Gnd_26
Mounting_L
Mounting_R
J2
3M_Rx_10226-1210VE
DDC_Gnd_1
RxIn3+
RxIn3Gnd
RxIn3DDC_+5VDC
USB_+5VDC
RxClkIn+
RxClkInGnd
RxClkInDDC/SCL
USBUSB_Shield
USB+
RxIn2+
RxIn2Gnd
RxIn2DDC/SDA
RxIn1+
RxIn1Gnd
RxIn1USB/DDC_Gnd
Sense
RxIn0+
RxIn0Gnd
RxIn0DDC_Gnd_26
Mounting_L
Mounting_R
13
12
11
10
9
2
26
25
24
23
22
21
20
8
19
6
7
18
5
16
17
4
15
3
14
2
1
2
Date:
Size
C
Title
1
Sheet
2
MDR / VHDM conversion
Document Number
of
2
Lattice Semiconductor Corporation
1
A1
Rev
A
B
C
D
Lattice Semiconductor
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Figure 15. Video Demo Board #4 Schematic (Cont.)
Lattice 7:1 LVDS Video Demo Kit
User’s Guide
Lattice Semiconductor
Modified Video Demo Board #1 Schematic
Rework instructions for Video Demo Board #1 so that it can be used on the Rx side. (Note that the reworked Video
Demo Board #1 is not equivalent to Video Demo Board #4. Please modify the .lpf preference file of reference
design RD1030, LatticeECP2/M 7:1 LVDS Video Interface, to match the board that you are using on the Rx side.
The Tx side can use either the reworked Board #1, non-reworked Board #1 or Board #4).
1. Solder a short wire from J2 pin 6 to J2 pin 20.
2. Use another short wire with the same length to connect J2 pin 7 to J2 pin 21.
26