LatticeECP3™ Video Protocol Board – Revision B User’s Guide March 2010 Revision: EB39_01.3 Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Introduction The LatticeECP3™ FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented with 16 channels of embedded SERDES/PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also be used to receive the TMDS signals of DVI or HDMI video standard. This user’s guide describes revision B of the LatticeECP3 Video Protocol Board featuring the LatticeECP3 LFE395E-7FN1156C FPGA device. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of many different video applications. Figure 1. LatticeECP3 Video Protocol Board – Revision B Features • Video interfaces for interconnection to video standard equipment • Allow the demonstration of SD/HD/3G-SDI, DisplayPort and PCI Express (x4) interfaces using SERDES channels • High speed Mezzanine connector connected to SERDES channels for future expansion • Allows the demonstration of LVDS video standards – ChannelLink and CameraLink • Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra) • Allows the demonstration of receiving TMDS signals using the DVI interface • On-board Boot Flash with Serial SPI Flash memory device • Shows interoperation with high performance DDR2 memory components • Driver-based “run-time” device configuration capability via an ORCAstra or RS232 interface • SMAs for external high-speed clock / PLL inputs • Switches, LEDs and LCD display header for demo purposes 2 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor • Mictor connector for using Logic Analyzer in the debugging phase • Input connection for lab-power supply • Power connections and power sources • ispVM™ programming support • On-board and external reference clock sources • Various high-speed layout structures • User-defined input and output points • Performance monitoring via test headers, LEDs and switches The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2 shows the functional partitioning of the board. Figure 2. LatticeECP3 Video Protocol Board – Revision B Functional Partition PCI Express x4 Edge DDR2 Memory Tx Refclk Generation Ckt. 27MHz VCO Refclk GS4911 GS4915 Ch3 Ch2 Ch1 DisplayPort Tx Ch0 Refclk Ch3 DisplayPort Rx Ch2 Ch1 Ch0 SDI Tx #1 3G-SDI Driver SDI Rx #1 3G-SDI Equalizer DDR2 Memory Ch2 Ch1 Ch0 Bank 0 Q U ECP3-95 A SERDES 1156 fpBGA D 1 Q U A D 0 DVI Tx Bank 3 Bank 2 3G-SDI Equalizer ChannelLink Tx SDI Tx #0 Bank 7 Bank 1 Refclk Ch3 3G-SDI Driver Bank 6 Q U A D 2 ChannelLink Rx RJ45 CameraLink Rx DVI Rx SDI Rx #0 LatticeECP3 Device This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeECP3 devices in the 1156-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP3 Family Data Sheet. 3 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Applying Power to the Board The LatticeECP3 Video Protocol Board is ready to power on. This board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench top supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J15 and plug wall-transformer into an AC wall outlet. Supply Power from Bench Power Supply The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is intended to be used with a bench top supply adjusted to provide a nominal 12V DC. All input power sources and on-board power supplies are fused with surface mounted fuses. Table 1 shows these fuses and the corresponding powers. Table 1. Board Power Supply Fuses Fuse # Rating Voltage F1 3A 2.5V F2 3A 1.8V Bank 6, Bank 7 I/Os, DDR2 regulator, DDR2 memory, Gennum clock chips 3A 5.0V Cable driver/equalizer power regulator, Gennum clock chips power regulators, DisplayPort power output regulators, Mezzanine connector, DVI power output for EDID, LCD module F4 3A 1.2V LatticeECP3 SERDES F5 10A 12V Main power supply F6 10A 1.2V LatticeECP3 Core 3.3V LatticeECP3 VCCAUX, PLL, JTAG, Bank 0 and 8 I/Os, SPI Flash memory, push-button debouncer, DVI transmitter, RS-232 driver/receiver, zero delay clock buffer, clock oscillators, MachXO™, cable driver/equalizer F3 F7 10A Usage EEPROM, DDR2 regulator, Bank 1, 2 and 3 I/Os, DIP switches Lattice’s ispPAC® Power Manager II device, the ispPAC-POWR1220AT8, is used for monitoring various voltages on the board. There are six LEDs used to indicate the status of the monitoring voltages. If the monitoring voltage is not in the +/- 5% voltage window, the corresponding LED will flash; otherwise, the LED will stay ON. Table 2 shows these six voltages and the corresponding LEDs. Table 2. Board Power Supply Monitoring Indicators Power LED # Voltage Range In Range Out of Range LatticeECP3 SERDES D33 1.2V +/- 5% On Flash LatticeECP3 Core D32 1.2V +/- 5% On Flash 3.3V D31 3.3V +/- 5% On Flash 2.5V D29 2.5V +/- 5% On Flash 5.0V D28 5.0V +/- 5% On Flash 1.8V D27 1.8V +/- 5% On Flash External power can be alternatively connected through TB1 rather than the wall transformer power pack. Table 3. Board Supply Disconnects TB1 Screw terminal for 12V DC +12V: Pin1 (closer to the wall transformer power jack J15) 12V DC GND: Pin2 (closer to the LCD connector) 4 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor PCI Express Power Interface Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power from a PCI Express host board. Configuration/Programming Headers Two programming headers are provided on the board for accessing to the LatticeECP3 JTAG port and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header. Table 4. sysCONFIG Connector Pinout (J37) Net Name LatticceECP3 Pin Header Pin Net Name CCLK SISPI LatticceECP3 Pin Header Pin C34 1 GND — 2 F33 3 D6 J34 4 CSSPI0N D34 5 3.3V — 6 CSSP1N E34 7 INITN C33 8 DONE G31 9 PROGRAMN B34 10 D7 F32 11 GND — 12 D6 J34 13 GND — 14 D5 H34 15 GND — 16 D4 G32 17 GND — 18 D3 G33 19 GND — 20 D2 H33 21 GND — 22 D1 G34 23 GND — 24 D0 E32 25 GND — 26 CSN F31 27 WRITE E31 28 CS1 G30 29 CFG0 B33 30 3.3V — 31 CFG1 F30 32 GND — 33 CFG2 D32 34 J28 is a 10-pin JTAG connector used in conjunction with the ispVM download cable to program and control the Lattice devices on this board. Table 5. ispVM JTAG Connector (J28) Pin # Description Pin 1 VCC Pin 2 TDO Pin 3 TDI Pin 4 PROGRAMN Pin 5 NC Pin 6 TMS Pin 7 GND Pin 8 TCK Pin 9 DONE Pin 10 INITN This board includes three Lattice programmable devices that can be programmed in a daisy chain (U30 = LatticeECP3-95, U1 = MachXO LCMXO256, and U36 = ispPAC-POWR1220AT8). Other than the LatticeECP3-95, the JTAG connector provides access to the JTAG ports of the ispPAC-POWR1220AT8 and the MachXO. With 5 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor proper jumper selection, the JTAG ports of these devices can be chained together for programming. Table 6 shows the jumper settings of J32, J33 and J34 used to configure the JTAG connections. Table 6. JTAG Connection Settings (J32, J33, J34) Jumper Settings JTAG Connection J32 J33 J34 TDI ECP3 MachXO ispPAC 1 TDO J32 J33 J34 TDI ECP3 MachXO ispPAC 2 TDO J32 J33 J34 TDI TDO 3 ECP3 J32 J33 J34 MachXO ispPAC MachXO ispPAC TDI ECP3 4 TDO J32 J33 J34 TDI ECP3 MachXO ispPAC ECP3 MachXO ispPAC 5 TDO J32 J33 J34 TDI 6 TDO J32 J33 J34 TDI ECP3 7 TDO 6 MachXO ispPAC LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor There are several LEDs on the board to indicate the LatticeECP3 programming status. They are listed in Table 7. Table 7. LED Indicators for Configuration Status LED # Color Function D8 Red D11 Green D10 Red LED illuminated to indicate that PROGRAMN is low. D9 Red LED illuminated to indicate that GSRN is low. LED illuminated to indicate that the programming was aborted or reinitialized driving the INITN output low. LED illuminated to indicate the successful completion of configuration by releasing the open collector DONE output pin. The PROGRAMN pin of the LatticeECP3-95 is connected to a push-button switch (SW5). Depressing this button drives a logic level “0” to the PROGRAMN pin. This will force the LatticeECP3 into the configuration mode and initiate the configuration sequence. The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch. JTAG programming is independent of the MODE pins and is always available to the user. Pushing down the switch will turn it on and set the CFG value to 0. Table 8. CFG Mode Selections CFG2 (Sw2-1) CFG1 (Sw2-2) CFG0 (Sw2-3) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 1 (OFF) 0 (ON) SPIm 1 (OFF) 0 (ON) 0 (ON) Master Serial Selected Configuration Mode SPI Flash Mode (available on-board) 1 (OFF) 0 (ON) 1 (OFF) Slave Serial 1 (OFF) 1 (OFF) 0 (ON) Master Parallel 1 (OFF) 1 (OFF) 1 (OFF) Slave Parallel On-Board Flash Memory One SPI (16-pin TSSOP 64M) Flash memory device (U32) is on board for non-volatile configuration memory storage. The CFG [2:0] setting must be [000] for the LatticeECP3 to enable the SPI Flash mode. Video Clock Management and SDI Cable Driver/Equalizer Industry standard video clocks are generated and managed via Gennum chipsets. These chipsets are used to generate both transmit and receive reference clocks for LatticeECP3 SERDES. The GS4911 clock generator device produces multiple video standard reference clocks from an on-board 27MHz crystal. The GS4915 clock cleaner is used to reduce clock jitter to produce a clean clock for video signal quality using a high performance VCO. Two cable drivers and two cable equalizers are placed on-board for SD/HD/3G-SDI applications that require delivering video signal over 75 ohm coaxial cable. The control and status pins of the Gennum chipsets and the cable drivers/equalizers are connected to the MachXO I/O pins. By using the signals connected between the MachXO and LatticeECP3, the Gennum chipsets and cable drivers/equalizers can be controlled from the design in the LatticeECP3. Figure 3 shows the block diagram of the control/status buses of the connections between these devices. The MachXO pins connected to these devices are shown in Tables 9 to 12. 7 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Figure 3. Block Diagram of Gennum Chipsets and Cable Driver/Equalizer Controls RX_GS4911_RESETn SDI Tx #1 Cable Driver (U24) Rx Refclk Generator GS4911 (U2) SDI Rx #1 Cable Equalizer (U21) Rx Refclk Cleaner GS4915 (U6) MachXO SDI Tx #0 Cable Driver (U22) Tx Refclk Generator GS4911 (U3) SDI Rx #0 Cable Equalizer (U25) 12 LatticeECP3 Tx Refclk Cleaner GS4915 (U7) TX_GS4911_RESETn Table 9. MachXO Pin Connections to GS4911 Devices Signal Type Control U2 (for Rx Refclk) U3 (for Tx Refclk) Pull-low/high VID_STD0 GS4911 Pin Name K2 G13 High VID_STD1 L1 H13 Low VID_STD2 L2 J13 High VID_STD3 M1 J14 Low VID_STD4 M2 K13 High VID_STD5 N1 K14 Low /GENLOCK M3 M13 High ASR_SEL0 H2 — Low ASR_SEL1 G2 — Low F2 — Low N11 N11 — P13 P13 — — N12 — ASR_SEL2 JTAG / HOSTn1 1 SCLK_TCLK SDIN_TDI SDOUT_TDO P12 — — CSn_TMS P11 P14 — /RESET D17 (from LatticeECP3) D12 (from LatticeECP3) LOCK_LOST Status — Low L14 — REF_LOST — L13 — TIMING_OUT_1 K1 F14 — TIMING_OUT_2 J2 F13 — TIMING_OUT_3 J1 E14 — TIMING_OUT_4 — E13 — 1. These are the signals controlled by the same MachXO I/O pins. 8 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 10. MachXO Pin Connections to GS4915 Devices Signal Type Control Status GS4915 Pin Name U6 (for Rx Refclk) U7 (for Tx Refclk) Pull-low/high /RESET F1 D14 High IPSEL E2 D13 Low BYPASS E1 C14 Low /AUTOBYPASS C2 C13 Low FCTRL0 D1 B14 Low FCTRL1 D2 C12 Low DOUBLE C1 A13 Low SKEW_EN B1 A12 Low LOCK B11 B12 — Table 11. MachXO Pin Connections to LMH0303 or GS2978 Cable Driver Devices Signal Type Driver Pin Name U22 (for Tx #0) SD / HDn N5 N14 Low Control ENABLE (/DISABLE) N6 M14 High /RSTI N7 — High /FAULT N13 N13 — U21 (for Rx #1) Pull-low/high Status U24 (for Tx #1) Pull-low/high Table 12. MachXO Pin Connections GS2974 Cable Equalizer Devices Signal Type Control Status Driver Pin Name U25 (for Rx #0) BYPASS P3 P8 Low MUTE P4 N8 Low MCLADJ Controlled by potentiometer VR3 Controlled by potentiometer VR2 — /CD N3 P9 — Table 13. MachXO Pin Connections GS2974 Cable Equalizer Devices MachXO Pin LatticeECP3 Pin ECP3_XO_SIG0 Net Name B10 AM31 ECP3_XO_SIG1 A9 AL31 ECP3_XO_SIG2 A7 AN31 ECP3_XO_SIG3 A6 AP31 ECP3_XO_SIG4 A5 AM32 ECP3_XO_SIG5 B4 AN32 ECP3_XO_SIG6 A3 AB33 ECP3_XO_SIG7 B3 AB34 ECP3_XO_SIG8 A2 Y31 ECP3_XO_SIG9 C3 Y32 ECP3_XO_SIG10 A1 Y33 ECP3_XO_SIG11 B2 Y34 The status pins of these devices can also be observed from LED indicators. Table 13 shows the these LEDs with the associated signals. 9 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 14. LED Indicators for Video Clocking and Cable Equalizer Status LED # Color Function Description D4 Red Rx GS4911 REF LOST D1 Red Tx GS4911 REF LOST D3 Red Rx GS4911 LOCK LOST LED illuminated to indicate the GS4911 clock output is not genlocked to Tx GS4911 LOCK LOST the input reference signals. D2 Red D5 Green Rx GS4915 LOCK D6 Green Tx GS4915 LOCK D9 Orange SDI Rx #0 Carrier Detect LED illuminated to indicate that no reference signal is applied or the FSYNC, VSYNC, HSYNC input reference signals do not meet the min/max timing requirement. LED illuminated to indicate that the GS4915 output clock is locked to the input clock selected by IPSEL. LED illuminated to indicate that the equalizer has detected the presence of a good input video signal. SERDES There are three SERDES quads available for the LatticeECP3-95. Each quad include four SERDES channels. These 12 SERDES channels are used for implementing high-speed serial link interfaces. Figure 4 shows the how these channels are used. Figure 4. Block Diagram of SERDES Usage PCI Express x4 Edge 27MHz VCO GS4911 Mezzanine Connector (J19) Mezz Si570 (U9) Tx Refclk Generation Ckt. SMA (J7, J8) GS4915 Refclk Ch3 Ch2 DisplayPort Tx (J4) Ch1 Ch0 3.3V Voltage Regulator Refclk DisplayPort Rx (J3) Ch3 Ch2 3.3V Voltage Regulator SDI Tx #1 (J2) SDI Rx #1 (J1) Ch1 Ch0 Driver (U24) Refclk Ch3 Equalizer (U21) Ch2 Ch1 Ch0 Driver (U22) Equalizer (U25) SDI Tx #0 (J5) SDI Rx #0 (J6) Q U A D 2 Q U A D 1 Q U A D 0 Bank 6 SERDES ECP3-95 1156 fpBGA Bank 3 The power supply of the input and output buffers of the SERDES quads can be individually set to either 1.2V or 1.5V. This is done by headers J18, J20~J24. Table 15 shows the jumper settings of these headers for applying either 1.2V or 1.5V power to the SERDES input and output buffers. 10 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 15. Jumper Settings for SERDES I/O Buffer (J18, J20~J24) Header J24 J20 J23 J21 J22 J18 Buffer Quad 0 Input Quad 0 Output Quad 1 Input Quad 1 Output Quad 2 Input Quad 2 Output Jumper Setting Function 1-2 Set PCSA_VCCIB (J24 pin 2) to 1.2V 2-3 Set PCSA_VCCIB (J24 pin 2) to 1.5V 1-2 Set PCSA_VCCOB (J20 pin 2) to 1.2V 2-3 Set PCSA_VCCOB (J20 pin 2) to 1.5V 1-2 Set PCSB_VCCIB (J23 pin 2) to 1.2V 2-3 Set PCSB_VCCIB (J23 pin 2) to 1.5V 1-2 Set PCSB_VCCOB (J21 pin 2) to 1.2V 2-3 Set PCSB_VCCOB (J21 pin 2) to 1.5V 1-2 Set PCSC_VCCIB (J22 pin 2) to 1.2V 2-3 Set PCSC_VCCIB (J22 pin 2) to 1.5V 1-2 Set PCSC_VCCOB (J18 pin 2) to 1.2V 2-3 Set PCSC_VCCOB (J18 pin 2) to 1.5V Quad 0 (3G-SDI and DisplayPort Video Interfaces) Quad 0 is used for SDI and DisplayPort video protocols. Channel 0 and 1 of quad 0 are used for SD/HD/3G-SDI. The SD/HD/3G-SDI video signal is a signal-ended video signal transmitting through 75-ohm coaxial cable connecting through BNC connectors. Two cable drivers and two cable equalizers are placed on board for using longer coaxial cable. Channels 2 and 3 are used for support Displayport up to two data lanes. Table 16 shows the ECP3 connections for the SD/HD/3G-SDI video interface connectors. Table 16. SD/HD/3G-SDI Connections (J1, J2, J5 and J6) Connector Description Cable Driver/Equalizer SERDES Pin Names LatticeECP3 Pin # J5 SDI Tx #0 Driver (U22) PCSA_HDOUT[P:N]0 AP21, AN21 J6 SDI Rx #0 Equalizer (U25) PCSA_HDIN[P:N]0 AL21, AK21 J2 SDI Tx #1 Driver (U24) PCSA_HDOUT[P:N]1 AP20, AN20 J1 SDI Rx #1 Equalizer (U21) PCSA_HDIN[P:N]1 AL20, AK20 There are two instances of Gennum clocking circuitry on this board, one for Rx side and the other for Tx side. Since the specification of the high-speed video output stream jitter is critical, it is important to have a clean reference clock for the Tx side serializer. The reference clock of the SERDES channel can come from different a path, but the clock coming in through the dedicated reference clock pins will have the lowest jitter. The dedicated reference clock pins of quad 0 can be sourcing from the following clocks: • Clock generated by the on-board Gennum clocking chipsets • Clock generated by the Silicon Labs Si570 • External differential clock coming through the two SMA connectors Other than generating from the Gennum chipsets, the transmit reference clock can also receive input clock from an external clock source via a pair of SMA connectors, or from the on-board Silicon Labs Si570. To avoid PCB trace stub and minimize the jitter of the Tx reference clock, two zero-ohm resistors are used for selecting the clock from one of the three clock sources. Figure 5 shows how these two zero-ohm resistors are installed to select a difference clock source. See the schematic in Appendix A (Figure 20) for the detailed clock multiplexing circuitry. 11 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Figure 5. Resistors for Quad 0 Reference Clock Selection Select clock from Gennum chipsets TP11 Select clock from SMA connectors Select clock from Silicon Labs Si570 TP13 R47 R48 TP12 TP14 On-board Default Figure 6 shows the block diagram of the DisplayPort circuitry on this board. Since only two channels in SERDES Quad 0 are used, the DisplayPort video interface on this board can only support up to two lanes. Two instances of 3.3V voltage regulators are used for providing power to the off-board DisplayPort devices when necessary. Figure 6. Block Diagram of the DisplayPort Video Interface DisplayPort Rx (J3) LatticeECP3 (U30) ML0_P_IN ML0_N_IN 0.1uF AL19 0.1uF AK19 ML1_P_IN ML1_N_IN 0.1uF AL18 0.1uF AK18 0.1uF 3.3V 1M Quad 0 CH2 AP19 0.1uF AN19 0.1uF Quad 0 CH3 AP18 0.1uF AN18 0.1uF N27 AUX_P 49.9 DisplayPort Tx (J4) 1M 49.9 0.1uF 100K AUX_N 0.1uF C32 HPD_OUT 100K CONFIG1 CONFIG2 3.3V 100 C31 100K 49.9 R25 100 HPD_OUT 49.9 0.01uF N28 AUX_N AUX_P 100 0.01uF 100K 1K CONFIG1 CONFIG2 1K 1K 1K 5.0V 5.0V PWR_OUT ML1_P_OUT ML1_N_OUT 0.1uF R26 100 ML0_P_OUT ML0_N_OUT 3.3V Voltage Regulator (U19) J16 G17 enable enable 3.3V Voltage Regulator (U23) PWR_OUT Table 17 shows the pin connections of the DisplayPort video interface. Table 17. DisplayPort Connections (J3 and J4) Connector DisplayPort Tx (J4) DisplayPort Rx (J3) Pin Name Pin # LatticeECP3 Pin Name LatticeECP3 Pin # ML0_[P:N]_OUT 1 and 2 PCSA_HDOUT[P:N]2 AP19, AN19 ML1_[P:N]_OUT 4 and 6 PCSA_HDOUT[P:N]3 AL18, AK18 AUX_[P:N] 15 and 17 PR31[A:B] R26, R25 HPD_IN 18 PT143B C32 ML0_[P:N]_IN 10 and 12 PCSA_HDIN[P:N]2 AL19, AK19 ML1_[P:N]_IN 7 and 8 PCSA_HDIN[P:N]3 AL18, AK18 AUX_[P:N] 15 and 17 PR22[A:B] N27, N28 HPD_OUT 18 PT145B C31 12 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Quad 1 (PCI Express x4) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into a x1 host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections. All channels of Quad 1 are connected to the PCI Express Edge connector (CN1) for implementing a PCI Express x4 interface. The dedicated reference clock input pins and a reset control signal are also connected to the PCI Express edge connector. Table 18. SERDES PCI Express Interconnections PCI Express Name PCI Express Pin # LatticeECP3 Pin Name LatticeECP3 Pin # AC Coupling PERp0 A16 PCSB_HDOUTP0 AP17 C365 PERn0 A17 PCSB_HDOUTN0 AN17 C366 PERp1 A21 PCSB_HDOUTP1 AP16 C372 PERn1 A22 PCSB_HDOUTN1 AN16 C375 PERp2 A25 PCSB_HDOUTP2 AP15 C376 PERn2 A26 PCSB_HDOUTN2 AN15 C379 PERp3 A29 PCSB_HDOUTP3 AP14 C382 PERn3 A30 PCSB_HDOUTN3 AN14 C383 PETp0 B14 PCSB_HDINP0 AL17 None PETn0 B15 PCSB_HDINN0 AK17 None PETp1 B19 PCSB_HDINP1 AL16 None PETn1 B20 PCSB_HDINN1 AK16 None PETp2 B23 PCSB_HDINP2 AL15 None PETn2 B24 PCSB_HDINN2 AK15 None PETp3 B27 PCSB_HDINP3 AL14 None PETn3 B28 PCSB_HDINN3 AK14 None REFCLK+ A13 PCSB_REFCLKP AH15 None REFCLK- A14 PCSB_REFCLKN AH16 None PERST# A11 PT109A J21 None PCI Express Pin Description Receiver differential pair, Lane 0 Receiver differential pair, Lane 1 Receiver differential pair, Lane 2 Receiver differential pair, Lane 3 Transmitter differential pair, Lane 0 Transmitter differential pair, Lane 1 Transmitter differential pair, Lane 2 Transmitter differential pair, Lane 3 Reference clock (differential pair) Fundamental reset Quad 2 (Daughter Board Expansion) All channels of Quad 2 are connected to a high-speed Molex Mezzanine connector for working with a 3 x 2.5” daughter board. Users can design a daughter board for implementing anything that requires the SERDES quad, such as the high-speed HDMI/DVI video interface. 13 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Figure 7. Daughter Board Connection Daughter Board Power Connector (J17) Power Lattice ECP3 MDR MDR MDR MDR 2.5"x3.0" R x T x Mezzanine Connector (J19) R x T x D P D P Hole for standoffs to secure the Daughter Board Other than the four input/output Quad 2 SERDES channels and the differential reference clock pair, there are three differential pairs of general purpose I/Os connected between the Mezzanine connector and the LatticeECP3 device. These signals can be used for the control or status signals of the daughter board. A 4-pin power connector is used to provide power to the daughter board. Tables 19 and 20 show the pin connections of the Mezzanine and the power connectors. Table 19. Mezzanine Connections (J19) J19 Pin # LatticeECP3 Pin Name LatticeECP3 Pin # 1 PCSC_HDINP3 AL22 2 PCSC_HDINN3 AK22 3 PCSC_HDINP2 AL23 4 PCSC_HDINN2 AK23 5 PCSC_HDINP1 AL24 6 PCSC_HDINN1 AK24 7 PCSC_HDINP0 AL25 8 PCSC_HDINN0 AK25 9 PR25A P28 10 PR25B P27 11 PR28A R28 12 PR28B R27 13 PCSC_HDOUTP3 AL22 14 PCSC_HDOUTN3 AK22 15 PCSC_HDOUTP2 AL23 16 PCSC_HDOUTN2 AK23 17 PCSC_HDOUTP1 AL24 18 PCSC_HDOUTN1 AK24 19 PCSC_HDOUTP0 AL25 20 PCSC_HDOUTN0 AK25 21 PCSC_REFCLKP AH22 22 PCSC_REFCLKN AH23 14 Description SERDES Quad 2 Channel 3 Input SERDES Quad 2 Channel 2 Input SERDES Quad 2 Channel 1 Input SERDES Quad 2 Channel 0 Input User-defined Differential Signal Pair 1 User-defined Differential Signal Pair 2 SERDES Quad 2 Channel 3 Output SERDES Quad 2 Channel 2 Output SERDES Quad 2 Channel 1 Output SERDES Quad 2 Channel 0 Output SERDES Quad 2 Reference Clock LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 19. Mezzanine Connections (J19) (Continued) J19 Pin # LatticeECP3 Pin Name LatticeECP3 Pin # 23 PR19A N26 24 PR19B P26 Description User-defined Differential Signal Pair 0 Table 20. Daughter Board Power Connections (J17) J17 Pin # Voltage 1 5.0V 2 GND 3 3.3V 4 GND Maximum Current — — Figure 8 shows the mechanical dimensions required for designing a daughter board. Figure 8. Mechanical Drawing of the Daughter Board Connection 1.5" 0.4" 0.6" Circuit #1 Circuit #3 1.9" J19 Daughter Board (Size 2.5” x 3.0”) 0.0689" LatticeECP3 0.2" 2.1" Circuit #1 0.3" Circuit #13 0.937" 2.20" 2.50" ChannelLink and CameraLink Video Interfaces There are two LVDS video interfaces on the board, ChannelLink and CameraLink. Both interfaces include transmit and receive channels. All these four channels are using the same on-board 3M MDR-26(p/n 10226-1210VE) connectors. However, since the pinouts of these two interfaces are different, different 3M Mini D Ribbon (MDR) Cables must be used. The cables are listed below. They look the same but have different pinouts. • 3M ChannelLink Cable: 14526-EZ8B-XXX-07C • 3M CameraLink Cable: 14X26-SZLB-XXX-0LC Tables 21 to 23 show the connections of these four 3M connectors. 15 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 21. ChannelLink Tx Connections (J9) Signal Name J9 Pin # LatticeECP3 Pin # TX OUT0+ 15 AM29 TX OUT0- 14 AN29 TX OUT1+ 5 AL30 TX OUT1- 4 AM30 TX OUT2+ 7 AJ31 TX OUT2- 6 AK31 TX OUT3+ 13 AA28 TX OUT3- 12 AA27 TX CLKOUT+ 23 AH33 LatticeECP3 Pin Type External Resistor True LVDS Output None True LVDS Output None True LVDS Output None True LVDS Output None True LVDS Output None Table 22. ChannelLink Rx Connections (J10) Signal Names J10 Pin # LatticeECP3 Pin# RX IN0+ 12 V31 RX IN0- 13 V30 RX IN1+ 22 W34 RX IN1- 23 W33 RX IN2+ 20 W32 RX IN2- 21 W31 RX IN3+ 14 W29 RX IN3- 15 W28 RX CLKIN+ 4 U28 LatticeECP3 Pin Type External Resistor LVDS Input R65 (100 _) LVDS Input R63 (100 _) LVDS Input R60 (100 _) LVDS Input R58 (100 _) LVDS Input R61 (100 _) Table 23. RJ45 Connections (J44 and J45) Signal Name Pin# LatticeECP3 Pin# RJ45_OUT_P0 1 (J44) W27 RJ45_OUT_N0 2 (J44) W26 RJ45_OUT_P1 3 (J44) AA25 RJ45_OUT_N1 6 (J44) AA26 RJ45_OUT_P2 4 (J44) W30 RJ45_OUT_N2 5 (J44) W29 RJ45_OUT_P3 7 (J44) Y26 RJ45_OUT_N3 8 (J44) Y25 RJ45_IN_P0 1 (J45) AM34 RJ45_IN_N0 2 (J45) AM33 RJ45_IN_P1 3 (J45) AC32 RJ45_IN_N1 6 (J45) AC31 RJ45_IN_P2 4 (J45) AA34 RJ45_IN_N2 5 (J45) AA33 RJ45_IN_P3 7 (J45) P30 RJ45_IN_N3 8 (J45) R29 16 LatticeECP3 Pin Type External Resistor True LVDS Output None True LVDS Output None Emulated LVDS Output None True LVDS Output None LVDS Input R65 (100_) LVDS Input R63 (100_) LVDS Input R60 (100_) LVDS Input R58 (100_) LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 24. CameraLink Rx Connections (J12) Signal Name J12 Pin # LatticeECP3 Pin# X0+ 12 U32 X0- 25 U31 X1+ 11 U34 X1- 24 U33 X2+ 10 T34 X2- 23 T33 X3+ 8 T32 X3- 21 T31 XCLK+ 9 U26 XCLK- 22 U27 SerTC+ 20 N30 SerTC- 7 N29 LatticeECP3 Pin Type External Resistor LVDS Input R80 (100 _) LVDS Input R76 (100 _) LVDS Input R71 (100 _) LVDS Input R68 (100 _) LVDS Input R70 (100 _) RN33A Emulated LVDS Output ECP3 165 140 165 SerTFG+ 6 P32 SerTFG- 19 P31 CC1+ 5 R34 CC1- 18 R33 LVDS Input R206 (100 _) RN32A Emulated LVDS Output ECP3 165 140 165 CC2+ 17 R31 CC2- 4 R30 RN32B Emulated LVDS Output ECP3 165 140 165 CC3+ 3 P34 CC3- 16 P33 RN31A Emulated LVDS Output ECP3 165 140 165 CC4+ 15 N34 CC4- 2 N33 RN31B Emulated LVDS Output ECP3 165 140 165 DVI Video Interface There are two DVI video connectors on this board, one for DVI receive and the other for DVI transmit. The I/Os on the banks 0 and 1 of LatticeECP3 support thee TRLVDS (Transition Reduced LVDS) I/O standard and can be used to receive video signals with TMDS standard such as DVI and HDMI. These I/Os can support a maximum bandwidth of up to 1Gbps. The TMDS signals of DVI Rx connector (J16). For DVI Tx, the TMDS transmitter TFP410 from TI is used to convert and encode the parallel R, G, B pixel data to TMDS signals. These TMDS signals are then connected to J14. Tables 25 and 26 show the LatticeECP3 pin connections to these two DVI connectors. 17 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 25. DVI Rx Connections (J16) J16 Pin # Pin Name LatticeECP3 Pin # Description 18 TMDS_Data0+ C16 17 TMDS_Data0- D16 10 TMDS_Data1+ A16 9 TMDS_Data1- B16 2 TMDS_Data2+ C17 1 TMDS_Data2- D17 23 TMDS_Clock0+ J17 24 TMDS_Clock0- H17 6 DDC_Clock D14 DVI Rx DDC Clock 7 DDC_Data J15 DVI Rx DDC Data 16 Hot Plug Detect F13 DVI Rx Hot Plug Detect TMDS Blue Data Channel TMDS Green Data Channel TMDS Red Data Channel TMDS Clock Channel Table 26. DVI Tx Connections (J14) J14 Pin # J14 Pin Name 18 and 17 TMDS_Data0+TMDS_Data0- 10 and 9 TMDS_Data1+TMDS_Data1- 2 and 1 TMDS_Data2+TMDS_Data2- TFP410 Pin TFP410 Pin # LatticeECP3 Pin # DATA7 54 DATA6 55 A5 DATA5 58 G12 DATA4 59 G13 DATA3 60 A12 DATA2 61 B12 DATA1 62 J14 Description A4 (MSB) DATA0 63 H13 (LSB) DATA15 44 B3 (MSB) DATA14 45 A2 DATA13 46 D5 DATA12 47 C6 DATA11 50 B4 DATA10 51 A3 DATA9 52 D6 DATA8 53 C5 (LSB) DATA23 36 C3 (MSB) DATA22 37 C4 DATA21 38 D3 DATA20 39 C2 DATA19 40 B1 DATA18 41 B2 DATA17 42 E4 DATA16 43 D4 (LSB) TMDS Blue Data Channel TMDS Green Data Channel TMDS Red Data Channel 6 DDC_Clock — — C14 DVI Tx DDC Clock 7 DDC_Data — — G15 DVI Tx DDC Data — — IDCKP 57 K14 — — — DE 2 D13 — — — VSYNC 5 J13 — 18 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 26. DVI Tx Connections (J14) (Continued) J14 Pin # J14 Pin Name TFP410 Pin TFP410 Pin # LatticeECP3 Pin # Description — — HSYNC 4 H14 — — — ISEL/RSTN 13 G21 — — — BSEL/SCL 15 B13 — — — DSEL/SDA 14 A13 — RS-232 Interface A 2x5 header (J38) provides a RS-232 port connection to the LatticeECP3 device via a RS-232 transceiver MAX232. Either the DB25 or DB9 cable can be connected to this header for providing a RS-232 pot with industrial standard pinout. Table 27 shows the pin connections of this header. Table 27. RS-232 Interface Header Pin Connections (J38) J38 Pin # Pin Name Net Name LatticeECP3 Pin # J38 Pin # Pin Name Net Name LatticeECP3 Pin # 1 N.C. — — 2 N.C. — — 3 TXD RS232_TXD F12 (Input) 4 N.C. — — 5 RXD RS232_RXD E11 (Output) 6 N.C. — — 7 N.C. — — 8 N.C. — — 9 N.C. GND — 10 N.C. — — LCD Interface A 2x9 header (J43) provides a connection to LCD modules such as the 20-character x 2 line LCD module LCMS02002DSR or LCM-S02002DSR (with backlight LED) from Lumex. The board includes two variable resistors for LCD adjustments. VR6 adjusts the backlight and VR5 provides contrast adjustment. A user design must be included in the FPGA to drive this feature. This header can also be used for probe points for observing FPGA pins. Pin 1 and Pin 2 of header J43 are dummy pins that connect to nothing. When installing the Lumex LCD module, these two pins should be skipped. Table 28 shows the pin connections of this header. Table 28. LCD Interface Header Pin Connections (J43) J43 Pin# LatticeECP3 Pin # LCM-S02002 Pin # 1 — — N.C. (Dummy) 2 3 — 1 GND 5 — 3 VO (Contrast) 7 A8 5 Net Names J43 Pin# LatticeECP3 LCM-S02002 Pin # Pin# Net Names — — N.C. (Dummy) 4 — 2 5V 6 H15 4 LCD5 / LCD_RS LCD0 / LCD_R/W 8 E17 6 LCD6 / LCD_E 9 A9 7 LCD1 / LCD_DB0 10 B14 8 LCD7 / LCD_DB1 11 A7 9 LCD2 / LCD_DB2 12 A14 10 LCD8 / LCD_DB3 13 E15 11 LCD3 / LCD_DB4 14 E13 12 LCD9 / LCD_DB5 15 D15 13 LCD4 / LCD_DB6 16 E12 14 LCD10 / LCD_DB7 17 — 15 ANODE (Backlight) 18 — 16 GND 19 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Switches and LEDs There are many on-board DIP switches, push-button switches, discrete LEDs and a 16-segment LED display that can be used to provide static inputs and outputs for a design. Figure 9 shows the locations of these components. Figure 9. Locations of Switches and LEDs SW1 SW3 SW4 SW10 SW9 SW8 SW7 D10 D11 D12 D13 D22 D23 D24 D26 D14 D15 D16 D17 SW6 D30 DIP Switches (SW1, SW3 and SW4) There are three SPDT toggle-DIP switches on this board. Each of these switches includes four positions to make a total number of 12 static input signals to a design. Table 29 shows the pin connections and colors of these LEDs. Table 29. DIP Switch Connections Switch # SW1 SW3 SW4 Position # Signal LatticeECP3 Pin # 1 SWITCH1 Y5 2 SWITCH2 Y4 3 SWITCH3 Y9 4 SWITCH4 Y10 1 SWITCH5 AD2 2 SWITCH6 AD1 3 SWITCH7 AC6 4 SWITCH8 AC7 1 SWITCH9 AM1 2 SWITCH10 AM2 3 SWITCH11 AE1 4 SWITCH12 AE2 20 LatticeECP3 I/O Bank (Voltage) Bank 6 (1.8V) LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Push-button Switches (SW6, SW7, SW8, SW9 and SW10) Five push-buttons can also be used to provide inputs that require pulses. There are de-bouncers between the push-buttons and the LatticeECP3 to remove the glitches of the push-button signals. When pressing these pushbuttons, logic 0 will be sent to the connected LatticeECP3 pins. Table 30 shows the corresponding pin connections between the push-buttons and the LatticeECP3 pins. Table 30. Push-button Switch Connections Signal Switch # LatticeECP3 Pin # LatticeECP3 I/O Bank (Voltage) GSRN SW6 J20 Bank 1 (2.5V) PB4 SW7 P2 PB3 SW8 P1 PB2 SW9 U5 PB1 SW10 U4 Bank 7 (1.8V) Discrete LEDs (D10~D17, D22~D24, and D26) There are 12 discrete LEDs for use as status indicators. These 12 LEDs are divided into three groups, (D10, D11, D12, D13), (D14, D15, D16, D17) and (D22, D23, D24, D26). Each group has four LEDs and each LED is in a different color. Table 31 shows the pin connections and colors of these LEDs. Table 31. Discrete LED Connections Signal LED # LatticeECP3 Pin # ECP3 I/O Bank (Voltage) Color LED12 D10 AA31 Blue LED11 D11 AN34 Green LED10 D12 AN33 LED9 D13 AP33 LED8 D14 AP32 Blue LED7 D15 AL32 Green LED6 D16 AK32 Orange LED5 D17 N32 Red LED4 D22 N31 LED3 D23 T29 Orange Bank 3 (2.5V) Red Blue Bank 2 (2.5V) Green LED2 D24 T28 Orange LED1 D26 T27 Red 21 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor 16-Segment LED Display (D30) The LatticeECP3 general-purpose I/O pins are connected to a 16-segment display, as shown in Table 32. These pins can be driven low to illuminate the display segments. Table 32. 16-Segment LED Display Connections Segment LatticeECP3 Pin A H20 B A18 C G18 D D18 DP B18 E L19 F C19 G J19 H K19 K G19 M H19 N K20 P F19 R H18 S J18 T D19 U E18 A H B K M N U G P T S F C R E D DP Logic Analyzer Connector and Test Points For debugging purposes, all unused LatticeECP3 I/Os are connected to connectors/headers for debugging a design using test equipment such as logic analyzers or scopes. Logic Analyzer Connector An on-board Mictor connector is connected to many LatticeECP3 I/Os to make it easy to use a logic analyzer for debugging the FPGA design. The Mictor connector pins are connected to different I/O banks with different Vccio voltages. Users may need to configure the threshold voltage of the logic analyzer pod to match the signals being monitored. Other than connecting to the Mictor connector, these LatticeECP3 pins are also connected to two standard 100-mil pitch headers for use with logic analyzers or scopes that do not support Mictor connection. Table 30 shows the LatticeECP3 pin connections to the Mictor connector and the two headers. Table 33. Logic Analyzer Connections (J29, J35 and J36) J29 Pin # Signal J35 Pin # J36 Pin # LatticeECP3 Pin # LatticeECP3 I/O Bank (Voltage) 1 — — — — — 2 — — — — — 3 — — — GND — 4 — — — — — 5 LA1 — 1 D33 6 LA2 1 — D31 7 LA3 — 2 K15 8 LA4 2 — C13 22 Bank 8 (3.3V) Bank 0 (3.3V) LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor Table 33. Logic Analyzer Connections (J29, J35 and J36) (Continued) J29 Pin # J36 Pin # LatticeECP3 Pin # Signal J35 Pin # 9 LA5 — 3 J22 10 LA6 3 — J23 11 LA7 — 4 F22 12 LA8 4 — G23 13 LA9 — 5 A24 14 LA10 5 — B24 15 LA11 — 6 H22 16 LA12 6 — H23 17 LA13 — 7 K23 18 LA14 7 — K24 19 LA15 — 8 C28 20 LA16 8 — D28 LatticeECP3 I/O Bank (Voltage) Bank 1 (2.5V) 21 LA17 — 9 G26 22 LA18 9 — AA2 23 LA19 — 10 AJ6 24 LA20 10 — AL8 25 LA21 — 11 AM5 26 LA22 11 — AM6 27 LA23 — 12 AN6 28 LA24 12 — AL7 29 LA25 — 13 AM4 30 LA26 13 — AP5 31 LA27 — 14 AP6 32 LA28 14 — — — Bank 6 (1.8V) 33 LA29 — 15 — — 34 LA30 15 — — — 35 LA31 — 16 — — 36 LA32 16 — — — 37 LA33 — 17 — — 38 LA34 17 — — — Ordering Information Description LatticeECP3 Video Protocol Board Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) LFE3-95E-V-EVN Known Issues The 50 ohm pull-up resistors are required and should be placed as close as possible to the LatticeECP3’s TRLVDS input pins for receiving the DVI’s TMDS signals. These resistors are missing in the initial PCB design. With these resistors soldered on the opposite side of the DVI Rx connector (J16) to pull the input signals up to 3.3V, the DVI video with 1024x768 at both 60Hz and 75Hz frame rates has been tested and the DVI’s TMDS video data can be received properly through the TRLVDS pins. In this case, the DVI clock speed is running at 78 MHz and the input 23 LatticeECP3 Video Protocol Board – Revision B User’s Guide Lattice Semiconductor data rate is 780 Mbps. If these resistors are placed as close as possible to the LatticeECP3’s TRLVDS pins, significant improvement in the Rx bandwidth is expected. These resistors will be added to future revisions of this PCB. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version February 2009 01.0 Initial release. Change Summary July 2009 01.1 Updated pinout information. September 2009 01.2 Added Known Issue text section. March 2010 01.3 Added references to revision B. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 25 A B C D (Sheet 4) (Sheet 3) 5 (Sheet 5) 3 2 Bank6 4 3 (Sheet 13) Quad A (Sheet 7) SerDes (1156fpBGA) (Sheet 15, Sheet 16) Quad B (Sheet 8) ECP3 FPGA SDI Cable Drivers & Cable Equalizers (Sheet 7) (Sheet 14) Bank7 (Sheet 12) (Sheet 7) DisplayPort Quad C (Sheet 11) Bank3 (Sheet 11) Bank2 (Sheet 6) 2 Push Buttons & 16-Seg LED Bank8 Bank1 (Sheet 12) Bank0 (Sheet 11) TI ADC (Sheet 10) (Sheet 9) RS232 (Sheet 8) (Sheet 9) LCD SDI Rx Reference Clock & Tx Reference Clock PCIe x4 SDI Reference Clock Control (Sheet 8) DDR2 Memory (Sheet 12) Logic Analyzer Probe (Sheet 10) DVI Other Devices Power Management FPGA Power 4 (Sheet 7) Mezzanine Connector (Sheet 12) LED (Sheet 10) Date: Size C Title Channel-Link (Sheet 10) RJ45 Tx/Rx (Sheet 10) Friday, June 12, 2009 1 Sheet 1 of 16 ECP3 Video Protocol Board Schematic Project 1 B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 Block Diagram Camera-Link Rx (Sheet 11) Clocks (Sheet 12) Switches (Sheet 6) FPGA Config ECP3 Video Protocol Board Power Generation 5 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Appendix A. Schematic Figure 10. Block Diagram 26 4 3 2 Date: Size C Friday, June 12, 2009 1 Sheet 2 of 16 ECP3 Video Protocol Board Schematic Project Assembly Drawing B Rev A A 5 Title B B Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 1 C 2 C 3 D 4 D 5 Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 11. Assembly Drawing A B C 5_0V 1 SENSE U12 [4] 2_5_TRIM [4] R120 10K [4] 5 GP13 GP15 C324 0.01uF S1 S2 S3 G Q28 1 2 3 4 NTMS4503NR2G SOIC-8 D4 D3 D2 D1 + C264 100uF, Tant EIA3528 2_5V 2.5V + R176 169, 1% R178 390, 1% C316 22uF, X5R, 6.3V 0805 3_3V_SDI_DE 5_0V U4 NS C64 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 1 BYPASS SHDN 8 2 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 4 fz = 1 / (2*3.1416*390*0.01uF) = 40KHz fz is within the recommanded 20KHz to 100KHz range Vout = 1 + (390/169) = 3.3078V C56 22uF, X5R, 6.3V 0805 1 SERDES_PWR_EN C418 330uF, Tant 3_3V 3.3V GP2 GP7 GP3 GP12 GP17 GP16 Vout = 1.21 * ( 1 + 191/180 ) + 0.000003 * 191 = 2.4945V C266 33uF, Tant 0805 F1 FUSEBLOCK W/3A FUSE SMD 0154003.DR C415 0.01uF 8 7 6 5 + C416 10uF, Tant 0805 GP22 GP1 GP18 GP8 J39 HEADER 2x1 GP11 GP4 GP5 GP24 3.3V for SD/HD/3G-SDI Cable Drivers and Equalizers R114 180, 1% + + C419 10uF, Tant 0805 3_3V_GATE R115 191, 1% R328 0R fz = 1 / (2*3.1416*390*0.01uF) = 40KHz fz is within the recommanded 20KHz to 100KHz range Vout = 1 + (390/169) = 3.3078V GP9 GP14 GP6 GP19 GP21 2 1 GP20 F7 3_3VIN FUSEBLOCK W/10A FUSE SMD 0154010.DR SERDES_PWR_EN LT LT1764AEQ#PBF 1 2 3 4 5 5 6 3_3VIN 3_3_TRIM 2_5V_EN R321 2K R325 0R SHDN IN GND6 GND OUT ADJ [4] PTH12060W VOUT U20 NS C289 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 1 BYPASS SHDN 8 2 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 6 GND1 R331OPEN 1 INHIBIT# 3 VIN ADJUST 4 2 10 MUP 9 MDWN 8 TRACK GND7 7 U18 C298 22uF, X5R, 6.3V 0805 12_0V 1 2 GND9 9 1 2 U17 GND1 VIN C286 330uF, Tant U14 1_8_TRIM LT LT1764AEQ#PBF SHDN IN GND6 GND OUT ADJ [4] C34 0.01uF R17 169, 1% R16 390, 1% SENSE 3_3VIN C41 22uF, X5R, 6.3V 0805 3_3V_SDI_CLK VOUT 3 R124 10K 0R 1 + + C413 330uF, Tant C268 33uF, Tant 0805 F2 FUSEBLOCK W/3A FUSE SMD 0154003.DR + 1_8V C267 100uF, Tant EIA3528 1.8V Voltage adjustment range : 1.0V to 1.2V Turn clockwise to increase the voltage SERDES_PWR_EN U26 NS C380 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 1 BYPASS SHDN 8 2 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 fz = 1 / (2*3.1416*113*0.01uF) = 140KHz fz is within the recommanded 50KHz to 200KHz range Vout = 1 + (113/560) = 1.2018V C378 22uF, X5R, 6.3V 0805 3_3VIN R121 390, 1% R122 191, 1% 2 VR4 20K Copal ST32ETB203 + C412 10uF, Tant 0805 C368 0.01uF [4] [4] R190 560, 1% R188 113, 1% 2 6 [4] 1 2 3 4 5 PTH12060W VCCA_TRIM SENSE [4] R132 390, 1% C285 33uF, Tant 0805 Date: Size C Title C367 0.01uF Power Generation C282 100uF, Tant EIA3528 R191 226, 1% R189 113, 1% C373 22uF, X5R, 6.3V 0805 1_5V_IO 1.5V for SerDes I/O Buffer Friday, June 12, 2009 1 Sheet 3 of 16 ECP3 Video Protocol Board Schematic Project + 1_2V_A B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 fz = 1 / (2*3.1416*113*0.01uF) = 140KHz fz is within the recommanded 50KHz to 200KHz range Vout = 1 + (113/226) = 1.5000V C273 100uF, Tant EIA3528 Vout = 1.21 * ( 1 + 0/390 ) + 0.000003 * 0 = 1.21V + + 5_0V 1.2V J15 Power Jack Male Power Jack 2.1mm 2.5A 16V PJ-002A 12_0VIN 1 3 5.0V 1 F4 FUSEBLOCK W/3A FUSE SMD 0154003.DR + C422 10uF, Tant 0805 SERDES_PWR_EN R340 0R F3 FUSEBLOCK W/10A FUSE SMD 0154010.DR D7 SCHOTTKY Vishay V12P10-E3/87A F5 FUSEBLOCK W/10A FUSE SMD 0154010.DR U27 NS C381 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 2 1 BYPASS SHDN 8 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 C377 22uF, X5R, 6.3V 0805 1 R134 10K 5_0_TRIM 5 6 12_0V VOUT 3_3VIN R342 280 R341 0R 3_3VIN LT LT1764AEQ#PBF SHDN IN GND6 GND OUT ADJ U16 SERDES_PWR_EN C374 22uF, X5R, 6.3V 0805 1_2V_IO OPEN GND1 VIN 5_0V_EN R339 1 2 U40 Terminal Block ED120/2DS GND +12VDC 12_0VIN POWER INPUT TB1 12_0V 2 1 12_0VIN 2 1.2V for SerDes I/O Buffer Vout = 1.21 * ( 1 + 191/390 ) + 0.000003 * 191 = 1.8032V R318 0R VCC_CORE 1.2V Core 12VIN GOOD D35 LED-SMT1206_GREEN R334 680 PCB Footprint = 1206 12_0V F6 FUSEBLOCK W/10A FUSE SMD 0154010.DR R323 OPEN R324 5 6 C421 330uF, Tant R322 12.1K 3.3V for SD/HD/3G-SDI Clocking Circuitry 6 1 2 3 4 5 + 12_0V PTH12060L 1_8V_EN VCC_TRIM [4] [4] CORE_EN [4] R326OPEN 12_0V + 12_0V INHIBIT# 3 D 2 1 1 2 ADJUST 4 GP23 1 2 1 2 GND9 9 10 MUP 9 MDWN 8 TRACK GND7 7 GP10 2 1 1 3 Distributed around the board as GND reference for test equipments. 1 2 1 2 GND9 9 INHIBIT# 3 GND Vias (40-mil) for soldering pins. 2 1 ADJUST 4 3 1 2 10 MUP 9 MDWN 8 TRACK GND7 7 1 2 4 2 1 GND9 9 2 5 1 27 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 12. Power Generation A B C + R262 1K R261 1K BAV74LT1 Monolithic Dual Switching Diode 3_3VIN WP VCC A2 GND SCL SDA 8 7 6 5 [6] [6] TP22 TP21 TP20 TP17 R263 R285 5 OPEN TRIM1 TRIM2 R269 OPEN OPEN R307 R308 C397 2200pF 226, 1% C400 0.1uF 2_5V VMON1+ VMON1GS VMON2+ VMON2GS VMON3+ VMON3GS VMON4+ VMON4GS VMON5+ VMON5GS VMON6+ VMON6GS VMON7+ VMON7GS VMON8+ VMON8GS VMON9+ VMON9GS VMON10+ VMON10GS VMON11+ VMON11GS VMON12+ VMON12GS OPEN OPEN OPEN OPEN R274 R277 TRIM5 TRIM4 R282 R284 TRIM3 OPEN OPEN OPEN OPEN R281 R276 R273 R267 50 48 3_3V TRIM6 52 51 1_2V_A OPEN 54 53 47 46 56 55 5_0V 62 61 64 63 66 65 68 67 70 69 72 71 GSRN DONE_ECP3 1_8V VCC_CORE R258 INITN_ECP3 C278 0.01uF [6,11] [6] [6] C277 0.1uF TEMP_GND TEMP 3_3V EEPROM 4 3 A0 A1 58 57 R265 C398 0.1uF C399 0.1uF 1 2 C275 0.01uF D25 BAV74/SOT C271 0.1uF 2_5V 2_5V 2(Anode) 1(Anode) Top View SOT-23 3(Cathode) R260 3K 12_0VIN 0R 1 R272 C276 1uF, X5R, 6.3V R259 3K 12_0V C269 22uF, Tant 0805 3_3VIN 0R 3 1 R266 1 2 2 1 2 1 2 D 1 2 1 2 0R 0R TP36 TP32 TP37 C396 0.1uF 3 2 1 DXN DXP VCC U34 MAX6692 SDA SCLK ALERT 3_3VIN OVERT 4 TP15 7 8 4 6 TP16 U36 POWR1220AT8 TQFP100 Lattice ispPAC 3_3VIN TP26 TP 4 [9,13,14] [9,13,14] PLDCLK TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 HVOUT4 HVOUT3 HVOUT2 HVOUT1 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 SMBA/OUT5 PLDCLK TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 73 74 75 79 80 82 83 84 95 HVOUT4 HVOUT3 HVOUT2 HVOUT1 40 42 85 86 R292 10K R315 PWR_GOOD_VCCA PWR_GOOD_VCC PWR_GOOD_3_3V PWR_GOOD_2_5V PWR_GOOD_5_0V PWR_GOOD_1_8V PAC_OUT9 PAC_OUT8 PAC_OUT7 PAC_OUT6 PAC_OUT5 1 2_5V_EN [6] [6] 100 3 8 7 6 5 1 1 R264 OPEN R268 OPEN R275 OPEN R278 OPEN R283 OPEN R286 OPEN TP19 TP18 3_3V_GATE R125 10K 3_3VIN R131 10K 10K OPEN EXB28V102JV 3_3VIN R291 R295 1K [3] 2_5_TRIM 1_8_TRIM 5_0_TRIM VCCA_TRIM 3_3_TRIM VCC_TRIM [3] [3] [3] [3] [3] [3] Q8 2N2222 MMBT2222ALT1G 1_8V_EN Q9 2N2222 MMBT2222ALT1G 5_0V_EN 3_3VIN 3_3V [3] [3] ispPAC PCIe Edge 12V Wall Adapter 12V Input Terminal 12V INPUT TP24 TP23 TP28 TP35 TP39 TP34 TP38 TP33 [3] RN26 1 2 3 4 3 Q7 2N2222 MMBT2222ALT1G TMS_PAC TCK_PAC TDO_PAC [6] TDI_PAC [6] TCK_PAC TDO_PAC TDI_PAC TMS_PAC 25 24 23 21 20 19 18 17 16 15 14 12 11 10 9 8 R123 10K 3_3VIN TDO_PAC TDI_PAC ATDI_PAC TMS_PAC TCK_PAC TDISEL_PAC I2C_SDA I2C_SCL NC1 NC2 NC3 NC4 NC5 26 27 29 35 41 U35 EEPROM Microchip 24AA1025-I/SM 3_3VIN VCCPROG 39 2 PAC_VMON9 PAC_VMON10 PAC_VMON11 PAC_VMON12 10K R290 5 PAC_IN3 PAC_IN4 PAC_IN5 5 97 1 2 4 6 7 GND 5 10K R298 VCCD13 VCCD38 VCCD94 13 38 94 3 2 TP27 TP25 PAC_VPS0 PAC_VPS1 89 90 VPS0 VPS1 PAC_MCLK 96 MCLK GNDD3 GNDD22 GNDD36 GNDD43 GNDD88 GNDD98 3 22 36 43 88 98 1 2 93 92 SDA SCL PAC_RESETn 91 RESETb VCCA 60 VCCINP IN1 IN2 IN3 IN4 IN5 IN6 44 59 100 99 GNDA87 GNDA45 3 2 3 2 RES1 RES2 NC12 NC11 87 45 PWR_GOOD_VCC VCC CORE PWR_GOOD_1_8V 1.8V PWR_GOOD_5_0V 5.0V PWR_GOOD_2_5V 2.5V PWR_GOOD_3_3V 3.3V CORE_EN 2 2 D27 D28 D29 D31 D32 D33 [3] LED-SMT1206_GREEN LED-SMT1206_GREEN LED-SMT1206_GREEN LED-SMT1206_GREEN LED-SMT1206_GREEN R271 150 R280 150 R288 150 R297 150 R306 150 R314 150 Friday, June 12, 2009 1 Sheet 4 of 16 ECP3 Video Protocol Board Schematic Project B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 PWR_GOOD_1_8V PWR_GOOD_5_0V PWR_GOOD_2_5V PWR_GOOD_3_3V PWR_GOOD_VCC Power Management R270 10K R279 10K R287 10K R296 10K R305 10K [3] PWR_GOOD_VCCA Q11 2N2222 MMBT2222ALT1G R313 10K Date: Size C Title 3_3VIN 1 R135 10K SERDES_PWR_EN 1_2V_IO, SerDes I/O Buffer (+1.2V, 0.8A) LDO LP3878 3_3VIN 1_5V_IO, SerDes I/O Buffer (+1.5V, 0.8A) 1_2V_A, SerDes (+1.2V, 3A) LDO LT1764 3_3V_SDI_CLK, SDI Clock (+3.3V, 0.8A) 3_3V_SDI_DE, SerDes VCCAUX Drivers/Equalizers (+3.3V, 0.8A) DP_TX_PWR_OUT, DisplayPort Tx (+3.3V, 0.8A) DP_RX_PWR_OUT, DisplayPort Rx (+3.3V, 0.8A) 1 LDO LP3878 1_8V, DDR2 (+1.8V, 3A) 2_5V, LVDS (+2.5V, 3A) 3_3V, (+3.3V, 3.2A) LDO LP3878 LDO LP3878 LDO LP3878 LDO LP3878 LDO LT1764 LDO LT1764 MOSFET NTR4501N 3_3VIN, (+3.3V, 10A) VCC_CORE, (+1.2v, 10A) 5_0V, LCD (+5V,10A) LED-SMT1206_GREEN Q10 2N2222 MMBT2222ALT1G VCCA 1 PWR_GOOD_VCCA R133 10K 3_3VIN POL PTH12060W POL PTH12060L POL PTH12060W 3 2 33 34 31 30 28 37 32 VCCJ TDO TDI ATDI TMS TCK TDISEL NC6 NC7 NC8 NC9 NC10 49 76 77 78 81 3 28 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 13. Power Management A B C D M12 M23 Y3 Y29 Y24 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y11 W21 W20 W19 W18 W17 W16 W15 W14 W12 V6 V32 V25 V21 V20 V19 V18 V17 V16 V15 V14 V10 U3 U29 U25 U21 U20 U19 U18 U17 U16 U15 U14 U10 T23 T21 T20 T19 T18 T17 T16 T15 T14 T12 R6 R32 R24 R21 R20 R19 R18 R17 R16 R15 R14 R11 P3 P29 P24 P21 P20 P19 P18 P17 P16 P15 P14 P11 M6 M32 M24 M19 M16 M11 L3 L29 L24 L23 L21 L20 L15 L14 L12 L11 K18 K17 J5 J33 J30 J2 H8 H27 F23 F20 F17 F14 F11 E9 E5 E33 E30 E26 E2 AP10 AP11 AP12 AP13 U30L GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130 GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160 GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 5 ECP3-95 GND401 GND403 GND402 GND404 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97 GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 VSS AC12 AC23 A1 A34 AA11 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA24 AA32 AA6 AC11 AC16 AC19 AC24 AC29 AC3 AD11 AD12 AD14 AD15 AD20 AD21 AD23 AD24 AD32 AD6 AE10 AE11 AE17 AE18 AE24 AE25 AF10 AF2 AF25 AF30 AF33 AF5 AG10 AG25 AG27 AG8 AH10 AH11 AH14 AH17 AH18 AH21 AH24 AH25 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ9 AK2 AK26 AK30 AK33 AK5 AK9 AL26 AL9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM9 AN26 AN30 AN5 AN9 AP1 AP26 AP34 AP9 B26 B30 B5 B9 C12 C15 C18 C21 C24 4 C201 0.1uF VCCPLL C152 0.1uF 3_3V C148 0.1uF 2_5V C151 0.1uF 1_8V C175 0.01uF C233 0.1uF C230 0.1uF C214 0.1uF C188 1000pF C145 0.01uF C150 0.1uF C222 0.01uF C167 1000pF C166 0.01uF C189 0.01uF C153 0.01uF 4 C234 1000pF C220 0.01uF C187 1000pF C177 0.01uF C163 1000pF C226 0.01uF ALL CAPS PLACED UNDER BGA 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 NC164 NC165 NC166 NC167 NC159 NC158 NC157 NC156 B27 B29 B8 NC175 NC176 NC177 AN13 AN12 AN11 AN10 C26 C27 C7 C8 C9 NC181 NC182 NC183 NC184 NC185 NC145 NC144 NC143 NC142 AL13 AL12 AL11 AL10 E14 NC195 D26 D27 D7 D8 D9 NC135 NC134 NC133 NC132 AK13 AK12 AK11 AK10 NC129 NC128 NC127 AJ32 AJ30 AJ29 NC189 NC190 NC191 NC192 NC193 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C181 1000pF C223 1000pF C154 1000pF 1 5 NC123 AH8 E25 E27 E28 E29 E6 E7 E8 NC121 NC120 NC119 NC118 NC117 NC116 NC115 NC114 NC113 AH6 AH5 AH4 AH34 AH32 AH31 AH30 AH3 AH29 NC200 NC201 NC202 NC203 NC204 NC205 NC206 3 C217 1000pF 3 VCCA1 VCCA2 VCCA3 VCCA4 VCCA5 VCCA6 VCCA7 VCCA8 VCCA9 VCCA10 VCCA11 VCCA12 VCCA13 VCCA14 VCCA15 VCCA16 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCPLL_L_1 VCCPLL_L_2 VCCPLL_R_1 VCCPLL_R_2 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 C232 22uF, Tant 0805 VCC CORE ECP3-95 U30I + C237 1uF, X5R, 6.3V ECP3-95 OTHER SUPPLIES U30J AA13 AA22 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P13 P22 R13 R22 U13 U22 V13 V22 Y13 Y22 AD16 AD18 AE19 AC17 AC18 AD13 AE16 AD17 AC22 AE23 AE12 AD22 AE22 AC13 AE13 AD19 Y23 AA23 P12 AC20 AC14 M20 AA12 Y12 R12 AC15 AC21 M21 R23 M15 M14 P23 T13 W13 T22 W22 2 VCC_CORE 3_3V 1_2V_A C146 0.01uF C261 1uF, X5R, 6.3V C228 1uF, X5R, 6.3V C133 0.1uF C225 0.1uF C131 0.01uF + C262 22uF, Tant 0805 BLM21AG601SN1D FB40 3_3V C227 0.1uF C134 0.1uF C224 0.1uF + C219 0.1uF C141 1uF, X5R, 6.3V C204 0.01uF C127 22uF, Tant 0805 C208 1000pF VCC_CORE C185 0.01uF VCC_CORE C184 0.1uF C209 1000pF C197 0.01uF C168 0.1uF 2 C211 1000pF C199 0.01uF C164 0.1uF C205 1000pF C196 0.01uF C156 0.1uF C198 1000pF C171 0.01uF C157 0.1uF C212 1000pF C195 0.01uF C158 0.1uF C218 1000pF C170 0.01uF C162 0.1uF 1 C210 1000pF C207 1000pF C229 0.01uF U30K ECP3-95 Friday, June 12, 2009 1 Sheet 5 of 16 B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 C173 1000pF C213 0.01uF C206 0.01uF NO CONNECT ECP3 Video Protocol Board Schematic Project C215 0.01uF C161 0.1uF FPGA Power C182 1000pF C169 0.01uF C160 0.1uF Date: Size C Title C200 1000pF C172 0.01uF C159 0.1uF ALL CAPS PLACED UNDER BGA C260 0.1uF C144 0.01uF VCCPLL C240 22uF, Tant 0805 VCC_CORE + 3_3V C149 0.1uF 1_2V_A ALL CAPS PLACED UNDER BGA NC109 NC108 NC107 NC106 AH2 AH13 AH12 AH1 F24 F25 F26 F27 F28 F29 F4 F5 F6 F7 F8 F9 G10 NC104 NC103 NC102 NC101 NC100 NC99 NC98 NC97 NC96 NC95 NC94 NC93 AG7 AG6 AG5 AG4 AG34 AG33 AG32 AG31 AG30 AG3 AG29 AG28 NC210 NC211 NC212 NC213 NC214 NC215 NC216 NC217 NC218 NC219 NC220 NC221 NC222 NC91 NC90 NC89 NC88 NC87 AG2 AG13 AG12 AG11 AG1 G24 G27 G28 G29 NC85 NC84 NC83 NC82 NC81 AF8 AF7 AF6 AF4 AF34 NC226 NC227 NC228 NC229 NC78 NC77 NC76 NC75 AF3 AF29 AF28 AF27 1 NC73 NC72 NC71 NC70 AF13 AF12 AF11 AF1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 NC68 NC67 NC66 NC65 AE8 AE7 AE6 AE5 G6 G7 G8 G9 H10 H11 H12 H24 H28 H29 H30 H31 H32 NC63 NC62 AE34 AE33 NC232 NC233 NC234 NC235 NC236 NC237 NC238 NC239 NC240 NC241 NC242 NC243 NC244 NC56 NC55 AE28 AE27 H6 H7 H9 J10 J11 NC52 NC51 AE15 AE14 NC247 NC248 NC249 NC250 NC251 NC47 NC46 AD7 AD5 1 2 1 2 1 2 1 2 1 2 J24 J25 J26 J27 J28 J29 J31 J32 J4 J6 J7 J8 J9 K1 K11 NC44 NC43 NC42 NC41 AD34 AD33 AD31 AD30 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 NC254 NC255 NC256 NC257 NC258 NC259 NC260 NC261 NC262 NC263 NC264 NC265 NC266 NC267 NC268 NC39 NC38 NC37 NC36 NC35 AD29 AD28 AD27 AD26 AD25 2 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 AC28 AC27 AC26 AC25 AC2 AC10 AC1 AB8 AB7 AB6 AB4 AB32 AB31 AB3 K2 K25 K26 K27 K28 K29 K3 K30 K31 K32 K33 K34 K4 K5 K6 K7 NC33 NC32 NC31 NC30 AC9 AC8 AC5 AC4 2 NC11 NC10 NC9 NC8 NC7 1 2 1 2 1 2 1 2 AB27 AB26 AB25 AB10 AA9 1 2 1 2 1 2 1 2 1 2 1 NC271 NC272 NC273 NC274 NC275 NC276 NC277 NC278 NC279 NC280 NC281 NC282 NC283 NC284 NC285 NC286 L1 L10 L2 L25 L26 L27 L28 L30 L31 L32 L33 L34 L4 L5 L6 L7 L8 L9 M1 M2 M25 M26 M27 M28 M29 M3 M30 M31 M33 M34 M4 M7 M8 M9 N9 NC289 NC290 NC291 NC292 NC293 NC294 NC295 NC296 NC297 NC298 NC299 NC300 NC301 NC302 NC303 NC304 NC305 NC306 NC307 NC308 NC309 NC310 NC311 NC312 NC313 NC314 NC315 NC316 NC317 NC318 NC319 NC320 NC321 NC322 NC323 1 2 1 2 1 2 NC401 NC402 NC403 NC404 NC405 NC406 NC407 NC408 NC409 1 1 2 G14 G15 F15 E16 F16 H21 G22 AJ1 AK1 2 29 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 14. FPGA Power A B C D FPGA_CSSPI0N_DI FPGA_D7 SPI0_Q FLASH_DIS R226 10K 3(D) 2(S) D19 LED-SMT1206_RED Q22 MOSFET N GSD 1 BSS138LT1G 4 2 4 2 11 8 4Y 3Y 5 74LVC125 4A 4OE_N 3A 3OE_N U11B 12 13 9 10 Tactile Switch TL3301SPF160QG 3 1 SW5 PROGRAMN Tactile Switch TL3301SPF160QG 3 1 SW6 FPGA GSRN 6 3 2Y 1Y R116 4.7K R118 4.7K R239 10K D18 LED-SMT1206_GREEN 3_3V INITN_ECP3 74LVC125 2A 2OE_N 1A 1OE_N U11A 1 5 4 2 3 1 C265 0.1uF 3_3V DONE_ECP3 R223 10K PROGRAMN_ECP3 R107 100 4 6 U13 MAX6817 GSRN [4,11] D21 LED-SMT1206_RED R244 150 3_3V OUT2 R225 10K D20 LED-SMT1206_RED R242 150 3_3V SPI_CLK FPGA_SISPI OUT1 R111 100 IN2 IN1 U32 Flash STMicroelectronics M25P64-VMF6TP HOLD# CK 16 VCC D 15 DU1 DU8 14 DU2 DU7 13 DU6 12 DU3 DU4 DU5 11 S# VSS 10 W# 9 Q DONE indicator will light when configuration is successfully completed R241 150 PROGRAMN_ECP3 GSRN (J20) 1 2 3 4 5 6 7 8 INITN indicator will light if an error occurs during configuration programming PROGRAMN & GSRN Pushbuttons 1(G) Top View SOT-23 R240 150 3_3V CONFIG Status LEDs R214 10K 3 SPI FLASH 5 VCC C389 0.01uF R119 OPEN C390 0.1uF 4 ECP3-95 R110 10K R103 10K TDI TCK TMS TDO VCCJ E1 D1 D2 C1 K10 P25 N25 F33 F32 J34 H34 G32 G33 H33 G34 E32 F34 E31 E34 D34 F31 G30 D33 G31 C34 C33 B34 B33 F30 D32 C31 D31 C32 B32 D29 D30 A33 A32 W23 AN4 AP4 R98 R97 R96 CFG0 CFG1 CFG2 CFG0 X 1(OFF) X X 1(OFF) 0(ON) 1(OFF) 0(ON) 0(ON) 1(OFF) 1(OFF) 0(ON) CFG1 10K 10K 10K ON TDO_ECP3 TMS_ECP3 TCK_ECP3 TDI_ECP3 TDI_ECP3 TCK_ECP3 TMS_ECP3 TDO_ECP3 3_3V LA2 LA1 SPI0_Q 8 7 6 5 EXB28V102JV ispJTAG 3 Slave Parallel Slave Serial SPIm SPI Flash C onfi gu ration Mode 3_3V [7] [7] DP_RX_HPD_OUT [8,9,11,12] DP_TX_HPD_OUT [11] LA[1..33] SW2 SW DIP-3 CTS 194-3MST 1K 3_3V 3 10K, 1% TI_ADC[0..4] R59 [4] RN12 1 2 3 4 TEMP [4] TEMP_GND TI_ADC0 TI_ADC1 TI_ADC2 TI_ADC3 TI_ADC4 FPGA_XRES DONE_ECP3 FPGA_CCLK INITN_ECP3 PROGRAMN_ECP3 CFG0 CFG1 CFG2 FPGA_SISPI FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 SPI_CLK FPGA_WRITEN FPGA_CSSPI1N_DOUT FPGA_CSSPI0N_DI FPGA_CSN FPGA_CS1N 1(OFF) 0(ON) 0(ON) CFG2 3_3V CONFIG CFG Switches R113 10K 3_3V BANK 8/CONFIG VCCIO8_1 VCCIO8_2 PR16B/BUSY/SISPI/AVDN PR16A/D7/SPID0 PR14B/D6/SPID1 PR14A/D5 PR13B/D4/SO PR13A/D3/SI PR11B/D2 PR11A/D1 PR10B/D0/SPIFASTN PR8B/MCLK PR10A/WRITEN PR8A/DOUT/CSON/CSSPI1N PR5B/DI/CSSPI0N/CEN PR7B/CSN/SN/CONT1N/OEN PR7A/CS1N/HOLD/CONT2N/RDY PR5A/HFP DONE CCLK INITN PROGRAMN CFG0 CFG1 CFG2 PT145B/XD15 PT145A/XD14 PT143B/XD13 PT143A/XD12 PT142B/XD11 PT142A/XD10 PT140B/XD9 PT140A/XD8 XRES TEMPSENSE TEMPVSS U30G ECP3 Configuration I/Os INITN_ECP3 3_3V PROGRAMN_ECP3 3_3V 4 DONE_ECP3 5 GND 2 R117 OPEN 2 14 VCC GND 7 6 5 4 30 1 2 3 1 2 1 2 3 [4] [4] TCK_PAC TCK_XO TCK_ECP3 TMS_PAC TMS_XO INITN_ECP3 DONE_ECP3 [4] [14] [4] [14] TMS_ECP3 10K R112 R109 R108 R245 R106 R105 R243 R104 R102 J32 J33 J34 J32 J33 J34 J32 J33 J34 J32 J33 J34 FPGA_CS1N R101 10K PROGRAMN_ECP3 HEADER 3x1 J31 SPIFASTN R100 3_3V HEADER 2x1 J30 OPEN OPEN 0R 0R 0R 0R 0R 0R 0R TDO TDI TDO TDI TDO TDI TDO TDI 1 2 3 2 ECP3 ECP3 ECP3 ECP3 HEADER 3x1 J27 FPGA_D0 2 PAC PAC PAC PAC 1 2 3 4 TMS TCK TDO TDI PROGRAMN HEADER 4x1 J32 DONE INITN XO XO XO XO FPGA_CSN R99 10K TDO_PAC TDI_ECP3 [4] TDO TDI TDO TDI TDO TDI 1 2 3 4 VCC INITN GND DONE TCK TMS NC ispEN_N TDI TDO 7 1 TDI_XO XO XO XO [14] PAC PAC PAC 1 2 3 4 TMS GND TCK DONE INITn +3.3V TDO TDI PROGRAMn HEADER 4x1 J34 FPGA_WRITEN CFG0 CFG1 CFG2 Date: Size C Title FPGA Configuration Friday, June 12, 2009 1 Sheet 6 of 16 ECP3 Video Protocol Board Schematic Project [4] [14] B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 (From ispVM Download Cable) TDI_PAC TDO_XO sysCONFIG Connector FPGA_D6 3_3V INITN_ECP3 PROGRAMN_ECP3 C263 0.1uF 3_3VIN TDO_ECP3 ECP3 ECP3 ECP3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 JTAG CONNECTOR HEADER 10x1 2 3 4 5 6 8 9 10 J28 J37 HEADER 17x2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 HEADER 4x1 J33 J32 J33 J34 J32 J33 J34 J32 J33 J34 FPGA_CCLK FPGA_SISPI FPGA_CSSPI0N_DI FPGA_CSSPI1N_DOUT DONE_ECP3 FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 FPGA_CSN FPGA_CS1N 3_3V 1 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 15. FPGA Configuration A B C D ECP3-95 AL21 AK21 AL20 AK20 AL19 AK19 AL18 AK18 AP21 AN21 AP20 AN20 AP19 AN19 AP18 AN18 AH19 AH20 AF21 AF20 AF19 AF18 AG21 AG20 AG19 AG18 AL17 AK17 AL16 AK16 AL15 AK15 AL14 AK14 AP17 AN17 AP16 AN16 AP15 AN15 AP14 AN14 AH15 AH16 AF17 AF16 AF15 AF14 AG17 AG16 AG15 AG14 AL25 AK25 AL24 AK24 AL23 AK23 AL22 AK22 AP25 AN25 AP24 AN24 AP23 AN23 AP22 AN22 AH22 AH23 AF24 AF23 AF22 AE20 AG24 AG23 AG22 AE21 PCSA_HDOUTP0 PCSA_HDOUTN0 PCSA_HDOUTP1 PCSA_HDOUTN1 PCSA_HDINP0 PCSA_HDINN0 PCSA_HDINP1 PCSA_HDINN1 PCSC_VCCOB PCSC_VCCIB MZ_HDINP0 MZ_HDINN0 MZ_HDINP1 MZ_HDINN1 MZ_HDINP2 MZ_HDINN2 MZ_HDINP3 MZ_HDINN3 MZ_HDOUTP0 MZ_HDOUTN0 MZ_HDOUTP1 MZ_HDOUTN1 MZ_HDOUTP2 MZ_HDOUTN2 MZ_HDOUTP3 MZ_HDOUTN3 MZ_REFCLKP MZ_REFCLKN PCSB_VCCOB PCSB_VCCIB x4_PETp0 x4_PETn0 x4_PETp1 x4_PETn1 x4_PETp2 x4_PETn2 x4_PETp3 x4_PETn3 PCSB_HDOUTP0 PCSB_HDOUTN0 PCSB_HDOUTP1 PCSB_HDOUTN1 PCSB_HDOUTP2 PCSB_HDOUTN2 PCSB_HDOUTP3 PCSB_HDOUTN3 x4_PCIE_CLKP x4_PCIE_CLKN PCSA_VCCOB PCSA_VCCIB PCSA_HDOUTP2 PCSA_HDOUTN2 PCSA_HDOUTP3 PCSA_HDOUTN3 PCSA_REFCLKP PCSA_REFCLKN PCSA_HDINP2 PCSA_HDINN2 PCSA_HDINP3 PCSA_HDINN3 [13] [13] [13] [13] [13] [13] [13] [13] 1 2 3 1 2 3 1 2 3 1 2 3 HEADER 3x1 J18 HEADER 3x1 J22 HEADER 3x1 C363 0.01uF R50 OPEN SI570_SCL [11] 5 SI570_SDA C362 0.1uF [11] C364 0.01uF PCSA_REFCLKN PCSA_REFCLKP TP14 [8,11] SI570_EN 6 7 8 1 2 VDD SDA SCL NC OE + GND CLK+ CLK- 3 4 5 [16] [16] C97 22uF, Tant 0805 C103 22uF, Tant 0805 TX_GC4915_CLKOUTN U9 Si570 Silicon Labs 570QAC000215DG SI570_CLK_N PCSA_SMA_N 0R FB34 + R350 C99 22uF, Tant 0805 C105 22uF, Tant 0805 C98 22uF, Tant 0805 C104 22uF, Tant 0805 TX_GC4915_CLKOUTP 1_5V_IO TP12 FB35 470 + BLM21AG601SN1D 1_2V_IO SI570_CLK_P 0R + BLM21AG601SN1D 1_5V_IO PCSA_SMA_P FB33 R349 1_2V_IO 1_5V_IO TP13 3_3V_SDI_CLK R48 R47 TP11 FB37 + BLM21AG601SN1D 1_2V_IO J21 1 2 3 FB32 + BLM21AG601SN1D 1_2V_IO 1_5V_IO 1_5V_IO 1 2 3 FB36 BLM21AG601SN1D 1_2V_IO 1_5V_IO BLM21AG601SN1D 1_2V_IO HEADER 3x1 J23 HEADER 3x1 J20 HEADER 3x1 J24 Quad A Reference Clock PCS/SERDES PCSA_HDINP0 PCSA_HDINN0 PCSA_HDINP1 PCSA_HDINN1 PCSA_HDINP2 PCSA_HDINN2 PCSA_HDINP3 PCSA_HDINN3 PCSA_HDOUTP0 PCSA_HDOUTN0 PCSA_HDOUTP1 PCSA_HDOUTN1 PCSA_HDOUTP2 PCSA_HDOUTN2 PCSA_HDOUTP3 PCSA_HDOUTN3 PCSA_REFCLKP PCSA_REFCLKN PCSA_VCCIB0 PCSA_VCCIB1 PCSA_VCCIB2 PCSA_VCCIB3 PCSA_VCCOB0 PCSA_VCCOB1 PCSA_VCCOB2 PCSA_VCCOB3 PCSB_HDINP0 PCSB_HDINN0 PCSB_HDINP1 PCSB_HDINN1 PCSB_HDINP2 PCSB_HDINN2 PCSB_HDINP3 PCSB_HDINN3 PCSB_HDOUTP0 PCSB_HDOUTN0 PCSB_HDOUTP1 PCSB_HDOUTN1 PCSB_HDOUTP2 PCSB_HDOUTN2 PCSB_HDOUTP3 PCSB_HDOUTN3 PCSB_REFCLKP PCSB_REFCLKN PCSB_VCCIB0 PCSB_VCCIB1 PCSB_VCCIB2 PCSB_VCCIB3 PCSB_VCCOB0 PCSB_VCCOB1 PCSB_VCCOB2 PCSB_VCCOB3 PCSC_HDINP0 PCSC_HDINN0 PCSC_HDINP1 PCSC_HDINN1 PCSC_HDINP2 PCSC_HDINN2 PCSC_HDINP3 PCSC_HDINN3 PCSC_HDOUTP0 PCSC_HDOUTN0 PCSC_HDOUTP1 PCSC_HDOUTN1 PCSC_HDOUTP2 PCSC_HDOUTN2 PCSC_HDOUTP3 PCSC_HDOUTN3 PCSC_REFCLKP PCSC_REFCLKN PCSC_VCCIB0 PCSC_VCCIB1 PCSC_VCCIB2 PCSC_VCCIB3 PCSC_VCCOB0 PCSC_VCCOB1 PCSC_VCCOB2 PCSC_VCCOB3 1 2 1 2 1 2 4 1 C115 0.01uF PCSC_VCCOB C138 0.01uF PCSC_VCCIB C118 0.01uF PCSB_VCCOB C142 0.01uF PCSB_VCCIB C112 0.01uF PCSA_VCCOB C140 0.01uF PCSA_VCCIB C124 1uF, X5R, 6.3V C110 1uF, X5R, 6.3V C122 1uF, X5R, 6.3V C132 0.1uF C116 0.1uF C137 0.1uF C120 1uF, X5R, 6.3V C119 1uF, X5R, 6.3V C117 0.1uF C111 0.1uF C135 1uF, X5R, 6.3V C130 0.1uF 1 1 J8 SMA 73391-0060 J7 SMA 73391-0060 Place under ECP3 device C121 0.1uF C136 0.1uF C114 0.1uF C128 0.1uF C123 0.1uF C125 0.1uF Quad A Reference Clock Options: (1) Gennum Clock Chips (2) Silicon Labs Si570 (3) SMA Connectors C102 1uF, X5R, 6.3V PCSC_VCCOB C108 1uF, X5R, 6.3V PCSC_VCCIB 470 C101 1uF, X5R, 6.3V PCSB_VCCOB C107 1uF, X5R, 6.3V PCSB_VCCIB C100 1uF, X5R, 6.3V PCSA_VCCOB C106 1uF, X5R, 6.3V PCSA_VCCIB 4 1 2 5 1K R358 1 2 1 2 2 1 2 1 2 1 1 2 1 2 1 2 2 1 2 1 2 1 2 3 U19 NS C308 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 1 BYPASS SHDN 8 2 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 R51 OPEN Place near ECP3 x4_PERp3 x4_PERn3 x4_PERp2 x4_PERn2 x4_PERp1 x4_PERn1 x4_PERp0 x4_PERn0 R154 169, 1% R149 390, 1% x4_PCIE_CLKN C383 0.1uF, X5R, 10V C382 0.1uF, X5R, 10V C379 0.1uF, X5R, 10V C376 0.1uF, X5R, 10V C375 0.1uF, X5R, 10V C372 0.1uF, X5R, 10V C366 0.1uF, X5R, 10V C365 0.1uF, X5R, 10V C296 0.01uF DP_TX_PWR_OUT_EN 3_3V R162 169, 1% R160 390, 1% 3 1 3 5 7 9 5_0V DW-05-08-F-D-275 2 4 6 8 10 HEADER 5X2 Samtec J17 3_3V 1_8V Mezzanine Board Connection (Quad C) 2 1 3 5 7 9 11 13 15 17 19 x4_PERp3 x4_PERn3 x4_PERp2 x4_PERn2 x4_PERp1 x4_PERn1 x4_PERp0 x4_PERn0 x4_PCIE_CLKP x4_PCIE_CLKN PCIE_3V3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 1 J4 20 18 16 14 12 10 8 20 18 16 14 12 10 8 6 4 2 PCIe x4 Finger B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 DP-CON Molex 47272-0001 ML3_N_out CONFIG1 CONFIG2 AUX_P GND16 AUX_N HPD_IN RTN PWR_OUT GND11 ML1_N_out ML2_P_out GND8 ML2_N_out ML3_P_out GND5 PRSNT1# +12V_B1 +12V_A2 +12V_B2 +12V_A3 RSVD_B3 GND_A4 GND_B4 JTAG2 SMCLK JTAG3 SMDAT JTAG4 GND_B7 JTAG5 +3.3V_B8 +3.3V_A9 JTAG1 +3.3V_A10 3.3Vaux PERST# WAKE# GND_A12 RSVD_B12 REFCLK+ GND_B13 REFCLKPETp0 GND_A15 PETn0 GND_B16 PERp0 PERn0 PRSNT3# GND_A18 GND_B18 RSVD_A19 PETp1 GND_A20 PETn1 PERp1 GND_B21 PERn1 GND_B22 GND_A23 PETp2 GND_A24 PETn2 PERp2 GND_B25 PERn2 GND_B26 GND_A27 PETp3 GND_A28 PETn3 PERp3 GND_B29 PERn3 RSVD_B30 GND_A31 PRSNT4# RSVD_A32 GND_B32 CN1 GND2 ML0_N_out ML1_P_out ML0_P_out Tx 19 17 15 13 11 9 7 5 3 MZ_CTRL1 MZ_CTRL3 MZ_CTRL5 MZ_CTRL7 MZ_CTRL9 MZ_CTRL11 MZ_CTRL13 MZ_CTRL15 MZ_CTRL17 MZ_CTRL19 DW-10-08-F-D-275 2 4 6 8 10 12 14 16 18 20 HEADER 10X2 Date: Size C Title 1 PCSA_HDINN2 PCSA_HDINP2 0.1uF, X5R, 10V 0.1uF, X5R, 10V R54 x4_PETp3 x4_PETn3 x4_PETp2 x4_PETn2 x4_PETp1 x4_PETn1 R49 x4_PETp0 x4_PETn0 PCIE_3V3 0R OPEN TP10 DP_TX_HPD_OUT R146 1K R354 1K R353 1K PCSA_HDOUTP3 PCSA_HDOUTN3 DP_RX_HPD_OUT R141 1K C6 C7 1 2 3 4 5 6 7 8 9 10 11 12 J19 Mez MZ_SIG0_P MZ_SIG0_N MZ_HDOUTP3 MZ_HDOUTN3 MZ_HDOUTP2 MZ_HDOUTN2 MZ_HDOUTP1 MZ_HDOUTN1 MZ_HDOUTP0 MZ_HDOUTN0 MZ_HDINP0 MZ_HDINN0 Molex 75005-0006 [10] [10] [6] [6] Friday, June 12, 2009 1 Sheet 7 of 16 B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 13 14 15 16 17 18 19 20 21 22 23 24 ECP3 Video Protocol Board Schematic Project SERDES [8] MZ_SE_SIG0 MZ_SE_SIG1 MZ_SIG1_P MZ_SIG1_N MZ_CTRL[0..19] [10] [10] [10] [10] MZ_HDINP3 MZ_HDINN3 MZ_HDINP2 MZ_HDINN2 MZ_HDINP1 MZ_HDINN1 MZ_REFCLKP MZ_REFCLKN X4 PCIe Board Fingers Samtec J47 0.1uF, X5R, 10V C10 3_3V 0.1uF, X5R, 10V C11 R145 1K R351 1K R352 1K 4 2 6 DP-CON Molex 47272-0001 ML2_P_IN ML1_N_IN GND8 ML1_P_IN ML0_N_IN GND11 ML0_P_IN CONFIG1 CONFIG2 AUX_P GND16 AUX_N HPD_OUT RTN PWR_OUT GND5 GND2 ML3_P_IN ML2_N_IN ML3_N_IN Rx 19 17 15 13 11 9 7 5 3 1 J3 B side = PRIMARY Component Side(TOP) A side = SECONDARY Component Side(BOTTOM) PCIE_PERSTN 12_0VIN DP_TX_AUX_P DP_TX_AUX_N [10] 0.1uF, X5R, 10V 0.1uF, X5R, 10V 3_3V 0.1uF, X5R, 10V C5 R138 1K 0.1uF, X5R, 10V C4 PCSA_HDOUTN2 [10] [11] C8 PCSA_HDOUTP2 DP_RX_AUX_N C9 PCSA_HDINP3 PCSA_HDINN3 DP_RX_AUX_P C309 22uF, X5R, 6.3V 0805 [9] MZ_CTRL0 MZ_CTRL2 MZ_CTRL4 MZ_CTRL6 MZ_CTRL8 MZ_CTRL10 MZ_CTRL12 MZ_CTRL14 MZ_CTRL16 MZ_CTRL18 [10] [10] 2 C292 22uF, X5R, 6.3V 0805 [9] All Nets are 100-ohm differential pairs. The P and N traces shall be <20mil matched in length x4_PCIE_CLKP PCSB_HDOUTP3 PCSB_HDOUTN3 PCSB_HDOUTP2 PCSB_HDOUTN2 PCSB_HDOUTP1 PCSB_HDOUTN1 PCSB_HDOUTP0 PCSB_HDOUTN0 PCIe x4 (Quad B) C299 0.01uF R155 10K fz = 1 / (2*3.1416*390*0.01uF) = 40KHz fz is within the recommanded 20KHz to 100KHz range Vout = 1 + (390/169) = 3.3078V C321 22uF, X5R, 6.3V 0805 5_0V U23 NS C328 0.01uF, NPO LP3878MR-ADJ/NOPB 1206 1 2 1 BYPASS SHDN 8 2 NC1 NC2 7 3 GND3 ADJ 6 4 IN OUT 5 3_3V DP_RX_PWR_OUT_EN R171 10K fz = 1 / (2*3.1416*390*0.01uF) = 40KHz fz is within the recommanded 20KHz to 100KHz range Vout = 1 + (390/169) = 3.3078V C293 22uF, X5R, 6.3V 0805 5_0V 1 DisplayPort (Quad A, Ch 2, Ch3) 1 1 2 1 2 1 2 GND9 9 GND9 9 2 1 2 2 1 2 1 1 2 1 2 1 2 100K R143 1 2 1M R139 1M R140 100K R144 100K R137 100K R142 U30H 1K R359 31 S1 S2 S3 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 16. SERDES A B 2_DDR2_CS0# C425 0.01uF C424 0.01uF MZ_CTRL[0..19] LA24 LA20 MZ_CTRL1 MZ_CTRL0 MZ_CTRL2 MZ_CTRL5 MZ_CTRL4 MZ_CTRL3 MZ_CTRL6 MZ_CTRL7 MZ_CTRL8 DDR2_A1 DDR2_BA1 PL62A PL62B PL64A* PL64B* PL65A PL65B PL67A/LDQS67 PL67B PL68A PL68B PL70A* PL70B* PL70E_A/LLM2_GPLLT_FB_A PL70E_B/LLM2_GPLLT_FB_B PL70E_C/LLM2_GPLLT_IN_A PL70E_D/LLM2_GPLLT_IN_B PB2A PB2B PB4A PB4B PB5A PB5B PB7A PB7B PB8A PB8B PB10A PB10B PB11A PB11B BANK 6 SI570_2_SCL SI570_2_SDA 5 [7,11] VTT6_1 VTT6_2 SI570_EN 3_3V_SDI_CLK ECP3-95 VCCIO6_1 VCCIO6_2 VCCIO6_3 VCCIO6_4 PL89A PL89B PL91A* PL91B* PL92A PL92B PL94A/LDQS94 PL94B PL95A PL95B PL97A* PL97B* PL80A PL80B PL82A* PL82B* PL83A PL83B PL85A/LDQS85 PL85B PL86A PL86B PL88A* PL88B* PB13A PB13B PB14A PB14B PB16A PB16B PL71A PL71B PL74A PL74B PL77A PL77B PL79E_A/LLM3_GPLLT_FB_A PL79E_B/LLM3_GPLLT_FB_B PL79E_C/LLM3_GPLLT_IN_A PL79E_D/LLM3_GPLLT_IN_B C426 0.1uF AH7 AJ7 AE9 AD10 AK6 AL6 AF9 AG9 AK7 AL7 AK8 AL8 AM7 AM8 PL53A PL53B PL55A* PL55B* PL56A PL56B PL58A/LDQS58 PL58B PL59A PL59B PL61A* PL61B* PL61E_A/LLM1_GPLLT_FB_A PL61E_B/LLM1_GPLLT_FB_B PL61E_C/LLM1_GPLLT_IN_A PL61E_D/LLM1_GPLLT_IN_B W11 W10 AB11 AB12 V11 V12 AN3 AM3 AJ5 AJ6 AL5 AM5 AM6 AN6 AL4 AM4 AP5 AP6 AN1 AN2 AD9 AD8 AP2 AP3 AJ2 AJ3 AL3 AK3 AJ4 AK4 AH9 AJ8 AN7 AP7 AN8 AP8 AD4 AD3 AE2 AE1 AE4 AE3 AM1 AM2 AL1 AL2 AA2 AA1 Y7 AA7 AA4 AA3 AA10 AB9 AB2 AB1 AA5 AB5 AD2 AD1 AC6 AC7 W2 W1 W8 W9 W4 W3 W6 Y6 Y2 Y1 Y8 AA8 Y5 Y4 Y9 Y10 MZ_CTRL19 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH9 SWITCH10 MZ_CTRL12 MZ_CTRL14 DDR2_BA0 MZ_CTRL13 MZ_CTRL18 MZ_CTRL17 SWITCH12 SWITCH11 MZ_CTRL16 MZ_CTRL15 SI570_2_CLK_P SI570_2_CLK_N 6 7 8 VDD SDA SCL NC OE GND CLK+ CLK- 3 4 5 U15 Si570 Silicon Labs 570QAC000215DG C186 0.1uF 1_8V DDR2_A5 DDR2_A3 4 + + C113 22uF, Tant 0805 R95 510, 1% 2 C259 0.01uF R93 OPEN R92 0R C155 0.01uF 2_5V C147 0.1uF DDR2 Micron MT47H128M16HG-3 IT VDD_A1 VDD_E1 VDD_J9 VDD_M9 VDD_R1 VDDQ_A9 VDDQ_C1 VDDQ_C3 VDDQ_C7 VDDQ_C9 VDDQ_E9 VDDQ_G1 VDDQ_G3 VDDQ_G7 VDDQ_G9 VSS_A3 VSS_E3 VSS_J3 VSS_N1 VSS_P9 VSSQ_A7 VSSQ_B2 VSSQ_B8 VSSQ_D2 VSSQ_D8 VSSQ_E7 VSSQ_F2 VSSQ_F8 VSSQ_H2 VSSQ_H8 VREF_J2 VDDL_J1 VSSDL_J7 U29B C139 0.1uF DDR2_VREF C126 1uF, X5R, 6.3V VDDL C143 0.1uF C193 1uF, X5R, 6.3V A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7 DDR2 Micron MT47H128M16HG-3 IT DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7 U29A Voltage adjustment range : 0.82V to 0.98V VR1 Turn clockwise to increase the voltage 100 Copal ST32ETB101 R94 510, 1% + FB38 BLM21AG601SN1D 1_8V C129 0.01uF C191 22uF, Tant 0805 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7 C178 1uF, X5R, 6.3V DDR2_A13 DDR2_BA2 DDR2_A14 DDR2_DQ15 DDR2_DQ14 DDR2_DQ13 DDR2_DQ12 DDR2_DQ11 DDR2_DQ10 DDR2_DQ9 DDR2_DQ8 DDR2_DQ7 DDR2_DQ6 DDR2_DQ5 DDR2_DQ4 DDR2_DQ3 DDR2_DQ2 DDR2_DQ1 DDR2_DQ0 DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_DQS0 DDR2_DQS0# DDR2_DQS1 DDR2_DQS1# DDR2_DM0 DDR2_DM1 DDR2_K DDR2_K# DDR2_CKE DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_ODT0 DDR2_CS0# DDR2_BA0 DDR2_BA1 C192 22uF, Tant 0805 1_8V [10,15] R57 100 DDR2_VREF C109 0.01uF ACLK[1..3] 1_8V Place under ECP3 SI570_2_CLK_P SI570_2_CLK_N C174 0.01uF LA25 LA26 LA27 LA21 LA22 LA23 LA19 ACLK2 ACLK1 LA18 MZ_CTRL[0..19] [7] SWITCH[1..12] [12] DDR2_VREF C183 0.01uF LA[1..34] FPGA_VTT [6,9,11,12] DDR2_A12 DDR2_CKE DDR2_A11 DDR2_A9 DDR2_A14 DDR2_A6 DDR2_A2 DDR2_A7 DDR2_BA2 MZ_CTRL11 MZ_CTRL10 MZ_CTRL9 DDR2_RAS# DDR2_A10 DDR2_WE# 1 2 C194 0.1uF DDR2_A0 DDR2_K DDR2_K# DDR2_CS0# DDR2_ODT0 SI570_2_SDA SI570_2_SCL DDR2_CAS# DDR2_A4 DDR2_A8 DDR2_A13 SWITCH5 SWITCH6 SWITCH7 SWITCH8 DDR2_DQ0 DDR2_DQ7 DDR2_DM0 DDR2_DQ3 DDR2_DQ6 DDR2_DQ4 DDR2_DQS0 DDR2_DQS0# DDR2_DQ5 DDR2_DQ2 DDR2_DQ1 DDR2_DQ8 DDR2_DQ14 DDR2_DQ9 DDR2_DM1 DDR2_DQ10 DDR2_DQ12 DDR2_DQ11 DDR2_DQS1 DDR2_DQS1# DDR2_DQ13 DDR2_DQ15 1 2 U2 U1 V9 V8 V2 V1 V5 W5 V4 V3 V7 W7 1 2 PL44A PL44B PL46A*/PCLKT6_0 PL46B*/PCLKC6_0 PL47A PL47B PL49A/LDQS49 PL49B PL50A PL50B PL52A*/VREF1_6 PL52B*/VREF2_6 4 1 U30E ALL Memory controller buses, clocks, and control traces must be no more than 1.5 inches long using 50 Ohm Transmission lines 1 2 1 2 C 1 2 1 2 1 2 C257 0.1uF 3 R224 3 C256 0.01uF 1_8V C252 0.1uF 2_DDR2_RAS# 2_DDR2_WE# 2_DDR2_A0 2_DDR2_A2 2_DDR2_CAS# 2_DDR2_ODT0 PL2A PL2B PL4A PL4B PL5A PL5B 5 4 2 U30F PL8A PL8B PL10A* PL10B* PL11A PL11B PL13A/LDQS13 PL13B PL14A PL14B PL16A* PL16B* ECP3-95 VDDQ VTT VREF VSENSE SD VTT7_1 VTT7_2 3 8 2 C176 + 0.01uF PB3 PB4 PB1 PB2 C253 0.01uF C250 0.01uF 0R R69 2 1_8V C248 0.1uF C258 22uF, X5R, 6.3V 0805 C179 0.1uF C249 0.01uF C202 22uF, Tant 0805 [12] [11] [11] C216 0.01uF + C238 0.01uF C246 22uF, Tant 0805 C247 22uF, Tant 0805 + Date: Size C Title C239 0.1uF A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7 C243 0.01uF C242 0.1uF DDR2 MT47H128M16HG-3 IT Micron VDD_A1 VDD_E1 VDD_J9 VDD_M9 VDD_R1 VDDQ_A9 VDDQ_C1 VDDQ_C3 VDDQ_C7 VDDQ_C9 VDDQ_E9 VDDQ_G1 VDDQ_G3 VDDQ_G7 VDDQ_G9 VSS_A3 VSS_E3 VSS_J3 VSS_N1 VSS_P9 VSSQ_A7 VSSQ_B2 VSSQ_B8 VSSQ_D2 VSSQ_D8 VSSQ_E7 VSSQ_F2 VSSQ_F8 VSSQ_H2 VSSQ_H8 VREF_J2 VDDL_J1 VSSDL_J7 U31B DDR2 Micron MT47H128M16HG-3 IT DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7 Friday, June 12, 2009 1 Sheet 8 of 16 ECP3 Video Protocol Board Schematic Project 1 U31A B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 C235 1uF, X5R, 6.3V 2_VDDL C236 0.1uF C245 1uF, X5R, 6.3V DDR2 Memory C221 22uF, Tant 0805 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7 C244 1uF, X5R, 6.3V 2_DDR2_A13 2_DDR2_BA2 2_DDR2_A14 2_DDR2_DQ15 2_DDR2_DQ14 2_DDR2_DQ13 2_DDR2_DQ12 2_DDR2_DQ11 2_DDR2_DQ10 2_DDR2_DQ9 2_DDR2_DQ8 2_DDR2_DQ7 2_DDR2_DQ6 2_DDR2_DQ5 2_DDR2_DQ4 2_DDR2_DQ3 2_DDR2_DQ2 2_DDR2_DQ1 2_DDR2_DQ0 2_DDR2_A0 2_DDR2_A1 2_DDR2_A2 2_DDR2_A3 2_DDR2_A4 2_DDR2_A5 2_DDR2_A6 2_DDR2_A7 2_DDR2_A8 2_DDR2_A9 2_DDR2_A10 2_DDR2_A11 2_DDR2_A12 2_DDR2_DQS0 2_DDR2_DQS0# 2_DDR2_DQS1 2_DDR2_DQS1# 2_DDR2_DM0 2_DDR2_DM1 2_DDR2_K 2_DDR2_K# 2_DDR2_CKE 2_DDR2_WE# 2_DDR2_RAS# 2_DDR2_CAS# 2_DDR2_ODT0 2_DDR2_CS0# 2_DDR2_BA0 2_DDR2_BA1 FB39 BLM21AG601SN1D 1_8V C388 120uF, SP-Cap EIA7343 Panasonic EEF-SL0E121R FPGA_VTT + + 1_8V R79 100 DDR2_VREF C203 0.01uF DDR2_VREF SMA_CLK_P SMA_CLK_N PB[1..4] FPGA_VTT Place under ECP3 C190 0.1uF 1_8V 2_DDR2_A12 2_DDR2_BA2 2_DDR2_A3 2_DDR2_A9 2_DDR2_A6 2_DDR2_A4 2_DDR2_A5 2_DDR2_A1 2_DDR2_A11 2_DDR2_CKE 2_DDR2_A10 2_DDR2_A13 2_DDR2_BA0 2_DDR2_BA1 2_DDR2_A8 2_DDR2_K 2_DDR2_K# 2_DDR2_A14 2_DDR2_A7 2_DDR2_DQ7 2_DDR2_DQ0 2_DDR2_DQ6 2_DDR2_DQ1 2_DDR2_DQ2 2_DDR2_DQ5 2_DDR2_DQS0 2_DDR2_DQS0# 2_DDR2_DQ3 2_DDR2_DQ4 2_DDR2_DM0 2_DDR2_DQ12 2_DDR2_DQ9 2_DDR2_DQ14 2_DDR2_DM1 2_DDR2_DQ15 2_DDR2_DQ11 2_DDR2_DQS1 2_DDR2_DQS1# 2_DDR2_DQ8 2_DDR2_DQ13 2_DDR2_DQ10 ALL Memory controller buses, clocks, and control traces must be no more than 1.5 inches long using 50 Ohm Transmission lines C251 0.1uF C255 0.1uF T11 T10 U12 U11 N12 N11 T6 T5 R8 T7 T4 T3 T9 T8 T2 T1 U9 U8 U5 U4 U6 U7 R7 R5 P9 P10 R2 R1 P7 P6 R4 R3 R9 R10 N4 N3 M5 N5 N2 N1 M10 N10 P5 P4 N8 P8 P2 P1 N7 N6 F2 F1 F3 E3 G2 G1 G3 H3 H1 J1 J3 H2 U10 LP2997 National Semiconductor LP2997MR BANK 7 VCCIO7_1 VCCIO7_2 VCCIO7_3 VCCIO7_4 PL35A PL35B PL37A*/LUM0_GDLLT_IN_A PL37B*/LUM0_GDLLT_IN_B PL38A/LUM0_GDLLT_FB_A PL38B/LUM0_GDLLT_FB_B PL40A/LDQS40 PL40B PL41A PL41B PL43A*/PCLKT7_0 PL43B*/PCLKC7_0 PL43E_A/LUM0_GPLLT_FB_A PL43E_B/LUM0_GPLLT_FB_B PL43E_C/LUM0_GPLLT_IN_A PL43E_D/LUM0_GPLLT_IN_B PL26A PL26B PL28A* PL28B* PL29A PL29B PL31A/LDQS31 PL31B PL32A PL32B PL34A*/VREF1_7 PL34B*/VREF2_7 PL17A PL17B PL19A* PL19B* PL20A PL20B PL22A/LDQS22 PL22B PL23A PL23B PL25A* PL25B* PL25E_A/LUM2_GPLLT_FB_A PL25E_B/LUM2_GPLLT_FB_B PL25E_C/LUM2_GPLLT_IN_A PL25E_D/LUM2_GPLLT_IN_B C254 0.01uF G4 G5 K9 K8 H5 H4 Controller Instance #2 1 2 D 1K R360 1 2 1 Controller Instance #1 1K R361 1 2 2 3 1 1 2 2 1 2 5 1 2 4.7K 1 2 1 2 6 7 AVIN PVIN BGND GND 9 1 1 LDQS94 2 1 2 32 LDQS85 1 1 2 LDQS67 2 LDQS40 1 LDQS58 LDQS31 2 LDQS49 LDQS22 1 LDQS13 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 17. DDR2 Memory A B C D 5 LED_SEG[1..17] F18 G18 F19 A11 B11 F10 E10 D10 C10 A10 B10 J12 K12 C11 D11 G11 3_3V M17 L13 M13 L17 A15 B15 H16 G16 C16 D16 K16 L16 A16 B16 J16 G17 C17 D17 J17 H17 C3 C4 D3 C2 B1 B2 E4 D4 B3 A2 D5 C6 B4 A3 D6 C5 A4 A5 B7 A7 B6 A6 A8 A9 D12 E12 G12 G13 A12 B12 J14 H13 E13 F13 K14 K15 C13 D13 J13 H14 A13 B13 F12 E11 C14 D14 K13 J15 A14 B14 E17 H15 D15 E15 C393 0.1uF RS-232 C394 0.1uF Contrast Adjustment 2 [4,13,14] [4,13,14] [16] [15] [15] [15] + C391 0.1uF [7] [7] C395 0.1uF 4 RS232_TXD C392 0.1uF 3_3V 16 1 3 4 5 2 6 11 10 13 8 1 3 5 7 9 11 13 15 17 GND T1OUT T2OUT R1OUT R2OUT 15 14 7 12 9 NC2 VDD RS E DB1 DB3 DB5 DB7 CATHODE MAX3232IPWR VCC C1+ C1C2+ C2V+ V- T1IN T2IN R1IN R2IN U33 NC1 VSS VO R/W DB0 DB2 DB4 DB6 ANODE J43 HDR 9x2 C165 1uF, X5R, 6.3V TMDS_RX_DATA2_P TMDS_RX_DATA2_N TMDS_RX_DATA1_P TMDS_RX_DATA1_N LCD_R/W LCD_DB0 LCD_DB2 LCD_DB4 LCD_DB6 RS232_RXD LCD0 LCD1 LCD2 LCD3 LCD4 Backlight Adjustment LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 TMDS_RX_DATA0_P TMDS_RX_DATA0_N VR6 10K Copal ST32ETB103 ANODE 2 C241 22uF, Tant 0805 3_3V TMDS_RX_CLK_P TMDS_RX_CLK_N DP_TX_PWR_OUT_EN DP_RX_PWR_OUT_EN [15] [16] LCD9 LCD10 LCD0 LCD1 LCD2 [6,8,11,12] RS232_TXD RS232_RXD DVI_TX_DDC_CLK DVI_RX_DDC_CLK DVI_TX_DDC_DATA DVI_RX_DDC_DATA RX_SE_REFCLK TX_SE_REFCLK TX_VSYNC RX_HSYNC RX_VSYNC RX_FSYNC [15] LA[1..34] DVI_RX_HPD I2C_SDA I2C_SCL DVI_TX_CLK LA3 LA4 DVI_TX_DE DVI_TX_VSYNC DVI_TX_HSYNC DVI_TX_B5 DVI_TX_B4 DVI_TX_B3 DVI_TX_B2 DVI_TX_B1 DVI_TX_B0 VR5 10K Copal ST32ETB103 R136 10K 4 RX_GS4911_RESETn DVI_TX_R7 DVI_TX_R6 DVI_TX_R5 DVI_TX_R4 DVI_TX_R3 DVI_TX_R2 DVI_TX_R1 DVI_TX_R0 DVI_TX_G7 DVI_TX_G6 DVI_TX_G5 DVI_TX_G4 DVI_TX_G3 DVI_TX_G2 DVI_TX_G1 DVI_TX_G0 DVI_TX_B7 DVI_TX_B6 LCD Connector ECP3-95 VCCIO0_1 VCCIO0_2 VCCIO0_3 VCCIO0_4 BANK 0 PT62A PT62B PT61B PT58A PT65A PT65B PT67A PT67B PT68A PT68B PT61A PT58B PT71A PT71B PT73A/PCLKT0_0 PT73B/PCLKC0_0 PT2A PT2B PT4A/VREF1_0 PT4B/VREF2_0 PT20A PT5A PT20B PT5B PT22A PT7A PT22B PT7B PT23A PT8A PT23B PT8B PT10A PT25A PT10B PT26A PT11A PT26B PT11B PT13A PT31A PT31B PT13B PT43A PT14A PT43B PT14B PT16A PT64B PT16B PT70A PT17A PT70B PT17B PT19A PT19B PT35A PT35B PT25B PT40A PT32A PT32B PT34A PT34B PT38A PT38B PT37A PT37B PT44A PT44B PT28B PT40B PT41A PT41B PT29B PT29A PT50A PT50B PT28A PT46A PT56A PT56B PT64A PT46B PT59A PT59B U30A + C288 10uF, Tant 0805 5_0V [11,12] LED_SEG10 LED_SEG11 [16] TX_HSYNC SEG_C SEG_P [16] TX_FSYNC [16] 1 3 TX_GS4911_RESETn 3 1 2 4 6 8 10 12 14 16 18 DVDD I2C_SCL R293 R299 R303 HEADER 5x2 2 4 6 8 10 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD[0..10] DVDD DVDD DVDD I2C_SDA LCD_RS LCD_E LCD_DB1 LCD_DB3 LCD_DB5 LCD_DB7 J38 1 3 5 7 9 R126 TFP410_ISEL 33 33 33 33 EXB28V330JV 8 7 6 5 EXB28V330JV 8 7 6 5 EXB28V330JV 8 7 6 5 EXB28V330JV 8 7 6 5 EXB28V330JV 8 7 6 5 EXB28V330JV 8 7 6 5 C287 0.1uF 33 33 33 33 33 33 [11] R337 R338 R336 R335 RN38 1 2 3 4 RN13 1 2 3 4 RN15 1 2 3 4 RN14 1 2 3 4 RN17 1 2 3 4 RN16 1 2 3 4 4.7K 4.7K 4.7K DVDD DVDD 4.7K R294 R300 R302 3 4.7K 4.7K 4.7K R289 OPEN TP29 TP31 TP30 TFP410_VREF TFP410_VSYNC TFP410_HSYNC TFP410_DE 3(D) BLM21AG601SN1D FB42 BLM21AG601SN1D FB41 BLM21AG601SN1D FB43 2(S) DVI_RX_HPD 1(G) Top View SOT-23 R327 PDN C409 0.1uF C405 0.1uF C279 0.1uF C272 0.1uF C407 0.1uF DGND_16 DGND_48 DGND_64 DVDD_1 DVDD_12 DVDD_33 PGND PVDD TFADJ TGND_20 Clk Out TXCP TXCN TVDD_23 TX0P TX0N TGND_26 TX1P TX1N 1 2 C410 0.01uF TI_PVDD C403 0.01uF C280 0.01uF C274 0.01uF DVDD C408 0.01uF C401 1000pF C406 1000pF TI_TVDD C411 1000pF C404 1000pF 2 11 49 34 16 48 64 1 12 33 17 18 19 20 22 21 23 25 24 26 28 27 29 31 30 32 + + DVDD 5_0V C270 22uF, Tant 0805 C283 22uF, Tant 0805 R345 1K J46 HEADER 3x1 RX_DDC_CLK TX_DDC_DATA RX_DDC_DATA 5_0V Date: Size C Title TMDS_RX_CLK_P TMDS_RX_CLK_N TMDS_RX_DATA0_N TMDS_RX_DATA0_P C5 C6 C4 C1 C2 C3 23 24 22 20 21 19 17 18 16 14 15 12 13 11 9 10 8 6 7 4 5 3 1 2 C5 C6 C4 C1 C2 C3 23 24 22 20 21 19 17 18 16 14 15 12 13 11 9 10 8 6 7 4 5 3 1 2 1 Friday, June 12, 2009 1 Sheet 9 of 16 ECP3 Video Protocol Board Schematic Project DVI Rx DVI Tx B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 Molex 74320-1004 Analog_Ground_1 Analog_Ground_2 Analog_Horizontal_Sync Analog_Red Analog_Green Analog_Blue TMDS_Clock+ TMDS_Clock- TMDS_Clock_Shield TMDS_Data5TMDS_Data5+ TMDS_Data0/5_Shield TMDS_Data0TMDS_Data0+ Hot_Plug_Detect +5V_Power GND(for +5V) TMDS_Data3TMDS_Data3+ TMDS_Data1/3_Shield TMDS_Data1TMDS_Data1+ Analog_Vertical_Sync DDC_Clock DDC_Data TMDS_Data4TMDS_Data4+ TMDS_Data2/4_Shield TMDS_Data2TMDS_Data2+ DVI-Integrated Molex 74320-1004 J16 Analog_Ground_1 Analog_Ground_2 Analog_Horizontal_Sync Analog_Red Analog_Green Analog_Blue TMDS_Clock+ TMDS_Clock- TMDS_Clock_Shield TMDS_Data5TMDS_Data5+ TMDS_Data0/5_Shield TMDS_Data0TMDS_Data0+ Hot_Plug_Detect +5V_Power GND(for +5V) TMDS_Data3TMDS_Data3+ TMDS_Data1/3_Shield TMDS_Data1TMDS_Data1+ Analog_Vertical_Sync DDC_Clock DDC_Data TMDS_Data4TMDS_Data4+ TMDS_Data2/4_Shield TMDS_Data2TMDS_Data2+ DVI-Integrated J14 DVI / LCD / RS-232 R346 OPEN TMDS_RX_DATA1_N TMDS_RX_DATA1_P TMDS_RX_DATA2_N TMDS_RX_DATA2_P 510, 1% TI_TVDD TI_PVDD R312 TMDS_TX_CLK_P TMDS_TX_CLK_N TMDS_TX_DATA0_P TMDS_TX_DATA0_N TMDS_TX_DATA1_P TMDS_TX_DATA1_N TI_TVDD TMDS_TX_DATA2_P TMDS_TX_DATA2_N TX_DDC_CLK Q31 MOSFET N GSD 1 BSS138LT1G C402 1000pF MSEN HEADER 2x2 1 2 HEADER 2x2 MSEN/PO1 N/C RESERVED (Tie to GND) R310 4.7K Q27 MOSFET N GSD 1 BSS138LT1G TX2P TX2N TVDD_29 G/CTL1 B/CTL3:2 DVDD J41 J40 2 TGND_32 R/HVSync D34 LED-SMT1206_GREEN 3 4 3 4 1K BSEL/SCL DSEL/SDA CTL3/A3/DK3 CTL2/A2/DK2 CTL1/A1/DK1 ISEL/RSTN DKEN EDGE/HTPLG VREF VSYNC HSYNC DE IDCKP IDCKN DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 DATA15 DATA14 DATA13 DATA12 U37 TFP410 R311 150 10 15 14 6 7 8 13 35 9 3 5 4 2 57 56 50 51 52 53 54 55 58 59 60 61 62 63 TFP410_D11 TFP410_D10 TFP410_D9 TFP410_D8 TFP410_D7 TFP410_D6 TFP410_D5 TFP410_D4 TFP410_D3 TFP410_D2 TFP410_D1 TFP410_D0 TFP410_IDCK 36 37 38 39 40 41 42 43 44 45 46 47 TFP410_D23 TFP410_D22 TFP410_D21 TFP410_D20 TFP410_D19 TFP410_D18 TFP410_D17 TFP410_D16 TFP410_D15 TFP410_D14 TFP410_D13 TFP410_D12 LED will be ON when connecting a powered DVI receiver to the DVI Tx connector. C414 0.1uF EDGE OPEN PDN OPEN DKEN OPEN + C284 10uF, Tant 0805 3_3V R304 R309 R301 3 3 2 GND65 65 5 1 2 1 2 1 2 1 2 1 2 1 2 3 2 1 3 33 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 18. DVI/LCD/RS-232 T25 T24 2_5V 34 R67 100 [7] [7] 4 VTT3_1 VTT3_2 OPEN OPEN MZ_SIG1_P MZ_SIG1_N MZ_SIG0_P MZ_SIG0_N R61 R58 R60 R63 R65 100 100 100 100 100 CN_RX_CLKIN_P CN_RX_CLKIN_N CN_RX_IN3_P CN_RX_IN3_N CN_RX_IN2_P CN_RX_IN2_N CN_RX_IN1_P CN_RX_IN1_N CN_RX_IN0_P CN_RX_IN0_N Place close to ECP3 device R78 R72 R56 R55 510, 1% AB23 AB24 V24 V23 W25 W24 CN_TX_OUT0_P CN_TX_OUT0_N CN_TX_OUT1_P CN_TX_OUT1_N CN_TX_OUT2_P CN_TX_OUT2_N ECP3_XO_SIG[0..11] BANK 3 (2.5V) ECP3_XO_SIG1 ECP3_XO_SIG0 ECP3_XO_SIG3 ECP3_XO_SIG2 ECP3_XO_SIG5 ECP3_XO_SIG4 LED7 LED6 LED9 LED8 LED11 LED10 LED12 3 R195 R194 R192 R204 R206 R70 R68 R71 R76 R80 100 100 100 100 100 100 100 100 100 100 RJ45_IN_P2 RJ45_IN_N2 RJ45_IN_P1 RJ45_IN_N1 RJ45_IN_P0 RJ45_IN_N0 RJ45_IN_P3 RJ45_IN_N3 CM_RX_SerTFG_P CM_RX_SerTFG_N CM_RX_XCLK_P CM_RX_XCLK_N CM_RX_X3_P CM_RX_X3_N CM_RX_X2_P CM_RX_X2_N CM_RX_X1_P CM_RX_X1_N CM_RX_X0_P CM_RX_X0_N Place close to ECP3 device 2_5V 510, 1% CN_TX_CLKOUT_P CN_TX_CLKOUT_N AN32 AM32 AL30 AM30 AP31 AN31 AP29 AP30 AL31 AM31 AM29 AN29 AN34 AN33 AH33 AJ33 AP33 AP32 AL34 AL33 AL32 AK32 AJ31 AK31 [15] [15] ECP3_XO_SIG7 ECP3_XO_SIG6 ECP3_XO_SIG9 ECP3_XO_SIG8 Tx CN_TX_OUT3_P CN_TX_OUT3_N CN_TX_CLKOUT_P CN_TX_CLKOUT_N CN_TX_OUT2_P CN_TX_OUT2_N CN_TX_OUT1_P CN_TX_OUT1_N CN_TX_OUT0_P CN_TX_OUT0_N CMR_CC3_N CMR_CC4_N CMR_CC4_P 4 3 2 1 4 CMR_CC2_N CMR_CC3_P 3 CMR_CC2_P 1 2 CMR_CC1_N CMR_CC1_P 4 3 1 2 CMR_SerTC_N 2 165 165 165 RN31 165 165 165 165 RN32 165 165 165 165 RN33 165 RJ45_IN_P0 RJ45_IN_P1 RJ45_IN_N2 RJ45_IN_P3 J9 CM_RX_CC2_P CM_RX_CC2_N 7 6 5 CM_RX_CC4_P 6 CM_RX_CC4_N 7 5 CM_RX_CC3_P CM_RX_CC3_N 8 CAT16-LV2F6LF CM_RX_CC1_P CM_RX_CC1_N 8 CAT16-LV2F6LF 5 6 CM_RX_SerTC_P CM_RX_SerTC_N MDR-26 3M 10226-1210VE Mounting_R Mounting_L DDC_Gnd_1 TxOut0TxOut0Gnd TxOut0+ Sense USB/DDC_Gnd TxOut1TxOut1Gnd TxOut1+ DDC/SDA TxOut2TxOut2Gnd TxOut2+ USB+ USB_Shield USBDDC/SCL TxClkOutTxClkOutGnd TxClkOut+ USB_+5VDC DDC_+5VDC TxOut3TxOut3Gnd TxOut3+ DDC_Gnd_26 7 27 28 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 1 3 5 7 J44 RJ45_OUT_N0 RJ45_OUT_P2 RJ45_OUT_N1 RJ45_OUT_N3 measurement across CAT-5 cable (Not an Ethernet Port) RJ-45 Output RJ-45 Connector for signal quality 2 4 6 8 RJ45_IN_N0 RJ45_IN_P2 RJ45_IN_N1 RJ45_IN_N3 Rx CN_RX_IN0_N CN_RX_IN0_P CN_RX_IN1_N CN_RX_IN1_P CN_RX_IN2_N CN_RX_IN2_P CN_RX_CLKIN_N CN_RX_CLKIN_P CN_RX_IN3_N CN_RX_IN3_P Date: Size C Title MDR-26 3M 10226-1210VE mount-L mount-R inner shield1 inner shield2 X0X0+ X1X1+ X2X2+ XCLKXCLK+ X3X3+ SerTC+ SerTCSerTFGSerTFG+ CC1CC1+ CC2+ CC2CC3CC3+ CC4+ CC4inner shield3 inner shield4 Friday, June 12, 2009 1 Sheet 10 of 16 ECP3 Video Protocol Board Schematic Project B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 27 28 1 14 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 13 26 J12 MDR-26 3M 10226-1210VE DDC_Gnd_1 RxIn3+ RxIn3Gnd RxIn3DDC_+5VDC USB_+5VDC RxClkIn+ RxClkInGnd RxClkInDDC/SCL USBUSB_Shield USB+ RxIn2+ RxIn2Gnd RxIn2DDC/SDA RxIn1+ RxIn1Gnd RxIn1USB/DDC_Gnd Sense RxIn0+ RxIn0Gnd RxIn0DDC_Gnd_26 Mounting_L Mounting_R J10 ChannelLink/CameraLink Rx CM_RX_X0_N CM_RX_X0_P CM_RX_X1_N CM_RX_X1_P CM_RX_X2_N CM_RX_X2_P CM_RX_XCLK_N CM_RX_XCLK_P CM_RX_X3_N CM_RX_X3_P CM_RX_SerTC_P CM_RX_SerTC_N CM_RX_SerTFG_N CM_RX_SerTFG_P CM_RX_CC1_N CM_RX_CC1_P CM_RX_CC2_P CM_RX_CC2_N CM_RX_CC3_N CM_RX_CC3_P CM_RX_CC4_P CM_RX_CC4_N 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 28 27 measurement across CAT-5 cable (Not an Ethernet Port) RJ-45 Input RJ-45 Connector for signal quality 2 4 6 8 CameraLink RJ-45 1 3 5 7 J45 Differential Input Pair Traces RJ-45 RJ45_OUT_P0 RJ45_OUT_P1 RJ45_OUT_N2 RJ45_OUT_P3 8 CAT16-LV2F6LF Place close to ECP3 device CMR_SerTC_P [14] (AM34, AM33) (AC32, AC31) (AA34, AA33) (P30, R29) 1 Differential Output Pair Traces Category-5 Cable Pairing Information: (1,2), (3,6), (4,5), (7,8) 0 1 2 3 ChannelLink Pair Pair Pair Pair (W27, W26) (AA25, AA26) (W30, W29) (Y26, Y25) Category-5 Cable Pairing Information: (1,2), (3,6), (4,5), (7,8) 0 1 2 3 140 DP_TX_AUX_N R62 49.9, 1% C180 0.01uF DP_TX_AUX_P R66 49.9, 1% [7] BANK 3 VCCIO3_1 VCCIO3_2 VCCIO3_3 VCCIO3_4 PR89A PR89B PR91A* PR91B* PR92A PR92B PR94A/RDQS94 PR94B PR95A PR95B PR97A* PR97B* PR80A PR80B PR82A* PR82B* PR83A PR83B PR85A/RDQS85 PR85B PR86A PR86B PR88A* PR88B* RX_GC4915_CLKOUTP RX_GC4915_CLKOUTN RJ45_IN_P0 RJ45_IN_N0 RX_GS4911_PCLK1 [15] OSC_IN2 RJ45_OUT_P1 RJ45_OUT_N1 CN_TX_OUT3_P CN_TX_OUT3_N RJ45_IN_P1 RJ45_IN_N1 Place close to ECP3 device ECP3-95 PR137A PR137B PR139A PR139B PR140A PR140B PR142A PR142B PR143A PR143B PR145A PR145B PR131A PR131B PR133A PR133B PR134A PR134B PR136A PR136B AM34 AM33 AJ34 AK34 [16] RJ45_OUT_P3 RJ45_OUT_N3 RJ45_IN_P2 RJ45_IN_N2 ECP3_XO_SIG11 ECP3_XO_SIG10 RJ45_OUT_N2 R128 140 RJ45_OUT_P2 Pair Pair Pair Pair 140 5 DPT_AUX_N 100 R64 C231 0.01uF DP_RX_AUX_N R74 49.9, 1% [7] AM28 AL28 AK27 AJ27 AK28 AJ28 AH27 AH28 AL29 AK29 AF26 AE26 AP28 AN28 AP27 AN27 AM27 AL27 AH26 AG26 PR79E_A/RLM3_GPLLT_FB_A PR79E_B/RLM3_GPLLT_FB_B PR79E_C/RLM3_GPLLT_IN_A PR79E_D/RLM3_GPLLT_IN_B AB34 AB33 AA25 AA26 AA31 AA30 AC34 AC33 AB30 AC30 AA28 AA27 AC32 AC31 AB28 AB29 R129 158 R130 158 RJ45_OUT_P0 RJ45_OUT_N0 TX_X1 [11] TX_GS4911_PCLK1 ECP3_RJ45_OUT_P2 ECP3_RJ45_OUT_N2 CN_RX_IN2_P CN_RX_IN2_N CN_RX_IN3_P CN_RX_IN3_N CN_RX_IN0_P CN_RX_IN0_N CN_RX_CLKIN_P CN_RX_CLKIN_N CN_RX_IN1_P CN_RX_IN1_N 140 DPT_AUX_P 100 R73 DP_RX_AUX_P R77 49.9, 1% TX_CLKIN_SE RX_CLKIN_SE [8,15] [11,14] PR62A PR62B PR64A* PR64B* PR65A PR65B PR68A PR68B PR67A/RDQS67 PR67B PR70A* PR70B* PR70E_A/RLM2_GPLLT_FB_A PR70E_B/RLM2_GPLLT_FB_B PR70E_C/RLM2_GPLLT_IN_A PR70E_D/RLM2_GPLLT_IN_B PR71A PR71B PR74A PR74B PR77A PR77B W30 W29 W27 W26 Y34 Y33 Y30 AA29 Y32 Y31 Y26 Y25 AA34 AA33 Y28 Y27 V31 V30 U28 V28 W34 W33 V27 V26 W32 W31 V29 W28 2 140 DPR_AUX_N 100 R81 [16] [15] ACLK[1..3] OSC_IN[1..4] LED1 AE32 AE31 AE30 AE29 AF32 AF31 PR53A PR53B PR55A* PR55B* PR56A PR56B PR58A/RDQS58 PR58B PR59A PR59B PR61A* PR61B* PR61E_A/RLM1_GPLLT_FB_A PR61E_B/RLM1_GPLLT_FB_B PR61E_C/RLM1_GPLLT_IN_A PR61E_D/RLM1_GPLLT_IN_B PR44A PR44B PR46A*/PCLKT3_0 PR46B*/PCLKC3_0 PR47A PR47B PR49A/RDQS49 PR49B PR50A PR50B PR52A*/VREF1_3 PR52B*/VREF2_3 3 11 12 11 12 U30D RDQS94 DPR_AUX_P Place under ECP3 device R52 510, 1% R53 510, 1% ACLK3 OSC_IN2 LED3 LED2 LED5 LED4 4 RDQS85 140 A VTT2_1 BANK 2 VTT2_2 N24 U23 N23 U24 [11] CMR_CC1_P CMR_CC1_N CMR_CC2_P CMR_CC2_N CMR_CC3_P CMR_CC3_N CM_RX_SerTFG_P CM_RX_SerTFG_N CMR_CC4_P CMR_CC4_N CM_RX_X0_P CM_RX_X0_N CM_RX_XCLK_P CM_RX_XCLK_N CM_RX_X1_P CM_RX_X1_N CM_RX_X2_P CM_RX_X2_N CM_RX_X3_P CM_RX_X3_N [7] [7] RJ45_IN_P3 RJ45_IN_N3 MZ_SIG1_P MZ_SIG1_N OSC_IN1 RX_X1 [7] [7] MZ_SE_SIG0 [7] MZ_SE_SIG1 [7] DPT_AUX_P DPT_AUX_N BANK 2 (2.5V) ECP3-95 RDQS40 VCCIO2_1 VCCIO2_2 VCCIO2_3 VCCIO2_4 T32 T31 T26 T27 T34 T33 T30 U30 U32 U31 U26 U27 U34 U33 V34 V33 P34 P33 R28 R27 R31 R30 R26 R25 R34 R33 T29 T28 MZ_SIG0_P MZ_SIG0_N DPR_AUX_P DPR_AUX_N CMR_SerTC_P CMR_SerTC_N LED[1..12] RDQS67 B RDQS31 PR35A PR35B PR37A*/RUM0_GDLLT_IN_A PR37B*/RUM0_GDLLT_IN_B PR38A/RUM0_GDLLT_FB_A PR38B/RUM0_GDLLT_FB_B PR40A/RDQS40 PR40B PR41A PR41B PR43A*/PCLKT2_0 PR43B*/PCLKC2_0 PR43E_A/RUM0_GPLLT_FB_A PR43E_B/RUM0_GPLLT_FB_B PR43E_C/RUM0_GPLLT_IN_A PR43E_D/RUM0_GPLLT_IN_B PR26A PR26B PR28A* PR28B* PR29A PR29B PR31A/RDQS31 PR31B PR32A PR32B PR34A*/VREF1_2 PR34B*/VREF2_2 N30 N29 N26 P26 N32 N31 N27 N28 N34 N33 P28 P27 P32 P31 P30 R29 [12] RDQS58 C D PR17A PR17B PR19A* PR19B* PR20A PR20B PR22A/RDQS22 PR22B PR23A PR23B PR25A* PR25B* PR25E_A/RUM2_GPLLT_FB_A PR25E_B/RUM2_GPLLT_FB_B PR25E_C/RUM2_GPLLT_IN_A PR25E_D/RUM2_GPLLT_IN_B RDQS22 11 12 RDQS49 11 12 U30C 5 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 19. ChannelLink/CameraLink 140 F21 G20 A21 B21 E22 E23 C20 D20 ECP3-95 PT95A PT95B VCCIO1_1 VCCIO1_2 VCCIO1_3 VCCIO1_4 BANK 1 PT83A PT83B PT85A PT85B PT86A PT86B PT98A PT88A PT88B PT98B PT112A PT89A PT112B PT89B PT82A PT82B PT101A PT101B PT103A PT103B PT104A PT104B PT106A PT106B PT107A PT107B PT109A PT91A PT91B PT110A PT110B PT97B PT97A PT118A PT113A PT113B PT115A PT115B PT116A PT116B PT109B PT118B PT119A PT119B PT121A PT121B PT122A PT122B PT124A PT124B PT125A PT125B PT127A PT127B PT128A PT128B PT130A PT130B PT131A PT131B PT133A PT133B PT134A PT134B PT136A/VREF1_1 PT136B/VREF2_1 PT74A PT74B PT76A/PCLKT1_0 PT76B/PCLKC1_0 PT77A PT77B PT79A PT79B PT80A PT80B U30B 5 2_5V A19 B19 K20 L19 C19 D19 J19 K19 A20 B20 G19 H19 D21 E21 H20 J20 A22 B22 J22 J23 C22 D22 J21 G21 A23 B23 F22 G23 C23 D23 K22 K21 A24 B24 H22 H23 D24 E24 K23 K24 A25 B25 C28 D28 C25 D25 G26 G25 B28 A28 A26 A27 A29 A30 H26 H25 A31 B31 C29 C30 L22 L18 M22 M18 D7_P D7_M SEG_N SEG_E SEG_F SEG_T SEG_G SEG_H D5_P D5_M SEG_K SEG_M D4_P D4_M SEG_A A17 B17 E19 E20 A18 B18 J18 H18 D18 E18 D0_P D0_M D1_P D1_M D2_P D2_M DA1_P DA1_M D3_P D3_M DB0_P DB0_M DA0_P DA0_M DB1_P DB1_M DC1_P DC1_M FCLK_P FCLK_M DD1_P DD1_M DC0_P DC0_M DD0_P DD0_M LA5 LA6 GSRN SI570_SCL SI570_SDA SI570_EN LA17 LA15 LA16 LA13 LA14 LA9 LA10 LA11 LA12 LA7 LA8 [7] [7] [7,8] [4,6] [9,12] LA[1..34] LED_SEG[1..17] PCIE_PERSTN [7] TFP410_ISEL [9] LED_SEG1 LED_SEG3 LED_SEG2 LED_SEG9 LED_SEG8 LED_SEG7 LED_SEG6 LED_SEG5 LED_SEG4 D6_P D6_M DCLK_P DCLK_M SEG_B LED_SEG17 SEG_DP LED_SEG16 SEG_S LED_SEG15 SEG_R LED_SEG14 SEG_D LED_SEG13 SEG_U LED_SEG12 BANK 1 (2.5V) [6,8,9,12] D7_M 4 R221 100 R222 100 100 R89 100 R88 100 R219 100 R220 100 R87 100 R86 100 R91 100 R90 100 R85 100 R84 R217 100 R218 100 R215 100 R216 100 100 R83 100 R82 RN18 EXBV8VR000V 165 D0_MS 8 1 165 D0_PS 7 2 165 D1_MS 6 3 165 D1_PS 5 4 RN34 EXBV8VR000V 165 D2_PS 1 8 165 D2_MS 2 7 165 D3_PS 6 3 165 D3_MS 4 5 RN35 EXBV8VR000V 165 DA0_PS 1 8 165 DA0_MS 2 7 165 DA1_PS 3 6 165 DA1_MS 4 5 RN19 EXBV8VR000V 165 DB0_MS 1 8 165 DB0_PS 2 7 165 DB1_MS 3 6 165 DB1_PS 4 5 RN22 EXBV8VR000V 165 DCLK_MS 1 8 165 DCLK_PS 2 7 165 FCLK_MS 3 6 165 FCLK_PS 4 5 RN20 EXBV8VR000V 165 DC1_MS 8 1 165 DC1_PS 2 7 165 DC0_MS 6 3 165 DC0_PS 4 5 RN36 EXBV8VR000V 165 DD0_MS 1 8 165 DD0_PS 7 2 165 DD1_MS 3 6 165 DD1_PS 4 5 RN21 EXBV8VR000V 165 D4_MS 8 1 165 D4_PS 7 2 165 D5_MS 6 3 165 D5_PS 5 4 RN37 EXBV8VR000V 165 D6_PS 1 8 165 D6_MS 7 2 165 D7_PS 6 3 165 D7_MS 4 5 3 For LVDS Tx: Populate CAT16-LV2F6LF instead and remove 100 Ohm Resistor For LVDS Rx: Populate EXBV8VR000V (Zero Ohm Jumper) and 100 Ohm Resistor 140 D7_P D6_M D6_P D5_P D5_M D4_P D4_M DD1_P DD1_M DD0_P DD0_M DC0_P DC0_M DC1_P DC1_M FCLK_P FCLK_M DCLK_P DCLK_M DB1_P DB1_M DB0_P DB0_M DA1_M DA1_P DA0_M DA0_P D3_M D3_P D2_M D2_P D1_P D1_M D0_P D0_M Place close to ECP3 TI ADC 140 A B C D 3 FCLK_MS FCLK_PS DCLK_MS DCLK_PS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 J42 Samtec QSH QSH-060-01-F-D-A [6] TI_ADC0 TI_ADC1 TI_ADC2 TI_ADC3 TI_ADC4 TI_ADC0 TI_ADC1 TI_ADC2 TI_ADC3 TI_ADC4 2 TI_ADC[0..4] 1 2 3 4 5 J13 HEADER 5x1 ADC_RST FPGA_PDN FPGA_SEN FPGA_SDATA FPGA_SCLK 2 1 1 2 3 4 U28 CY2304-1 OUT Vcc 8 7 6 5 GND N/C 2 1 OSC_IN3 OSC_IN4 Y3 OSC OSC 100 MHz 3.3V SMD 50ppm REF FBK CLKA1 VDD CLKA2 CLKB2 GND CLKB1 3 4 FB44 Date: Size C Title C387 1uF, X5R, 6.3V BLM21AG601SN1D FB45 C386 0.1uF 3_3V C385 1uF, X5R, 6.3V BLM21AG601SN1D C384 0.1uF 3_3V SMA_CLK_P OPEN R208 OPEN R198 1 SMA_CLK_N J26 SMA 73391-0060 1 J25 SMA 73391-0060 TX_X1 [10] 33 RX_X1 [10] Y5 OSC OSC 27 MHz 3.3V SMD 25ppm R200 Friday, June 12, 2009 1 Sheet 11 of 16 ECP3 Video Protocol Board Schematic Project 33 [8] [8] [10,14] C370 0.01uF Y4 OSC OSC 27 MHz 3.3V SMD 25ppm R193 SMA_CLK_N SMA_CLK_P OSC_IN[1..4] C369 0.1uF 3_3V B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 TI-ADC / Clocks (N6) (N7) SMA & OSC REF CLKs OSC_IN1 OSC_IN2 C371 0.1uF 3_3V 100MHZ GENERAL PURPOSE CLOCKS 1 2 1 2 4 4 Vcc N/C 1 2 5 140 1 140 2 140 1 35 140 4 140 Vcc 140 N/C 140 1 140 3 140 OUT 140 GND 140 2 140 3 140 OUT 140 GND 1 2 140 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 20. TI-ADC/Clocks 140 A B C D SEG_H LED_SEG4 SEGMENT ------A M K H G T F E N C P U D R S DP B BGA --H20 H19 G19 K19 J19 D19 C19 L19 K20 G18 F19 E18 D18 H18 J18 B18 A18 (U4) PB4 (U5) PB3 (P1) PB2 (P2) PB1 SW10 4 3 3 4 2 4 3 4 3 5 Tactile Switch TL3301SPF160QG 2 1 SW7 Tactile Switch TL3301SPF160QG 2 1 SW8 Tactile Switch TL3301SPF160QG 1 SW9 Tactile Switch TL3301SPF160QG 2 1 R320 4.7K R332 4.7K R316 4.7K R330 4.7K SEG_A SEG_G LED_SEG5 LED_SEG1 SEG_T LED_SEG6 SEG_K SEG_F LED_SEG7 SEG_M SEG_E LED_SEG8 LED_SEG3 SEG_N LED_SEG2 SEG_P SEG_D SEG_U LED_SEG13 LED_SEG12 SEG_C SEG_R LED_SEG14 LED_SEG11 SEG_S LED_SEG15 LED_SEG9 SEG_DP LED_SEG16 LED_SEG10 SEG_B LED_SEG17 TACT SWITCHES SIGNAL -----LED_SEG1 LED_SEG2 LED_SEG3 LED_SEG4 LED_SEG5 LED_SEG6 LED_SEG7 LED_SEG8 LED_SEG9 LED_SEG10 LED_SEG11 LED_SEG12 LED_SEG13 LED_SEG14 LED_SEG15 LED_SEG16 LED_SEG17 LED_SEG[1..17] 3 1 C417 0.1uF 3 1 IN2 IN1 IN2 IN1 OUT2 OUT2 OUT1 PB3 PB4 6 4 R317 4.7K PB2 4 R319 4.7K PB1 R329 4.7K SG_A SG_B SG_C SG_D SG_E SG_F SG_G SG_H SG_K SG_M SG_N SG_P SG_R SG_S SG_T SG_U SG_DP 6 U38 MAX6817 3_3V R333 4.7K EXB28V151JV SG_H 8 SG_K 7 SG_M 6 SG_A 5 EXB28V151JV SG_E 8 SG_F 7 SG_T 6 SG_G 5 EXB28V151JV SG_U 8 SG_P 7 SG_C 6 SG_N 5 U39 MAX6817 OUT1 SG_B EXB28V151JV SG_DP 8 SG_S 7 SG_R 6 SG_D 5 150 3_3V RN28 150 1 2 3 4 RN30 150 1 2 3 4 RN29 150 1 2 3 4 RN27 150 1 2 3 4 R127 C420 0.1uF 16-SEGMENT DISPLAY [9,11] 5 VCC 5 VCC 2 1 16 13 9 8 6 5 4 3 17 15 12 11 7 14 10 18 3_3V LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 LA2 LA4 LA6 LA8 LA10 LA12 LA14 LA16 LA18 LA20 LA22 LA24 LA26 LA28 LA30 LA32 LA34 RN23 4 3 2 1 LA[1..34] [6,8,9,11] DIODE ----D26 D24 D23 D22 D17 D16 D15 D14 D13 D12 D11 D10 LED[1..12] SIGNAL -----LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 [10] LEDs LED1 4 PB[1..4] [8] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 7 7 7 2_5V SWITCH8 SWITCH7 SWITCH6 SWITCH12 SWITCH11 SWITCH10 1 76STC04T SW4A SWITCH9 3 76STC04T SW4B 4 76STC04T SW4C 6 76STC04T SW4D 9 10 12 SWITCH4 SWITCH3 SWITCH2 1 76STC04T SW3A SWITCH5 3 76STC04T SW3B 12 4 76STC04T SW3C 6 76STC04T SW3D 9 10 1 76STC04T SW1A SWITCH1 3 76STC04T SW1B 4 76STC04T SW1C 10 6 76STC04T SW1D 9 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LA2 LA4 LA6 LA8 LA10 LA12 LA14 LA16 LA18 LA20 LA22 LA24 LA26 LA28 LA30 LA32 LA34 J35 HEADER 18x1 SCL SDA CLK 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 PLACE CLOSE TO LA CONNECTOR J36 HEADER 18x1 GND39 GND40 GND41 GND42 GND43 DIP SWITCHES LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 39 40 41 42 43 5V GND CLK1 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 1K 1K 3 [8] EXB28V102JV 5 6 7 8 EXB28V102JV 5 6 7 8 EXB28V102JV 5 6 7 8 SWITCH[1..12] RN25 4 3 2 1 RN24 4 3 2 1 1K SIGNAL SWITCH/POS --------------SWITCH1 SW1-1 SWITCH2 SW1-2 SWITCH3 SW1-3 SWITCH4 SW1-4 SWITCH5 SW3-1 SWITCH6 SW3-2 SWITCH7 SW3-3 SWITCH8 SW3-4 SWITCH9 SW4-1 SWITCH10 SW4-2 SWITCH11 SW4-3 SWITCH12 SW4-4 BGA --Y5 Y4 Y9 Y10 AD2 AD1 AC6 AC7 AM1 AM2 AE1 AE2 COLOR ----Red Orange Green Blue Red Orange Green Blue Red Orange Green Blue LED12 LED11 LED10 LED9 LED8 LED7 LED6 LED5 LED4 LED3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 J29 Mictor Conn LOGIC ANALYZER PROBE 3 LED2 LTP-587HR Lite-On 16-Seg D30 4 1 0 1 0 5 GND 2 GND 2 1 0 5 8 1 0 8 1 0 8 1 0 5 1 0 5 1 0 2 1 0 11 1 0 11 1 0 11 2 1 0 36 2 2 1K BGA --T27 T28 T29 N31 N32 AK32 AL32 AP32 AP33 AN33 AN34 AA31 1K 1K R197 R209 R203 1K 1K 1K 1K 1K R212 R228 R231 R234 R237 1K 1K R250 R247 1K 1K R253 R256 2 2(S) LED6 LED5 LED4 LED3 1(G) Top View SOT-23 3(D) LED2 LED1 10K 10K R235 R238 R248 R251 10K 10K 10K 10K MOSFET N-Channel BSS138LT1G R254 R257 1 1 1 1 1 1 LED7 LED8 LED9 LED10 LED11 Date: Size C Title LED12 10K 10K 10K 10K 10K 10K 1 1 1 1 1 1 Friday, June 12, 2009 1 Sheet 12 of 16 ECP3 Video Protocol Board Schematic Project Q14 MOSFET N GSD BSS138LT1G D10 LED-SMT1206_BLUE R196 680 12_0V Q15 MOSFET N GSD BSS138LT1G D11 LED-SMT1206_GREEN R202 680 12_0V Q16 MOSFET N GSD BSS138LT1G D12 LED-SMT1206_ORANGE R207 680 12_0V Q17 MOSFET N GSD BSS138LT1G D13 LED-SMT1206_RED R211 680 12_0V Q18 MOSFET N GSD BSS138LT1G D14 LED-SMT1206_BLUE R227 680 12_0V B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 R199 R205 R210 R213 R229 R232 Q19 MOSFET N GSD BSS138LT1G D15 LED-SMT1206_GREEN R230 680 12_0V LEDs/Switches/LA Probe Q20 MOSFET N GSD BSS138LT1G D16 LED-SMT1206_ORANGE R233 680 12_0V Q21 MOSFET N GSD BSS138LT1G D17 LED-SMT1206_RED R236 680 12_0V Q23 MOSFET N GSD BSS138LT1G D22 LED-SMT1206_BLUE R246 680 12_0V Q24 MOSFET N GSD BSS138LT1G D23 LED-SMT1206_GREEN R249 680 12_0V Q25 MOSFET N GSD BSS138LT1G D24 LED-SMT1206_ORANGE R252 680 12_0V Q26 MOSFET N GSD BSS138LT1G D26 LED-SMT1206_RED R255 680 12_0V 1 3 2 3 2 3 2 3 A 2 B 3 C 2 D 3 E 2 F 3 G 2 H 3 K 2 M 3 N 2 P 3 R 2 S 3 T 2 U 3 DP 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 21. LEDs/Switches/LA Probe A B C D R184 L4 C356 PCSA_HDOUTN0 [7] C313 0.01uF C307 4.7uF, Tant 0805_1 5 3_3V_SDI_DE SDI_DRV_RSTI DISABLE_CH0 [14] [14] C12 22uF, Tant 0805 + 3_3V_SDI_DE [14] R183 75 DDI DDI VEE RSET C1 22uF, Tant 0805 R156 4.7K + R158 750, 1% 1 2 3 4 C343 0.01uF C65 22uF, Tant 0805 VEE_A_1 SDI SDI VEE_A_4 SDO SDO SD/HD VCC 12 11 10 9 U25 GS2974B 4 [4,9,14] [4,9,14] C297 0.01uF 3_3V_SDI_DE BYPASS_CH0 12 11 10 9 CD_CH0 VEE_D_12 SDO SDO VEE_D_9 R187 4.7K I2C_SCL I2C_SDA U22 LMH0303 C360 0.47uF C359 0.47uF 1 2 3 4 BSS138LT1G Q30 MOSFET N GSD 1 R344 150 3_3V C355 1uF, X5R, 6.3V SDI_DRV_FAULT R185 37.4, 1% C348 1uF, X5R, 6.3V 3_3V_SDI_DE BSS138LT1G Q13 MOSFET N GSD 1 D9 LED-SMT1206_ORANGE R181 150 3_3V_SDI_DE + R152 4.7K 49.9, 1% 49.9, 1% R167 75 6.2nH 0.25pF R173 3_3V_SDI_DE PCSA_HDOUTP0 [7] C317 4.7uF, Tant 0805_1 Driver channel 0 J6 BNC C-SX-069 SDI Rx #0 3 2 3 2 C342 0.01uF R148 4.7K + [14] 75 SD_HD_CH0 R153 75 [14] 6.2nH 75 75 0.25pF C300 4.7uF, Tant 0805_1 R168 R172 R174 L3 C319 C357 4.7uF, Tant 0805_1 [14] PCSA_HDINN0 PCSA_HDINP0 MUTE_CH0 [7] [7] J5 BNC C-SX-069 C312 0.01uF 3_3V_SDI_DE C320 4.7uF, Tant 0805_1 SDI Tx #0 VR3 10K Copal ST32ETB103 Voltage adjustment range : 0.0V to 3.3V Turn clockwise to increase the voltage 3_3V_SDI_DE 2 R182 4.7K C345 4.7uF, Tant 0805_1 3_3V_SDI_DE R186 OPEN [14] 3 3 [7] [7] R147 L1 C290 [14] C332 0.01uF DISABLE_CH1 PCSA_HDOUTN1 PCSA_HDOUTP1 C333 4.7uF, Tant 0805_1 Driver channel 1 J1 BNC C-SX-069 SDI Rx #1 Equalizer channel 1 R180 C334 4.7uF, Tant 0805_1 3_3V_SDI_DE 1 2 3 4 2 C302 0.01uF DDI DDI VEE RSET 2 VEE_A_1 SDI SDI VEE_A_4 I2C_SCL I2C_SDA SDO SDO SD/HD VCC U24 LMH0303 C305 0.47uF C306 0.47uF 1 2 3 4 BSS138LT1G Q29 MOSFET N GSD 1 R343 150 3_3V C294 1uF, X5R, 6.3V R177 750, 1% R175 4.7K R150 37.4, 1% C295 1uF, X5R, 6.3V R151 75 3_3V_SDI_DE 49.9, 1% 49.9, 1% R179 75 6.2nH 0.25pF 3_3V_SDI_DE BSS138LT1G Q12 MOSFET N GSD 1 D8 LED-SMT1206_ORANGE R157 150 3_3V 3 2 3_3V 16 15 14 13 VCC_A CD MUTE VCC_D AGC AGC BYPASS MCLADJ Center PAD 5 6 7 8 17 + + 3 2 Equalizer channel 0 3 1 16 15 14 13 12 11 10 9 U21 GS2974B BYPASS_CH1 C315 0.01uF 3_3V_SDI_DE R161 4.7K 12 11 10 9 CD_CH1 VEE_D_12 SDO SDO VEE_D_9 VCC_A CD MUTE VCC_D AGC AGC BYPASS MCLADJ Center PAD 5 6 7 8 17 C314 0.01uF [14] [7] [7] Friday, June 12, 2009 1 Sheet 13 of 16 B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 C303 0.01uF J2 BNC C-SX-069 SDI Tx #1 3_3V_SDI_DE C291 4.7uF, Tant 0805_1 VR2 10K Copal ST32ETB103 Voltage adjustment range : 0.0V to 3.3V Turn clockwise to increase the voltage PCSA_HDINN1 ECP3 Video Protocol Board Schematic Project [14] PCSA_HDINP1 MUTE_CH1 SDI Drivers and Equalizers SD_HD_CH1 R159 75 Date: Size C 75 75 75 6.2nH 0.25pF C310 4.7uF, Tant 0805_1 R165 R164 R166 L2 C301 Title R163 4.7K + [14] C323 4.7uF, Tant 0805_1 3_3V_SDI_DE 2 R170 4.7K 1 C322 4.7uF, Tant 0805_1 3_3V_SDI_DE R169 OPEN [14] + + 4 + 3 1 5 Center PAD 16 15 14 13 RSTO NC1 NC2 FAULT RSTI ENABLE SDA SCL 5 6 7 8 + 17 Center PAD 16 15 14 13 RSTO NC1 NC2 FAULT RSTI ENABLE SDA SCL + + 5 6 7 8 + 17 37 + A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 22. SDI Drivers and Equalizers 38 TDO_XO TDI_XO [6] [6] BYPASS_CH0 SD_HD_CH0 3_3V [15] GSPI_DO [16] GSPI_DI [15,16] GSPI_CLK [16] TX_GSPI_CSn [13] SDI_DRV_FAULT [15] RX_GSPI_CSn [15,16] GSPI_HST_JTAG [13] DISABLE_CH0 [13] SDI_DRV_RSTI [13] BYPASS_CH1 [13] MUTE_CH1 [13] CD_CH1 [13] [13] MUTE_CH0 [13] CD_CH0 [13] P10 G1 P1 H1 N2 N10 P11 N11 P12 N12 P13 P14 N13 P2 P3 N4 P4 N3 P5 N5 P6 N6 N7 P8 N8 P9 VCCIO0_B5 VCCIO0_A14 VCCIO0_H14 GNDIO0_G14 GNDIO0_B13 GNDIO0_A4 PT3A PT2F PT2E PT2D PT2C PT2B PT2A PR2A PT5C PT5B PT5A PT4F PT4E PT4D PT4C PT4B (PCLK0_1) PT4A (PCLK0_0) PT3D PT3C PT3B PR5D PR5C PR5B PR5A PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR9B PR9A PR8B PR8A PR7D PR7C PR7B PR7A PR6B PR6A B5 A14 H14 G14 B13 A4 B4 A3 B3 A2 C3 A1 B2 A13 A12 B11 A11 B12 A10 B10 A9 A8 B8 A7 A6 A5 G13 F14 F13 E14 E13 D14 D13 C14 C13 B14 C12 N14 M14 L13 L14 M13 K14 K13 J14 J13 H13 3_3V 4 SD_HD_CH1 [13] DISABLE_CH1 [13] TX_REF_LOST [16] TX_LOCK_LOST [16] TX_GS4911_CTRL[1:7] ECP3_XO_SIG5 ECP3_XO_SIG6 ECP3_XO_SIG7 ECP3_XO_SIG8 ECP3_XO_SIG9 ECP3_XO_SIG10 ECP3_XO_SIG11 ECP3_XO_SIG2 ECP3_XO_SIG3 ECP3_XO_SIG4 ECP3_XO_SIG0 ECP3_XO_SIG1 TX_LOCK_GS4915 RX_LOCK_GS4915 [16] [15] TX_GS4915_CTRL6 TX_GS4915_CTRL7 3 TX_GS4911_OUT[1:4] [16] [16] [10] OSC_IN[1..4] [10,11] TX_GS4915_CTRL[0:7] [16] R21 0R I2C_SCL [4,9,13] R20 0R I2C_SDA [4,9,13] ECP3_XO_SIG[0..11] OSC_IN3 OSC_IN4 XO_SDA XO_SCL TX_GS4911_OUT1 TX_GS4911_OUT2 TX_GS4911_OUT3 TX_GS4911_OUT4 TX_GS4915_CTRL0 TX_GS4915_CTRL1 TX_GS4915_CTRL2 TX_GS4915_CTRL3 TX_GS4915_CTRL4 TX_GS4915_CTRL5 TX_GS4911_CTRL1 TX_GS4911_CTRL7 TX_GS4911_CTRL6 TX_GS4911_CTRL5 TX_GS4911_CTRL4 TX_GS4911_CTRL3 TX_GS4911_CTRL2 NOTE: 1. All GPIOs' connection order can be changed for PCB layout. 2. All Clock input pins can be exchaged with each other for PCB layout. VCCIO1_P10 VCCIO1_G1 VCCIO1_P1 GNDIO1_H1 GNDIO1_N2 GNDIO1_N10 PB4A PB4B PB4C PB4D PB5A PB5C PB5D TMS PL9B TCK PB2A PB2B TDO PB2C TDI PB2D PB3A (PCLK1_1) PB3B PB3C (PCLK1_0) PB3D PL5C PL5D (GSRN) PL6A PL6B (TSALL) PL7A PL7B PL7C PL7D PL8A PL8B PL9A PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL5A PL5B 3_3V + POWER FILTER 2 C57 22uF, Tant 0805 C39 0.1uF R15 1K 3_3V C47 0.1uF B7 P7 B6 (2 of 2) TDI_XO TDO_XO TCK_XO TMS_XO Title RN1 1 2 3 4 C38 0.1uF 1K 8 7 6 5 C23 0.1uF GND_N9 GND_B9 N9 B9 3_3V Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 EXB28V102JV C22 0.1uF M12 is NC for E devices C50 0.1uF SLEEPN VCCAUX VCC_P7 VCC_B6 C30 0.1uF M12 3_3V U1-2 XO LCMXO256C-4MN100C 1 C D Date: Size C Friday, June 12, 2009 1 Sheet 14 of 16 ECP3 Video Protocol Board Schematic Project SDI Reference Clock Control B Rev A TCK_XO [6] H2 J1 J2 K1 K2 L1 L2 M1 M2 N1 M3 B1 C1 D2 D1 C2 E1 E2 F1 F2 G2 2 A TMS_XO [6] RX_GS4911_OUT3 RX_GS4911_OUT2 RX_GS4911_OUT1 RX_GS4911_CTRL1 RX_GS4911_CTRL2 RX_GS4911_CTRL3 RX_GS4911_CTRL4 RX_GS4911_CTRL5 RX_GS4911_CTRL6 RX_GS4911_CTRL7 ASR_SEL0 ASR_SEL2 ASR_SEL1 RX_GS4911_OUT[1:3] RX_GS4911_CTRL[1:7] [15] ASR_SEL[0..2] RX_GS4915_CTRL[0:7] U1-1 XO LCMXO256C-4MN100C (1 of 2) 3 B 5 [15] [15] [15] RX_GS4915_CTRL7 RX_GS4915_CTRL6 RX_GS4915_CTRL5 RX_GS4915_CTRL4 RX_GS4915_CTRL3 RX_GS4915_CTRL2 RX_GS4915_CTRL1 RX_GS4915_CTRL0 4 B C D 5 Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 23. SDI Reference Clock Control A B C D C53 0.01uF PLL_GND C42 0.01uF C25 0.01uF Place @ P3 & P54 of GS4911 device 1V8_PLL C31 0.01uF C60 0.01uF C36 0.01uF Place on P5 of GS4911 device C330 0.01uF XTAL_GND 5 C338 0.01uF RX_FSYNC [14] RX_GS4911_OUT[1:3] RX_GS4911_CTRL3 RX_GS4911_CTRL2 RX_GS4911_CTRL1 RX_GS4911_CTRL7 RX_GS4911_CTRL6 RX_GS4911_CTRL5 RX_GS4911_CTRL4 C26 0.01uF C29 0.01uF Place @ P10 & P14 of GS4911 device APLL_GND GND_PAD LOCK_LOST REF_LOST VID_PLL_VDD VID_PLL_GND XTAL_VDD X1 X2 XTAL_GND CORE_GND ANALOG_VDD NC1 ANALOG_GND AUD_PLL_GND AUD_PLL_VDD 10FID HSYNC RX_VSYNC 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RX_GENLOCKn IO_VDD 4 RX_GS4911_OUT1 RX_GS4911_OUT2 RX_GS4911_OUT3 RX_GS4911_RESETn RX_VID_STD4 RX_VID_STD5 RX_GENLOCKn RX_VID_STD0 RX_VID_STD1 RX_VID_STD2 RX_VID_STD3 Default VID_STD[5:0] to 21d = 010101b [9] [9] APLL_GND 1V8_APLL 1V8_APLL XTAL_GND 1V8_PLL PLL_GND XTAL_VDD 1V8_APLL RX_GS4911_CTRL[1:7] XTAL_VDD C52 0.01uF [14] PCLK_GND Place @ P18, 31, 38, 50, 62 of GS4911 device IO_VDD C43 0.01uF 22 R11 0R RX_HSYNC R12 C48 0.01uF [9] R9 1M RX_REF_LOST C59 0.01uF 1V8_PCLK 1 RX_LOCK_LOST 10K Y2 XTAL Citizen CS10-27.000MABJ-UT R8 Q4 MOSFET N GSD BSS138LT1G D3 LED-SMT1206_RED R4 150 3_3V Q3 MOSFET N GSD BSS138LT1G Place @ P45 & P53 of GS4911 device 24pF 39pF 1 3 Place @ P26 & P44 of GS4911 device 4911_CORE_VDD XTAL_GND C18 C17 10K RX LOCK LOST R7 RX REF LOST D4 LED-SMT1206_RED R18 10K PLL_GND 1V8_PLL 1V8_PCLK PCLK_GND 2 3 2 1K 1K EXB28V102JV 1 2 3 4 TP5 RX_TIMING_OUT8 RX_TIMING_OUT7 RX_TIMING_OUT6 RX_TIMING_OUT5 TP1 TP9 RX_TIMING_OUT4 RX_TIMING_OUT1 RX_TIMING_OUT2 RX_TIMING_OUT3 3_3V [8,10] TP3 TP7 [9] 3 BLM21AG601SN1D FB14 BLM21AG601SN1D FB15 [14] PAD RESETb AGND_9 CLKIN_SE SE_IN_VDD(1.8) AGND_6 CLKIN+ CLKIN- PLL_VDD (1.8) AGND_2 REG_VDD (3.3) GND_A_2 VCO_VDD_2 C70 0.01uF C69 0.01uF C75 0.01uF Place on P1 of GS4915 device GND_A_2 C72 0.1uF R32 150K R31 150K R37 1, 1% VCO_VDD_2 CLKOUT- CLKOUT+ AGND_30 U6 GS4915 C82 33uF, Tant 0805 CLKOUT_SE SE_OUT_VDD (1.8) AGND_26 DIFF_OUT_VDD(1.8) + C87 0.01uF FB28 BLM21AG601SN1D FB29 BLM21AG601SN1D C90 0.01uF 1V8_D_2 RX_CLKOUT_SE 3V3_D_2 25 24 23 2 22 C89 0.1uF + C92 0.01uF Place on P23 of GS4915 device BLM21AG601SN1D FB22 BLM21AG601SN1D 1_8V_FLTRD FB23 [14] C352 33uF, Tant 0805 [14] Date: Size C 1 Q6 MOSFET N GSD BSS138LT1G Friday, June 12, 2009 1 Sheet 15 of 16 ECP3 Video Protocol Board Schematic Project B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 10K D5 LED-SMT1206_GREEN R42 150 3_3V SDI Rx Reference Clock GND_D_2 Title R43 RX LOCK C91 0.01uF 1 RX GS4915 STATUS LED Place on P15, P25 of GS4915 device [9] C84 0.01uF 1V8_D_2 RX_SE_REFCLK [10] [10] RX_GS4915_CTRL[0:7] RX_LOCK_GS4915 RX_LOCK_GS4915 R45 Locate close to U1 GND_D_2 GND_A_2 C358 33uF, Tant 0805 VCO_GND_2 RX_GC4915_CLKOUTN 26 21 3 GO1555 NC 1 2 100-ohm Diffential matched pair 1V8_A_2 22 O/P GND2 RX_GC4915_CLKOUTP 27 GND_A_2 VCTR GND6 VCC U5 RX_GS4915_CTRL3 RX_GS4915_CTRL2 RX_GS4915_CTRL1 RX_GS4915_CTRL0 3V3_D_2 + 29 30 28 5 6 7 C76 0.1uF VCO_VDD_2 2 RX_GS4915_CTRL7 RX_GS4915_CTRL6 RX_GS4915_CTRL5 RX_GS4915_CTRL4 GND_D_2 GND_D_2 LOCK GND_22 SE_LVL_VDD(1.8 or 3.3) Place on P3, P7, P27, P32 of GS4915 device 1V8_A_2 RX_GS4915_RESETn 3_3V_FLTRD_2 C351 33uF, Tant 0805 EXB28V102JV 1 2 3 4 EXB28V102JV 1 2 3 4 + C79 0.01uF Place on P38 of GS4915 device C346 100uF, Tant EIA3528 1K RN9 8 7 6 5 + 1K RN11 8 7 6 5 BLM21AG601SN1D FB21 41 ASR_SEL[0..2] GND_A_2 BLM21AG601SN1D 1_8V_FLTRD FB20 3_3V 9 RX_GS4915_RESETn 10 GND_A_2 8 7 RX_CLKIN_SE 3_3V ASR_SEL2 ASR_SEL1 ASR_SEL0 [10] 6 1V8_A_2 4 5 3 2 GND_A_2 1V8_A_2 GND_A_2 1 + C349 10uF, Tant 0805 3_3V_FLTRD_2 Place close to GS4915 RX_PCLK3_N R34 100 BLM21AG601SN1D FB17 FB16 BLM21AG601SN1D [10] RX_PCLK3_P RX_GS4911_PCLK1 1V8_PCLK 4911_CORE_VDD RX_TIMING_OUT8 RX_TIMING_OUT7 RX_TIMING_OUT6 RX_TIMING_OUT5 RX_TIMING_OUT4 IO_VDD RX_TIMING_OUT3 RX_TIMING_OUT2 RX_TIMING_OUT1 PCLK_GND ACLK[1..3] Locate close to GS4911 RN6 33 EXB28V330JV 1 8 2 7 3 6 4 5 RN4 8 7 6 5 RN2 8 7 6 5 ACLK3 ACLK2 ACLK1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EXB28V102JV 1 2 3 4 LVDS/PCLK3_GND PCLK3 PCLK3 LVDS/PCLK3_VDD CORE_VDD_44 TIMING_OUT8 TIMING_OUT7 TIMING_OUT6 TIMING_OUT5 TIMING_OUT4 IO_VDD_38 TIMING_OUT3 TIMING_OUT2 TIMING_OUT1 ASR_SEL0 ASR_SEL1 U2 GS4911B R23 22 R19 22 RX_GSPI_CSn [14] GSPI_DO [14] GSPI_DO_TX [16] GSPI_CLK [14,16] GSPI_HST_JTAG [14,16] RX_GS4911_RESETn 2_5V 3 VCO_VDD_2 38 10K R39 37 R3 150 IO_VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GENLOCK NC3 IO_VDD_62 RESET CS_TMS SDOUT_TDO SDIN_TDI SCLK_TCLK JTAG/HOST PHS_GND PHS_VDD PCLK1&2_VDD PCLK1&2_GND PCLK1 IO_VDD_50 PCLK2 VSYNC IO_VDD_18 FSYNC NC2 VID_STD0 VID_STD1 VID_STD2 VID_STD3 VID_STD4 CORE_VDD_26 VID_STD5 ACLK1 ACLK2 ACLK3 IO_VDD_31 ASR_SEL2 17 IO_VDD 18 19 20 21 22 23 24 25 4911_CORE_VDD 26 27 28 29 30 31 32 IO_VDD 0.1uF RX GS4911 STATUS LEDs 22 22 R30 4 RX_TIMING_OUT[1..8] GND_A_2 40 AGND_40 IPSEL 11 RX_IPSEL C85 3_3V GND_D_2 CP_CTRL/Rset VCO_VDD_2 39 VCO_VDD(2.5) GND_12 12 CP_VDD (2.5) 36 LF D_VDD (1.8) 15 1V8_D_2 BYPASS 13 RX_BYPASS AUTOBYPASSb 14 RX_AUTOBYPASS VCO_GND_2 35 16 VCO_GND 1V8_A_2 RX_FCTRL0 FCTR0 34 17 VCOb 33 VCO RX_FCTRL1 FCTR1 32 DIV_VDD(1.8) GND_A_2 31 AGND_31 GND_20 20 DOUBLE 18 RX_DOUBLE SKEW_EN 19 RX_SKEW_EN 8 GND8 GND4 4 5 22 R29 39 R28 3 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 24. SDI Rx Reference Clock A B C D C311 33uF, Tant 0805 PLL_GND C67 0.1uF C15 OPEN R348 [14] [14] 1 R5 10K 5 1 TX LOCK LOST 10K C340 0.01uF Q1 MOSFET N GSD BSS138LT1G D2 LED-SMT1206_RED R1 150 3_3V Q2 MOSFET N GSD BSS138LT1G 22 65 TX_GENLOCKn LOCK_LOST REF_LOST VID_PLL_VDD VID_PLL_GND XTAL_VDD X1 X2 XTAL_GND CORE_GND ANALOG_VDD NC1 ANALOG_GND AUD_PLL_GND AUD_PLL_VDD 10FID HSYNC GND_PAD TX_FSYNC C40 0.1uF [14] TX_GS4911_OUT[1:4] TX_GS4911_CTRL3 TX_GS4911_CTRL2 TX_GS4911_CTRL1 TX_GS4911_CTRL7 TX_GS4911_CTRL6 TX_GS4911_CTRL5 TX_GS4911_CTRL4 + FB7 BLM21AG601SN1D FB3 BLM21AG601SN1D C32 0.1uF 4 TX_GS4911_OUT1 TX_GS4911_OUT2 TX_GS4911_OUT3 TX_GS4911_OUT4 TX_GS4911_RESETn TX_VID_STD4 TX_VID_STD5 TX_GENLOCKn TX_VID_STD0 TX_VID_STD1 TX_VID_STD2 TX_VID_STD3 Default VID_STD[5:0] to 21d = 010101b [9] [9] APLL_GND 1V8_APLL 1V8_APLL XTAL_GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + C335 10uF, Tant 0805 3_3V_SDI_CLK + C327 10uF, Tant 0805 TX_VSYNC C49 0.01uF 1V8_PLL PLL_GND XTAL_VDD TX_HSYNC R13 R14 0R TX_REF_LOST [9] C46 0.01uF Place @ P45 & P53 of GS4911 device C61 0.01uF TX_LOCK_LOST D1 LED-SMT1206_RED R2 150 3_3V C45 0.01uF Place @ P26 & P44 of GS4911 device TX_GS4911_CTRL[1:7] XTAL_GND [14] OPEN R10 1M C62 0.1uF C51 0.1uF 1V8_PLL C24 0.01uF OSC OSC 27 MHz 3.3V SMD 25ppm Y6 R347 Y1 XTAL Citizen CS10-27.000MABJ-UT TX REF LOST R6 C341 33uF, Tant 0805 PCLK_GND + TX GS4911 STATUS LEDs TX_LOCK_LOST TX_REF_LOST XTAL_GND C423 0.01uF XTAL_VDD 24pF 39pF FB11 BLM21AG601SN1D C16 C337 33uF, Tant 0805 1V8_PCLK FB10 BLM21AG601SN1D C58 0.1uF + C304 0.1uF 1V8_PLL 4911_CORE_VDD FB8 BLM21AG601SN1D XTAL_GND + C344 10uF, Tant 0805 1_8V + C339 10uF, Tant 0805 1_8V + FB2 BLM21AG601SN1D C21 0.1uF 4 FB4 BLM21AG601SN1D IO_VDD + C318 10uF, Tant 0805 1 2 C44 0.1uF 1K 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RN7 1 2 3 4 EXB28V102JV 1 2 3 4 EXB28V102JV 1 2 3 4 1V8_PCLK 4911_CORE_VDD TX_TIMING_OUT8 TX_TIMING_OUT7 TX_TIMING_OUT6 TX_TIMING_OUT5 TX_TIMING_OUT4 IO_VDD TX_TIMING_OUT3 TX_TIMING_OUT2 TX_TIMING_OUT1 TX_TIMING_OUT7 TX_TIMING_OUT8 TP6 TX_TIMING_OUT6 TP8 TX_TIMING_OUT5 TX_TIMING_OUT1 TX_TIMING_OUT2 TX_TIMING_OUT3 TX_TIMING_OUT4 3_3V FB19 FB18 BLM21AG601SN1D 3 7 1V8_A 3 BLM21AG601SN1D FB13 BLM21AG601SN1D FB12 3_3V BLM21AG601SN1D FB26 PAD C80 0.01uF R35 150K R33 150K C20 0.1uF C88 0.01uF R38 1, 1% C74 0.1uF C73 0.01uF CLKOUT- CLKOUT+ AGND_30 U7 GS4915 C81 33uF, Tant 0805 C28 0.01uF FB31 BLM21AG601SN1D FB30 BLM21AG601SN1D C71 0.01uF GND_D 1V8_D TX_CLKOUT_SE 3V3_D GND_D 25 24 23 22 C66 100uF, Tant EIA3528 C361 33uF, Tant 0805 2 R46 22 FB25 BLM21AG601SN1D FB27 BLM21AG601SN1D C96 0.01uF Place on P23 of GS4915 device C78 0.1uF C93 0.1uF [14] Date: Size C Title [9] 10K 1 C95 0.01uF Q5 MOSFET N GSD BSS138LT1G D6 LED-SMT1206_GREEN Friday, June 12, 2009 1 Sheet 16 of 16 ECP3 Video Protocol Board Schematic Project B Rev Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon. 97124 C83 0.01uF Place on P15, P25 of GS4915 device R44 TX LOCK R41 150 3_3V TX GS4915 STATUS LED 1 SDI Tx Reference Clock C353 33uF, Tant 0805 GND_D + 1V8_D [14] TX_SE_REFCLK TX_GS4915_CTRL[0:7] TX_LOCK_GS4915 1_8V_FLTRD FB9 BLM41PG600SN1L [7] [7] Locate close to U1 TX_LOCK_GS4915 GND_D GND_A 26 21 1V8_A 27 GND_D + 100-ohm Diffential matched pair VCO_GND TX_GC4915_CLKOUTN 3V3_D + 3 2 1 GO1555 NC TX_GC4915_CLKOUTP TX_GS4915_CTRL3 TX_GS4915_CTRL2 TX_GS4915_CTRL1 TX_GS4915_CTRL0 1_8V O/P GND2 29 VCTR GND6 VCC U8 GND_A 5 6 7 C77 0.1uF VCO_VDD 28 30 2 TX_GS4915_CTRL7 TX_GS4915_CTRL6 TX_GS4915_CTRL5 TX_GS4915_CTRL4 LOCK GND_22 SE_LVL_VDD(1.8 or 3.3) CLKOUT_SE SE_OUT_VDD (1.8) AGND_26 DIFF_OUT_VDD(1.8) + C27 0.01uF 1V8_APLL Place @ P10 & P14 of GS4911 device VCO_VDD C94 0.01uF Place on P1 of GS4915 device C68 0.01uF Place on P3, P7, P27, P32 of GS4915 device TX_GS4915_RESETn 3_3V_FLTRD C347 100uF, Tant EIA3528 GND_A + GND_A + C354 33uF, Tant 0805 EXB28V102JV 1 2 3 4 EXB28V102JV 1 2 3 4 41 RESETb AGND_9 CLKIN_SE SE_IN_VDD(1.8) AGND_6 CLKIN+ CLKIN- C326 33uF, Tant 0805 Place on P38 of GS4915 device PLL_VDD (1.8) AGND_2 + 1V8_APLL APLL_GND REG_VDD (3.3) 1V8_A 1K 1K BLM21AG601SN1D FB24 1_8V_FLTRD RN8 8 7 6 5 RN10 8 7 6 5 GND_A TX_GS4915_RESETn 10 9 8 6 GND_A 4 5 2 1 + C350 10uF, Tant 0805 VCO_VDD 1V8_A GND_A FB6 BLM21AG601SN1D GND_A 3_3V_FLTRD FB5 BLM21AG601SN1D C35 0.1uF BLM21AG601SN1D 2_5V TX_CLKIN_SE 3_3V [10] TX_PCLK3_N R36 100 TX_PCLK3_P 3 + C329 10uF, Tant 0805 1_8V Place close to GS4915 [10] [9] C37 0.01uF TX_GS4911_PCLK1 TP4 EXB28V330JV 8 7 6 5 C55 0.01uF TX_GS4911_RESETn C63 0.01uF TP2 33 C54 0.01uF PCLK_GND R24 22 R22 22 C33 0.01uF Locate close to GS4911 RN5 8 7 6 5 RN3 8 7 6 5 1K LVDS/PCLK3_GND PCLK3 PCLK3 LVDS/PCLK3_VDD CORE_VDD_44 TIMING_OUT8 TIMING_OUT7 TIMING_OUT6 TIMING_OUT5 TIMING_OUT4 IO_VDD_38 TIMING_OUT3 TIMING_OUT2 TIMING_OUT1 ASR_SEL0 ASR_SEL1 U3 GS4911B C331 0.01uF Place on P5 of GS4911 device Place @ P18, 31, 38, 50, 62 of GS4911 device IO_VDD C19 0.1uF TX_GSPI_CSn [14] GSPI_DO_TX [15] GSPI_DI [14] GSPI_CLK [14,15] GSPI_HST_JTAG [14,15] C336 33uF, Tant 0805 IO_VDD C325 33uF, Tant 0805 XTAL_GND + XTAL_VDD PLL_GND 1V8_PLL 1V8_PCLK PCLK_GND 3_3V_SDI_CLK IPSEL 11 Place @ P3 & P54 of GS4911 device VCO_VDD(2.5) GND_12 12 5 1 4 Vcc N/C IO_VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 IO_VDD 18 19 20 21 22 23 24 25 4911_CORE_VDD 26 27 28 29 30 31 32 10K CP_VDD (2.5) BYPASS 13 TX_IPSEL GENLOCK NC3 IO_VDD_62 RESET CS_TMS SDOUT_TDO SDIN_TDI SCLK_TCLK JTAG/HOST PHS_GND PHS_VDD PCLK1&2_VDD PCLK1&2_GND PCLK1 IO_VDD_50 PCLK2 VSYNC IO_VDD_18 FSYNC NC2 VID_STD0 VID_STD1 VID_STD2 VID_STD3 VID_STD4 CORE_VDD_26 VID_STD5 ACLK1 ACLK2 ACLK3 IO_VDD_31 ASR_SEL2 IO_VDD VCO_VDD AUTOBYPASSb 14 TX_BYPASS FB1 BLM21AG601SN1D 22 22 R27 GND_A 40 AGND_40 VCO_VDD D_VDD (1.8) 15 1V8_D TX_AUTOBYPASS 39 VCO_GND FCTR0 16 TX_FCTRL0 38 C86 VCOb FCTR1 17 TX_FCTRL1 8 GND8 GND4 4 1_8V TX_TIMING_OUT[1..8] 36 LF R40 37 CP_CTRL/Rset VCO_GND DOUBLE 18 34 SKEW_EN 19 TX_DOUBLE 35 0.1uF 33 VCO GND_A 31 AGND_31 1V8_A 32 DIV_VDD(1.8) GND_20 20 TX_SKEW_EN GND_D 3 OUT GND 2 3 2 3 2 22 R26 40 R25 3 2 A B C D Lattice Semiconductor LatticeECP3 Video Protocol Board – Revision B User’s Guide Figure 25. SDI Tx Reference Clock