LatticeECP2M™ SMPTE SDI Evaluation Board User’s Guide December 2007 Revision: EB27_01.4 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Introduction The key circuits inside the LatticeECP2M devices and the features of the SMPTE SDI Evaluation Board help audio and video engineers with prototyping and testing their specific designs. For example, the integration of multi-gigabit serial transceivers and advanced I/O features has enabled the support of many more networking standards than previously possible. This now includes HD-SDI (SMPTE292M), SDI (SMPTE259M), and DVB-ASI, as well as others. This user’s guide describes the LatticeECP2M SMPTE SDI Evaluation Board featuring the LatticeECP2M LFE2M35-FF672 FPGA device. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to demonstrate SMPTE 259 and 292 capabilities The board demonstrates that it is now viable to integrate HD-SDI, SDI and DVB-ASI encoders and decoders into an FPGA. The evaluation board includes provisioning to connect SERDES channels via standard video BNC connectors to test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 75-ohm for differential traces SERDES connected to video channels. The PCB can be equipped with any LatticeECP2M device offered in the 672-ball fpBGA package. The board limitations are based on the FPGA array included on the board. The board has several debugging and analyzing features for complete customer evaluations of the LatticeECP2M device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeECP2M FPGA. Figure 1. LatticeECP2M SMPTE SDI Evaluation Board 2 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Features • For LatticeECP2M-35 and LatticeECP2M-50 Devices: – Video interface for interconnection to video standard equipment – Provide SATA interfaces to SERDES channels – Allow demonstration of PCI Express (x1) interfaces – Allow the demonstration of LVDS I/O signal integrity performance for rates up to 1Gbps – Allow control of SERDES PCS registers using the Serial Client Interface (ORCAstra) – On-board Boot Flash; both Serial SPI Flash and Parallel Flash via MachXO™ programming bridge – Show interoperation with high performance DDR2 memory components – Have a driver based “run-time” device configuration capability via a ORCAstra or RS232 interface – SMAs for external high-speed clock / PLL inputs – Switches, LEDs, displays for demo purposes – Input connection for lab-power supply – Power connections and power sources – ispVM® programming support – On-board and external reference clock sources – ORCAstra Demonstration Software interface via standard ispVM JTAG connection – Various high-speed layout structures – User-defined input and output points – SMA connectors included (10) for high-speed clock or data interfacing – Performance monitoring via test headers, LEDs and switches • For LatticeECP2M-50 Only: – Additional SERDES connection for video channel allowing loop timing recovery using dual quad approach – On-board, inter-channel loop back between two SERDES channels – SERDES channel connection to DC coupled SMAs for SERDES performance monitoring and testing The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 1 shows the functional partitioning of the board. Figure 2. LatticeECP2M SMPTE SDI Evaluation Board Outline Drawing 3 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Figure 3. LatticeECP2M SMPTE SDI Evaluation Board JTAG SPI Flash On-Board Stuffing Options to Determine Clock Connectivity Video Duplex Channel 18-bit DDR2 18-bit DDR2 Parallel Flash SMAs 75-ohm CH3 GS4911 GS4915 CH1 FPGA I/O VCO CH2 CFG Upper 27M Osc SATA Host SATA Target FPGA CH0 Differential U_Refclk L_Refclk Two Instances CH1 Video Duplex Channel CH2 75-ohm Lower CH0 SMAs FPGA I/O CH3 Single-ended 8 Differential Loops Gennum Control and Status 8 Switches 16-Segment Display PCI Express x1 Edge 8 LEDs Rx and Tx Video Connetions LatticeECP2M Device This board features a LatticeECP2M FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeECP2M devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP2M Family Data Sheet on the Lattice website at www.latticesemi.com. Note: The connections referenced in this document refer to the LFE2M35E-FF672 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. However, only the LFE2M50E-FF672 device allows full use of the high-speed SERDES test SMAs and SMPTE BNC connections. Applying Power to the Board The LatticeECP2M PCI Express Evaluation Board is ready to power on. The Evaluation Board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench top supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory supplied wall transformer, simply connect the output connection of the power cord to J1 and plug wall-transformer into an AC wall outlet. 4 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Power Supplies (see Appendix A, Figure 9) The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided to use with a bench top supply adjusted to provide a nominal 12V DC. All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies Table 1. Board Power Supply Fuses (see Appendix A, Figure 9) F1 1.2V Core Fuse F2 1.5V Fuse F3 3.3V Fuse F4 1.2V Fuse F5 2.5V Fuse F6 1.8V Fuse Table 2. Board Power Supply Indicators (see Appendix A, Figure 9) D1 2.5V Source Good Indicator D2 3.3V Source Good Indicator D3 12V Input Good Indicator D4 1.2V VCC Core Source Good Indicator D5 1.5V Source Good Indicator D6 1.8V Source Good Indicator D7 1.2V Source Good Indicator External power can be alternatively connected rather than the wall transformer power pack Table 3. Board Supply Disconnects (see Appendix A, Figure 9) TB1 Screw terminal for 12V DC Pin1 (square PCB pad) → 12V DC Pin2 → Ground PCI Express Power Interface Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power from a PCI Express host board. Programming/FPGA Configuration (see Appendix A, Figure 11) A programming header is provided on the evaluation board, providing access to the LatticeECP2M JTAG port. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2M FPGA device and render the board inoperable. An ispDOWNLOAD® cable is included with each ispLEVER® design tool shipment. Cables may also be purchased separately from Lattice. 5 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor ispVM Download Interface J8 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control the device. Table 4. ispVM JTAG Connector (see Appendix A, Figure 9) Pin 1 VCC Pin 2 TDO Pin 3 TDI Pin 4 PROGRAMN Pin 5 NC Pin 6 TMS Pin 7 GND Pin 8 TCK Pin 9 DONE Pin 10 INITN Programming Daisy Chain This board includes two Lattice Semiconductor programmable (U1 = LatticeECP2M, U29 = LCMXO1200) devices that can be programmed in a daisy chain. A jumper setting of J120 controls the chain. Both devices are in the programming chain from the JTAG header J8 with jumpers on J120 across Pins {1-2}, Pins {3-4}, and Pins {5-6}. Also a jumpers on J121 across Pins {1-2}, Pins {3-4} are also required for both devices to be in the chain. If the user desires to only program U1, J120 requires jumpers across Pins {1-2} and Pins{3-5}, J10 requires only a jumper should be across Pins {1-2}. Download Procedures Requirements: • PC with ispVM System v.16.0 (or later) programming management software, installed with appropriate drivers (USB driver for USB cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD cable). Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.) JTAG Download The LatticeECP2M device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the ispDOWNLOAD cable to the appropriate header. J8 is used for the 1x10 cable. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2M FPGA device and render the board inoperable. 2. Connect the LatticeECP2M Evaluation Board to the appropriate power sources and power-up the board. 3. Start the ispVM System software. 4. Press the SCAN button located in the toolbar. The LatticeECP2M device should be automatically detected. 6 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Figure 4. ispVM Programming Window 5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. Figure 5. ispVM Device Information Window 6. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. 7 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Configuration Status Indicators (see Appendix A, Figure 11) These LEDs indicate the status of configuration to the FPGA. • D8 (RED) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low. • D11 (GREEN) is illuminated, this indicates the successful completion of configuration by releasing the open collector DONE output pin. • D12 (GREEN) will flash indicating TDI activity. • D10 (RED) illuminated, this indicates that PROGRAMN is low. • D9 (RED) illuminated, this indicates that GSRN is low. PROGRAMN & GSRN (see Appendix A, Figure 11) These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2). Depressing the button drives a logic level “0” to the device. The GSRN push-button is connected to a general purpose FPGA pin (BGA AA20). It must be specifically included by the user in the FPGA design, if needed. CFG [2:0] (see Appendix A, Figure 11) The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG programming is independent of the MODE pins and is always available to the user. Pushing in (depressing) the switch is ON and sets the value to 0. Table 5. CFG Mode Selections CFG2 CFG1 CFG0 Configuration Mode 0 (ON) 0 (ON) 0 (ON) SPI Flash Mode (available on-board) 0 (ON) 1 (OFF) 0 (ON) SPIm 1 (OFF) 0 (ON) 0 (ON) Master Serial 1 (OFF) 0 (ON) 1 (OFF) Slave Serial 1 (OFF) 1 (OFF) 0 (ON) Master Parallel 1 (OFF) 1 (OFF) 1 (OFF) Slave Parallel X (don’t care) X (don’t care) X (don’t care) ispJTAG On-Board Flash Memory (see Appendix A, Figure 11) One SPI (16-pin TSSOP 64M) Flash memory devices (U12) is on board for non-volatile configuration memory storage. The CFG [2:0] need to be [000] all depressed and J60 jumper installed on pins 2-3. A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO CPLD device to act as a programming bridge from the Flash device. The CFG [2:0] needs to be [111] all up and J60 jumper installed on pins 12. 8 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Video Clock Management (see Appendix A, Figures 16 and 17) Industry standard video clocks are generated and managed via Gennum chipsets. These chipsets are used to generate both transmit and receive clocks. The GS4911 clock generator device produces multiple video standard reference clocks from an on-board 27MHz oscillator. This device can also receive input clock from an external clock source via a SMA. The GS4915 clock cleaner is used to reduce clock jitter to produce a clean clock for video signal quality using a high performance VCO. Both the GS4911 and GS4915 are controlled by on-board switches and connections to the FPGA. Device status is also observed from LED indicators. Table 6. Gennum Clock Device Control and Status Components GS4911 Clock Gen GS4915 Clock Cleaner Video Clock Selection Switch Control Switch Ref Clk Lost Lock Lost Lock TX Clock U24 U22 SW11 SW7 D23 D24 D25 RX Clock U27 U26 SW10 SW8 D26 D27 D28 Both GS4911 clock generator devices use a DIP switch (SW10 and SW11) to control the desired frequency generated by the devices. These switches control the VID[0:5] as outlined in Table 20 of the GS4911B/GS4910B data sheet. Figure 6. VID Switch Position (SW10 and SW11) 1 1 2 3 4 5 6 0 The control signals to the Gennum Clock chipsets can also be controlled via the FPGA. Table 7 outlines the connections between the Gennum Clocking devices and the FPGA. 9 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Table 7. Gennum Clock Devices to FPGA Interconnections GS4911B- Schematic Designator U27 Signal GS4911B- Schematic Designator U24 Clock Pin Name FPGA Pin Clock Pin Name FPGA Pin rx_gs4911_ctrl_0 RESETn F7 tx_gs4911_ctrl_0 Signal RESETn C8 rx_gs4911_ctrl_1 GENLOCKn G9 tx_gs4911_ctrl_1 GENLOCKn G12 rx_gs4911_ctrl_2 VID_STD5 C4 tx_gs4911_ctrl_2 VID_STD5 D8 rx_gs4911_ctrl_3 VID_STD4 B2 tx_gs4911_ctrl_3 VID_STD4 H12 rx_gs4911_ctrl_4 VID_STD3 C5 tx_gs4911_ctrl_4 VID_STD3 A6 rx_gs4911_ctrl_5 VID_STD2 B3 tx_gs4911_ctrl_5 VID_STD2 A5 rx_gs4911_ctrl_6 VID_STD1 E7 tx_gs4911_ctrl_6 VID_STD1 A4 rx_gs4911_ctrl_7 VID_STD0 H10 tx_gs4911_ctrl_7 VID_STD0 A3 rx_gs4911_out_1 TIMING_OUT1 E10 tx_gs4911_out_1 TIMING_OUT1 D10 rx_gs4911_out_2 TIMING_OUT2 F12 tx_gs4911_out_2 TIMING_OUT2 F13 rx_gs4911_out_3 TIMING_OUT3 A8 tx_gs4911_out_3 TIMING_OUT3 E11 rx_gs4911_out_4 TIMING_OUT4 B9 tx_gs4911_out_4 TIMING_OUT4 G14 rx_gs4911_out_5 TIMING_OUT5 E8 tx_gs4911_out_5 TIMING_OUT5 B10 rx_gs4911_out_6 TIMING_OUT6 A9 tx_gs4911_out_6 TIMING_OUT6 A10 rx_gs4911_out_7 TIMING_OUT7 H14 tx_gs4911_out_7 TIMING_OUT7 H15 rx_gs4911_pclk PCLK2 F14 tx_gs4911_pclk PCLK2 C11 rx_hsync HSYNC H16 tx_hsync HSYNC A11 SE_CLKOUT C12 VSYNC A12 rx_se_refclkGS4515 SE_CLKOUT G15 tx_se_refclk rx_vsync VSYNC D12 tx_vsync fsync FSYNC H18 A control interface to the clock devices is connected to the FPGA to dynamically control the video clocking modes. This control bus GSPI uses a simple 3-pin interface to control the GS4911 clock generators. A chip select is used to pick which clock device is being controlled. Table 8. Gennum Serial Peripheral Interface GSPI Bus FPGA Pin RX GSPI CSn G7 TX GSPI CSn G8 GSPI CLK F8 GSPI DI J10 GSPI DO D4 SW7 and SW8 DIP switches can be used to set the control signals to the Gennum clock devices. SW7 controls the TX chipsets and SW8 controls the RX chipsets. Figure 7. Gennum Clocking Control Switches ON 1 2 3 4 5 6 10 7 8 9 10 OFF LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Table 9. Gennum Clock Control Switch Connections SW8 Control Switches SW7 Control Switches 1 TX RESET GS4911 2 TX RESET GS4915 2 RX RESET GS4915 3 TX SKEW EN 3 RX SKEW EN 4 TX DOUBLE 4 RX DOUBLE 5 TX FCRTL1 5 RX FCRTL1 6 TX FCTRL0 6 RX FCTRL0 7 TX AUTOBYPASS 7 RX AUTOBYPASS 8 TX BYPASS 8 RX BYPASS 9 TX IPSEL 9 RX IPSEL 10 TX GENLOCKN 10 RX GENLOCKN 1 RX RESET GS4911 Clock Status Indicators The board includes several LED indicators that are used to monitor the status of the Gennum clock devices. Table 10. Gennum Clock Device Status Indicators Indicator LED Designation Description TX REF LOST D23 Will light GREEN when TX GS4911(U24) REF_LOST pin is high. This indicates no reference signal applied to device or other conditions. Refer to GS4911 data sheet. Otherwise, it will be RED. TX LOCK LOST D24 Will light GREEN if the GS4911(U24) LOCK_LOST is high indicating the output is not Genlocked to the input. Otherwise. it will be RED. TX LOCK D25 RED indicates the TX GS4915(U22) LOCK pin is high which indicates the output clock is locked to the selected input. Otherwise it will be GREEN. RX REF LOST D26 Will light GREEN when TX GS4911(U27) REF_LOST pin is high. This indicates no reference signal applied to device or other conditions. Refer to GS4911 data sheet. Otherwise it will be RED. RX LOCK LOST D27 Will light GREEN if the GS4911(U27) LOCK_LOST is high indicating the output is not Genlocked to the input. Otherwise, it will be RED. RX LOCK D28 RED indicates the TX GS4915(U26) LOCK pin is high which indicates the output clock is locked to the selected input. Otherwise, it will be GREEN. 11 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor SERDES (see Appendix A, Figure 13) SERDES Reference Clocks Note: This board supports many application specific SERDES capabilities. The board has to be provisioned correctly comply with the appropriate clock rate required for the particular application. The 50-ohm terminated SMA connectors are provided the supply reference clocks directly to the LatticeECP2M device. These SMAs are board provisioned by resistor shunt connections that can be optionally removed. Table 11. SERDES Reference Clocks Connector SERDES Signal FPGA Pin Resistor Shunt J14 U_REFCLKP D19 R67 J15 U_REFCLKN E19 R69 J106 L_REFCLKP AC191 R223 J107 L_REFCLKN AB191 R225 1. Pins only available with LatticeECP2M-50 device. The user must provision the board correctly to select the proper clocking for the application. This is done by removal or shunting of SMT resistor pads. For PCI Express the clock is sourced from the PCI Express edge connection. For SMPTE the clocks are generated from the Gennum Video Clock sources. Table 12 outlines the different clock provisioning per application. Table 12. Reference Clock Source Selection R79 R80 R262 R263 R334 R335 SMPTE open open shunt shunt shunt shunt PCI Express shunt shunt open open open open SATA open open open open open open Note: SATA must be clocked via an external clock source from the SMA clock inputs. SERDES Channels Video Interface Connections The 75-ohm terminated BNC edge launch connectors provide the video signals directly to the LatticeECP2M device. Table 13. SERDES Video Interconnections Connector SERDES Signal FPGA Pin J18 U_HDINP3 J21 U_HDINN3 B14 J19 U_HDOUTP3 A17 J22 U_HDOUTN3 J24 L_HDINP3 AF171 J26 L_HDINN3 AE171 J25 L_HDOUTP3 AF141 J27 L_HDOUTN3 AE141 1. Pins only available with LatticeECP2M-50 device. 12 A14 B17 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Surface Mounted SMA Connections (see Appendix A, Figure 12) DC coupled top-mounted SMA connectors connect to the four SERDES Tx and Rx channels. These pins are directly coupled to the designated SMA connector creating a path for both input and output differential data. Table 14. SERDES Connectors (see Appendix A, Figure 12) SMA Channel Name FPGA Pin SMA Channel Name FPGA Pin J112 L_HDINP2 AF15 J113 L_HDOUTP3 AF18 J114 L_HDINN2 AE15 J115 L_HDOUTN3 AE18 Note: Only available with the LatticeECP2M-50 device. SERDES SATA Channels (see Appendix A, Figure 12) The board contains two SATA host connectors that can be connected to a SATA device (such as a hard disk) using a standard SATA cable. The SATA connectors are connections that are included to attach SATA type cables to SERDES channels for board-to-board or loopback purposes. The connectors are configured using the 7-pin SATA specifications. The SATA physical interface can carry SERDES signals up to 1.5 Gbps for general-purpose usage. The board ships with a SATA cable that is used as a loopback connection between the two SATA connectors for loopback testing and bit error rate testing (BERT). The SATA crossover cable can also be used to connect between two boards. Table 15. SERDES SATA Interconnections Host Pin Name Target SERDES Pin FPGA Pin Pin Name SERDES Pin FPGA Pin OUT_HOST+ U_HDOUTP1 A20 OUT_HOST- U_HDOUTN1 B20 OUT_TARGET+ U_HDOUTP2 A18 OUT_TARGET- U_HDOUTN2 B18 IN_HOST+ U_HDINP1 A23 IN_HOST- U_HDINN1 B23 IN_TARGET+ U_HDINP2 A15 IN_TARGET- U_HDINN2 B15 SERDES PCI Express Channels (see Appendix A, Figure 12) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections. Table 16. SERDES PCI Express Interconnections Pin Name FPGA Pin PCI Express Edge U_HDOUTP_0 A21 A16 U_HDOUTN_0 B21 A17 U_HDINP_0 A24 B14 U_HDINN_0 B24 B15 U_REFCLKP D19 A13 U_REFCLKN E19 A14 AA20 A11 PCIE_PERSETN Description Integrated Endpoint block transmit pair Integrated Endpoint block receive pair Integrated Endpoint block differential clock pair Fundamental PCI Express Reset 13 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Low Speed Video Connections (see Appendix A, Figure 20, J124 and J125) 3M™ Mini D Ribbon (MDR) Cables are used in conjunction with the on-board MDR-26(p/n 10226-1210VE) Tx and Rx connectors. These connections include five LVDS pairs (four data pairs and one clock pair). All five Tx pairs are assigned to the pins using the same edge clock. It’s the same for the five Rx pairs. The Rx clock input pair is assigned to the dedicated PLL clock input. Table 17. MDR Connector to FPGA I/O Video TX- J124 FPGA Pin Video RX J125 FPGA Pin TX OUT0+ F21 RX IN0+ M24 TX OUT0- H20 RX IN0- M22 TX OUT1+ F22 RX IN1+ L24 TX OUT1- J18 RX IN1- L22 TX OUT2+ K19 RX IN2+ L26 TX OUT2- G22 RX IN2- M26 TX OUT3+ H24 RX IN3+ N25 TX OUT3- H23 RX IN3- N24 TX CLKOUT+ E23 RX CLKIN+ K26 TX CLKOUT- E24 RX CLKIN- K25 FPGA Test Pins (see Appendix A, Figure 20) General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS designated according to Table 18. Push-button switches are available for connection to general purpose FPGA pins. The switches are debounced and can be used for user designs. Table 18. FPGA Test pins (see Appendix A, Figure 14) Switch BGA Netname LED BGA SW6D T3 Switch1 D16 U3 RED1 SW6C T4 Switch2 D17 U4 YELLOW1 SW6B P8 Switch3 D19 U5 GREEN1 SW6A R6 Switch4 D21 U6 BLUE1 NetName SW5D T1 Switch5 D15 U2 RED2 SW5C U1 Switch6 D18 V1 YELLOW2 SW5B R7 Switch7 D20 W2 GREEN2 SW5A T5 Switch8 D22 V2 BLUE2 SW12 AD26 PB1 SW13 AC23 PB2 SW14 AC25 PB3 SW15 W20 PB4 Note: LEDs will illuminate if connected to an unprogrammed FPGA pin. It is recommended that a pull-down be programmed on FPGA output pins. 14 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor LCD Interface (see Appendix A, Figure 19) A 2x8 Header (J126) provides a connection to 16-character x 2 line LCD modules such as Varitronix VDM16265. A ribbon cable connection will allow attachment to the connector. The board includes two variable resistors for LCD adjustments. VR1 adjusts the backlight and VR2 provides contrast adjustment. A user design must be included in the FPGA to drive this feature. This header can also be used for probe points for observing FPGA pins. Table 19. Header J26 Pin Connections NetName 672-Ball BGA Header Pin Number LCD0 AA3 7 LCD1 Y21 9 LCD2 Y5 11 LCD3 AB2 13 LCD4 AA4 15 LCD5 Y6 6 LCD6 U9 8 LCD7 AA5 10 LCD8 AA6 12 LCD9 Y7 14 LCD10 V9 16 17-Segment LED Display (see Appendix A, Figure 17) General-purpose FPGA pins are connected to a 17-segment display according to Table 20. These pins can be driven low to illuminate the display segments. Table 20. 17-Segment LED Display Segment BGA A W16 B AC20 C AB20 D AB17 E W15 F AC17 G Y15 H AA15 K AB16 M AC16 N AB15 P AC15 R AA14 S AB14 T AC14 U Y14 DP AC13 A H B K M N U G 15 P T S F C R E D DP LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Test SMA Connections General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit evaluations of several types of FPGA I/O buffers. The use of several termination schemes permits easy interfaces for the type of buffer. Table 21. FPGA I/O Test SMA Connectors (see Appendix A, Figure 16) Name LFE2M35E Signal J37 LVDS_INP0 PR37A N23 J39 LVDS_INN0 PR37B M21 J41 LVDS_INP1 PR41A P24 J43 LVDS_INN1 PR41B P23 J45 LVDS_INP2 PR51A T24 J47 LVDS_INN2 PR51B U24 J49* LVDS_INP3 PR57A V24 J51* LVDS_INN3 PR57B W24 J38 LVDS_OUTP0 PR50A T23 J40 LVDS_OUTN0 PR50B T22 J42 LVDS_OUTP1 PR53A V26 J44 LVDS_OUTN1 PR53B V25 J46 LVDS_OUTP2 PR55A W26 J48 LVDS_OUTN2 PR55B W25 J50 LVDS_OUTP3 PR59A Y26 J52 LVDS_OUTN3 PR59A AA26 SMA Designation 672-Ball fpBGA Termination Description Termination Resistor(s) 100-ohm Differential R130 100-ohm Differential R132 100-ohm Differential R134 100-ohm Differential R136 100-ohm Differential R131 100-ohm Differential R133 100-ohm Differential R135 100-ohm Differential R137 High Speed Test Point DP1 (see Appendix A, Figure 16) General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance probe to measure the performance of a coupled-differential output buffer pair. Logic Analyzer Probe (see Appendix A, Figure 19) An AMP/TYCO 767004 38 position 0.025 VERT SMD logic analyzer probe connection is provided for the user to utilize for test points. This connection provides 34 general I/O signals to be observed on a Logic Analyzer probes using Mictor connections such as the Agilent 5346A. General Purpose I/O/sysCONFIG Header (see Appendix A, Figure 19) Header J6 is available to access configuration and dual purpose FPGA pins. This header provides probe points to the specific pins. 16 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor Table 22. J6 Header Pinout Crossover Net Name 672-Ball BGA Header Pin Net Name CCLK AB241 1 GND 672-Ball BGA Header Pin 2 SISPI Y24 3 N/C 4 CSSPI0N V20 5 3.3V 6 1 CSSP1N W23 7 INITN AA23 8 DONE AB251 9 PROGRAMN AC261 10 D7 W21 11 GND 12 D6 AA24 13 GND 14 D5 Y23 15 GND 16 D4 W18 17 GND 18 D3 W22 19 GND 20 D2 Y20 21 GND 22 D1 W19 23 GND 24 D0 Y22 25 GND 26 CSN AB26 27 WRITE Y19 28 CS1 Y21 29 CFG0 AB231 30 3.3V 31 CFG1 AA221 32 GND 33 CFG2 AA211 34 1. This pin cannot be used for any other purpose. Table 23. Logic Analyzer To FPGA Pin Reference Signal FPGA Pin Signal FPGA Pin LA1 AA17 LA2 AA18 LA3 Y17 LA4 AC21 LA5 W17 LA6 AA19 LA7 Y18 LA8 AC22 LA9 P3 LA10 P2 LA11 P5 LA12 N6 LA13 P4 LA14 R3 LA15 P6 LA16 N7 LA17 E13 LA18 H17 LA19 E12 LA20 F15 LA21 D13 LA22 D14 LA23 E14 LA24 G17 LA25 E15 LA26 G18 LA27 D15 LA28 E16 LA29 F18 LA30 F19 LA31 D16 LA32 F17 LA33 D17 LA34 E17 17 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor DDR2 Memory Devices U18 and U133 (see Appendix A, Figure 15) The LatticeECP2M Evaluation Board is equipped with two 84-ball BGA DDR2 SDRAM memory devices such as a Micron MT47H16M16BG-3 device. The two independent DDR2 memory interfaces includes a 16-bit wide device. The evaluation board includes termination of address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeECP2M device. Board Jumpers The board is equipped with several 0.1 headers. These headers are used to field provision specific features. Table 24. Default PCB Jumper Settings Header Designation Description Factory Default1 J2 Selects SPIFASTN. If low, the LatticeECP2/M will use SPI Serial Flash fast read opcode 0B (hex). The fast read op-code 0B (hex) accommodates higher frequency read clocks. 1-2 J3 CSN: Driving both CSN and CS1N high causes the LatticeECP2/M to exit Bypass or Flow-Through mode and resets the Bypass register. 1-2 J4 CS1N: See description above (J3) for more information. 1-2 J5 Selects the connection of theCSSPI0N between using it as DI (Data Input) for Serial configurations In SPI or SPIm mode the CSSPI0N becomes a low true Chip Select output that drives the SPI Serial Flash Chip Select. The board connects this pin the the sysCONFIG™ header. 1-2 J60 Selects the connection from the FPGA CCLK to either a SPI Flash device or the parallel Flash device. 2-3 J98 Selects the VDDIB for the CML between 1.2V or 1.5V. Default 1.2V. 2-3 J99 Selects the VDDOB for the CML between 1.2V or 1.5V. Default 1.5V. 1.2 J116 Connects D7 to SPI Flash Q. J120 Selects the JTAG path from the ispVM download cable. J121 Selects the device TMS pins for JTAG. 1-2 J129 Tristates the MachXO device when not being used for parallel loading. 1-2 1-2 1-2, 3-5 1. Indicates which pins on header are connected with a jumper. References • GS4911B/GS4915B Device Data Sheet 36655-3, August 2006, Gennum Corporation • GS4915 Preliminary Device Data Sheet 39145-0, November 2006, Gennum Corporation Additional Resources The use of the LatticeECP2M device in a SMPTE video system requires following quality PCB design practices. Lattice provides several technical notes regarding PCB design that assist users in building a reliable SERDES system. These documents address topics such as power supply selection, routing practices, and other component selections. Please refer to these documents when adopting the Lattice SMPTE design to your PCB system. • TN1033 - High-Speed PCB Design Considerations • TN1114 - Electrical Recommendations for Lattice SERDES • TN1162 - LatticeECP2/M Hardware Checklist 18 LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Lattice Semiconductor These technical notes can be found by visiting the Lattice website at www.latticesemi.com, and typing the reference number of the document (e.g., TN1033) in the search box. Known Issues The initial PCB design has higher than desired clock jitter due to the proximity of the clock circuitry to the FPGA. A significant improvement in clock jitter can be made by locating clock circuitry as close as possible to the FPGA. This will be considered in future revisions of this PCB. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary June 2007 01.0 Initial release. October 2007 01.1 Product name changed from LatticeECPM SMPTE Video Evaluation Board to LatticeECPM SMPTE SDI Evaluation Board. Miscellaneous changes to Gennum Clock Device Status Indicators table. Miscellaneous changes to Default PCB Jumper Settings table. Updated Appendix A schematics. November 2007 01.2 Added “Additional Resources” and “Known Issues” text sections. December 2007 01.3 Added Header J26 Pin Connections table. Added General Purpose I/O/sysCONFIG text section and J6 Header Pinout Crossover table. December 2007 01.4 Updated Configuration/Testpoints and FPGA Test schematics in Appendix A. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 19 20 3 X1 PCIe Edge Connector 2 User Switches Title Cover Page 1605 Valley Center Parkway Bethlehem, PA 18017 Logic Analyzer Probe User LEDs 1 C D 1 ECP2M VIDEO Card P roje c t D a te : Thurs. April 19, 2007 S iz e C S he e t 1 of 13 R ev 1.0 A SATA Host and Target Interface Connectors Clock Status Indicators 2 A 4 SMPTE Video Channel 1 Available in ECP2M35 and ECP2M50 SMPTE Video Channel 2 Available in ECP2M50 Only Pushbutton Switches 3 B 5 ECP2M-672fpBGA Video Evaluation Board 4 B C D 5 Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Appendix A. Schematic Figure 8. Cover Page A B C R30 0R-0805SMT C16 10UF-16V_TANTBSMT 3_3VIN 1 1 1 1 1 1 R14 0R-0805SMT TP11 TP9 TP7 TP5 TP3 C3 10UF-16V_TANTBSMT 3_3VIN TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TP4 1 5 1 TP12 1 TP10 1 TP8 1 TP6 1 TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT C17 2 4 5 100NF-0603SMT D 100NF-0603SMT 2 4 5 R8 1 10K-0603SMT LED-SMT1206_GREEN D4 R17 1 3 22UF-16V_TANTBSMT 124R-0603SMT BOURNS-3224W-2K R24 AMS1503CT SENSE ADJUST_GND VCONTROL OUTPUT OUTPUT R33 1 3 C18 22UF-16V_TANTBSMT 124R-0603SMT BOURNS-3224W-5K R39 AMS1503CT SENSE ADJUST_GND VCONTROL VPOWER 5A Fast-Blo SMT Socketed Fuse 1_8V C10 1.5V C19 4 C11 4 R9 1 10K-0603SMT R31 OPEN-0805SMT 1 2 1 2 GND VIN GND VIN R10 1 10K-0603SMT U5 U6 12_0V 12_0V Q3 2N2222/SOT23 LED-SMT1206_GREEN D6 1_8V 1. 8V R4 470R-1206SMT 12_0V PTH12060W SENSE PTH12060W BOURNS-3224W-100K R34 R15 0R-0603SMT 5 6 0R-0603SMT R28 R26 100K-0603SMT 1_8K-0603SMT R25 R35 1M-0603SMT C14 10UF-16V_TANTBSMT SENSE VOUT BOURNS-3224W-10K R21 5 6 R12 100K-0603SMT R11 1 10K-0603SMT C4 10UF-16V_TANTBSMT VOUT Q4 2N2222/SOT23 3 1_2V LED-SMT1206_GREEN D7 1.2V R5 470R-1206SMT 12_0V 3 1.2V 330UF-FKSMT C5 + 3_3V 330UF-FKSMT 3.3V C6 10UF-16V_TANTBSMT R32 OPEN-0805SMT R7 150R-0603SMT 3.3V D2 LED-SMT1206_GREEN 3_3V F3 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse F4 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse C15 + 1_2V G 3_3VIN R6 100R-0603SMT 2. 5V D1 LED-SMT1206_GREEN 2_5V G POWER RAIL GOOD INDICATORS R18 OPEN-0805SMT LED-SMT1206_GREEN D5 1_5V 1.5V R3 470R-1206SMT 12_0V Q2 2N2222/SOT23 1.8V 1_5V VCC_CORE V C C _C O R E F2 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse VPOWER U4 Q1 2N2222/SOT23 F6 F1228CT-ND C9 U8 R2 470R-1206SMT G 3 2 TP2 27R-0603SMT TP1 R36 GND Pads Distributed around the board R20 56R-0603SMT G 3 2 G 3 2 G 3 2 12_0V 100NF-0603SMT INHIBIT# 3 10 MUP INHIBIT# 3 1 2 U7 12_0V C1 2 GND VIN OPEN-0805SMT R19 3_3VIN LED-SMT1206_GREEN 12_0V R1 470R-1206SMT 12VIN GOOD D3 2 PTH12060W 1 2 U3 VOUT GND +12VDC 12_0V PTH03010W VOUT BOURNS-3224W-10K R22 5 6 0R-0603SMT R29 R27 100K-0603SMT R38 2_2K-0603SMT 4.32K Typical 5 6 0R-0603SMT R16 R13 100K-0603SMT 1 12_0V 1 S he e t 2 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP2M VIDEO Card P roje c t J1 330UF-FKSMT C7 + DC/DC Conversion D a te : Fri. March 09, 2007 S iz e C Title 2.5V R23 15K-0603SMT 330UF-FKSMT C13 + 2_5V C8 10UF-16V_TANTBSMT SENSE VCC_CORE F1 F1251CT-ND 10A Fast-Blo SMT Socketed Fuse FPGA VCC_CORE 100UF-FKSMT + Male Power Jack 2.1mm 22HP037 3 POWER INPUT Terminal Block/ED1202DS TB1 C12 10UF-16V_TANTBSMT SENSE BOURNS-3224W-10K R37 C2 2 1 F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse GND VIN 470UF-FKSMT + 12_0V 12_0V 1 2 5 100NF-0603SMT 10 MUP 9 MDWN ADJUST 4 3_3_TRIM 9 MDWN 8 TRACK ADJUST 4 INHIBIT# 3 8 TRACK 7 10 MUP INHIBIT# ADJUST 4 G 3 GND 1_2_TRIM 9 MDWN ADJUST 4 10 MUP 9 MDWN 8 TRACK GND 7 CORE_TRIM 7 GND 8 TRACK 7 2_5_TRIM 21 GND A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 9. DC/DC Conversion A B C D C35 C36 C37 C46 5.6nF 0402 C121 1 1 C122 JUMPER1 J101 JUMPER1 J100 C71 C72 C73 C74 VCC_PLL G19 J17 H7 K6 R8 P7 V18 P20 J99 HEADER 3 VCC Core U1I 1_5V J98 HEADER 3 C123 C124 ecp2m-672fpbga 2 2 1_5V 1_2V C125 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 1_2V L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 C126 PP6 VCC_CORE + C419 + C417 22UF-16V_TANTBSMT C127 C420 VDDOB C418 VDDIB 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C70 ecp2m-672fpbga PLL RLM0_PLLCAP LLM0_PLLCAP RUM0_VCCPLL RUM1_VCCPLL LUM0_VCCPLL LUM1_VCCPLL LLM0_VCCPLL LLM2_VCCPLL RLM0_VCCPLL RLM2_VCCPLL + C38 C128 C20 1UF-16V-0805SMT C129 PP1 C133 C134 C135 C136 C137 C138 C139 C140 C141 5 4 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C132 VCC_CORE 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C120 VCC_CORE C47 5.6nF 0402 T8 V19 U1G 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C28 VCC_PLL 1UF-16V-0805SMT 1UF-16V-0805SMT 1 2 100NF-0603SMT C114 VDDRX_U 100NF-0603SMT C106 VDDTX_U 100NF-0603SMT C98 VDDP_U 1_8V C21 C22 C23 C40 C24 C25 C26 C27 C31 C42 C32 C43 C33 C44 C34 C45 C49 C50 C51 C52 C53 C54 C55 C56 C60 C64 C65 C66 C67 C68 C61 C69 10NF-0603SMT C115 10NF-0603SMT C107 10NF-0603SMT C99 + C87 3_3V 100NF-0603SMT C116 100NF-0603SMT C108 100NF-0603SMT C100 C88 C83 C101 10NF-0603SMT C117 10NF-0603SMT C109 10NF-0603SMT C94 VDDIB AE25 AD23 AD15 AE13 B25 C23 C15 B13 A22 C20 C18 A16 AF16 AD20 AD18 AF22 AE19 B19 C92 C96 ecp2m-672fpbga C102 3 100NF-0603SMT C118 100NF-0603SMT C110 100NF-0603SMT C103 10NF-0603SMT C119 10NF-0603SMT C111 10NF-0603SMT 1_2V SERDES Supplies L_VCCIB0 L_VCCIB1 L_VCCIB2 L_VCCIB3 U_VCCIB0 U_VCCIB1 U_VCCIB2 U_VCCIB3 U_VCCOB0 U_VCCOB1 U_VCCOB2 U_VCCOB3 L_VCCOB3 L_VCCOB1 L_VCCOB2 L_VCCOB0 L_VCCAUX33 U_VCCAUX33 U1H 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C90 VDDOB VDDIB VDDIB FB1 BLM41PG600SN1 FB3 BLM41PG600SN1 FB2 BLM41PG600SN1 + C130 VDDRX_U + C112 VDDTX_U + C104 VDDP_U PP12 PP2 PP3 2 C113 C131 C105 100NF-0603SMT C93 VDDP_U VDDP_L VDDTX_U VDDTX_L VDDRX_U VDDRX_L 1_8V 10NF-0603SMT C95 AD25 AD24 AD13 AD14 C25 C24 C14 C13 AD16 AD17 AD21 AD22 C22 C21 C17 C16 C19 AD19 100NF-0603SMT C91 VDDOB L_VCCRX0 L_VCCRX1 L_VCCRX3 L_VCCRX2 U_VCCRX0 U_VCCRX1 U_VCCRX2 U_VCCRX3 L_VCCTX3 L_VCCTX2 L_VCCTX1 L_VCCTX0 U_VCCTX0 U_VCCTX1 U_VCCTX2 U_VCCTX3 U_VCCP L_VCCP 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C63 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C48 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C41 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C39 3 1 2 FB8 22UF-16V_TANTBSMT BLM41PG600SN1 1 2 3 1 2 3 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 2_5V 100NF-0603SMT 2 R336 PP8 OPEN-0805SMT R340 PP7 OPEN-0805SMT R338 PP5 OPEN-0805SMT 1UF-16V-0805SMT C76 C77 B7 B12 F11 J13 K12 D18 F16 J14 K15 G25 L21 M17 M25 N18 P18 R17 R25 T21 Y25 AC18 AA16 U15 V14 AA11 AE7 U12 V13 AE12 P9 R10 R2 T6 Y2 G2 L6 M10 M2 N9 VDDRX_L VDDTX_L VDDP_L R341 0R-0805SMT R339 0R-0805SMT R337 0R-0805SMT 1 C78 ecp2m-672fpbga VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 U1J 3_3V D a te : S iz e C Title VCC_CORE Fri. March 09, 2007 22UF-16V_TANTBSMT C62 3_3V PP4 10NF-0603SMT C82 1UF-16V-0805SMT 1 S he e t 3 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 10NF-0603SMT C81 + C59 ECP2M VIDEO Card P roje c t U17 AC24 10NF-0603SMT C80 Power Supplies 10NF-0603SMT C79 Power Supplies VCCIO8 VCCIO8 VCCJ VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX AA7 J11 J12 J15 J16 L18 L9 M18 M9 R18 R9 T18 T9 V11 V12 V15 V16 Banks 0, 4, 6 = 3.3V Banks 1, 2, 3, 4 = 2.5V Banks 5 & 7 = 1.8V 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C75 C58 C30 C519 10NF-0603SMT C97 + C57 + C29 2_5V + C518 3_3V 1UF-16V-0805SMT 1UF-16V-0805SMT 4 100NF-0603SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1 2 1 2 1_2V 1 2 1UF-16V-0805SMT C89 1 2 5 1UF-16V-0805SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1UF-16V-0805SMT 1UF-16V-0805SMT 2 1 1 2 1 22 2 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 10. Power Supplies A B C 1(OFF) D11 0(ON) 1(OFF) X 1(OFF) 1(OFF) X INITN 5 PROGRAMN PROGRAMN GSRN [5,12] GSRN 3_3V 3 4 3 6 3 2Y 1Y Momentary Switch B3F-1150 2 1 SW3 2 4 Momentary Switch B3F-1150 1 SW2 5 4 2 1 3 1 SN74LVC125A/SO14 2A 2OE_N 1A 1OE_N U14A 3_3V CONFIG Status LEDs DONE FPGA RESETN/GSRN 1 R55 10K-0603SMT D9 LED-SMT1206_RED DONE indicator will light when configuration is successfully completed LED-SMT1206_RED R D8 680R-0603SMT R51 ispJTAG Slave Parallel INITN indicator will light if an error occurs during configuration programming R52 680R-0603SMT 3_3V Slave Serial 1(OFF) 0(ON) Master Parallel Master Serial SPIm CONFIG Pushbuttons Q5 2N2222/SOT23 X 1(OFF) R54 SPI Flash 0(ON) 0(ON) 0(ON) 0(ON) 1(OFF) LED-SMT1206_GREEN 1(OFF) 220R-0603SMT G 3 2 3_3V OUT2 OUT1 4 6 LED-SMT1206_RED D10 4 11 8 4Y CFG0 R48 10K-0603SMT 3Y CFG2 CFG1 R47 10K-0603SMT 3_3V C143 12 13 9 10 3_3V C144 SN74LVC125A/SO14 4A 4OE_N 3A 3OE_N U14B ON R45 10K-0603SMT 680R-0603SMT R53 3_3V MAX6817 IN2 IN1 U11 Y 0(ON) GND 0(ON) 100NF-0603SMT GSRN C145 0(ON) R62 6 5 4 1 2 3 10NF-0603SMT 3_3V 1 2 3 SPIFASTN R44 SPI0_Q HEADER 3 J60 1 2 1 2 LOADER_CK FPGA_CCLK 10K-0603SMT CK D DU8 DU7 DU6 DU5 VSS W# [5] TMS_XO 16 15 14 13 12 11 10 9 TMS_EC TMS_XO TDI_BUF TDI_XO TDO_XO M25P64-FLASH HOLD# VCC DU1 DU2 DU3 DU4 S# Q U12 [5] TDI_XO [5] TDO_XO 1 2 3 4 5 6 7 8 3 1 1 JUMPER1 J119 JUMPER1 J117 FPGA_SISPI SPI FLASH HEADER 2 J2 HEADER 2 J116 FLASH_DIS FPGA_CSSPI0N SPI0_Q SW1 SW DIP-3 CTS 194-3MST R56 10K-0603SMT 1(OFF) 4_7K-0603SMT R60 10K-0603SMT D 5 VCC Y R65 R58 4_7K-0603SMT PROGRAMN 100R-0603SMT GND 2 R66 100R-0603SMT R59 4_7K-0603SMT 1 3 5 1 1 1 JUMPER1 2 2 1 3 2 LCD1 1 2 3 ecp2m-672fpbga PR62A/BUSY PR62B/DOUT/CSON PR63A/DI PR63B/D7 PR64A/D6 PR64B/D5 PR65A/D4 PR65B/D3 PR66A/D2 PR66B/D1 PR67A/D0 PR67B/CSN PR68A/CS1N PR68B/WRITEN U1B FPGA_D[0..7] FPGA_CSSPI1N Y24 W23 V20 W21 AA24 Y23 W18 W22 Y20 W19 Y22 AB26 Y21 Y19 4 6 OUT Y2 OUT Y1 3_3V TCK_BUF TMS_BUF 4.7K 4.7K 4.7K OUT Y2 OUT Y1 4.7K 2 EXBV8V472JV 4 6 NC7WZ16-MACO6A/Fairchild TinyLogic R63 220R-0603SMT D12 LED-SMT1206_GREEN This LED indicates activity on TDI. TDI_BUF NC7WZ16-MACO6A/Fairchild TinyLogic JTAG HEADER 3 J5 CSN CS1N WRITEN [5] TCK_BUF FPGA_D7 [12] FPGA_SISPI FPGA_CSSPI1N FPGA_CSSPI0N FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 TDI_EC TDO_EC LOCAL_TDO JUMPER1 J118 J123 JUMPER1 HEADER 2X2 J122 2 4 J121 HEADER 3X2 2 4 6 J120 2 2 3_3V LOADER_CK [5] FPGA_D0 FPGA_D7 R61 10K-0603SMT Configuration Mode R CFG0 RN2B CFG1 RN2C 3_3V 5 CFG2 3_3V IN A2 IN A1 U9 U13 IN A2 IN A1 3 1 DONE FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 CSN CS1N 3_3V FPGA_CCLK FPGA_SISPI FPGA_CSSPI0N HEADER 3 J3 CONFIG CFG2 CFG1 CFG0 PROGRAMN DONE INITN CCLK TCK TMS TDO TDI XRES 3 1 1 2 3 FPGA_CCLK TCK_BUF TMS_EC TDO_EC TDI_EC CFG2 CFG1 CFG0 CSN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 3 1 2 3 R46 WRITEN CFG0 CFG1 CFG2 3_3V LOCAL_TMS LOCAL_TCK DONE INITN LOCAL_TDO LOCAL_TDI VCC INITN GND DONE TCK TMS NC ispEN_N TDI TDO HEADER 10 7 1 4.7K 4.7K EXBV8V472JV 1 Monday, December 17, 2007 1 ECP2M VIDEO Card P roje c t S he e t 4 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 PROGRAMN [5] DONE [5] INITN [5] Configuration/Testpoints 4.7K D a te : S iz e C Title 4.7K J8 2 3 4 5 6 8 9 10 3_3V sysCONFIG Connector 3_3V INITN PROGRAMN CS1N R50 10K-0603SMT 10K-0603SMT PROGRAMN DONE INITN R43 4_7K-0603SMT R40 R41 R42 10K-0603SMT 10K-0603SMT 10K-0603SMT 3_3V FROM ISPVM CABLE HEADER 17X2 J6 R49 10K-0603SMT J4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 3_3V AA21 AA22 AB23 AC26 AB25 AA23 AB24 AC3 AC4 V8 W8 H19 C142 100NF-0603SMT [5] FPGA_D[0..7] RN2D C147 VCC GND 2 5 VCC GND 2 100NF-0603SMT CONFIG CFG Switches RN1B 2 RN1C 3 100NF-0603SMT 4 1 RN2A 8 RN1D 4_7K-0603SMT R57 7 4 TCK_BUF 5 100NF-0603SMT 14 VCC 2 7 TDI_BUF 3 6 TMS_BUF 3 6 1 RN1A 8 LOCAL_TDO 2 7 LOCAL_TDI 4 LOCAL_TCK 5 5 C146 23 LOCAL_TMS A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 11. Configuration/Testpoints A B C 3_3V 3_3V 2 R374 4_7K-0603SMT 4 2 5 Momentary Switch B3F-1150 3 1 SW9 CPLD RESET JUMPER1 1 2 1 2 J129 HEADER 2X1 1 R345 1K-0603SMT J128 3_3V R344 2_2K-0603SMT [4] FPGA_D[0..7] 4.7K RN24C D 3 4.7K DONE GSRN [4] [4,12] 4.7K 4.7K FPGA_D0 FPGA_D1 FPGA_D2 FPGA_D3 FPGA_D4 FPGA_D5 FPGA_D6 FPGA_D7 LOADER_CK 3_3V 4 N14 GSRN R346 1K-0603SMT TCK_BUF TDI_XO TDO_XO TMS_XO A4 DONE M1 P13 P10 N7 N8 P11 N13 N1 N3 N4 P1 M12 M2 M3 M4 M6 M7 B1 L3 A3 A2 M9 N12 P4 M5 N5 P3 K12 A1 J2 H2 G1 A5 P8 M8 J3 K1 E3 B7 P5 INITN PROGRAMN EXBV8V472JV [4] TCK_BUF [4] TDI_XO [4] TDO_XO [4] TMS_XO INITN [4] [4] PROGRAMN [4] LOADER_CK FPGA_D[0..7] 4 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC SLEEPN TCK TDI TDO TMS FUNC_RESET FPGA_RESETN FPGA_DONE FPGA_INITN TSALL C553 100NF-0603SMT FPGA_PROGRAMN FPGA_DATA_0 FPGA_DATA_1 FPGA_DATA_2 FPGA_DATA_3 FPGA_DATA_4 FPGA_DATA_5 FPGA_DATA_6 FPGA_DATA_7 FPGA_CCLK U29 3_3V C554 10NF-0603SMT C555 100NF-0603SMT C556 LCMXO1200C-CSBGA132 Lattice FPGA Loader C557 100NF-0603SMT 3 3 FLASH_ADDRESS_0 FLASH_ADDRESS_1 FLASH_ADDRESS_2 FLASH_ADDRESS_3 FLASH_ADDRESS_4 FLASH_ADDRESS_5 FLASH_ADDRESS_6 FLASH_ADDRESS_7 FLASH_ADDRESS_8 FLASH_ADDRESS_9 FLASH_ADDRESS_10 FLASH_ADDRESS_11 FLASH_ADDRESS_12 FLASH_ADDRESS_13 FLASH_ADDRESS_14 FLASH_ADDRESS_15 FLASH_ADDRESS_16 FLASH_ADDRESS_17 FLASH_ADDRESS_18 FLASH_ADDRESS_19 FLASH_ADDRESS_20 FLASH_ADDRESS_21 FLASH_DQ_31 FLASH_DQ_30 FLASH_DQ_29 FLASH_DQ_28 FLASH_DQ_27 FLASH_DQ_26 FLASH_DQ_25 FLASH_DQ_24 FLASH_DQ_23 FLASH_DQ_22 FLASH_DQ_21 FLASH_DQ_20 FLASH_DQ_19 FLASH_DQ_18 FLASH_DQ_17 FLASH_DQ_16 FLASH_DQ_15 FLASH_DQ_14 FLASH_DQ_13 FLASH_DQ_12 FLASH_DQ_11 FLASH_DQ_10 FLASH_DQ_9 FLASH_DQ_8 FLASH_DQ_7 FLASH_DQ_6 FLASH_DQ_5 FLASH_DQ_4 FLASH_DQ_3 FLASH_DQ_2 FLASH_DQ_1 FLASH_DQ_0 CLOCK FLASH_WE_N FLASH_WP_N_ACC FLASH_RESET_N FLASH_OE_N FLASH_CEm FLASH_RD/BY FLASH_BYTEn FLASH_CE1_N FLASH_CE0_N 10NF-0603SMT GND C9 5 C561 100NF-0603SMT G12 VCC GND D13 4 C7 VCC GND E1 RN24D H3 VCC GND F1 5 TDO_XO B11 VCCIO1 GND J14 2 E12 VCCIO2 GND L2 6 TDI_XO L12 VCCIO3 L13 RN24B P6 VCC GND M10 VCCIO4 GND RN24A A7 VCCAUX GND N2 VCCIO5 GND 1 8 P7 VCCAUX B4 K3 VCCIO6 GND P2 7 TMS_XO C5 VCCIO0 A10 D2 VCCIO7 GND P9 24 N11 C558 B6 A6 B3 B5 A9 B9 C10 B10 C11 A11 D14 C8 A14 B8 C14 B12 C13 A13 B13 A12 C12 B14 F12 H14 N10 N6 M14 M13 H13 H12 C6 C2 K14 P12 L14 M11 G2 E2 E14 D12 J12 G14 J13 F14 F13 E13 D3 C4 J1 H1 N9 K13 G13 G3 A8 K2 L1 P14 C1 B2 D1 F2 F3 C3 FLASH_D15 FLASH_D14 FLASH_D13 FLASH_D12 FLASH_D11 FLASH_D10 FLASH_D9 FLASH_D8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 FLASH_CLK FLASH_WE_N FLASH_WP_N_ACC FLASH_RESET_N FLASH_OE_N FLASH_CEm FLASH_RD/BY FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 10NF-0603SMT FLASH_CLK [12] FLASH_A[0..21] FLASH_A21 FLASH_A20 FLASH_A19 FLASH_A18 FLASH_A17 FLASH_A16 FLASH_A15 FLASH_A14 FLASH_A13 FLASH_A12 FLASH_A11 FLASH_A10 FLASH_A9 FLASH_A8 FLASH_A7 FLASH_A6 FLASH_A5 FLASH_A4 FLASH_A3 FLASH_A2 FLASH_A1 FLASH_A0 2 46 27 13 10 9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 2 U30 VCC DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CEn OEn WEn RD/BY BYTEn WPn RESETn FLASH_D[0..15] S29GL064A GND GND A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 37 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 26 28 11 15 47 14 12 3_3V C559 C560 1 ECP2M VIDEO Card P roje c t S he e t 5 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 Parallel FPGA Loader FLASH_D[0..15] 10NF-0603SMT D a te : Fri. March 09, 2007 S iz e C Title FLASH_D15 FLASH_D14 FLASH_D13 FLASH_D12 FLASH_D11 FLASH_D10 FLASH_D9 FLASH_D8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 FLASH_CEm FLASH_OE_N FLASH_WE_N FLASH_RD/BY FLASH_BYTEn FLASH_WP_N_ACC FLASH_RESET_N 100NF-0603SMT 1 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 12. Parallel FPGA Loader A B C D OUT_SATA_TGT+ OUT_SATA_TGT- OUT_SATA_HOST+ OUT_SATA_HOST- 50 50 50 50 50 PERp0 PERn0 PCIE_CLKP PCIE_CLKN PCIE_3V3 12_0V C423 150R-0603SMT R233 U_HDOUTN1 U_HDOUTP1 U_HDOUTN2 U_HDOUTP2 U_HDINN1 U_HDINP1 U_HDINN2 U_HDINP2 OUT_SATA_HOST- OUT_SATA_TGT- C430 C426 C424 C422 PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND CN4 +12V +12V RSVD_B3 GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE# RSVD_B12 GND PETp0 PETn0 GND PRSNT3# GND PCI Express x1 Edge Finger Conn. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 x1 50 50 PETp0 PETn0 PCIE_3V3 X1 PCIe Board Fingers x1 Populate for PCIe Clock from Edge Finger 150R-0603SMT R232 150R-0603SMT R231 10NF-0402SMT C428 10NF-0402SMT C425 10NF-0402SMT 150R-0603SMT OUT_SATA_HOST+ C421 10NF-0402SMT R230 10NF-0402SMT 10NF-0402SMT 10NF-0402SMT OUT_SATA_TGTOUT_SATA_TGT+ IN_SATA_TGT+ IN_SATA_TGT- IN_SATA_HOSTIN_SATA_HOST+ OUT_SATA_HOST+ OUT_SATA_HOST- 4 1 U_HDOUTN0 50 5 U_HDOUTP0 50 C156 100NFX5R-0402SMT 100NFX5R-0402SMT C157 PERn0 PERp0 4 B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM) [12] PCIE_PERSTN IN_SATA_HOST- 50 1 2 3 4 5 6 7 10NF-0402SMT SATA G A+ AG BB+ G CN2 SATA G A+ AG BB+ G 1 2 3 4 5 6 7 SATA CN1 OUT_SATA_TGT+ IN_SATA_HOST+ 50 IN_SATA_TGT+ IN_SATA_TGT- 50 50 Target Host 50 5 TP18 TESTPOINT A14 B14 A15 B15 A23 B23 A24 B24 D19 E19 AF14 AE14 AF15 AE15 AF23 AE23 AF24 AE24 AC19 AB19 L_REFCLKP R335 R334 R263 R262 R80 R79 0R-0603SMT 0R-0603SMT 0R-0603SMT 0R-0603SMT OPEN-0603SMT OPEN-0603SMT OPEN-0603SMT U_REFCLKN U_REFCLKP L_REFCLKN U_REFCLKN [9] [9] TX_GC4915_CLKOUTN [10] TX_GC4915_CLKOUTP [10] RX_GC4915_CLKOUTN RX_GC4915_CLKOUTP L_REFCLKN L_REFCLKP U_HDOUTP3 U_HDOUTN3 U_HDOUTP2 U_HDOUTN2 U_HDOUTP1 U_HDOUTN1 U_HDOUTP0 U_HDOUTN0 L_HDOUTP3 L_HDOUTN3 SERDES_OUT_P2 SERDES_OUT_N2 SERDES_LOOP_P0 SERDES_LOOP_N0 SERDES_LOOP_P1 SERDES_LOOP_N1 1 SERDES_OUT_N2 1 SERDES_OUT_P2 3 The source to U_REFCLK can be from the VIDEO Source, PCIe X1 interface, or SMA inputs. These resistors connect the appropriate clock source to the U & L_REFCLK input. L_REFCLKN L_REFCLKP U_REFCLKN U_REFCLKP PCIE_CLKN R216 Place near U1 OPEN-0603SMT L_SMA_REFCLKN R225 0R-0603SMT R226 51R-0603SMT 1 R215 L_SMA_REFCLKP R223 0R-0603SMT R224 51R-0603SMT U_REFCLKN U_SMA_REFCLKN R69 0R-0603SMT R70 51R-0603SMT 1 1 U_REFCLKP U_SMA_REFCLKP R67 0R-0603SMT R68 51R-0603SMT SERDES A17 B17 A18 B18 A20 B20 A21 B21 AF17 AE17 AF18 AE18 AF20 AE20 AF21 AE21 1 ecp2m-672fpbga U_HDINP3 U_HDINN3 U_HDINP2 U_HDINN2 U_HDINP1 U_HDINN1 U_HDINP0 U_HDINN0 U_REFCLKP U_REFCLKN L_HDINP3 L_HDINN3 L_HDINP2 L_HDINN2 L_HDINP1 L_HDINN1 L_HDINP0 L_HDINN0 L_REFCLKP L_REFCLKN U_HDOUTP3 U_HDOUTN3 U_HDOUTP2 U_HDOUTN2 U_HDOUTP1 U_HDOUTN1 U_HDOUTP0 U_HDOUTN0 L_HDOUTP3 L_HDOUTN3 L_HDOUTP2 L_HDOUTN2 L_HDOUTP1 L_HDOUTN1 L_HDOUTP0 L_HDOUTN0 J115 Rosenberger 32K153-400E3 1 SERDES_IN_N2 U1A J113 Rosenberger 32K153-400E3 U_REFCLKP PCIE_CLKP J107 Rosenberger 32K153-400E3 J106 Rosenberger 32K153-400E3 J15 Rosenberger 32K153-400E3 J14 Rosenberger 32K153-400E3 U_HDINP3 U_HDINN3 U_HDINP2 U_HDINN2 U_HDINP1 U_HDINN1 PETp0 PETn0 U_REFCLKP U_REFCLKN L_HDINP3 L_HDINN3 SERDES_IN_P2 SERDES_IN_N2 SERDES_LOOP_P1 SERDES_LOOP_N1 SERDES_LOOP_P0 SERDES_LOOP_N0 L_REFCLKP L_REFCLKN J114 Rosenberger 32K153-400E3 2 2 3 1 SERDES_IN_P2 2 2 J112 Rosenberger 32K153-400E3 2 2 2 2 2 2 2 2 2 2 2 25 2 SMPTE_CH1_P SMPTE_CH1_N U_HDOUTP3 U_HDOUTN3 SMPTE_CH2_P SMPTE_CH2_N L_HDOUTP3 L_HDOUTN3 2 BNC-Trompeter/UCBBJE20-7 1 J27 BNC-Trompeter/UCBBJE20-7 1 J25 BNC-Trompeter/UCBBJE20-7 1 J26 BNC-Trompeter/UCBBJE20-7 1 J24 BNC-Trompeter/UCBBJE20-7 1 J22 BNC-Trompeter/UCBBJE20-7 1 J19 BNC-Trompeter/UCBBJE20-7 1 J21 2.7UF-0603SMT C443 2.7UF-0603SMT C442 2.7UF-0603SMT C441 2.7UF-0603SMT C440 L_HDINN3 L_HDINP3 U_HDINN3 U_HDINP3 VIDEO BNCs D a te : S iz e C Title Fri. March 09, 2007 1 S he e t 6 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 ECP2M VIDEO Card P roje c t SERDES 50-OHM Lines PETp0/PETn0 U_HDOUTP0/U_HDOUTN0 U_HDINP1/U_HDINN1 U_HDOUTP1/U_HDOUTN1 U_HDINP2/U_HDINN2 U_HDOUTP2/U_HDOUTN2 SERDES_IN_P2/SERDES_IN_N2 SERDES_OUT_P2/SERDES_OUT_N2 SERDES_LOOP_P1/SERDES_LOOP_N1 SERDES_LOOP_P0/SERDES_LOOP_N0 75-OHM Lines U_HDINP3/U_HDINN3 U_HDOUTP3/U_HDOUTN3 L_HDINP3/L_HDINN3 L_HDOUTP3/L_HDOUTN3 BNC-Trompeter/UCBBJE20-7 1 J18 2 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 13. SERDES A B C ODT0 CS0# CAS# RAS# A4 A7 BA0 A11 A5 BA1 A1 A6 A3 A2 A0 A9 A12 DQ8 DQ9 DQ15 DQ14 DQ12 DQ13 DQ10 DQ11 DQS1 DQS1# DM1 A8 DM0 WE# DQS0 DQS0# DQ0 DQ1 DQ3 DQ7 DQ6 DQ4 DQ2 DQ5 CKE0# A10 K K# DDR_VREF1 5 AB6 Y8 AD1 AD2 AC5 AA8 AC6 W9 AB7 Y9 AD3 AD4 AA9 W10 AC7 Y10 AE2 AD5 AE4 AE3 W11 AB8 AE5 AD6 AA10 AC8 W12 AC9 W13 AB10 AF3 AF4 AF5 AF6 Y12 AB11 AD7 AF7 AD8 AA12 AE8 AF8 AD9 AC10 AC11 AB12 AD10 Y13 AF9 AE9 AF10 AE10 AD11 AF11 AA13 AB13 W14 AC12 AF12 AD12 U1C SP12 SP11 SP6 SP3 SP5 SP10 SP9 SP4 1 1 1 1 1 1 1 1 1 1 1 R127 0R-0603SMT Bank7 ecp2m-672fpbga PB2A PL2A* PB2B PL2B* PB3A PL3A PB3B PL3B PB4A PL4A* PB4B PL4B* PB5A PL5A PB5B PL5B PB6A PL6A* PB6B PL6B* PB7A PL7A PB7B PL7B PB8A PL8A* PB8B PL8B* PB9A PL9A/VREF2_7 PB9B PL9B/VREF1_7 PB10A PL11A*/LUM0_SPLLT_IN_A PB10B PL11B*/LUM0_SPLLC_IN_A PB11A PL12A/LUM0_SPLLT_FB_A PB11B PL12B/LUM0_SPLLC_FB_A PB12A PL13A* PB12B PL13B* PB13A PL14A PB13B PL14B PB14A PL16A PB14B PL16B PB15A PL17A* PB15B PL17B* PB16A PL19A* PB16B PL19B* PB17A PL20A PB17B PL20B PB18A PL21A* PB18B PL21B* PB19A PL22A PB19B PL22B PB20A PL23A* PB20B PL23B* PB21A PL24A PB21B PL24B PB22A PL25A* PB22B PL25B* PB23A PL26A PL26B PB23B PB24A PL28A*/LUM1_SPLLT_IN_A PB24B PL28B*/LUM1_SPLLC_IN_A PB25A PL29A/LUM1_SPLLT_FB_A PB25B PL29B/LUM1_SPLLC_FB_A PB26A PL30A* PB26B PL30B* PB27A PL31A PB27B PL31B PL32A* PB28A PB28B PL32B* PB33A PL33A PB33B PL33B PB34A/VREF2_5 PL34A* PB34B/VREF1_5 PL34B* PB35A/PCLKT5_0 PL35A/PCLKT7_0 PB35B/PCLKC5_0 PL35B/PCLKC7_0 C2 C1 F6 H9 D3 D2 F5 H8 E3 E2 J9 E4 E1 D1 J8 F4 F3 F1 G6 K9 G5 G4 H5 H6 J7 H4 H3 G3 G1 H1 J3 J4 H2 J2 K7 J6 K5 L5 K4 L4 K3 L3 J1 K2 K1 L1 K8 M5 M4 M3 L8 M6 M1 N1 N3 N2 N5 N4 M7 M8 2_DQ7 2_DQ6 2_DQS0 2_DQS0# 2_DQ0 2_DQ1 2_DQ2 2_DQ3 2_DQ4 2_DQ5 2_DM0 2_A5 2_BA0 2_A10 2_A8 2_A0 2_A4 2_BA1 2_A7 2_A6 2_A11 2_A12 2_ODT0 2_DM1 2_DQ14 2_DQ15 2_DQS1 2_DQS1# 2_DQ12 2_DQ13 2_DQ9 2_DQ8 2_DQ11 2_DQ10 2_CAS# 2_A1 2_A3 2_A9 2_WE# 2_CS0# 2_CKE0# 2_A2 2_RAS# 2_K 2_K# [8] DDR2_DQS1 [8] DDR2_DQS1# [8] DDR2_DQS0 [8] DDR2_DQS0# RN12 1 2 3 4 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 4 1_8V 2_DDR_VREF1 R347 0R-0603SMT RN14 DDR2_DQS1 1 DDR2_DQS1# 2 DDR2_DQS0 3 DDR2_DQS0# 4 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 RN11 1 2 3 4 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 RN13 1 2 3 4 RN10 1 2 3 4 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 1_8V R83 OPEN-0603SMT 1K_ADJ/SMT3MM R82 A3 B3 C3 D3 E3 F3 G3 H3 J3 K K# CS0# BA0 BA1 WE# RAS# CAS# ODT0 A12 DM0 DM1 CKE0# A8 A9 A10 A11 A4 A5 A6 A7 A0 A1 A2 A3 741X083 741X083 741X083 741X083 741X083 741X083 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RN3 1 2 3 4 22 22 22 22 22 22 RN9 8 7 6 5 RN8 8 7 6 5 RN7 8 7 6 5 RN6 8 7 6 5 RN5 8 7 6 5 C176 C177 R1=50 Ohm C178 FPGA_VTT R1 R1 C179 RP1 A1 B1 C1 D1 E1 F1 G1 H1 J1 C180 A1 B1 C1 D1 E1 F1 G1 H1 J1 C181 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 VDDQ VREF SD U16 LP2996-SO8 5 4 2 1_8V VTT VSENSE 3 C172 8 3 + + C173 C174 + R86 0R-0603SMT DDR2_A[0:12] FPGA_VTT DDR2_K [8] DDR2_K# [8] DDR2_CS0# [8] DDR2_BA0 [8] DDR2_BA1 [8] DDR2_WE# [8] DDR2_RAS# [8] DDR2_CAS# [8] DDR2_ODT0 [8] DDR2_DM0 [8] DDR2_DM1 [8] DDR2_CKE0 [8] PP9 FPGA_VTT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C175 CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 FPGA_VTT DDR2_K DDR2_K# DDR2_CS0# DDR2_BA0 DDR2_BA1 DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_ODT0 DDR2_A12 DDR2_DM0 DDR2_DM1 DDR2_CKE0# DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 741X083 DDR2_A0 8 DDR2_A1 7 DDR2_A2 6 DDR2_A3 5 RN4 8 7 6 5 22 This RT140287/50-ohm pack should be placed near the FPGA. DQS1 DQS1# DQS0 DQS0# DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DDR_VREF1 R87 0R-0603SMT 2_5V 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 33 33 33 33 33 J2 J2 C169 [8] DDR2_DQ[0:15] F2 F2 SP8 E2 E2 SP7 B2 1 Bank5 All these 741X083/22-ohm devices should be placed near the FPGA. A2 SP2 H2 H2 C170 [8] R217 51R-0603SMT DDR2_DQS1 SP1 G2 G2 100NF-0603SMT R218 51R-0603SMT DDR2_DQS1# D R126 0R-0603SMT D2 1UF-16V-0805SMT R219 51R-0603SMT DDR2_DQS0 All these 741X083/33-ohm devices should be placed near the FPGA. R85 4_7K-0603SMT C2 C167 R220 51R-0603SMT DDR2_DQS0# 1_8V [8] 2_DDR2_DQS1 [8] 2_DDR2_DQS1# [8] 2_DDR2_DQS0 [8] 2_DDR2_DQS0# [8] 2_DDR2_DQ[0:15] 2 1_8V 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 2_FPGA_VTT 2_A8 2_A9 2_A10 2_A11 2_A4 2_A5 2_A6 2_A7 2_A0 2_A1 2_A2 2_A3 2_DQS1 2_DQS1# 2_DQS0 2_DQS0# 2_K 2_K# 2_CS0# 2_BA0 2_BA1 2_WE# 2_RAS# 2_CAS# 2_ODT0 2_DQ12 2_DQ13 2_DQ14 2_A12 2_DQ15 2_DM0 2_DM1 2_CKE0# 2_DQ8 2_DQ9 2_DQ10 2_DQ11 2_DQ4 2_DQ5 2_DQ6 2_DQ7 2_DQ0 2_DQ1 2_DQ2 2_DQ3 C564 R1 C565 2_FPGA_VTT R1=50 Ohm C566 R1 A1 B1 C1 D1 E1 F1 G1 H1 J1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 C567 RP2 A1 B1 C1 D1 E1 F1 G1 H1 J1 741X083 741X083 741X083 741X083 741X083 741X083 RN28 1 2 3 4 22 22 22 22 22 22 C568 2_DDR2_DQ9 2_DDR2_DQ10 2_DDR2_DQ11 2_DDR2_DQ12 2_DDR2_DQ13 2_DDR2_DQ14 2_DDR2_DQ15 RN38 8 7 6 5 RN37 8 7 6 5 RN36 8 7 6 5 RN34 8 7 6 5 RN32 8 7 6 5 0R-0603SMT 2 VDDQ VREF SD LP2996-SO8 5 4 U31 1_8V VTT VSENSE 3 + C576 + 1 ECP2M VIDEO Card P roje c t 2_DDR2_K [8] 2_DDR2_K# [8] 2_DDR2_CS0# [8] 2_DDR2_BA0 [8] 2_DDR2_BA1 [8] 2_DDR2_WE# [8] 2_DDR2_RAS# [8] 2_DDR2_CAS# [8] 2_DDR2_ODT0 [8] 2_DDR2_DM0 [8] 2_DDR2_DM1 [8] 2_DDR2_CKE0 [8] 2_DDR2_A[0:12] S he e t 7 of 13 [8] R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 PP13 2_FPGA_VTT DDR2 FPGA Controller C575 R353 0R-0603SMT D a te : Fri. March 09, 2007 S iz e C Title C574 8 + 2_FPGA_VTT 2_DDR2_K 2_DDR2_K# 2_DDR2_CS0# 2_DDR2_BA0 2_DDR2_BA1 2_DDR2_WE# 2_DDR2_RAS# 2_DDR2_CAS# 2_DDR2_ODT0 2_DDR2_A12 2_DDR2_DM0 2_DDR2_DM1 2_DDR2_CKE0# 2_DDR2_A8 2_DDR2_A9 2_DDR2_A10 2_DDR2_A11 2_DDR2_A4 2_DDR2_A5 2_DDR2_A6 2_DDR2_A7 741X083 2_DDR2_A0 8 2_DDR2_A1 7 2_DDR2_A2 6 2_DDR2_A3 5 RN30 8 7 6 5 22 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C563 CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 C562 2_DDR2_DQ0 A3 2_DDR2_DQ1 B3 2_DDR2_DQ2 C3 2_DDR2_DQ3 D3 2_DDR2_DQ4 E3 2_DDR2_DQ5 F3 2_DDR2_DQ6 G3 2_DDR2_DQ7 H3 2_DDR2_DQ8 J3 2_5V 33 33 33 33 33 1 All these 741X083/22-ohm devices should be placed near the FPGA. This RT140287/50-ohm pack should be placed near the FPGA. RN35 2_DDR2_DQS1 1 2_DDR2_DQS1# 2 2_DDR2_DQS0 3 2_DDR2_DQS0# 4 2_DDR_VREF1 R372 R354 OPEN-0603SMT 1K_ADJ/SMT3MM R129 RN31 1 2 3 4 RN29 1 2 3 4 RN27 1 2 3 4 RN33 2_DDR2_DQ12 1 2_DDR2_DQ13 2 2_DDR2_DQ14 3 2_DDR2_DQ15 4 2_DDR2_DQ8 2_DDR2_DQ9 2_DDR2_DQ10 2_DDR2_DQ11 2_DDR2_DQ4 2_DDR2_DQ5 2_DDR2_DQ6 2_DDR2_DQ7 2_DDR2_DQ0 2_DDR2_DQ1 2_DDR2_DQ2 2_DDR2_DQ3 All these 741X083/33-ohm devices should be placed near the FPGA. 2 C569 A2 C168 J2 J2 100NF-0603SMT B2 100NF-0603SMT H2 H2 C570 3 C171 G2 G2 1UF-16V-0805SMT D2 6 7 AVIN PVIN R81 1K-0603SMT R84 1K-0603SMT 47UF-16V_TANTBSMT 100UF-FKSMT F2 F2 4 C166 10NF-0603SMT 100NF-0603SMT 1UF-16V-0805SMT B2 B2 5 10UF-16V_TANTBSMT R128 1K-0603SMT R373 1K-0603SMT D2 D2 C572 R348 51R-0603SMT 2_DDR2_DQS1 2_DDR2_DQ[0:15] C602 10NF-0603SMT A2 A2 C571 R349 51R-0603SMT 2_DDR2_DQS1# C2 C2 100NF-0603SMT C2 GND 1 C573 R350 51R-0603SMT 2_DDR2_DQS0 ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines 1 2 47UF-16V_TANTBSMT 100UF-FKSMT R352 4_7K-0603SMT E2 E2 6 7 AVIN PVIN GND 1 100NF-0603SMT 1UF-16V-0805SMT 26 1 R351 51R-0603SMT 2_DDR2_DQS0# DDR2_A[0:12] 2 2_DDR2_A[0:12] 10UF-16V_TANTBSMT A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 14. DDR2 FPGA Controller DDR2_DQ[0:15] A B C202 FB4 10NF-0603SMT 5 BLM41PG600SN1 C197 10NF-0603SMT 1_8V C203 + C211 VDDL R93 OPEN-0603SMT R90 1K-0603SMT R94 1K-0603SMT C212 + C200 1_8V + C198 1_8V C213 R92 22UF-16V_TANTBSMT 100NF-0603SMT 1K_ADJ/SMT3MM 1UF-16V-0805SMT C201 C199 C214 R88 4_7K-0603SMT PP11 1_8V VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREF VDDL VSSDL 100NF-0603SMT U18B VDDQ VREF SD DDR2-SDRAM-84FBGA A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7 5 4 1UF-16V-0805SMT U17 C183 2 16-BIT DDR2 INSTANCE #1 C184 8 3 4 DDR2-SDRAM-84FBGA U18A C194 + B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7 C195 10UF-16V_TANTBSMT DDR2_DQ15 DDR2_DQ14 DDR2_DQ13 DDR2_DQ12 DDR2_DQ11 DDR2_DQ10 DDR2_DQ9 DDR2_DQ8 DDR2_DQ7 DDR2_DQ6 DDR2_DQ5 DDR2_DQ4 DDR2_DQ3 DDR2_DQ2 DDR2_DQ1 DDR2_DQ0 DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_DQS0 DDR2_DQS0# DDR2_DQS1 DDR2_DQS1# DDR2_DM0 DDR2_DM1 DDR2_K DDR2_K# DDR2_CKE0# DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_ODT0 DDR2_CS0# DDR2_BA0 DDR2_BA1 C196 + 1UF-16V-0805SMT 47UF-16V_TANTBSMT C193 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7 100NF-0603SMT C185 LP2996-SO8 VTT VSENSE 100NF-0603SMT 100UF-FKSMT 6 7 AVIN PVIN GND 1 R89 0R-0603SMT PP10 DDR_VTT 1 2 + [7] [7] DDR2_DQS0 [7] DDR2_DQS0# [7] DDR2_DQS1 [7] DDR2_DQS1# [7] DDR2_DM0 [7] DDR2_DM1 [7] DDR2_K [7] DDR2_K# [7] DDR2_CKE0 [7] DDR2_WE# [7] DDR2_RAS# [7] DDR2_CAS# [7] DDR2_ODT0 [7] DDR2_CS0# [7] DDR2_BA0 [7] DDR2_BA1 [7] DDR2_A[0:12] DDR2_DQ[0:15] 3 1_8V 1K_ADJ/SMT3MM R359 R357 1K-0603SMT R361 1K-0603SMT R91 0R-0603SMT 1UF-16V-0805SMT 10NF-0603SMT C 1_8V 100NF-0603SMT 22UF-16V_TANTBSMT 1_8V + C592 2_VDDL R360 OPEN-0603SMT R358 0R-0603SMT FB12 C590 BLM41PG600SN1 C585 10NF-0603SMT C593 + C588 1_8V + C586 1_8V 1UF-16V-0805SMT C589 C587 2 1UF-16V-0805SMT 2 2_5V PP15 1_8V R355 4_7K-0603SMT 100NF-0603SMT VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREF VDDL VSSDL VDDQ VREF SD U33B 5 4 U32 C578 2 1UF-16V-0805SMT DDR2-SDRAM-84FBGA A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7 C577 2_5V C579 8 3 16-BIT DDR2 INSTANCE #2 + DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7 C582 D a te : 2_DDR2_DQ15 2_DDR2_DQ14 2_DDR2_DQ13 2_DDR2_DQ12 2_DDR2_DQ11 2_DDR2_DQ10 2_DDR2_DQ9 2_DDR2_DQ8 2_DDR2_DQ7 2_DDR2_DQ6 2_DDR2_DQ5 2_DDR2_DQ4 2_DDR2_DQ3 2_DDR2_DQ2 2_DDR2_DQ1 2_DDR2_DQ0 2_DDR2_A0 2_DDR2_A1 2_DDR2_A2 2_DDR2_A3 2_DDR2_A4 2_DDR2_A5 2_DDR2_A6 2_DDR2_A7 2_DDR2_A8 2_DDR2_A9 2_DDR2_A10 2_DDR2_A11 2_DDR2_A12 2_DDR2_DQS0 2_DDR2_DQS0# 2_DDR2_DQS1 2_DDR2_DQS1# 2_DDR2_DM0 2_DDR2_DM1 2_DDR2_K 2_DDR2_K# 2_DDR2_CKE0# 2_DDR2_WE# 2_DDR2_RAS# 2_DDR2_CAS# 2_DDR2_ODT0 2_DDR2_CS0# 2_DDR2_BA0 2_DDR2_BA1 C584 + 10UF-16V_TANTBSMT PP14 2_DDR_VTT 1 S he e t 8 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP2M VIDEO Card P roje c t Fri. March 09, 2007 [7] [7] 2_DDR2_DQS0 [7] 2_DDR2_DQS0# [7] 2_DDR2_DQS1 [7] 2_DDR2_DQS1# [7] 2_DDR2_DM0 [7] 2_DDR2_DM1 [7] 2_DDR2_K [7] 2_DDR2_K# [7] 2_DDR2_CKE0 [7] 2_DDR2_WE# [7] 2_DDR2_RAS# [7] 2_DDR2_CAS# [7] 2_DDR2_ODT0 [7] 2_DDR2_CS0# [7] 2_DDR2_BA0 [7] 2_DDR2_BA1 [7] 2_DDR2_A[0:12] 2_DDR2_DQ[0:15] DDR2 Device/Termination B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7 C583 R356 0R-0603SMT 1 2_DDR2_A[0:12] S iz e C Title DDR2-SDRAM-84FBGA U33A LP2996-SO8 VTT VSENSE + 1_8V 100NF-0603SMT C580 1_8V C591 47UF-16V_TANTBSMT C581 D 1 2 10NF-0603SMT 6 7 AVIN PVIN GND 1 100NF-0603SMT 100UF-FKSMT 2_5V 3 C594 1UF-16V-0805SMT 2_5V C215 100NF-0603SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 100NF-0603SMT 1 2 4 C595 C182 100NF-0603SMT 1 2 27 10NF-0603SMT DDR2_DQ[0:15] C596 2_DDR2_DQ[0:15] 100NF-0603SMT 5 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 15. DDR2 Device/Termination DDR2_A[0:12] 22UF-16V_TANTBSMT 1UF-16V-0805SMT 22UF-16V_TANTBSMT 1UF-16V-0805SMT A B C D C444 + R258 0R-0805SMT C490 39PF-0402SMT C487 6 5 4 3 2 1 3_3V 10 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 SW7 20 19 18 17 16 15 14 13 12 11 C466 C484 5 C467 TX_GS4911_CTRL7 TX_GS4911_CTRL6 TX_GS4911_CTRL5 TX_GS4911_CTRL4 TX_GS4911_CTRL3 TX_GS4911_CTRL2 TX_GS4911_CTRL1 TX_GS4911_CTRL0 TX_VID_STD5 TX_VID_STD4 TX_VID_STD3 TX_VID_STD2 TX_VID_STD1 TX_VID_STD0 TX_GENLOCKn TX_IPSEL TX_BYPASS TX_AUTOBYPASS TX_FCTRL0 TX_FCTRL1 TX_DOUBLE TX_SKEW_EN 1V8_APLL XTAL_GND TX_LOCK_LOST TX_REF_LOST 1V8_PLL PLL_GND XTAL_VDD C485 + R283 R284 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C469 C450 GND_PAD R249 0R-0805SMT R240 0R-0805SMT C470 + IO_VDD PLL_GND + 33UF-16V_TANTBSMT 1V8_PLL C451 C452 EXB2HV102JV TX_GS4915_RESETn TX_GS4911_RESETn 4 1V8_PLL C454 C472 C473 10NF-0603SMT R291 22R-0603SMT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R274 22R-0603SMT GS4911BCNE3 LVDS/PCLK3_GND PCLK3 PCLK3 LVDS/PCLK3_VDD CORE_VDD TIMING_OUT8 TIMING_OUT7 TIMING_OUT6 TIMING_OUT5 TIMING_OUT4 IO_VDD TIMING_OUT3 TIMING_OUT2 TIMING_OUT1 ASR_SEL0 ASR_SEL1 IO_VDD C474 C475 + C456 C476 22R-0603SMT TX_GS4911_OUT1 R292 TX_GS4911_OUT2 R293 TX_GS4911_OUT3 R294 TX_GS4911_OUT4 R295 TX_GS4911_OUT5 R296 TX_GS4911_OUT6 R297 TX_GS4911_OUT7 R298 TX_GS4911_OUT8 R299 A_GND TX_PCLK3R273 49_9R-0603SMT A_GND 3 TX_TIMING_OUT8 TX_TIMING_OUT7 TX_TIMING_OUT6 TX_TIMING_OUT5 TX_TIMING_OUT4 TX_TIMING_OUT3 TX_TIMING_OUT2 3_3V 41 10 9 8 7 1_8V_DIG TX_PCLK1 6 4 5 A_GND TX_GS4915_RESETn TX_TIMING_OUT1 Locate close to U1 C491 100NF-0603SMT TX_PCLK3+ R272 49_9R-0603SMT 2 3 1 A_GND C458 PAD RESETb AGND CLKIN_SE SE_IN_VDD(1.8) AGND CLKIN+ CLKIN- PLL_VDD (1.8) AGND 100NF-0603SMT C459 1V8_APLL C460 VCO_GND R254 7_5R-0805SMT 2 A_GND 1_8V_DIG TX_CLKOUT_SE 3_3VDD A_GND TX_LOCK_GS4915 27 25 24 23 22 21 + 3_3V_FLTRD FB11 BLM21AG601SN1 3_3V C492 10NF-0603SMT Place on P3 of GS4915 device R280 0R-0805SMT R277 0R-0805SMT A_GND + PLL_VDD + 2 A_GND C501 3_3VDD 0R-0805SMT R279 0R-0805SMT R275 O/P R267 1_8V_FLTRD C498 C510 5 R278 0R-0805SMT R276 3R3-0805SMT C497 C503 13 C504 C513 12 U23F 74LVC04/SO HSMF-C165 D25 RED 3_3V HSMF-C165 D24 RED 3_3V HSMF-C165 D23 RED 3_3V 1 S he e t 9 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 C517 ECP2M VIDEO Card P roje c t 10 U23E 74LVC04/SO 3_3V 150R-0603SMT R271 GREEN Place on P7,15,25,27,32 of GS4915 device 11 8 U23D 74LVC04/SO GREEN 150R-0603SMT R266 TX LOCK 4 U23B 74LVC04/SO TX Video Clocks 6 D a te : Tues. October 23, 2007 S iz e C Title A_GND + 1_8V_DIG [12] C496 9 3 TX_LOCK_LOST 3_3V GREEN 150R-0603SMT TX LOCK LOST 2 R260 TX REF LOST U23A 74LVC04/SO 3_3V TX STATUS LEDs VCO_GND R244 0R-0805SMT R246 0R-0805SMT R247 0R-0805SMT R253 0R-0805SMT Create wide bus 1 R243 0R-0805SMT R245 0R-0805SMT R250 0R-0805SMT R252 0R-0805SMT 3_3V 1 TX_REF_LOST U23C 74LVC04/SO 3_3V TX_GS4915_CTRL[0:7] TX_LOCK_GS4915 0R-0603SMT A_GND R242 0R-0805SMT TX_SE_REFCLK [12] VCO_GND Locate close to U1 TX_GC4915_CLKOUTN [6] TX_GC4915_CLKOUTP [6] 100-ohm Diffential matched pair VCO_GND Place on P1 and P23 of GS4915 device + 1 2 3 GO1555 NC GND FB10 BLM21AG601SN1 1_8V TX_SKEW_EN TX_GS4915_CTRL7 TX_DOUBLE TX_GS4915_CTRL6 TX_FCTRL1 TX_GS4915_CTRL5 TX_FCTRL0 TX_GS4915_CTRL4 TX_AUTOBYPASS TX_GS4915_CTRL3 T X _B Y P AS S T X _ G S 4915_ C T R L 2 TX_IPSEL TX_GS4915_CTRL1 TX_GS4915_CTRL0 EXB2HV102JV VCTR GND VCC U21 26 A_GND 5 6 7 C461 100NF-0603SMT VCO_VDD 1_8V_DIG 28 29 30 + GS4915-INE3 LOCK AGND SE_LVL_VDD(1.8 or 3.3) CLKOUT_SE SE_OUT_VDD (1.8) AGND DIFF_OUT_VDD(1.8) CLKOUT- CLKOUT+ AGND C479 10UF-16V_TANTBSMT R289 150K-0603SMT VCO_VDD Place @ P10 & P14 of GS4911 device Place on P38 of GS4915 device R288 150K-0603SMT REG_VDD (3.3) U22 VCO_GND + VCO_VDD C477 3_3VDD R255 0R-0805SMT 33UF-16V_TANTBSMT APLL_GND + 1V8_APLL C457 R251 0R-0805SMT R241 0R-0805SMT R237 0R-0805SMT PLL_VDD 100-ohm Diffential matched pair TX_CLKIN+ TX_CLKIN- Locate close to U22 22R-0603SMT R270 C488 PCLK_GND 100NF-0603SMT TX_PCLK3+ TX_PCLK31V8_PCLK C489 4911_CORE_VDD 100NF-0603SMT TX_TIMING_OUT8 TX_TIMING_OUT7 TX_TIMING_OUT6 TX_TIMING_OUT5 TX_TIMING_OUT4 IO_VDD TX_TIMING_OUT3 TX_TIMING_OUT2 TX_TIMING_OUT1 R269 22R-0603SMT 100NF-0603SMT FB9 BLM21AG601SN1 Locate close to U22 TX_GS4911_PCLK2 [12] TX_PCLK1 R290 22R-0603SMT Locate close to U22 [12] TX_GS4911_OUT[1:8] C455 10UF-16V_TANTBSMT Place @ P18, 31, 38, 50, 62 of GS4911 device 2_5V C453 10NF-0603SMT TX_GSPI_CSn [12] GSPI_DO_TX [10] GSPI_DI [12] GSPI_CLK [10,12] GSPI_HST_JTAG [10,12] C471 R236 0R-0805SMT TX_VID_STD0 TX_VID_STD1 TX_VID_STD2 TX_VID_STD3 TX_VID_STD4 TX_VID_STD5 TX_GENLOCKn TX_GS4911_RESETn LOCK_LOST REF_LOST VID_PLL_VDD VID_PLL_GND XTAL_VDD X1 X2 XTAL_GND CORE_GND ANALOG_VDD NC ANALOG_GND AUD_PLL_GND AUD_PLL_VDD 10FID HSYNC [12] TX_FSYNC 0R-0603SMT 0R-0603SMT + U24 C468 [12] TX_VSYNC APLL_GND 1V8_APLL 22R-0603SMT [12] TX_HSYNC R268 R264 0R-0603SMT 3_3V C449 Place @ P45 & P53 of GS4911 device OPEN-0603SMT 12 11 10 9 8 7 10NF-0603SMT Place @ P26 & P44 of GS4911 device 3_3V C448 TX CONTROL SWITCHES TDA10H0SK1 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 C447 R261 100NF-0603SMT R265 1M-0603SMT SW11 TDA06H0SK1 6 5 4 3 2 1 [12] TX_GS4911_CTRL[0:7] 3_3V Y3 CS10-27.000MABJ-UT R259 51R-0603SMT PCLK_GND + 1V8_PCLK + C482 C464 R256 0R-0805SMT J110 Johnson 142-0711-201 1 C481 XTAL_GND + C445 C463 24PF-0402SMT XTAL_GND C480 XTAL_GND 4911_CORE_VDD R248 0R-0805SMT R239 0R-0805SMT 33UF-16V_TANTBSMT 33UF-16V_TANTBSMT 100NF-0603SMT 100NF-0603SMT Place on P5 of GS4911 device 10NF-0603SMT 10UF-16V_TANTBSMT 1_8V C462 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT + 10NF-0603SMT XTAL_VDD C465 C483 1_8V 10UF-16V_TANTBSMT 10UF-16V_TANTBSMT 2 10NF-0603SMT C446 33UF-16V_TANTBSMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 13 10UF-16V_TANTBSMT 10UF-16V_TANTBSMT 10 VCO_VDD R235 0R-0805SMT 1K RN21B 16 RN21A 1 12 IO_VDD 10NF-0603SMT 15 2 14 1K RN21C 3 1K RN21D 4 1K RN21E 5 11 1K RN21F 6 1K RN21G 7 100NF-0603SMT 100NF-0603SMT TX_GENLOCKn 1K 9 1K RN21H 8 36 + 4911_CORE_VDD 10NF-0603SMT 10NF-0603SMT R257 1K-0603SMT 37 33UF-16V_TANTBSMT IO_VDD TX_GS4911_RESETn TX_GSPI_CSn TX_GSPI_SDOUT TX_GSPI_SDIN TX_GSPI_SCK TX_GSPI_HOST PLL_GND 1V8_PLL 1V8_PCLK PCLK_GND TX_PCLK1i IO_VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GENLOCK NC IO_VDD RESET CS_TMS SDOUT_TDO SDIN_TDI SCLK_TCLK JTAG/HOST PHS_GND PHS_VDD PCLK1&2_VDD PCLK1&2_GND PCLK1 IO_VDD PCLK2 VSYNC IO_VDD FSYNC NC VID_STD0 VID_STD1 VID_STD2 VID_STD3 VID_STD4 CORE_VDD VID_STD5 ACLK1 ACLK2 ACLK3 IO_VDD ASR_SEL2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO_VDD 10NF-0603SMT 10NF-0603SMT C486 34 10NF-0603SMT 11 A_GND 31 10UF-16V_TANTBSMT RN20A 11 A_GND 40 AGND IPSEL 15 RN20B 2 9 C478 1K 38 14 1K RN20C 3 13 4 1K RN20D C499 16TX_GS4915_RESETn 1 39 VCO_VDD(2.5) GND 12 CP_VDD (2.5) BYPASS 13 CP_CTRL/Rset AUTOBYPASSb 14 35 VCO_GND FCTR0 16 LF D_VDD (1.8) 15 1_8V_DIG PLL_VDD 32 DIV_VDD(1.8) SKEW_EN 19 VCOb FCTR1 17 VCO DOUBLE 18 AGND GND 20 33 100NF-0603SMT 6 12 5 C500 1K 10 1K RN20G 7 1K RN20H 8 3 C502 1K RN20E 100UF-10V_TANTBSMT C494 100NF-0603SMT C493 33UF-16V_TANTBSMT 8 GND GND 4 C495 1K RN20F 100NF-0603SMT 100UF-10V_TANTBSMT 1_8V 10NF-0603SMT Place @ P3 & P54 of GS4911 device 33UF-16V_TANTBSMT 100NF-0603SMT 10NF-0603SMT 14 7 14 7 14 7 14 7 14 7 10NF-0603SMT 4 10NF-0603SMT 1_8V 10NF-0603SMT 5 33UF-16V_TANTBSMT 14 7 3_3V 10NF-0603SMT 28 10NF-0603SMT A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 16. Tx Video Clocks A B C D 10NF-0603SMT C531 XTAL_GND 3_3V 6 5 4 3 2 1 3_3V 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 SW10 20 19 18 17 16 15 14 13 12 11 RX_GS4911_CTRL7 RX_GS4911_CTRL6 RX_GS4911_CTRL5 RX_GS4911_CTRL4 RX_GS4911_CTRL3 RX_GS4911_CTRL2 RX_GS4911_CTRL1 RX_GS4911_CTRL0 RX_VID_STD5 RX_VID_STD4 RX_VID_STD3 RX_VID_STD2 RX_VID_STD1 RX_VID_STD0 RX_GENLOCKn RX_IPSEL RX_BYPASS RX_AUTOBYPASS RX_FCTRL0 RX_FCTRL1 RX_DOUBLE RX_SKEW_EN R328 R329 5 RX CONTROL SWITCHES 20 19 18 17 16 15 14 13 12 11 3_3V 12 11 10 9 8 7 C524 C525 IO_VDD C526 C527 1V8_APLL XTAL_GND 65 GND_PAD [12] RX_FSYNC 0R-0603SMT 0R-0603SMT 4 EXB2HV102JV RX_GS4915_RESETn RX_GS4911_RESETn 4 RX_VID_STD0 RX_VID_STD1 RX_VID_STD2 RX_VID_STD3 RX_VID_STD4 RX_VID_STD5 RX_GENLOCKn RX_GS4911_RESETn LOCK_LOST REF_LOST VID_PLL_VDD VID_PLL_GND XTAL_VDD X1 X2 XTAL_GND CORE_GND ANALOG_VDD NC ANALOG_GND AUD_PLL_GND AUD_PLL_VDD 10FID HSYNC U27 [12] RX_VSYNC RX_LOCK_LOST RX_REF_LOST 1V8_PLL PLL_GND XTAL_VDD APLL_GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1V8_APLL C535 Place @ P10 & P14 of GS4911 device 1V8_APLL C534 C523 IO_VDD Place @ P18, 31, 38, 50, 62 of GS4911 device APLL_GND 1V8_APLL 22R-0603SMT [12] RX_HSYNC R313 R309 0R-0603SMT OPEN-0603SMT R310 1M-0603SMT PLL_GND R307 1V8_PLL C533 1V8_PLL C532 SW8 TDA10H0SK1 10 9 8 7 6 5 4 3 2 1 10NF-0603SMT TDA06H0SK1 6 5 4 3 2 1 C522 10NF-0603SMT Place @ P3 & P54 of GS4911 device C521 Y4 CS10-27.000MABJ-UT [12] RX_GS4911_CTRL[0:7] 24PF-0402SMT C541 39PF-0402SMT C538 XTAL_GND R308 51R-0603SMT J111 Johnson 142-0711-201 1 PCLK_GND C530 Place @ P45 & P53 of GS4911 device 1V8_PCLK XTAL_GND 10NF-0603SMT 10NF-0603SMT 5 10NF-0603SMT 4911_CORE_VDD 10NF-0603SMT C520 10NF-0603SMT 2 10NF-0603SMT 10NF-0603SMT 13 10NF-0603SMT 10NF-0603SMT 10 Place @ P26 & P44 of GS4911 device 15 10NF-0603SMT RX_GENLOCKn R305 22R-0603SMT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 [12] RX_GS4911_OUT[1:8] R319 22R-0603SMT GS4911BCNE3 LVDS/PCLK3_GND PCLK3 PCLK3 LVDS/PCLK3_VDD CORE_VDD TIMING_OUT8 TIMING_OUT7 TIMING_OUT6 TIMING_OUT5 TIMING_OUT4 IO_VDD TIMING_OUT3 TIMING_OUT2 TIMING_OUT1 ASR_SEL0 ASR_SEL1 22R-0603SMT R315 C540 100NF-0603SMT C539 100NF-0603SMT 2 A_GND A_GND A_GND RX_GS4915_RESETn 22R-0603SMT RX_GS4911_OUT1 R320 RX_GS4911_OUT2 R321 RX_GS4911_OUT3 R322 RX_GS4911_OUT4 R323 RX_GS4911_OUT5 R324 RX_GS4911_OUT6 R325 RX_GS4911_OUT7 R326 RX_GS4911_OUT8 R327 3 RX_TIMING_OUT8 RX_TIMING_OUT7 RX_TIMING_OUT6 RX_TIMING_OUT5 RX_TIMING_OUT4 RX_TIMING_OUT3 RX_TIMING_OUT2 RX_TIMING_OUT1 3_3V 41 10 9 8 7 1_8V_DIG RX_PCLK1 6 A_GND 4 5 3 1 3_3VDD PLL_VDD 100-ohm Diffential matched pair RX_CLKIN+ RX_CLKIN- Locate close to U1 C542 100NF-0603SMT VCO_VDD PAD RESETb AGND CLKIN_SE SE_IN_VDD(1.8) AGND CLKIN+ CLKIN- PLL_VDD (1.8) AGND REG_VDD (3.3) U26 VCO_GND Place on P38 of GS4915 device Locate close to U26 RX_PCLK3RX_PCLK3+ R317 R318 49_9R-0603SMT 49_9R-0603SMT R314 22R-0603SMT PCLK_GND RX_PCLK3+ RX_PCLK31V8_PCLK 4911_CORE_VDD RX_TIMING_OUT8 RX_TIMING_OUT7 RX_TIMING_OUT6 RX_TIMING_OUT5 RX_TIMING_OUT4 IO_VDD RX_TIMING_OUT3 RX_TIMING_OUT2 RX_TIMING_OUT1 RX_GS4911_PCLK2 [12] RX_PCLK1 R304 22R-0603SMT Locate close to U26 RX_GSPI_CSn [12] GSPI_DO [12] GSPI_DO_TX [9] GSPI_CLK [9,12] GSPI_HST_JTAG [9,12] 3 VCO_GND R302 2_5R-0805SMT VCO_VDD 29 A_GND 1_8V_DIG RX_CLKOUT_SE 3_3VDD A_GND RX_LOCK_GS4915 26 24 23 22 21 EXB2HV102JV C544 A_GND C550 C551 3_3VDD A_GND C543 C546 C547 2 Place on P1 and P23 of GS4915 device C545 1_8V_DIG Place on P7,15,25,27,32 of GS4915 device A_GND PLL_VDD RX_SKEW_EN RX_GS4915_CTRL7 RX_DOUBLE RX_GS4915_CTRL6 RX_FCTRL1 RX_GS4915_CTRL5 RX_FCTRL0 RX_GS4915_CTRL4 RX_AUTOBYPASS RX_GS4915_CTRL3 R X _ G S 4915_C T R L 2 R X _B Y P AS S RX_IPSEL RX_GS4915_CTRL1 RX_GS4915_CTRL0 O/P 2 1 3 [6] [6] 5 9 1 ECP2M VIDEO Card P roje c t 3_3V 13 150R-0603SMT R316 HSMF-C165 D28 RED 12 U28F 74LVC04/SO GREEN 3_3V HSMF-C165 D27 RED 3_3V HSMF-C165 D26 RED 3_3V S he e t 10 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 10 U28E 74LVC04/SO 8 GREEN 150R-0603SMT R311 RX LOCK U28D 74LVC04/SO RX Video Clocks 11 D a te : Tues. October 23, 2007 S iz e C Title [12] 6 U28C 74LVC04/SO 3_3V 4 U28B 74LVC04/SO 3_3V GREEN 150R-0603SMT RX LOCK LOST 2 R306 RX REF LOST RX STATUS LEDs 1 U28A 74LVC04/SO 3_3V 3_3V 3 RX_LOCK_LOST [12] 1 RX_REF_LOST RX_SE_REFCLK RX_GS4915_CTRL[0:7] RX_LOCK_GS4915 0R-0603SMT VCO_GND Place on P3 of GS4915 device R312 Locate close to U1 RX_GC4915_CLKOUTN RX_GC4915_CLKOUTP 100-ohm Diffential matched pair VCO_GND GO1555 NC GND C552 10NF-0603SMT 1_8V_DIG 27 VCTR GND VCC U25 25 28 A_GND 5 6 7 C528 100NF-0603SMT VCO_VDD 30 + GS4915-INE3 LOCK AGND SE_LVL_VDD(1.8 or 3.3) CLKOUT_SE SE_OUT_VDD (1.8) AGND DIFF_OUT_VDD(1.8) CLKOUT- CLKOUT+ AGND C536 10UF-16V_TANTBSMT R301 150K-0603SMT R300 150K-0603SMT 2 8 GND GND 4 XTAL_VDD 1K RN23C 16 RN23A 1 1K RN23B 2 14 3 1K RN23D 4 12 1K RN23E 5 11 1K RN23F 6 1K RN23G 7 10NF-0603SMT IO_VDD RX_GS4911_RESETn RX_GSPI_CSn GSPI_SDOUT GSPI_SDIN GSPI_SCK RX_GSPI_HOST PLL_GND 1V8_PLL 1V8_PCLK PCLK_GND RX_PCLK1i IO_VDD GENLOCK NC IO_VDD RESET CS_TMS SDOUT_TDO SDIN_TDI SCLK_TCLK JTAG/HOST PHS_GND PHS_VDD PCLK1&2_VDD PCLK1&2_GND PCLK1 IO_VDD PCLK2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1K 9 1K RN23H 8 IPSEL 11 15 RN22B 2 IO_VDD GND 12 10NF-0603SMT VSYNC IO_VDD FSYNC NC VID_STD0 VID_STD1 VID_STD2 VID_STD3 VID_STD4 CORE_VDD VID_STD5 ACLK1 ACLK2 ACLK3 IO_VDD ASR_SEL2 4911_CORE_VDD BYPASS 13 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AUTOBYPASSb 14 14 1K RN22C 3 1K RN22D 10NF-0603SMT 10NF-0603SMT IO_VDD 37 D_VDD (1.8) 15 13 4 1K RN22E 5 11 1K RN22F 16RX_GS4915_RESETn C537 10NF-0603SMT A_GND 40 AGND R303 1K-0603SMT FCTR0 16 1_8V_DIG FCTR1 10NF-0603SMT RN22A 1 38 CP_VDD (2.5) A_GND 17 CP_CTRL/Rset VCO_VDD 39 VCO_VDD(2.5) 36 LF PLL_VDD 32 DOUBLE 18 6 C529 1K 35 VCO_GND 34 VCOb 33 100NF-0603SMT VCO 31 AGND SKEW_EN 19 10NF-0603SMT 14 7 DIV_VDD(1.8) GND 20 10 14 7 14 7 14 7 14 7 Place on P5 of GS4911 device 1K 9 1K RN22H 8 1K RN22G 7 10NF-0603SMT 14 7 29 10NF-0603SMT A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 17. Rx Video Clocks A B C TX_OUT3_P TX_OUT3_N TX_CLKOUT_P TX_CLKOUT_N TX_OUT2_P TX_OUT2_N TX_OUT1_P TX_OUT1_N TX_OUT0_P 5 J51 Johnson 142-0711-201 J49 Johnson 142-0711-201 J47 Johnson 142-0711-201 J45 Johnson 142-0711-201 J43 Johnson 142-0711-201 J41 Johnson 142-0711-201 3M_10226-1210VE Mounting_R Mounting_L 27 28 26 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 Place resistors next to U1 DDC_Gnd_26 RxIn0RxIn0Gnd RxIn0+ Sense USB/DDC_Gnd RxIn1RxIn1Gnd RxIn1+ DDC/SDA RxIn2RxIn2Gnd RxIn2+ USB+ USB_Shield USBDDC/SCL RxClkInRxClkInGnd RxClkIn+ USB_+5VDC DDC_+5VDC RxIn3RxIn3Gnd RxIn3+ DDC_Gnd_1 J125 3M_10226-1210VE Mounting_R Mounting_L Video RX 27 28 J124 DDC_Gnd_1 TxOut0TxOut0Gnd TxOut0+ Sense USB/DDC_Gnd TxOut1TxOut1Gnd TxOut1+ DDC/SDA TxOut2TxOut2Gnd TxOut2+ USB+ USB_Shield USBDDC/SCL TxClkOutTxClkOutGnd TxClkOut+ USB_+5VDC DDC_+5VDC TxOut3TxOut3Gnd TxOut3+ DDC_Gnd_26 R150 100R-0603SMT 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 R151 100R-0603SMT TX_OUT0_N Video TX R152 100R-0603SMT 2 2 2 2 2 2 J39 Johnson 142-0711-201 R153 100R-0603SMT 2 4 2 LVDS_INN_0 LVDS_INP_1 LVDS_INN_1 LVDS_INP_2 LVDS_INN_2 LVDS_INP_3 1 1 1 1 1 1 1 RX_CLKIN_N RX_CLKIN_P RX_IN3_N RX_IN3_P RX_IN2_N RX_IN2_P RX_IN1_N RX_IN1_P RX_IN0_N RX_IN0_P LVDS_INN_3 DQS PAIR LVDS_INP_0 1 R154 100R-0603SMT R130 100R-0603SMT R132 100R-0603SMT R134 100R-0603SMT R136 100R-0603SMT J52 Johnson 142-0711-201 J50 Johnson 142-0711-201 J48 Johnson 142-0711-201 J46 Johnson 142-0711-201 J44 Johnson 142-0711-201 J42 Johnson 142-0711-201 J40 Johnson 142-0711-201 J38 Johnson 142-0711-201 DP1 R138 LVDS_OUTP_1 LVDS_OUTN_1 LVDS_OUTP_2 LVDS_OUTN_2 LVDS_OUTP_3 1 1 1 1 1 3 3 LVDS_PROBEN Place this resistor close to test point LVDS_PROBEP LVDS_OUTN_3 LVDS_OUTN_0 1 1 LVDS_OUTP_0 1 100R-0603SMT 1 2 2 2 2 2 2 2 2 R131 100R-0603SMT R133 100R-0603SMT R135 100R-0603SMT J37 Johnson 142-0711-201 RX_CLKIN_P RX_CLKIN_N LOOP_P7 LOOP_N7 RX_IN2_P RX_IN2_N LOOP_P6 LOOP_N6 RX_IN1_P RX_IN1_N LOOP_P5 LOOP_N5 RX_IN0_P RX_IN0_N RX_IN3_P RX_IN3_N LOOP_P7 LOOP_N7 LOOP_P6 LOOP_N6 LOOP_P5 LOOP_N5 TX_CLKOUT_P TX_CLKOUT_N LOOP_P0 LOOP_N0 TX_OUT0_P TX_OUT0_N LOOP_P1 LOOP_N1 TX_OUT1_P TX_OUT1_N LOOP_P2 LOOP_N2 TX_OUT2_P TX_OUT2_N LOOP_P3 LOOP_N3 TX_OUT3_P TX_OUT3_N LOOP_P4 LOOP_N4 E23 E24 F26 G26 F21 H20 F24 F23 F22 J18 G23 G24 K19 G22 H26 H25 H24 H23 J19 G21 J26 J25 J20 H22 K18 H21 J21 K20 J24 J23 K21 L19 K23 K24 K26 K25 M19 K22 L26 M26 M20 L23 L24 L22 N26 M23 M24 M22 N25 N24 Bank3 ecp2m-672fpbga Right PR9A/VREF1_2 PR9B/VREF2_2 PR11A*/RUM0_SPLLT_IN_A PR11B*/RUM0_SPLLC_IN_A PR37A*/PCLKT3_0 PR12A/RUM0_SPLLT_FB_A PR37B*/PCLKC3_0 PR12B/RUM0_SPLLC_FB_A PR38A/VREF1_3 PR13A* PR38B/VREF2_3 PR13B* PR39A* PR14A PR39B* PR14B PR40A PR40B PR15A* PR15B* PR41A*/RLM2_SPLLT_IN_A PR16A PR41B*/RLM2_SPLLC_IN_A PR16B PR42A/RLM2_SPLLT_FB_A PR42B/RLM2_SPLLC_FB_A PR17A* PR17B* PR44A* PR44B* PR18A PR18B PR45A PR19A* PR45B PR19B* PR46A* PR46B* PR20A PR20B PR47A PR21A* PR47B PR21B* PR48A* PR22A PR48B* PR22B PR49A PR23A* PR49B PR23B* PR50A* PR24A PR50B* PR51A PR24B PR25A* PR51B PR25B* PR53A* PR53B* PR26A PR26B PR54A PR28A*/RUM1_SPLLT_IN_A PR54B PR28B*/RUM1_SPLLC_IN_A PR55A* PR29A/RUM1_SPLLT_FB_A PR55B* PR29B/RUM1_SPLLC_FB_A PR56A PR30A* PR57A*/RLM0_GPLLT_FB_A PR30B* PR57B*/RLM0_GPLLC_FB_A PR31A PR58A/RLM0_GPLLT_IN_A PR31B PR58B/RLM0_GPLLC_IN_A PR59A*/RLM0_GDLLT_IN_A PR32A* PR32B* PR59B*/RLM0_GDLLC_IN_A PR33A PR60A/RLM0_GDLLT_FB_A PR33B PR60B/RLM0_GDLLC_FB_A PR34A* PR34B* PR35A/PCLKT2_0 PR35B/PCLKC2_0 U1E Place these resistors close to U1 Device LOOP_P0 LOOP_N0 Place these resistors close to SMA pair LOOP_P1 LOOP_N1 Place these resistors close to U1 Device LOOP_P2 LOOP_N2 R137 100R-0603SMT 2 LOOP_P6 3 LOOP_P3 2 LOOP_N3 2 Bank2 LOOP_P4 LOOP_N4 4 LOOP_P7 D 5 LOOP_P5 LOOP_N5 R141 100R-0603SMT R142 100R-0603SMT R143 100R-0603SMT R144 100R-0603SMT R145 100R-0603SMT R146 100R-0603SMT R147 100R-0603SMT R148 100R-0603SMT LOOP_N6 30 LOOP_N7 N23 M21 P26 P25 N22 N20 P22 N21 P24 P23 N19 R22 R24 R23 P19 P21 R26 T26 R20 R21 R19 T19 U26 U25 T23 T22 T24 U24 V26 V25 U22 U18 W26 W25 U21 V24 W24 U20 V23 Y26 AA26 U19 V21 D a te : S iz e C Title LVDS_OUTP_3 LVDS_OUTN_3 LVDS_INP_3 LVDS_INN_3 Fri. March 09, 2007 1 S he e t 11 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP2M VIDEO Card P roje c t Differential I/O DQS PAIR LOOP_P0 LOOP_N0 LVDS_OUTP_0 LVDS_OUTN_0 LVDS_INP_2 LVDS_INN_2 LVDS_OUTP_1 LVDS_OUTN_1 LVDS_PROBEP LVDS_PROBEN LVDS_OUTP_2 LVDS_OUTN_2 LOOP_P1 LOOP_N1 LOOP_P2 LOOP_N2 LOOP_P4 LOOP_N4 LVDS_INP_1 LVDS_INN_1 LOOP_P3 LOOP_N3 LVDS_INP_0 LVDS_INN_0 1 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 18. Differential I/O A B C PB4 PB3 PB2 PB1 [5] FLASH_CLK 100NF-0603SMT C231 SW12 3 SW13 3 2 1 4 3 3 4 2 Momentary Switch B3F-1150 1 SW15 Momentary Switch B3F-1150 SW14 2 4 Momentary Switch B3F-1150 1 2 4 Momentary Switch B3F-1150 1 1 2 3 4 3 4 GND N/C CY2304-1 REF FBK VDD CLKA1 CLKA2 CLKB2 CLKB1 GND U19 Y2 OUT Vcc 8 7 6 5 CTS-CB3LV-3C-100.00MHZ 2 1 5 3 1 1 3 U34 OUT2 OUT1 3_3V OUT2 OUT1 MAX6817 IN2 IN1 U36 MAX6817 IN2 IN1 3_3V PB1 PB2 PB3 PB4 6 4 6 4 PUSHBUTTON SWITCHES FLASH_CLK OSC_IN_2 3_3V 3 4 5 6 7 8 13 RN17E 16 RN17F 1 RN17G 2 RN17H [10] RX_GSPI_CSn [9] TX_GSPI_CSn [9,10] GSPI_CLK [9] GSPI_DI [10] GSPI_DO [9,10] GSPI_HST_JTAG [9] TX_FSYNC [10] RX_FSYNC R333 R332 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2_767004 5V SCL GND SDA CLK1 CLK 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 LA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 4 LA2 LA4 LA6 LA8 LA10 LA12 LA14 LA16 LA18 LA20 LA22 LA24 LA26 LA28 LA30 LA32 LA34 [4,5] 0R-0603SMT FSYNC OPEN-0603SMT RX_GS4911_CTRL7 RX_GS4911_CTRL6 RX_GS4911_CTRL5 RX_GS4911_CTRL4 RX_GS4911_CTRL3 RX_GS4911_CTRL2 RX_GS4911_CTRL1 RX_GS4911_CTRL0 RX_GS4915_CTRL7 RX_GS4915_CTRL6 RX_GS4915_CTRL5 RX_GS4915_CTRL4 RX_GS4915_CTRL3 RX_GS4915_CTRL2 RX_GS4915_CTRL1 RX_GS4915_CTRL0 TX_GS4911_CTRL7 TX_GS4911_CTRL6 TX_GS4911_CTRL5 TX_GS4911_CTRL4 TX_GS4911_CTRL3 TX_GS4911_CTRL2 TX_GS4911_CTRL1 TX_GS4911_CTRL0 TX_GS4915_CTRL7 TX_GS4915_CTRL6 TX_GS4915_CTRL5 TX_GS4915_CTRL4 TX_GS4915_CTRL3 TX_GS4915_CTRL2 TX_GS4915_CTRL1 TX_GS4915_CTRL0 RX_GS4911_OUT1 RX_GS4911_OUT2 RX_GS4911_OUT3 RX_GS4911_OUT4 RX_GS4911_OUT5 RX_GS4911_OUT6 RX_GS4911_OUT7 RX_GS4911_OUT8 TX_GS4911_OUT1 TX_GS4911_OUT2 TX_GS4911_OUT3 TX_GS4911_OUT4 TX_GS4911_OUT5 TX_GS4911_OUT6 TX_GS4911_OUT7 TX_GS4911_OUT8 FSYNC G7 G8 F8 J10 D4 C3 F7 G9 C4 B2 C5 B3 E7 H10 F9 G10 E6 D5 H11 D7 F10 C6 A3 A4 A5 A6 H12 D8 G12 C8 C7 D6 H13 D9 A7 B8 C9 G13 E10 F12 A8 B9 E8 C10 A9 H14 D10 F13 E11 G14 D11 B10 A10 H15 H18 H16 D12 A11 A12 F14 C11 G15 C12 ecp2m-672fpbga PT2A PT2B PT3A PT3B PT4A PT4B PT5A PT5B PT6A PT6B PT7A PT7B PT8A PT8B PT9A PT9B PT10A PT10B PT11A PT11B PT12A PT12B PT13A PT13B PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT21A PT21B PT22A PT22B PT23A PT23B PT24B PT29A PT29B PT30A PT30B PT31A PT31B PT32A PT32B PT33A PT33B PT34A PT34B PT35A PT35B PT36A/VREF1_0 PT36B/VREF2_0 PT37A/PCLKT0_0 PT37B/PCLKC0_0 U1F GSRN Top PT38A/PCLKT1_0 PT38B/PCLKC1_0 PT39A/VREF1_1 PT39B/VREF2_1 PT40A PT40B PT41A PT41B PT42A PT42B PT43A PT43B PT44A PT44B PT45A PT45B PT46A PT46B E13 H17 E12 F15 D13 D14 E14 G17 E15 G18 D15 E16 F18 F19 D16 F17 D17 E17 PCIE_PERSTN [6] R64 0R-0603SMT GSRN LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 OSC_IN_2 PB1 PB2 PB3 PB4 LOGIC ANALYZER PROBE 9 10 11 12 13 EXB2HV151JV 14 150R 15 16 9 10 11 12 13 Gennum Video Interface [10] RX_HSYNC [10] RX_VSYNC [9] TX_HSYNC [9] TX_VSYNC [10] RX_GS4911_PCLK2 [9] TX_GS4911_PCLK2 [10] RX_SE_REFCLK [9] TX_SE_REFCLK [9] TX_GS4911_OUT[1:8] [10] RX_GS4911_OUT[1:8] [9] TX_GS4915_CTRL[0:7] [9] TX_GS4911_CTRL[0:7] [10] RX_GS4915_CTRL[0:7] LA1 LA3 LA5 LA7 LA9 LA11 LA13 LA15 LA17 LA19 LA21 LA23 LA25 LA27 LA29 LA31 LA33 2 9 RN17D 8 4 RN16H 8 RN17C 7 3 RN16G 6 RN17B 6 17 RN16F 1 5 15 RN16E 5 RN17A 4 12 RN16D R157 150R-0603SMT 14 RN16A 1 16 EXB2HV151JV RN16B 2 15 7 150R 11 RN16C 3 14 10 LTP-587HR/16-SEGMENT C233 10NF-0603SMT 18 [10] RX_GS4911_CTRL[0:7] C232 100NF-0603SMT OSC_IN_3 OSC_IN_4 3_3V 100MHZ GENERAL PURPOSE CLOCKS 3_3V DP U T S R P N M K H G F E D C B A D 4_7K-0603SMT R366 C597 C598 R364 D14 Bank0 BGA W16 AC20 AB20 AB17 W15 AC17 Y15 AA15 AB16 AC16 AB15 AC15 AA14 AB14 AC14 Y14 AC13 Bank1 SEGMENT A B C D E F G H K M N P R S T U DP 4_7K-0603SMT 4_7K-0603SMT 100NF-0603SMT 100NF-0603SMT 3 3 AC13 Y14 AC14 AB14 AA14 AC15 AB15 AC16 AB16 AA15 Y15 AC17 W15 AB17 AB20 AC20 W16 AA17 AA18 Y17 AC21 W17 AA19 Y18 AC22 AB21 AD26 AC23 AC25 W20 V17 AA20 Bank4 C599 + 12_0V 7 7 2_5V 3 C605 100NFX5R-0402SMT 0402 12 VOUT U35 LD1085CDT50-DPAK VIN C606 100NFX5R-0402SMT 0402 2 C601 + C607 100NF-0603SMT 3_3V RS232_TXD 1 SW6A SWITCH4 3 SW6B SWITCH3 4 SW6C SWITCH2 10 6 SW6D SWITCH1 9 1 SW5A SWITCH8 3 SW5B SWITCH7 12 4 SW5C SWITCH6 10 6 SW5D SWITCH5 9 P3 P2 P5 N6 P4 R3 P6 N7 P1 R1 N8 R5 T3 T4 P8 R6 T1 U1 R7 T5 U3 U4 U5 U6 U2 V1 W2 V2 V4 V3 W4 W3 W1 Y1 AA1 AB1 U7 V6 W5 Y4 U8 W6 Y3 AA3 V7 Y5 AB2 AA4 Y6 U9 AA5 AA6 Y7 V9 2 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 RS232_RXD RS232_TXD OSC_IN_3 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 RED1 YELLOW1 GREEN1 BLUE1 RED2 YELLOW2 GREEN2 BLUE2 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 OSC_IN_4 LCD1 16 1 3 4 5 2 6 11 10 13 8 2 MAX3232 TSSOP16 VCC C1+ C1C2+ C2V+ V- T1IN T2IN R1IN R2IN U37 GND T1OUT T2OUT R1OUT R2OUT 15 14 7 12 9 Contrast Adjustment RN18A 470R-1206SMT R158 3 1 14 LED-SMT1206_RED D16 LED-SMT1206_GREEN D19 BLUE1 GREEN1 YELLOW1 RED1 RS232_RXD LCD0 LCD1 LCD2 LCD3 LCD4 RN18D 6 11 1 R170 680R-0603SMT R171 680R-0603SMT R172 680R-0603SMT R173 680R-0603SMT R168 680R-0603SMT R169 680R-0603SMT 91 8 EXB2HV103JV 10K RN18H D a te : S iz e C Title Monday, December 17, 2007 SC VIDEO Card P roje c t FPGA TEST HEADER 5X2 2 4 6 8 10 2 4 6 8 10 12 14 16 LED-SMT1206_YELLOW D18 LED-SMT1206_GREEN D20 LED-SMT1206_BLUE D22 RED2 LCD_RS LCD_E LCD_DB1 LCD_DB3 LCD_DB5 LCD_DB7 BLUE2 GREEN2 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 C600 100NF-0603SMT 0603 Q13 2N2222/SOT23 12_0V Q11 2N2222/SOT23 12_0V Q9 2N2222/SOT23 12_0V 1 S he e t 12 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 CATHODE VDD RS E DB1 DB3 DB5 DB7 LCD_Connector LCD[0..10] ANODE VSS VO R/W DB0 DB2 DB4 DB6 J126 J127 1 3 5 7 9 1 3 5 7 9 11 13 15 LED-SMT1206_RED D15 Q7 2N2222/SOT23 12_0V YELLOW2 470R-1206SMT R165 EXB2HV103JV 10K RN18F 470R-1206SMT R163 1 4 13 EXB2HV103JV 10K LCD Connector RS232 LCD_R/W LCD_DB0 LCD_DB2 LCD_DB4 LCD_DB6 R161 470R-1206SMT R167 680R-0603SMT BLUE2 GREEN2 YELLOW2 RN18B 470R-1206SMT R159 2 15 1 EXB2HV103JV 10K 1 R166 680R-0603SMT LED-SMT1206_BLUE D21 Q12 2N2222/SOT23 12_0V Q10 2N2222/SOT23 12_0V RED2 LEDs LED-SMT1206_YELLOW D17 Q8 2N2222/SOT23 12_0V Q6 2N2222/SOT23 12_0V VR1 20K POT Murata PV37W101C01 PV37W ANODE 2 7 10 1 EXB2HV103JV 10K RN18G 470R-1206SMT R164 5 12 1 EXB2HV103JV 10K RN18E 470R-1206SMT R162 EXB2HV103JV 10K RN18C 470R-1206SMT R160 1 16 1 EXB2HV103JV 10K Backlight Adjustment BLUE1 GREEN1 [4] YELLOW1 RED1 VR2 20K POT Murata PV37W203C01 PV37W 2 470R 470R 8 9 RN19H EXB2HV471JV 470R 7 10 RN19G EXB2HV471JV 6 11 RN19F EXB2HV471JV 470R 470R 5 12 RN19E EXB2HV471JV 470R 4 13 RN19D EXB2HV471JV 3 14 RN19C EXB2HV471JV 470R 470R 2 15 RN19B EXB2HV471JV 1 16 RN19A EXB2HV471JV DIP SWITCHES PL37A*/PCLKT6_0 PL37B*/PCLKC6_0 PL38A/VREF2_6 PL38B/VREF1_6 PL39A* PL39B* PL40A PL40B PL41A*/LLM2_SPLLT_IN_A PL41B*/LLM2_SPLLC_IN_A PL42A/LLM2_SPLLT_FB_A PL42B/LLM2_SPLLC_FB_A PL44A* PL44B* PL45A PL45B PL46A* PL46B* PL47A PL47B PL48A* PL48B* PL49A PL49B PL50A* PL50B* PL51A PL51B PL55A* PL55B* PL57A*/LLM0_GPLLT_IN_A PL57B*/LLM0_GPLLC_IN_A PL58A/LLM0_GPLLT_FB_A PL58B/LLM0_GPLLC_FB_A PL59A*/LLM0_GDLLT_IN_A PL59B*/LLM0_GDLLC_IN_A PL60A/LLM0_GDLLT_FB_A PL60B/LLM0_GDLLC_FB_A PL62A* PL62B* PL63A PL63B PL64A* PL64B* PL65A PL65B PL66A* PL66B* PL67A PL67B PL68A* PL68B* PL69A PL69B C603 100NFX5R-0402SMT C604 0402 100NFX5R-0402SMT 0402 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 LA32 LA33 LA34 ecp2m-672fpbga PB40A/PCLKT4_0 PB40B/PCLKC4_0 PB41B/VREF1_4 PB42A PB42B PB48A PB49A PB49B PB50B PB51A PB52A PB52B PB54A PB54B PB57A PB58A PB59B PB60A PB61A PB61B PB63A PB65A PB65B PB68B PB69A PB69B PB70B PB71A PB71B PB72B PB73A PB73B U1D 1 0 8 1 0 4 10UF-16V_TANTBSMT 4_7K-0603SMT R362 R365 R371 5 VCC 5 VCC 1 0 5 1 0 1 0 GND 1 5 8 R370 Bank6 R369 5 120R-0805SMT 16-SEGMENT DISPLAY 10UF-16V_TANTBSMT 1 0 11 1 0 11 2 1 0 2 390R-0805SMT GND 2 GND 2 1 3 R363 4_7K-0603SMT R367 4_7K-0603SMT 4_7K-0603SMT R368 4_7K-0603SMT 1 R 3 2 Y 3 2 G 3 2 B 3 2 R 3 2 Y 3 2 G 3 2 B 3 2 31 3 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 19. FPGA Test 32 A B C D 5 5 VDDTX VDDRX VDDP VDDOB VDDIB VCC CORE C236 C237 C238 C239 C240 C241 C242 C246 C247 C258 C251 C261 C252 C277 C278 22PF-0402SMT C267 C279 3_3V 1000PF-0402SMT C268 C285 C286 C287 MH6 M HOLE2 M HOLE2 MH5 M HOLE2 M HOLE2 MH4 M HOLE2 M HOLE2 MH2 MH1 MH3 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C284 VDDTX_U 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C276 VDDRX_U 1000PF-0402SMT C266 VDDP_U 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C250 VDDOB 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C245 VDDIB 4 VDDAUX33 22PF-0402SMT C269 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C235 VCC_CORE 4 ecp2m-672fpbga VSS U1K VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 A13 A19 A2 A25 AA2 AA25 AB18 AB22 AB5 AB9 AE1 AE11 AE16 AE22 AE26 AE6 AF13 AF19 AF2 AF25 B1 B11 B16 B22 B26 B6 E18 E22 E5 E9 F2 F25 G11 G16 J22 J5 K11 K13 K14 K16 L10 L11 L16 L17 L2 L20 L25 L7 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T2 T20 T25 T7 U11 U13 U14 U16 V22 V5 Y11 Y16 ALL CAPS PLACED UNDER BGA 3 VCCIO5 VCCIO7 VCCIO6 VCCIO4 VCCIO3 VCCIO2 VCCIO1 VCCAUX 1_8V 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V C253 C254 C243 C255 C244 C256 C257 C259 C249 C260 C263 C264 C265 C271 C272 C273 C274 C275 C281 C282 C283 C289 C290 C291 C292 C294 C295 C296 C297 C299 C300 C301 C302 2 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C298 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C293 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C288 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C280 SC VIDEO Card P roje c t VSS/Decoupling D a te : Fri. March 09, 2007 S iz e C Title 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C270 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C262 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C248 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 2 1 S he e t 13 of 13 R ev 1.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 A B C D Lattice Semiconductor LatticeECP2M SMPTE SDI Evaluation Board User’s Guide Figure 20. VSS/Decoupling