Data Sheet

PCA9554B; PCA9554C
Low-voltage 8-bit I2C-bus and SMBus low power I/O port with
interrupt, weak pull-up
Rev. 2 — 4 August 2015
Product data sheet
1. General description
The PCA9554B and PCA9554C are low-voltage 8-bit General Purpose Input/Output
(GPIO) expanders with interrupt and weak pull-up resistors for I2C-bus/SMBus
applications. The only difference between the PCA9554B and PCA9554C is their I2C fixed
address allowing a larger number of the same device on the I2C-bus with no chance of
address conflict. NXP I/O expanders provide a simple solution when additional I/Os are
needed while keeping interconnections to a minimum, for example, in ACPI power
switches, sensors, push buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V allow
the PCA9554B/PCA9554C to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9554B/PCA9554C contain a register set of 8-bit Configuration, Input, Output,
and Polarity Inversion registers.
The PCA9554B is a pin-to-pin replacement for the PCA9554, while the PCA9554C
replaces the PCA9554A. Both of these devices replace other industry-standard part
numbers. More fully-featured parts PCAL9554B and PCAL9554C are also available with
Agile I/O features. See the respective data sheet for more details.
The PCA9554B/PCA9554C open-drain interrupt (INT) output is activated when any input
state differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the
PCA9554B/PCA9554C can remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
All input/output pins have weak pull-up resistors connected to them to eliminate external
components.
Three hardware pins (A0, A1, A2) select the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus. The PCA9554B and PCA9554C differ only in
their base I2C-bus addresses permitting a total of 16 devices on the I2C-bus, minimizing
the chance for address conflict, even in the most complex system.
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
2. Features and benefits
 I2C-bus to parallel port expander
 Operating power supply voltage range of 1.65 V to 5.5 V
 Low standby current consumption:
 1.5 A (typical at 5 V VDD)
 1.0 A (typical at 3.3 V VDD)
 Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
 Vhys = 0.10  VDD (typical)
 5 V tolerant I/Os
 Open-drain active LOW interrupt output (INT)
 400 kHz Fast-mode I2C-bus
 Input/output configuration register
 Polarity inversion register
 Internal power-on reset
 Power-up with all channels configured as inputs with weak pull-up resistors
 No glitch on power-up
 Latched outputs with 25 mA drive maximum capability for directly driving LEDs
 Latch-up performance exceeds 100 mA per JESD78, Class II
 ESD protection exceeds JESD22
 2000 V Human Body Model (A114-A)
 1000 V Charged-Device Model (C101)
 Packages offered: TSSOP16 and HVQFN16
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
3. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9554BBS
P4B
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3  3  0.85 mm
SOT758-1
PCA9554BPW
PA9554B
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9554CBS
P4C
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3  3  0.85 mm
SOT758-1
PCA9554CPW
PA9554C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature range
PCA9554BBS
PCA9554BBSHP
HVQFN16
Reel pack, SMD,
13-inch, Turned
6000
Tamb = 40 C to +85 C
PCA9554BPW
PCA9554BPWJ
TSSOP16
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +85 C
PCA9554CBS
PCA9554CBSHP
HVQFN16
Reel pack, SMD,
13-inch, Turned
6000
Tamb = 40 C to +85 C
PCA9554CPW
PCA9554CPWJ
TSSOP16
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +85 C
4. Block diagram
A0
A1
A2
SCL
SDA
8-bit
INPUT
FILTER
I2C-BUS/SMBus
CONTROL
write pulse
INPUT/
OUTPUT
PORTS
read pulse
VDD
VSS
POWER-ON
RESET
P0
P1
P2
P3
P4
P5
P6
P7
VDD
PCA9554B
PCA9554C
INT
LP
FILTER
002aah117
Remark: All I/Os are set to inputs at reset.
Fig 1.
PCA9554B_PCA9554C
Product data sheet
Block diagram of PCA9554B; PCA9554C
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
5. Pinning information
4
P1
5
P2
6
11 P6
P3
7
10 P5
VSS
8
PCA9554BPW
PCA9554CPW
13 INT
12 P7
9
2
P1
3
P2
4
14 VDD
13 SDA
11 INT
10 P7
9
P4
P6
002aah120
Transparent top view
002aah119
Fig 2.
PCA9554BBS
PCA9554CBS
8
P0
P0
P5
14 SCL
12 SCL
7
3
1
P4
A2
A2
6
15 SDA
VSS
16 VDD
2
5
1
A1
P3
A0
16 A1
terminal 1
index area
15 A0
5.1 Pinning
Pin configuration for TSSOP16
Fig 3.
Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Symbol
PCA9554B_PCA9554C
Product data sheet
Pin description
Pin
Description
TSSOP16
HVQFN16
A0
1
15
address input 0
A1
2
16
address input 1
A2
3
1
address input 2
P0[1]
4
2
Port P input/output 0
P1[1]
5
3
Port P input/output 1
P2[1]
6
4
Port P input/output 2
P3[1]
7
5
Port P input/output 3
VSS
8
6[2]
supply ground
P4[1]
9
7
Port P input/output 4
P5[1]
10
8
Port P input/output 5
P6[1]
11
9
Port P input/output 6
P7[1]
12
10
Port P input/output 7
INT
13
11
interrupt output (open-drain)
SCL
14
12
serial clock line
SDA
15
13
serial data line
VDD
16
14
supply voltage
[1]
All I/O are configured as input at power-on.
[2]
HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6. Functional description
Refer to Figure 1 “Block diagram of PCA9554B; PCA9554C”.
6.1 Device address
slave address
0
1
0
0
A2
fixed
slave address
A1
A0 R/W
0
hardware
selectable
1
1
1
A2
fixed
A1
hardware
selectable
002aah121
002aah122
a. PCA9554B address
Fig 4.
A0 R/W
b. PCA9554C address
Device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9554B/PCA9554C. The
lower two bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Table 4.
Pointer register bits
Command byte
Pointer register bits
Command byte Register
(hexadecimal)
Protocol
Power-up
default
Input port
read byte
xxxx xxxx[1]
Output port
read/write byte
1111 1111
02h
Polarity Inversion
read/write byte
0000 0000
03h
Configuration
read/write byte
1111 1111
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
0
0
0
0
0
0
0
1
01h
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
[1]
Undefined.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.3 Interface definition
Table 5.
Interface definition
Byte
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
PCA9554B
I2C-bus slave address
L
H
L
L
A2
A1
A0
R/W
PCA9554C
I2C-bus slave address
L
H
H
H
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
I/O data bus
6.4 Register descriptions
6.4.1 Input port register (00h)
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. The
Input port register is read only; writes to this register have no effect. The default value ‘X’
is determined by the externally applied logic level. An Input port register read operation is
performed as described in Section 7.2 “Read commands”.
Table 6.
Input port register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Default
X
X
X
X
X
X
X
X
6.4.2 Output port register (01h)
The Output port register (register 1) shows the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins
defined as inputs. In turn, reads from this register reflect the value that was written to this
register, not the actual pin value.
Table 7.
Bit
Output port register (address 01h)
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
1
1
1
1
1
1
1
1
6.4.3 Polarity inversion register (02h)
The Polarity inversion register (register 2) allows polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a
‘0’), the corresponding port pin’s original polarity is retained.
Table 8.
Bit
PCA9554B_PCA9554C
Product data sheet
Polarity inversion register (address 02h)
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Default
0
0
0
0
0
0
0
0
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Rev. 2 — 4 August 2015
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this
register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 9.
Configuration register (address 03h)
Bit
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
1
1
1
1
1
1
1
1
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
output port
register data
configuration
register
data from
shift register
D
VDD
Q1
Q
FF
write configuration
pulse
CK
100 kΩ
Q
D
Q
FF
P0 to P7
write pulse
CK
Q2
output port
register
input port
register
D
Q
FF
read pulse
CK
VSS
input port
register data
to INT
polarity inversion
register
data from
shift register
D
Q
polarity inversion
register data
FF
write polarity
pulse
CK
002aah123
On power-up or reset, all registers return to default values.
Fig 6.
Simplified schematic of the I/Os (P0 to P7)
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.6 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the
PCA9554B/PCA9554C in a reset condition until VDD has reached VPOR. At that time, the
reset condition is released and the PCA9554B/PCA9554C registers and I2C-bus/SMBus
state machine initialize to their default states. After that, VDD must be lowered to below
VPORF and back up to the operating voltage for a power-reset cycle. See Section 8.2
“Power-on reset requirements”.
6.7 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when
data on the port is changed to the original setting or when data is read from the port that
generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the reset of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input port register.
The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT
should be connected to the voltage source of the device that requires the interrupt
information. When using the input latch feature, the input pin state is latched. The interrupt
is reset only when data is read from the port that generated the interrupt. The reset occurs
in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the
rising edge of the SCL signal.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7. Bus transactions
The PCA9554B/PCA9554C is an I2C-bus slave device. Data is exchanged between the
master and PCA9554B/PCA9554C through write and read commands using I2C-bus. The
two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCA9554B/PCA9554C by sending the device address and
setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The
command byte is sent after the address and determines which register receives the data
that follows the command byte. There is no limitation on the number of data bytes sent in
one write transmission.
SCL
1
2
3
4
5
6
7
8
9
slave address(1)
0
SDA S
1
0
0 A2 A1 A0 0
START condition
A
R/W
0
0
0
0
0
STOP
condition
data to port
command byte
0
0
acknowledge
from slave
1
A
DATA 1
A
P
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
data out from port
DATA 1 VALID
002aah124
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 7.
Write to Output port register
SCL
1
2
3
4
5
6
7
8
9
slave address(1)
SDA S
0
1
0
0 A2 A1 A0 0
START condition
R/W
A
0
0
0
0
0
0 1/0 1/0 A
acknowledge
from slave
STOP
condition
data to register
command byte
acknowledge
from slave
DATA 1
A
P
acknowledge
from slave
002aah125
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 8.
Write to Configuration or Polarity inversion registers
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7.2 Read commands
To read data from the PCA9554B/PCA9554C, the bus master must first send the
PCA9554B/PCA9554C address with the least significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which
register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the
PCA9554B/PCA9554C (see Figure 9 and Figure 10).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
slave address(1)
SDA S
0
1
0
0 A2 A1 A0 0
START condition
A
R/W
acknowledge from slave
slave address(1)
(cont.) S
0
1
0
acknowledge from slave
data from register
0 A2 A1 A0 1
(repeated)
START condition
(cont.)
A
COMMAND BYTE
A
DATA (first byte)
R/W
data from register
A
DATA (last byte)
NA P
acknowledge
no acknowledge
from master
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
acknowledge
from slave
STOP
condition
002aah126
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 9.
Read from register
SCL
1
2
3
4
5
6
7
8
9
slave address(1)
SDA S
0
1
0
data from port
0 A2 A1 A0 1
START condition
R/W
DATA 1
A
data from port
A
acknowledge from slave
DATA 4
data into
port
DATA 1
DATA 2
th(D)
DATA 3
tsu(D)
INT
tv(INT)
1
acknowledge from master
read from
port
trst(INT)
DATA 4
no acknowledge
from master
P
STOP
condition
DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT
002aah127
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 9).
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 10. Read Input port register
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8. Application design-in information
VDD
(3.3 V)
10 kΩ
10 kΩ
10 kΩ
2 kΩ
VDD
VDD
MASTER
CONTROLLER
PCA9554B
100 kΩ
(× 3)(1)
INT
SCL
SCL
P0
SDA
SDA
P1
INT
INT
SUB-SYSTEM 2
(e.g., counter)
P2
RESET
P3
VSS
SUB-SYSTEM 1
(e.g., temp sensor)
P4
A
controlled
switch
(e.g., CBT device)
enable
P5
A2
A1
A0
P6
P7
VSS
B
SUB-SYSTEM 3
(e.g., alarm system)
ALARM
VDD
002aah128
Device address is 0100 000x for this example (PCA9554B).
P0, P2, P3 configured as outputs.
P1, P4, P5 configured as inputs.
(1) External resistors are not needed due to the internal weak pull-up resistors.
Fig 11. Typical application
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 12 and Figure 13 show typical solutions to minimizing current consumption.
Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less
than the LED supply voltage by at least 1.2 V. However, the PCA9554B/PCA9554C needs
no external resistors due to the integrated 100 k pull-up resistors.
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
3.3 V
VDD
VDD
LED
5V
VDD
100 kΩ
LED
Pn
Pn
002aag164
002aag165
Fig 12. High value resistor in parallel with
the LED
Fig 13. Device supplied by a lower voltage
8.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA9554B/PCA9554C can be reset to its
default conditions by using the power-on reset feature. Power-on reset requires that the
device go through a power cycle to be completely reset. This reset also happens when the
device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 14 and Figure 15.
VDD
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD drops
below 0.2 V or to VSS
(dV/dt)r
002aah329
Fig 14. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD
VDD
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD drops
to VPOR(min) − 50 mV
time
(dV/dt)r
002aah330
Fig 15. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 10 specifies the performance of the power-on reset feature for
PCA9554B/PCA9554C for both types of power-on reset.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Table 10. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 14
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 14
0.1
-
2000
ms
td(rst)
reset delay time
Figure 14; re-ramp time when
VDD drops to VSS
1
-
-
s
Figure 15; re-ramp time when
VDD drops to VPOR(min)  50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 16
[1]
-
-
1.0
V
[2]
-
-
10
s
tw(gl)VDD
supply voltage glitch pulse width
Figure 16
VPOR(trip)
power-on reset trip voltage
falling VDD
0.7
-
-
V
rising VDD
-
-
1.4
V
[1]
Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5  VDD.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 16 and Table 10 provide more information on
how to measure these specifications.
VDD
∆VDD(gl)
tw(gl)VDD
time
002aah331
Fig 16. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 17 and Table 10 provide more details on this specification.
VDD
VPOR (rising VDD)
VPOR (falling VDD)
time
POR
time
002aah332
Fig 17. Power-on reset voltage (VPOR)
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 36
NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.3 Device current consumption with internal pull-up resistors
The PCA9554B/PCA9554C integrates pull-up resistors to eliminate external components
when pins are configured as inputs and pull-up resistors are required (for example,
nothing is driving the inputs to the power supply rails). Since these pull-up resistors are
internal to the device itself, they contribute to the current consumption of the device and
must be considered in the overall system design.
The internal pull-up resistor is connected to VDD, a current will flow from the VDD pin
through the resistor to ground when the pin is held LOW. This current will appear as
additional IDD upsetting any current consumption measurements.
The pull-up resistors are simple resistors and the current is linear with voltage. The
resistance specification for these devices spans from 50 k with a nominal 100 k value.
Any current flow through these resistors is additive by the number of pins held LOW and
the current can be calculated by Ohm’s law. See Figure 21 for a graph of supply current
versus the number of pull-up resistors.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
9. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+6.5
V
0.5
+6.5
V
0.5
+6.5
V
VI
input voltage
[1]
VO
output voltage
[1]
IIK
input clamping current
A0, A1, A2, SCL; VI < 0 V
-
20
mA
IOK
output clamping current
INT; VO < 0 V
-
20
mA
IIOK
input/output clamping current
P port; VO < 0 V or VO > VDD
-
20
mA
SDA; VO < 0 V or VO > VDD
-
20
mA
continuous; I/O port
-
50
mA
continuous; SDA, INT
-
25
mA
continuous; P port
LOW-level output current
IOL
IOH
HIGH-level output current
-
25
mA
IDD
supply current
-
160
mA
ISS
ground supply current
-
200
mA
Ptot
total power dissipation
-
200
mW
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 12.
Operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
1.65
5.5
V
VIH
HIGH-level input voltage
SCL, SDA
0.7  VDD
5.5
V
A0, A1, A2, P port
0.7  VDD
5.5
V
VIL
LOW-level input voltage
SCL, SDA
0.5
0.3  VDD
V
A0, A1, A2, P port
0.5
0.3  VDD
V
P port
-
10
mA
IOH
HIGH-level output current
IOL
LOW-level output current
P port
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
11. Thermal characteristics
Table 13.
Thermal characteristics
Symbol
Zth(j-a)
[1]
Parameter
Conditions
transient thermal impedance from junction to ambient
Max
Unit
HVQFN16 package
[1]
53
K/W
TSSOP16 package
[1]
108
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
12. Static characteristics
Table 14. Static characteristics
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD or VSS; IO = 0 mA
-
1.1
1.4
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 1.65 V to 5.5 V
3
-
-
mA
3
15[2]
-
mA
SDA
INT
P port
VOH
II
HIGH-level output voltage
input current
VOL = 0.5 V; VDD = 1.65 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD = 1.65 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD = 2.3 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD = 2.3 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD = 3.0 V
[3]
8
14
-
mA
VOL = 0.7 V; VDD = 3.0 V
[3]
10
19
-
mA
VOL = 0.5 V; VDD = 4.5 V
[3]
8
17
-
mA
VOL = 0.7 V; VDD = 4.5 V
[3]
10
24
-
mA
IOH = 8 mA; VDD = 1.65 V
[4]
1.2
-
-
V
IOH = 10 mA; VDD = 1.65 V
[4]
1.1
-
-
V
IOH = 8 mA; VDD = 2.3 V
[4]
1.8
-
-
V
IOH = 10 mA; VDD = 2.3 V
[4]
1.7
-
-
V
IOH = 8 mA; VDD = 3.0 V
[4]
2.6
-
-
V
IOH = 10 mA; VDD = 3.0 V
[4]
2.5
-
-
V
IOH = 8 mA; VDD = 4.75 V
[4]
4.1
-
-
V
IOH = 10 mA; VDD = 4.75 V
[4]
4.0
-
-
V
SCL, SDA; VI = VDD or VSS
-
-
0.1
A
A0, A1, A2; VI = VDD or VSS
P port
VDD = 1.65 V to 5.5 V
-
-
1
A
IIH
HIGH-level input current
P port; VI = VDD; VDD = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD = 1.65 V to 5.5 V
-
-
100
A
PCA9554B_PCA9554C
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Table 14. Static characteristics …continued
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Min
Typ[1]
Max
Unit
VDD = 3.6 V to 5.5 V
-
10
25
A
VDD = 2.3 V to 3.6 V
-
6.5
15
A
VDD = 1.65 V to 2.3 V
-
4
9
A
VDD = 3.6 V to 5.5 V
-
1.5
7
A
VDD = 2.3 V to 3.6 V
-
1
3.2
A
VDD = 1.65 V to 2.3 V
-
0.5
1.7
A
Symbol
Parameter
Conditions
IDD
supply current
SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS;
VI on P port and A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
SCL, SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS;
VI on P port and A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
Active mode; P port, A0, A1, A2;
VI on P port and A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz,
continuous register read
VDD = 3.6 V to 5.5 V
-
60
125
A
VDD = 2.3 V to 3.6 V
-
40
75
A
VDD = 1.65 V to 2.3 V
-
20
45
A
-
0.55
0.75
mA
SCL, SDA; one input at VDD  0.6 V, other
inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
-
-
25
A
P port, A0, A1, A2; one input at VDD  0.6 V,
other inputs at VDD or VSS;
VDD = 1.65 V to 5.5 V
-
-
80
A
with pull-ups;
P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS;
VI on P port = VSS;
VI on A0, A1, A2 = VDD or VSS;
IO = 0 mA; I/O = inputs with pull-up;
fSCL = 0 kHz
VDD = 1.65 V to 5.5 V
IDD
additional quiescent
supply current
Ci
input capacitance
VI = VDD or VSS; VDD = 1.65 V to 5.5 V
-
6
7
pF
Cio
input/output capacitance
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
7
8
pF
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
7.5
8.5
pF
input/output
50
100
150
k
Rpu(int)
internal pull-up resistance
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD = 3.3 V and Tamb = 25 C.
[2]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
[3]
Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[4]
The total current sourced by all I/Os must be limited to 85 mA.
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
12.1 Typical characteristics
002aah333
20
IDD
(μA)
16
12
002aah334
1400
IDD(stb)
(nA)
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
2.5 V
2.3 V
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
8
400
2.5 V
2.3 V
1.8 V
1.65 V
4
0
−40
200
VDD = 1.8 V
1.65 V
−15
10
35
0
−40
60
85
Tamb (°C)
Fig 18. Supply current versus ambient temperature
002aah335
20
IDD
(μA)
16
−15
10
35
60
85
Tamb (°C)
Fig 19. Standby supply current versus
ambient temperature
002aah212
0.8
Tamb = −40 °C
25 °C
85 °C
IDD
(mA)
0.6
12
0.4
8
0.2
4
0
1.5
0
2.5
3.5
4.5
5.5
0
VDD (V)
2
4
6
8
number of I/O held LOW
Tamb = 25 C
Fig 20. Supply current versus supply voltage
PCA9554B_PCA9554C
Product data sheet
Fig 21. Supply current versus number of I/O held LOW
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Rev. 2 — 4 August 2015
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Isink
(mA)
002aaf578
35
Isink
(mA)
30
Tamb = −40 °C
25 °C
85 °C
25
002aaf579
35
30
Tamb = −40 °C
25 °C
85 °C
25
20
20
15
15
10
10
5
5
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
a. VDD = 1.65 V
Isink
(mA)
b. VDD = 1.8 V
002aaf580
50
002aaf581
60
Isink
(mA)
40
Tamb = −40 °C
25 °C
85 °C
30
0.3
VOL (V)
Tamb = −40 °C
25 °C
85 °C
40
20
20
10
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
c. VDD = 2.5 V
Isink
(mA)
0.3
VOL (V)
d. VDD = 3.3 V
002aaf582
70
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
60
50
002aaf583
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
40
30
30
20
20
10
10
0
0
0
0.1
0.2
0.3
0
VOL (V)
0.1
0.2
0.3
VOL (V)
e. VDD = 5.0 V
f. VDD = 5.5 V
Fig 22. I/O sink current versus LOW-level output voltage
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
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19 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
002aah110
30
Isource
(mA)
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
20
002aah111
35
Tamb = −40 °C
25 °C
85 °C
30
25
20
15
10
10
5
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
0
a. VDD = 1.65 V
002aah112
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
40
0.4
0.6
VDD − VOH (V)
b. VDD = 1.8 V
60
Isource
(mA)
0.2
002aah113
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
30
20
20
10
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
c. VDD = 2.5 V
002aah114
0.4
0.6
VDD − VOH (V)
002aah115
90
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
60
0.2
d. VDD = 3.3 V
90
Isource
(mA)
0
Tamb = −40 °C
25 °C
85 °C
60
30
30
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
e. VDD = 5.0 V
0
0.2
0.4
0.6
VDD − VOH (V)
f. VDD = 5.5 V
Fig 23. I/O source current versus HIGH-level output voltage
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
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20 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
VOL
(mV)
002aah056
120
100
002aah343
200
VDD − VOH (mV)
160
(1)
80
120
VDD = 1.8 V
5V
60
(2)
80
40
(4)
20
0
−40
40
(3)
−15
10
35
60
85
Tamb (°C)
0
−40
−15
10
35
60
85
Tamb (°C)
Isource = 10 mA
(1) VDD = 1.8 V; Isink = 10 mA
(2) VDD = 5 V; Isink = 10 mA
(3) VDD = 1.8 V; Isink = 1 mA
(4) VDD = 5 V; Isink = 1 mA
Fig 24. LOW-level output voltage versus temperature
PCA9554B_PCA9554C
Product data sheet
Fig 25. I/O high voltage versus temperature
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Rev. 2 — 4 August 2015
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
13. Dynamic characteristics
Table 15. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 26.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
kHz
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 
(VDD / 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW to SDA
output valid
-
3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to SDA
(out) LOW
-
3.45
-
0.9
s
Table 16. Switching characteristics
Over recommended operating free air temperature range; CL  100 pF; unless otherwise specified. See Figure 26.
Symbol
Parameter
Conditions
Fast-mode
I2C-bus
Min
Max
Min
Max
-
1
-
1
Unit
s
tv(INT)
valid time on pin INT
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
PCA9554B_PCA9554C
Product data sheet
from P port to INT
Standard-mode
I2C-bus
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
14. Parameter measurement information
VDD
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aaf848
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD
0.3 × VDD
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD
SDA
tf
tHD;STA
tr
0.3 × VDD
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 9.
Fig 26. I2C-bus interface load circuit and voltage waveforms
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
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PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
VDD
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aah069
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address(1)
SDA S
SCL
0
1
0
1
2
3
0 A2 A1 A0 1
4
5
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
SCL
0.5 × VDD
DATA 2
R/W
0.3 × VDD
tv(INT)
trst(INT)
0.5 × VDD
Pn
0.7 × VDD
A
0.5 × VDD
INT
View A - A
View B - B
002aah130
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 27. Interrupt load circuit and voltage waveforms
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
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24 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
500 Ω
Pn
DUT
2 × VDD
CL = 50 pF
500 Ω
002aag805
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD
0.3 × VDD
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag806
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD
0.3 × VDD
tsu(D)
th(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7  VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 28. P port load circuit and voltage waveforms
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
25 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
15. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 29. Package outline SOT403-1 (TSSOP16)
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
26 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A
B
D
SOT758-1
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2
e
e
5
y
y1 C
v M C A B
w M C
b
8
L
4
9
e
e2
Eh
1/2
e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
0.5
1.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Fig 30. Package outline SOT758-1 (HVQFN16)
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
27 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9554B_PCA9554C
Product data sheet
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Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
28 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and 18
Table 17.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 18.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
29 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
30 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
5.600
5.300
5.800
7.450
sot403-1_fr
Fig 32. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
31 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
Hy
SPy tot
nSPx
Gy
SPy
nSPy
SLy
By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
1.50
Issue date
SPx tot SPy tot
0.90
0.90
SPx
SPy
Gx
Gy
Hx
Hy
0.30
0.30
3.30
3.30
4.25
4.25
12-03-07
12-03-08
sot758-1_fr
Fig 33. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
32 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
19. Abbreviations
Table 19.
Abbreviations
Acronym
Description
ACPI
Advanced Configuration and Power Interface
CBT
Cross-Bar Technology
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
FF
Flip-Flop
GPIO
General Purpose Input/Output
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light Emitting Diode
LP
Low-Pass
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
SCR
Silicon Controlled Rectifier
SMBus
System Management Bus
20. Revision history
Table 20.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9554B_PCA9554C v.2
20150804
Product data sheet
-
PCA9554B_PCA9554C v.1
Modifications:
PCA9554B_PCA9554C v.1
PCA9554B_PCA9554C
Product data sheet
•
Clarified pull-up information throughout document.
20120919
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
33 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9554B_PCA9554C
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
34 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
35 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
23. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.6
6.7
7
7.1
7.2
8
8.1
8.2
8.3
9
10
11
12
12.1
13
14
15
16
17
17.1
17.2
17.3
17.4
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pointer register and command byte . . . . . . . . . 5
Interface definition . . . . . . . . . . . . . . . . . . . . . . 6
Register descriptions . . . . . . . . . . . . . . . . . . . . 6
Input port register (00h) . . . . . . . . . . . . . . . . . . 6
Output port register (01h) . . . . . . . . . . . . . . . . . 6
Polarity inversion register (02h) . . . . . . . . . . . . 6
Configuration register (03h) . . . . . . . . . . . . . . . 7
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . . 8
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
Write commands. . . . . . . . . . . . . . . . . . . . . . . . 9
Read commands . . . . . . . . . . . . . . . . . . . . . . 10
Application design-in information . . . . . . . . . 11
Minimizing IDD when the I/Os are used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-on reset requirements . . . . . . . . . . . . . 12
Device current consumption with internal
pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating conditions. . . . . . . 15
Thermal characteristics . . . . . . . . . . . . . . . . . 15
Static characteristics. . . . . . . . . . . . . . . . . . . . 16
Typical characteristics . . . . . . . . . . . . . . . . . . 18
Dynamic characteristics . . . . . . . . . . . . . . . . . 22
Parameter measurement information . . . . . . 23
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
Handling information. . . . . . . . . . . . . . . . . . . . 28
Soldering of SMD packages . . . . . . . . . . . . . . 28
Introduction to soldering . . . . . . . . . . . . . . . . . 28
Wave and reflow soldering . . . . . . . . . . . . . . . 28
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 29
Soldering: PCB footprints. . . . . . . . . . . . . . . . 31
19
20
21
21.1
21.2
21.3
21.4
22
23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
34
34
34
35
35
36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 August 2015
Document identifier: PCA9554B_PCA9554C