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AP3598A
APPLICATION NOTE 1124
COMPACT DUAL-PHASE SYNCHRONOUS-RECTIFIED BUCK CONTROLLER
General Description
The AP3598A is a dual-phase synchronous buck PWM controller with integrated drivers which are optimized for high performance graphic card
and computer applications. The IC is capable of delivering up to 60A output current capability and supporting 12V MOSFET drivers with internal
bootstrap diodes.
The dynamic output voltage could be implemented by analog method with a switching device and a resistor network. The adjustable current
balance is achieved by RDS(ON) current sensing technique.
The AP3598A provides over current protection, input/output under voltage protection, over voltage protection and over temperature protection.
Other features include adjustable soft start, adjustable operation frequency and so on. With aforementioned functions, the IC adopts U-QFN404024 package.
EV Board Schematic
Supply Voltage
Driver Supply Voltage
AP3598A
15
VCC
VIN
PVCC
VCC
VPCC
21
CPVCC
CVCC
Frequency
Selection
9
HGATE1
FS
BOOT1
RPG
REN
RFS
RPSI
PHASE1
LGATE1
16
OUT
3
IN
RPSI2
IN
IN
RREFADJ
6
VIN
HGATE2
BOOT2
LGATE2
REFIN
GNDSNS
CREFIN
13 TSNS
External
Thermister
AP3598A Rev.1.0
G
S
CBT2
19
D
L2
Q4
G
20
RVOUT
RVGND
REFADJ
14 TALERT#
RTM
18
CVIN2
RHG2
17
COUT
Q3
S
VSNS
OUT
VOUT
S
Optional
Strap1
D
8 VREF
RTALERT
RVREF2
Q2
G
EN
RVREF1
RTM2
D
23
PGOOD
5 VID
7
L1
24
RLG1
PHASE2
VREF
CVIN1
S
CBT1
1
Q1
G
RHG1
2
4 PSI
CVREF
D
COMP
GND
THERM/GND
VGND_SNS
10
R2
11
C3
12
22
R1
C5
R3
VOUT_SNS
C4
Opamp Compensation
25
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Application Information
Component
Value
Unit
Component
Value
Unit
Component
Value
Unit
CVCC
10
µF
RTALERT
100
kΩ
C3
10
pF
CPVCC
10
µF
RTM2
TBD
kΩ
C4
2.2
nF
CVIN1
300
µF
RTM
TBD
kΩ
C5
1.5
nF
CVIN2
300
µF
RHG1
0
Ω
COUT
330*3
µF
RPG
100
kΩ
CBT1
100
nF
RVOUT
0
Ω
REN
100
kΩ
RLG1
Note 1
Ω
RVGND
0
Ω
RFS
33
kΩ
RHG2
0
Ω
CREFIN
0.033
µF
RPSI
100
kΩ
CBT2
100
nF
Q1
–
–
RPSI2
0
kΩ
R1
12
kΩ
Q2
–
–
CVREF
1
µF
R2
2.2
kΩ
Q3
–
–
RVREF1
4.75
kΩ
R3
560
Ω
Q4
–
–
RVREF2
4.22
kΩ
L1
0.36
µH
–
–
–
RREFADJ
6.34
kΩ
L2
0.36
µH
–
–
–
Table 1. Component Guide
Note 1:
RLG1 are OCP setting resisters:
5k for lower OCP threshold, IOCP=150mV/RDS(ON)
10k for medium OCP threshold, IOCP=250mV/RDS(ON)
>20k for disabling OCP function
PWM-VID Dynamic Voltage Control
PWM-VID is a single-wire dynamic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count
and enables a wide dynamic voltage range.
The PWM-VID duty cycle determines the variable output voltage at REFIN, as shown in Figure 1. VMIN is the zero percent duty cycle voltage value.
VMAX is the one hundred percent duty cycle voltage value. The resolution of each voltage step (VSTEP) is determined by the number of available
steps (NMAX) and the selection of the dynamic voltage range (VMAX-VMIN). N is the number of steps at a specific VOUT. N/NMAX ratio is equal to the
duty cycle. The dynamic voltage VID frequency (fSWVID) is determined by the unit pulse width (tU) and the available step number NMAX (tVID =
tU*NMAX, fVID = 1/ tVID). tU is programmable.
Figure 1. Dynamic Output
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Application Information (Cont.)
VSTEP, NMAX, VMIN, and VMAX are variables that determine VOUT. NMAX is limited by the unit pulse width and the minimum VID frequency.
The dynamic voltage output could be implemented by the analog method with a switching device and a resistor network. A buffer is used as the
switching device to create dynamic output. Resistor network sets the minimum offset voltage.
Figure 2 shows the analog circuit diagram for the PWM-VID dynamic voltage control. The buffer requires a stable, high precision voltage reference
(VREF) for the linear output. The dynamic range of the circuit is determined by the resistor selection. Resistor R REFADJ and capacitor CREFIN
function as a filter for the PWM signal, and will affect the ripple voltage and the slew rate at the output (REFIN) during voltage transitions.
VREF
VCC
IN
RVREF1
Buffer
PWM
REFIN
OE
A
RREFADJ
NC
GND
CREFIN
GND
RVREF2
GND
GND
Figure 2. PWM-VID Analog Circuit Diagram
Spec Description
Output Voltage Equation
–
NMAX: Total available voltage step number
N: The step number of the specific VOUT, N/NMAX ratio equals duty
–
cycle
VMAX: The output voltage of REFIN at one hundred percent duty
cycle
VREF
VREF
VMIN: The output voltage of REFIN at zero percent duty cycle
R VREF2
R VREF2 ( RVREF1 || R REFADJ )
RVREF 2 || R REFADJ
R VREF1 ( RVREF 2 || R REFADJ )
VMAX - VMIN
N MAX
VSTEP: The resolution of the voltage step
VMIN N VSTEP
VOUT: The output voltage at REFIN
1
tU N MAX
fSWVID: The dynamic voltage VID frequency
Table 2. REFIN Dynamic Range
There will be some ripple voltage at REFIN due to the nature of the PWM and filter. The error amplifier at REFIN will be able to tolerate a
reasonable amount of Ripple Voltage.
Figure 3 shows a dynamic voltage control circuit with the integrated buffer. This defines the implementation of the VID and REFADJ functions.
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Application Information (Cont.)
Controller
VREF
RVREF1
REFIN
RREFADJ
VSTANDBY
Block
RSTANDBY
External
Control
Q5
D
RVREF2
REFADJ
GND
GND
GND
PWM
S
GND
R15
GND
VCC Buffer
A
CREFIN
G
IN
OE
O
NC
IN
VID
GND
Figure 3. Integrated Buffer Circuit
Figure 4. The Behavior of the Buffer
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Application Information (Cont.)
Parameters
Sym
Min
Typ
Max
Unit
Notes
Buffer Supply Voltage
–
–
VREF
–
V
–
Unit Pulse Width
tU
–
27
–
ns
Configurable
Buffer Output Rise Time
tR
–
5
–
ns
–
Buffer Output Fall Time
tF
–
5
–
ns
–
Rising and Falling Edge Delay
Δt
–
–
0.5
ns
Δt=|tR-tF|
Propagation Delay
tPD
–
10
–
ns
tPD=tPHL=tPLH
ΔtPD
–
–
0.5
ns
ΔtPD=tPHL-tPLH
Upper Resister
RVREF1
–
4.75
–
kΩ
–
Lower Resister
RVREF2
–
4.22
–
kΩ
–
Filter Resister
RREFADJ
–
6.34
–
kΩ
–
RBOOT
–
–
–
kΩ
Project Specific
RSTANDBY
–
1.07
–
kΩ
–
CREFIN
–
0.033
–
μF
–
Propagation Delay Error
Boot Mode Resister
Standby Mode Resister
Filter Capacitor
Table 3. Electrical Characteristics
Figure 5 contains the details of the timing diagram. After VCC powers up, the controller generates the V REF. REFIN settles at VBOOT before the
GPU drives the VID pin. After the GPU powers up, V BOOT control will be pulled low by software. At the same time the VID is driven by a PWM
signal, moving REFIN into the normal operating mode. When the GPU is going to standby, software will tri-state VID and VBOOT control, and an
external control will enable RSTANDBY.
Figure 5. Time Diagram
Standby mode keeps the GPU in a low voltage state (in the range of 0.3V) for the quick recovery. As the GPU steps into the standby mode, the
resistor RSTANDBY and the switch Q6 (parallel to the RVREF2 and RBOOT) set the standby voltage. The accuracy of the reference voltage in the
standby mode could be reduced from the normal operating mode. Refer to Figure 6 for the illustration of the standby voltage.
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Application Information (Cont.)
Figure 6. Illustration for Standby Mode and Adjustable VBOOT Setting
PWM Compensation
The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase
shift in the control loop. A compensation network among COMP, VSNS, and VOUT should be added. The compensation network is shown in Figure
10. The output LC filters consist of the output inductors and output capacitors. For two-phase convertor, when assuming that VIN1 = VIN2 = VIN, L1
= L2 = L, the transfer function of the LC filter is given by:
Gain LC
1 s RESR COUT
s 2 (1 / 2) L COUT s RESR COUT 1
The poles and zero of the transfer functions are:
f LC
1
2 (1/ 2) L COUT
f ESR
1
2 RESR COUT
The fLC is the double-pole frequency of the two-phase LC filters, and fESR is the frequency of the zero introduced by the ESR of the output
capacitors.
VPHASE1
VPHASE2
L1=L
VOUT
L2=L
COUT
RESR
Figure 7. The Output LC Filter
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Application Information (Cont.)
Figure 8. Frequency Response of the LC Filters
The PWM modulator is shown in Figure 9. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of
the PWM modulator is given by:
GainPWM
VIN
VOSC
VIN
Driver
OSC
PWM
Comparator
-
ΔVOSC
PHASE
+
Output of Error
Amplifier
Driver
Figure 9. The PWM Modulator
The compensation network is shown in Figure 10. It provides a close loop transfer function with the highest zero crossover frequency and
sufficient phase margin. The transfer function of error amplifier is given by:
GainAMP
1
1
1
1
(s
) {s
}
//(R 2
)
VCOMP sC1
R
1
R
3
R
2
C
2
(
R
1
R
3) C 3
sC
2
1
C1 C 2
1
VOUT
R1 R3 C1
R1 //( R3
)
s( s
) (s
)
sC 3
R 2 C1 C 2
R3 C 3
The pole and zero frequencies of the transfer function are:
f Z1
1
2 R2 C 2
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Application Information (Cont.)
fZ 2
1
2 ( R1 R3) C 3
f P1
1
fP2
2 R2 (
C1 C 2
)
C1 C 2
1
2 R3 C 3
C1
R3
C3
R2
C2
VOUT
R1
FB
+
VCOMP
VREF
Figure 10. Compensation Network
The closed loop gain of the converter can be written as:
GainLC GainPWM Gain AMP
Figure 11 shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network.
Using the below guidelines will give a compensation similar to the curve plotted. A stable closed loop has a -20dB/decade slope and a phase
margin greater than 45 degree.
1. Choose a value for R1, usually between 1kΩ and 5kΩ.
2. Select the desired zero crossover frequency.
f O (1 / 5 ~ 1 / 10 ) f SW
Use the following equation to calculate R2:
R2
VOSC f O
R1
VIN
f LC
3. Place the first zero fZ1 before the output LC filter double pole frequency fLC.
f Z 1 0.75 f LC
Calculate the C2 by the equation:
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Application Information (Cont.)
C2
1
2 R 2 f LC 0.75
4. Set the pole at the ESR zero frequency fESR:
f P1 f ESR
Calculate the C1 by the following equation:
C1
C2
2 R 2 C 2 f ESR 1
5. Set the second pole fP2 at the half of the switching frequency and also set the second zero f Z2 at the output LC filter double pole fLC. The
compensation gain should not exceed the error amplifier open loop gain. Check the compensation gain at f P2 with the capabilities of the error
amplifier.
f P 2 0.5 f SW
f Z 2 f LC
Combine the two equations will get the following component calculations:
R3
C3
R1
f SW
1
2 f LC
1
R3 f SW
Figure 11. Converter Gain and Frequency
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Application Information (Cont.)
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as:
D VOUT / VIN
For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple current, ΔIP-P, and affects the load transient
response. Higher inductor value reduces the output capacitors’ ripple current and induces lower output ripple voltage. The ripple current can be
approximated by:
I P P
VIN 2VOUT VOUT
f SW L
VIN
Where fSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s
ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the
expense of higher ripple current. Increasing the switching frequency (fSW ) also reduces the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A
good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been
chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially
core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage.
Output Capacitor Selection
Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting output capacitors.
Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR
capacitors is recommended for switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the
output voltage ripple includes the capacitance voltage drop ΔVCOUT and ESR voltage drop ΔVESR caused by the AC peak-to-peak sum of the
inductor’s current. The ripple voltage of output capacitors can be represented by:
VCOUT
I P P
8 COUT f SW
VESR I P P RESR
These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled
to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors are
needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for
bypassing the noise is also recommended, and the voltage rating of the output capacitors must be considered too.
To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load
step change.
For getting same load transient response, the output capacitance of two-phase converter only needs to be around half of output capacitance of
single-phase converter.
Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current
specified on the capacitors in order to prevent the capacitor from overheating.
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Application Information (Cont.)
Input Capacitor Selection
Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET
turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of lowside MOSFET.
The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk
capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For twophase converter, the RMS current of the bulk input capacitor is roughly calculated as the following equation:
I RMS
I OUT
2 D (1 2 D)
2
For a through-hole design, several electrolytic capacitors may be needed. For surface mount design, solid tantalum capacitors can be used, but
caution must be exercised with regard to the capacitor surge current rating.
MOSFET Selection
The AP3598A requires two N-Channel power MOSFETs on each phase. These should be selected based upon RDS(ON), gate supply requirements
and thermal management requirements.
In high current applications, the MOSFET power dissipation, package selection, and heatsink are the dominant design factors. The power
dissipation includes two loss components: conduction loss and switching loss.
The conduction losses are the largest component of power dissipation for both the high-side and the low-side MOSFETs. These losses are
distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since
the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous
rectifier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due to the reverse-recovery
of the low-side MOSFET body diode. The gate-charge losses are dissipated by AP3598A and don’t heat the MOSFETs. However, large gatecharge increases the switching interval tSW, which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their
maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance
specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
For the high-side and low-side MOSFETs, the losses are approximately given by the following equations:
Where IOUT is the load current, TC is the temperature dependency of RDS(ON), fSW is the switching frequency, tSW is the switching interval, D is the
duty cycle.
Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, tSW, is
the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET.
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PCB Layout Guidance
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance
and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is
carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The
best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less
noise. Noisy traces beneath the IC are not recommended. Figure 12 illustrates the layout, with bold lines indicating high current paths; these
traces must be short and wide. Components along the bold lines should be placed close together. Below is a checklist for your layout:
1.
Keep the switching nodes (HGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast
moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with
theses traces on any layer.
2.
The signals going through theses traces have both high dv/dt and high dI/dt with high peak charging and discharging current. The traces from
the gate drivers to the MOSFETs (HGATEx and LGATEx) should be short and wide.
3.
Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide
layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the
MOSFETs (VIN and PHASEx nodes) can get better heat sinking.
4.
For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To
avoid the noise interference, the current sensing trace should be away from the noisy switching nodes.
5.
Decoupling capacitors, the resistor-divider, and the boot capacitor should be close to their pins. (For example, place the decoupling ceramic
capacitor as close as possible to the drain of the high-side MOSFET). The input bulk capacitors should be close to the drain of the high-side
MOSFET, and the output bulk capacitors should be close to the loads.
6.
The input capacitor’s ground should be close to the grounds of the output capacitors and the low-side MOSFET.
7.
Locate the resistor-divider close to the VREF and REFIN pins to minimize the high impedance trace. In addition, VSNS pin traces can’t be
close to the switching signal traces (HGATEx, LGATEx, BOOTx, and PHASEx).
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PCB Layout Guidance (Cont.)
Figure 12. The Layout of AP3598A
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PCB Layout Example
Top Layer
Bottom Layer
VCC Ldayer
AP3598A Rev.1.0
Ground Layer
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