A Product Line of
Diodes Incorporated
AP3598A
COMPACT DUAL-PHASE SYNCHRONOUS-RECTIFIED BUCK CONTROLLER
Pin Assignments
(Top View)
LGATE2
The AP3598A provides over current protection, input/output under
voltage protection, over voltage protection and over temperature
protection.
PHASE2
The dynamic output voltage could be implemented by analog method
with a switching device and a resistor network. The adjustable current
balance is achieved by RDS(ON) current sensing technique.
PVCC
24
GND
Pin 1 Mark
LGATE1
The AP3598A is a dual-phase synchronous buck PWM controller with
integrated drivers which are optimized for high performance graphic
card and computer applications. The IC is capable of delivering up to
60A output current capability, supporting 12V MOSFET drivers with
internal bootstrap diodes.
PHASE1
23
22
21
20
19
BOOT1
1
18
BOOT2
HGATE1
2
17
HGATE2
16
PGOOD
EN
3
PSI
4
VID
5
REFADJ
6
THERM/
GND
14 TALERT#
25
10
11
12
COMP
VREF
REFIN
9
VSNS
8
FS
7
Other features include adjustable soft start, adjustable operation
frequency and so on. With aforementioned functions, the IC adopts UQFN4040-24 package.
15 VCC
GNDSNS
NEW PRODUCT
Description
13
U-QFN4040-24
Features
Applications
Operate with Single Supply Voltage
Reference Voltage Output with 1% Accuracy
Simple Single Loop Voltage Mode Control
Middle-High End Graphic Card
12V Bootstrapped Drivers with Internal Boot-strap Diodes
Generic Desktop and Consumer Electronics
Adjustable Current Balancing by RDS(ON) Current Sensing
Adjustable Operation Frequency from 200kHz to7500kHz Per
Phase
External Compensation
Dynamic Output Voltage Adjustment
Adjustable Soft Start
Built-in UV and OV Protection Function
Built-in Over Current Protection
Built-in Thermal Shutdown Function
U-QFN4040-24 Package
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
TSNS
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
AP3598A
Document number: DS37261 Rev. 2 - 2
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AP3598A
Typical Applications Circuit
Driver Supply Voltage
Supply Voltage
AP3598A
15
VCC
VIN
PVCC
VCC
VPCC
21
CPVCC
CVCC
Frequency
Selection
9
FS
NEW PRODUCT
RPG
REN
RFS
RPSI
PHASE1
LGATE1
16
OUT
RPSI2
D
Q2
G
23
RLG1
CVREF
VIN
EN
D
17
5 VID
HGATE2
8 VREF
BOOT2 18
19
PHASE2
7
G
S
CBT2
6
RTALERT
RVREF2
L2
D
Q4
G
20
RVOUT
RVGND
S
RREFADJ
RTM2
LGATE2
REFIN
COUT
Q3
CVIN2
RHG2
RVREF1
VREF
VOUT
S
Optional
Strap1
4 PSI
IN
IN
L1
24
PGOOD
3
IN
CVIN1
S
CBT1
1
BOOT1
Q1
G
RHG1
2
HGATE1
D
REFADJ
VGND_SNS
GNDSNS 10
CREFIN
R2
VSNS 11
C3
C5
COMP 12
14 TALERT#
OUT
RTM
13
TSNS
R1
22
GND
VOUT_SNS
R3
C4
Opamp Compensation
25
THERM/GND
External
Thermister
Component
Value
Unit
Component
Value
Unit
Component
Value
Unit
CVCC
10
μF
RTALERT
100
kΩ
C3
10
pF
CPVCC
10
μF
RTM2
TBD
kΩ
C4
2.2
nF
CVIN1
300
μF
RTM
TBD
kΩ
C5
1.5
nF
CVIN2
300
μF
RHG1
0
Ω
COUT
330*3
μF
RPG
100
kΩ
CBT1
100
nF
RVOUT
0
Ω
REN
100
kΩ
RLG1
Note 4
Ω
RVGND
0
Ω
RFS
33
kΩ
RHG2
0
Ω
CREFIN
0.033
μF
RPSI
100
kΩ
CBT2
100
nF
Q1
–
–
RPSI2
0
kΩ
R1
12
kΩ
Q2
–
–
CVREF
1
μF
R2
2.2
kΩ
Q3
–
–
RVREF1
4.75
kΩ
R3
560
Ω
Q4
–
–
RVREF2
4.22
kΩ
L1
0.36
μH
–
–
–
RREFADJ
6.34
kΩ
L2
0.36
μH
–
–
–
Table 1. Component Guide
Note 4: RLG1 are OCP setting resisters:
5k for lower OCP threshold, IOCP = 150mV/RDS(ON)
10k for medium OCP threshold, IOCP = 250mV/RDS(ON)
>20k for disabling OCP function
AP3598A
Document number: DS37261 Rev. 2 - 2
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AP3598A
Pin Descriptions
Pin Name
1
BOOT1
High side gate driver supply of phase 1
2
HGATE1
High side gate driver output of phase 1
3
EN
Enable input
4
PSI
Power saving interface
5
VID
Voltage ID input
6
REFADJ
7
REFIN
External reference input
8
VREF
Output reference voltage. This is high precision voltage reference
9
FS
10
GNDSNS
11
VSNS
VOUT sense. Positive node of the remote differential voltage sense
12
COMP
Compensation. Use this pin in combination with VSNS to compensate the
feedback loop of the converter
13
TSNS
Temperature sensing input
14
TALERT#
15
VCC
16
PGOOD
Open drain power good output
17
HGATE2
High side gate driver output of phase 2
18
BOOT2
High side gate driver supply of phase 2
19
PHASE2
Switch node of phase 2
20
LGATE2
Low side gate driver output of phase 2
21
PVCC
Driver supply voltage
22
GND
Ground. Must be connected to GND on PCB
23
LGATE1
Low side gate driver output of phase 1
24
PHASE1
Switch node of phase 1
25
THERM/GND
NEW PRODUCT
Pin Number
AP3598A
Document number: DS37261 Rev. 2 - 2
Function
Reference adjustment output
Frequency selection. Connect a resistor from this pin to GND to select the
switching frequency
GND sense. Negative node of the remote voltage sense
Thermal alert. Active low open drain output
Supply voltage
Thermal connection to the PCB. Must be connected to GND on PCB
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AP3598A
Functional Block Diagram
VCC
PVCC
15
Reference
Voltage
8
NEW PRODUCT
VREF
21
1
Internal
Regulator
POR
BOOT1
2
HGATE1
6
REFADJ
VID
GNDSNS
PWM1
+
_
5
Gate
Control
Logic
10
24
23
OVP
UVP
7
+
_
REFIN
VSNS
COMP
PSI
11
12
PHASE1
LGATE1
Current
Balance
18
Error
Amplifier
BOOT2
17
HGATE2
4
Gate
Control
Logic
_
Power Saving
Setting
+
PWM2
19
PHASE2
20
LGATE2
TALERT#
TSNS
14
13
OTP
SHDN
3
16
EN
AP3598A
Document number: DS37261 Rev. 2 - 2
PG
PGOOD
Oscillator
9
22
FS
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GND
25
THERM/GND
November 2014
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AP3598A
Absolute Maximum Ratings (Note 5)
NEW PRODUCT
Symbol
Parameter
VCC, VPCC
VCC, PVCC Pin Voltage
VPHASE1, VPHASE2
PHASE to GND Voltage
VBOOT1_PHASE1,
VBOOT2_PHASE2
BOOT to PHASE Voltage
VBOOT1, VBOOT2
BOOT to GND Voltage
VHGATE1, VHGATE2
VLGATE1, VLGATE2
–
Note 5:
Rating
Unit
-0.3 to 15
V
<200ns
-5 to 32
>200ns
-0.3 to 26
V
-0.3 to 15
V
<200ns
-0.3 to 42
>200ns
-0.3 to 30
<200ns
-5 to VBOOT_PHASEx+5
>200ns
-0.3 to
VBOOT_PHASEx+0.3
<200ns
-5 to VIN+5
>200ns
-0.3 to VIN+0.3
V
HGATE to PHASE Voltage
LGATE to GND Voltage
V
V
Other Input, Output or I/O Pin Voltage
0 to 6
V
θJA
Thermal Resistance
40
ºC/W
PD
Power Dissipation (TA = +25ºC)
2.5
W
TJ
Operating Junction Temperature Range
-40 to +150
ºC
TSTG
Storage Temperature
-65 to +150
ºC
TLEAD
Lead Temperature (Soldering, 10sec)
+260
ºC
–
ESD(Machine Model)
200
V
–
ESD(Human Body Model)
2000
V
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied.
Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
VCC, VPCC
VOUT
TA
Parameter
Min
Max
Unit
Supply Input Voltage
4.5
13.2
V
Output Voltage
0.3
2
V
Operating Ambient Temperature
-40
+85
ºC
AP3598A
Document number: DS37261 Rev. 2 - 2
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AP3598A
Electrical Characteristics
Symbol
(VCC = 12V, VPCC = 12V, TA = +25ºC, unless otherwise specified.)
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Supply Current
HGATE and LGATE
Open, Switching
–
5
–
mA
ICC_Q
Quiescent Supply Current
No Switching
–
4
–
mA
ISHDN
Shutdown Supply Current
Shutdown
–
4
–
mA
VCCRTH
Under Voltage Lockout Threshold for
VCC
–
3.9
4.1
4.3
V
VCCHYS
Hysteresis for VCC
–
–
0.4
–
V
VPCCRTH
Under Voltage Lockout Threshold for
PVCC
–
3.9
4.1
4.3
V
VPCCHYS
Hysteresis for PVCC
–
–
0.4
–
V
1.98
2.00
2.02
Reference Voltage Accuracy
IREF = 100µA, TA =
+25ºC
IREF = 100µA,
TA = 0 to +150ºC
1.97
–
2.03
NEW PRODUCT
ICC
POR
REFERENCE VOLTAGE
VREF
V
Reference Voltage Load Regulation
IREF = 0 to 2mA
-5
–
5
mV
VREF Maximum Output Current
–
10
–
–
mA
Open Loop DC Gain
Guaranteed by design
70
80
–
dB
GBW
Gain-Bandwidth Product
CLOAD = 5pF,
Guaranteed by design
–
20
–
MHz
SR
Slew Rate
Guaranteed by design
15
20
–
V/µs
Maximum Current (Sink and Source)
VCOMP = 1.6V
1.5
2.0
–
mA
FS Voltage
RFS = 33kΩ
–
1
–
V
Switching Frequency Setting Range
–
200
–
500
kHz
fOSC
Free Run Switching Frequency
RFS = 33kΩ
270
300
330
kHz
∆fOSC
Switching Frequency Accuracy
fOSC = 200kHz to 500kHz
-15
–
15
%
–
Maximum Duty Cycle
–
35
40
–
%
–
Minimum Duty Cycle
–
–
0
–
%
Ramp Amplitude
VCC = 12V
–
3.5
–
V
VENIH
Enable High Threshold
–
1.4
–
–
V
VENIL
Enable Low Threshold
–
–
–
0.6
V
∆VREF
IREF
ERROR AMPLIFIER
AO
ICOMP
FREQUENCY SETTING
VFS
–
OSCILLATOR
∆VOSC
ENABLE FUNCTION
AP3598A
Document number: DS37261 Rev. 2 - 2
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AP3598A
Electrical Characteristics
(Cont. VCC = 12V, VPCC = 12V, TA = +25ºC, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dual Phase with FCCM
1.5
–
–
V
Single Phase with DCM
–
–
0.4
V
0.8
–
1.1
V
POWER SAVING INTERFACE
VPSIH
NEW PRODUCT
VPSIL
VPSIM
Power Saving Interface High
Threshold
Power Saving Interface Low
Threshold
Power Saving Interface
Intermediate Threshold
Single Phase with FCCM
POWER GOOD
Delay Time for PGOOD from
High to Low
Internal Power Good Pull Low
Resistance
–
–
10
–
µs
–
–
–
150
Ω
IHG_SRC
Upper Gate Sourcing Current
VBOOTx-VPHASEx = 6V
–
1.2
–
A
RHG_SNK
Upper Gate Sinking
Resistance
VUGATEx-VPHASEx = 0.1V
IUGATEx = 100mA
–
2
–
Ω
ILG_SRC
Lower Gate Sourcing Current
VCC-VLGATEx = 6V
–
1.2
–
A
RLG_SNK
Lower Gate Sinking
Resistance
VLGATEx = 0.1V
ILGATEx = 100mA
VPCC-VBOOT, IBOOT =
20mA
–
1.4
–
Ω
–
0.8
–
V
tPG_DLY
RPG
GATE DRIVER
VBOOT
Boot Diode Forward Voltage
PROTECTION
VUVP
Output Under Voltage
Protection Threshold
–
–
–
0.5*
VOUT
V
tUVP
Delay Time for UVP Triggered
–
–
50
–
μs
VOVP
Output Over Voltage Protection
Threshold
–
1.4*
VOUT
–
–
V
tOVP
Delay Time for OVP Triggered
–
–
50
–
μs
LGATE OC Setting Current
–
–
21.5
–
μA
Built-in Maximum OCP Voltage
–
–
0.35
–
V
Thermal Shutdown Threshold
–
+150
+160
+170
ºC
Minimum Thermal Alert
Threshold
–
+120
+130
+140
ºC
Temperature Sense Threshold
–
–
1.00
–
V
IOCSET
–
THERMAL PROTECTION
TSD
TALERT#
VTSNS
PWM-VID DYNAMIC VOLTAGE CONTROL
VIH
Logic High Level
–
1.5
–
–
V
VIL
Logic Low Level
–
–
–
0.4
V
VID
VID Voltage in High-Z Mode
–
–
1.1
–
V
Current Balance Sense Offset
–
–
0
–
μA
CURRENT BALANCE
IOFS
AP3598A
Document number: DS37261 Rev. 2 - 2
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AP3598A
Performance Characteristics
VREF Line Regulation
VREF Load Regulation
2.0000
2.020
1.9995
2.015
ILOAD=0mA
ILOAD=2mA
1.9990
1.9985
VREF (V)
VREF (V)
2.005
2.000
1.9980
1.995
1.9975
1.990
1.9970
1.985
1.9965
1.9960
1.980
4
6
8
10
12
0
14
2
4
6
8
10
ILOAD (mA)
VCC (V)
VCC vs. ICC
fOSC vs. RRT
1000
13
fOSC (kHz)
VCC (V)
12
11
10
100
9
10
8
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
10
6.3
100
RRT (k)
ICC (mA)
fOSC vs. VCC
fOSC vs. Temperature
300
290
295
285
290
285
280
fOSC (kHz)
fOSC (kHz)
NEW PRODUCT
2.010
275
280
275
270
270
265
260
-60
265
9
10
11
12
13
AP3598A
Document number: DS37261 Rev. 2 - 2
-40
-20
0
20
40
60
80
100
120
140
160
o
VCC (V)
Temperature ( C)
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AP3598A
Performance Characteristics (Cont.)
VREF vs. Temperature
VOUT vs. Duty Cycle
2.010
2.0
1.8
2.005
1.6
2.000
1.4
1.2
VOUT (V)
VREF (V)
NEW PRODUCT
1.995
1.990
1.985
1.0
0.8
0.6
1.980
0.4
1.975
0.2
1.970
0.0
-40
-20
0
20
40
60
80
100
120
140
0
o
EN On Waveform
(VIN=12V, VOUT=1.0V, IOUT=0A)
VEN
2V/div
VOUT
0.5V/div
VOUT
0.5V/div
VPHASE1
10V/div
VPHASE1
10V/div
VPHASE2
10V/div
VPHASE2
10V/div
Time 400µs/div
60
80
100
Time 400µs/div
EN Off Waveform
(VIN=12V, VOUT=1.0V, IOUT=0A)
EN Off Waveform
(VIN=12V, VOUT=1.0V, IOUT=60A)
VEN
2V/div
VEN
2V/div
VOUT
0.5V/div
VOUT
0.5V/div
VPHASE1
10V/div
VPHASE1
10V/div
VPHASE2
10V/div
VPHASE2
10V/div
Time 400µs/div
Time 400µs/div
Document number: DS37261 Rev. 2 - 2
40
EN On Waveform
(VIN=12V, VOUT=1.0V, IOUT=60A)
VEN
2V/div
AP3598A
20
Duty Cycle (%)
Temperature ( C)
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AP3598A
Performance Characteristics (Cont.)
NEW PRODUCT
Power On Waveform
(VIN=12V, VOUT=1.0V, IOUT=0A)
Power On Waveform
(VIN=12V, VOUT=1.0V, IOUT=60A)
VCC
10V/div
VCC
10V/div
VOUT
0.5V/div
VOUT
0.5V/div
VHGATE
20V/div
VHGATE
20V/div
VLGATE
10V/div
VLGATE
10V/div
Time 4ms/div
Time 4ms/div
Power Off Waveform
(VIN=12V, VOUT=1.0V, IOUT=0A)
VCC
10V/div
VOUT
0.5V/div
Power Off Waveform
(VIN=12V, VOUT=1.0V, IOUT=60A)
VCC
10V/div
VOUT
0.5V/div
VHGATE
20V/div
VHGATE
20V/div
VLGATE
10V/div
VLGATE
10V/div
Time 4ms/div
Time 4ms/div
Dead Time 1
VHGATE
5V/div
VPHASE
5V/div
Dead Time 2
VHGATE
VPHASE
VLGATE
5V/div
VLGATE
VHGATE
5V/div
VPHASE
5V/div
VLGATE
5V/div
Time 40ns/div
AP3598A
Document number: DS37261 Rev. 2 - 2
VHGATE
VLGATE
VPHASE
Time 40ns/div
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AP3598A
Performance Characteristics (Cont.)
NEW PRODUCT
Under Voltage Protection
(VIN=12V, VOUT=1.0V)
VOUT
1V/div
Over Voltage Protection
(VIN=12V, VOUT=1.0V)
VOUT
0.5V/div
VPGOOD
2V/div
VPGOOD
2V/div
VHGATE
20V/div
VHGATE
20V/div
VLGATE
10V/div
VLGATE
10V/div
Time 400µs/div
Time 400µs/div
Over Current Protection
(VIN=12V, VOUT=1.0V)
VOUT
0.5V/div
Over Temperature Protection
(VIN=12V, VOUT=1.0V)
VOUT
0.5V/div
VPHASE
10V/div
VPHASE
10V/div
VPGOOD
2V/div
VPGOOD
2V/div
IOUT
50A/div
Time 2ms/div
Time 400µs/div
Pre-bias Start-up
(VIN=12V, VOUT=2V before Power On)
VOUT
1V/div
VLGATE1
10V/div
VLGATE2
10V/div
VCC
5V/div
Time 4ms/div
AP3598A
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AP3598A
Application Information
1. Overview
The AP3598A is a dual-phase synchronous-rectified buck controller designed to deliver high quality output voltage for high power applications.
The IC is capable of delivering up to 60A output current with embedded bootstrapped drivers that support 12V+12V driver capability. The built-in
bootstrap diode simplifies the circuit design and reduces external part count and PCB space.
NEW PRODUCT
The output voltage is precisely regulated to the reference input that is dynamically adjustable by external voltage divider. The adjustable current
balance is achieved by RDS(ON) current sensing technique.
The AP3598A features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage
protection and over temperature protection.
Other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. With aforementioned
functions, the AP3598A provides customer a compact, high efficiency, well-protected and cost effective solution. It uses U-QFN4040-24 package.
2. Power On Reset
A Power On Reset (POR) circuitry continuously monitors the supply voltage at VCC and PVCC pin. Once the rising POR threshold is exceeded,
the AP3598A sets itself to active state and is ready to accept chip enable command. The rising POR threshold is typically 4.1V.
3. Soft Start
The AP3598A initiates its soft start cycle when EN is released from ground once the POR is granted.
Slew rate of voltage transition at REFIN and output voltage VSNS during soft start and V REFIN jumping is controlled by the capacitor connected to
the REFIN pin. This reduces inrush current to charge/discharge the large output capacitors during soft start and VID changing, and prevents OCP,
OVP, UVP false trigger.
4. Pre-Bias Function
The AP3598A features pre-bias start-up capability. If the output voltage is pre-biased voltage, which makes VSNS voltage higher than reference
voltage REFIN. The error amplifier keeps COMP voltage lower than the valley of the sawtooth waveform and makes PWM comparators output low
until the ramping REFIN voltage catches up the output voltage.
The AP3598A keeps both upper and lower MOSFETS off until the first pulse takes place.
5. Chip Oscillator Frequency Programming
A resistor RFS connected to FS pin programs the oscillator frequency as:
f OSC
10000
(kHz)
RFS (k)
Figure 1 shows the relationship between oscillation frequency and RFS.
RFS(kΩ)
Figure 1. Switching Frequency vs. RFS
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6. Current Balance
The AP3598A extracts phase currents for current balance by parasitic on-resistance of the lower switches when turned on as shown in Figure 2.
IOFS
_
PHASE
Sample
&Hold
+
ICS1
Current
Balance
NEW PRODUCT
ICS2
+
_
Reference
Voltage
Figure 2. RDS(ON) Current Sensing Scheme
The GM amplifier senses the voltage drop across the lower switch and converts it into current signal when it turns on. The sampled and held
current is expressed as:
ICSX I LX R DS(ON) 103 12A
Where ILX is the phase x current in Ampere, RDS(ON) is the on-resistance of low side MOSFET (Ω), 12µA is a constant current to compensate the
offset voltage of the current sensing circuit.
The AP3598A tunes the duty cycle of each channel for current balance according to the sensed inductor current signals as shown in Figure 3. If
the current of channel 1 is smaller than the current of channel 2, the AP3598A increases the duty cycle of the corresponding phase to increase its
phase current accordingly, vice versa.
RAMP1
COMP
+
_
PWM1
+
_
PWM2
RAMP2
ICS2
+
ICS1
_
+
Figure 3. Current Balance Scheme of AP3598A
7. Power Saving Interface (PSI)
This is a multilevel input to support Power Saving features. The AP3598A supports dual phase with FCCM and single phase with DCM and FCCM.
Mode
Descriptions
DCM
Discontinuous Conduction Mode decreases the switching frequency to improve the efficiency at light load
FCCM
Forced Continuous Conduction Mode does not change the switching frequency when the inductor current
goes to negative at light load. This mode is used to disable Power Saving features
Table 2. Description of Operating Modes
As shown in Table 2, an input high voltage (>1.5V) will set the controller to dual phase with FCCM mode; an input of intermediate level (between
0.8V and 1.1V) will set the controller to single phase with FCCM mode; an input low voltage will set the controller to single phase with DCM mode.
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8. Short Circuit Protection (SCP)
The AP3598A has over current (OCP) and output under voltage protection (UVP) functions.
8.1 OCP function
NEW PRODUCT
The AP3598A detects voltage drop across the lower MOSFET (PHASE voltage) of Channel 1 for over current protection when it is turned on. If
PHASE voltage is lower than the user programmable voltage V OCP, the AP3598A asserts OCP and shuts down the converter. The V OCP level is as
shown in Table 3. The over current IOCP can be calculated according to the on-resistance of the lower MOSFET used.
I OCP
VOCP
R DS( ON)
–
>20kΩ
10kΩ
5kΩ
VOCP (mV)
No OCP
250
150
Table 3. OCP Level Selection
A resistor ROCSET connected from LGATE1 pin sets the OCP threshold value VOCSET when Startup. An internal current source IOCSET (21.5µA
typically), flowing through ROCSET determines to select the VOCP level, which can be calculated using the following equation:
VOCSET I OCSET ROCSET
If VOCSET is lower than 150mV, VOCP will be set to 150mV; If VOCSET is between 350mV and 150mV, VOCP will be set to 250mV; If VOCSET is
higher than 350mV, VOCP will be disabled.
Because the RDS(ON) of MOSFET increases with temperature, it is necessary to take this thermal effect into consideration in calculating OCP point.
8.2 UVP Function
The output voltage VSNS is also monitored for under voltage protection. The UV threshold is set at 0.3V. The under voltage protection has 50µs
triggered delay. When UVP is triggered, both high side and low side are shutdown immediately.
OCP and UVP are latched function, the AP3598A can power off, and then power on or EN reset to restart again.
9. Over Voltage Protection (OVP)
The output voltage VSNS is continuously monitored for over voltage protection. When it is larger than 1.5 times as setting, the OVP function is
triggered. The over voltage protection has 50µs triggered delay. When OVP is triggered, LGATE will go high and UGATE will go low to discharge
the output capacitor.
10. Power Good
The PGOOD pin output is an open drain MOSFET. The output is pulled low when the AP3598A shuts down. It is recommended to use a pull-up
resistor between the values of 3kΩ and 100kΩ to a voltage source that is 5V or less. The PGOOD is in a valid state once the V CC voltage is
greater than 1.2V.
11. Thermal Shutdown
The AP3598A implements an internal thermal shutdown to protect itself if the junction temperature exceeds T J.
TSNS is the external thermistor temperature sensing input.
TALERT# is an active low open drain output warning signal to indicate when either the controller has reached 80% percent of T JMAX or MOSFET
has reached its threshold through the external thermistor.
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Application Information (Cont.)
AP3598A
RTALERT
TALERT#
Open Drain Output
VREF
Internal Die
Temperature
Sensor
NEW PRODUCT
RTM2
TSNS
RTM
External
Temperature
Sensing
Comparator
GND
Figure 4. Thermal Alert and Temperature Sense
12. PWM-VID Dynamic Voltage Control
PWM-VID is a single-wire dynamic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count
and enables a wide dynamic voltage range.
The PWM-VID duty cycle determines the variable output voltage at REFIN, as shown in Figure 5. VMIN is the zero percent duty cycle voltage value.
VMAX is the one hundred percent duty cycle voltage value. The resolution of each voltage step (V STEP) is determined by the number of available
steps (NMAX) and the selection of the dynamic voltage range (VMAX-VMIN). N is the number of steps at a specific VOUT. N/NMAX ratio is equal to the
duty cycle. The dynamic voltage VID frequency (f SWVID) is determined by the unit pulse width (t U) and the available step number NMAX (tVID =
tU*NMAX, fVID = 1/ tVID). tU is programmable.
Figure 5. Dynamic Output
VSTEP, NMAX, VMIN, and VMAX are variables that determine VOUT. NMAX is limited by the unit pulse width and the minimum VID frequency.
The dynamic voltage output could be implemented by the analog method with a switching device and a resistor network. A buffer is used as the
switching device to create dynamic output. Resistor network sets the minimum offset voltage.
12.1 Circuit Diagram
Figure 6 shows the analog circuit diagram for the PWM-VID dynamic voltage control. The buffer requires a stable, high precision voltage reference
(VREF) for the linear output. The dynamic range of the circuit is determined by the resistor selection. Resistor R REFADJ and capacitor CREFIN
function as a filter for the PWM signal, and will affect the ripple voltage and the slew rate at the output (REFIN) during voltage transitions.
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VREF
IN
RVREF1
Buffer
VCC
PWM
REFIN
OE
A
RREFADJ
NC
NEW PRODUCT
GND
CREFIN
GND
RVREF2
GND
GND
Figure 6. PWM-VID Analog Circuit Diagram
Spec Description
Output Voltage Equation
NMAX: Total available voltage step number
–
N: The step number of the specific VOUT, N/NMAX ratio equals duty cycle
–
VREF
VMAX: The output voltage of REFIN at one hundred percent duty cycle
VREF
VMIN: The output voltage of REFIN at zero percent duty cycle
R VREF2
R VREF2 ( RVREF1 || R REFADJ )
RVREF 2 || R REFADJ
R VREF1 ( RVREF 2 || R REFADJ )
VMAX - VMIN
N MAX
VSTEP: The resolution of the voltage step
VMIN N VSTEP
VOUT: The output voltage at REFIN
1
tU N MAX
fSWVID: The dynamic voltage VID frequency
Table 4. REFIN Dynamic Range
There will be some ripple voltage at REFIN due to the nature of the PWM and filter. The error amplifier at REFIN will be able to tolerate a
reasonable amount of Ripple Voltage.
12.2 Integrating the Buffer
Figure 7 shows a dynamic voltage control circuit with the integrated buffer. This defines the implementation of the VID and REFADJ functions.
Controller
VREF
RVREF1
REFIN
RREFADJ
RSTANDBY
External
Control
Q5
D
RVREF2
REFADJ
VSTANDBY
Block
GND
CREFIN
GND
PWM
S
GND
R15
GND
VCC Buffer
A
GND
G
IN
OE
O
NC
IN
VID
GND
Figure 7. Integrated Buffer Circuit
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NEW PRODUCT
12.3 Timing Diagram
Figure 8 contains the details of the timing diagram. After VCC powers up, the controller generates the V REF. REFIN settles at VBOOT before the
GPU drives the VID pin. After the GPU powers up, V BOOT control will be pulled low by software. At the same time the VID is driven by a PWM
signal, moving REFIN into the normal operating mode. When the GPU is going to standby, software will tri-state VID and VBOOT control, and an
external control will enable RSTANDBY.
Figure 8. Time Diagram
12.4 Standby Mode
Standby mode keeps the GPU in a low voltage state (in the range of 0.3V) for the quick recovery. As the GPU steps into the standby mode, the
resistor RSTANDBY and the switch Q6 (parallel to the RVREF2 and RBOOT) set the standby voltage. The accuracy of the reference voltage in the
standby mode could be reduced from the normal operating mode. Refer to Figure 9 for the illustration of the standby voltage.
Figure 9. Illustration for Standby Mode and Adjustable VBOOT Setting
12.5 Voltage Waveform and Propagation Delay
Figure 10. The Behavior of the Buffer
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12.6 Electrical Characteristics
NEW PRODUCT
Parameters
Sym
Min
Typ
Max
Unit
Notes
Buffer Supply Voltage
–
–
VREF
–
V
–
Unit Pulse Width
tU
–
27
–
ns
Configurable
Buffer Output Rise Time
tR
–
5
–
ns
–
Buffer Output Fall Time
tF
–
5
–
ns
–
Rising and Falling Edge Delay
Δt
–
–
0.5
ns
Δt=|tR-tF|
Propagation Delay
tPD
–
10
–
ns
tPD=tPHL=tPLH
ΔtPD
–
–
0.5
ns
ΔtPD=tPHL-tPLH
Upper Resister
RVREF1
–
4.75
–
kΩ
–
Lower Resister
RVREF2
–
4.22
–
kΩ
–
Filter Resister
RREFADJ
–
6.34
–
kΩ
–
RBOOT
–
–
–
kΩ
Project Specific
RSTANDBY
–
1.07
–
kΩ
–
CREFIN
–
0.033
–
μF
–
Propagation Delay Error
Boot Mode Resister
Standby Mode Resister
Filter Capacitor
13. PWM Compensation
The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase
shift in the control loop. A compensation network among COMP, VSNS, and V OUT should be added. The compensation network is shown in Figure
14. The output LC filters consist of the output inductors and output capacitors. For two-phase convertor, when assuming that VIN1 = VIN2 = VIN, L1
= L2 = L, the transfer function of the LC filter is given by:
Gain LC
1 s RESR COUT
s (1 / 2) L COUT s RESR COUT 1
2
The poles and zero of the transfer functions are:
f LC
1
2 (1/ 2) L COUT
f ESR
1
2 RESR COUT
The fLC is the double-pole frequency of the two-phase LC filters, and fESR is the frequency of the zero introduced by the ESR of the output
capacitors.
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L1=L
VPHASE1
VOUT
L2=L
VPHASE2
COUT
NEW PRODUCT
RESR
Figure 11. The Output LC Filter
Figure 12. Frequency Response of the LC Filters
The PWM modulator is shown in Figure 13. The input is the output of the error amplifier and the output is the PHASE node. The transfer function
of the PWM modulator is given by:
GainPWM
VIN
VOSC
VIN
Driver
OSC
PWM
Comparator
-
ΔVOSC
PHASE
+
Output of Error
Amplifier
Driver
Figure 13. The PWM Modulator
The compensation network is shown in Figure 14. It provides a close loop transfer function with the highest zero crossover frequency and
sufficient phase margin. The transfer function of error amplifier is given by:
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GainAMP
VCOMP
VOUT
1
1
1
1
(s
) {s
}
//(R 2
)
R2 C 2
( R1 R3) C 3
sC 2 R1 R3
sC1
1
C1 C 2
1
R1 R3 C1
R1 //( R3
)
s( s
) (s
)
sC 3
R 2 C1 C 2
R3 C 3
NEW PRODUCT
The pole and zero frequencies of the transfer function are:
f Z1
1
2 R2 C 2
fZ 2
1
2 ( R1 R3) C 3
f P1
1
fP2
2 R2 (
C1 C 2
)
C1 C 2
1
2 R3 C 3
C1
R3
C3
R2
C2
VOUT
R1
FB
+
VCOMP
VREF
Figure 14. Compensation Network
The closed loop gain of the converter can be written as:
GainLC GainPWM Gain AMP
Figure 15 shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network.
Using the below guidelines will give a compensation similar to the curve plotted. A stable closed loop has a -20dB/decade slope and a phase
margin greater than 45 degree.
1. Choose a value for R1, usually between 1kΩ and 5kΩ.
2. Select the desired zero crossover frequency.
f O (1 / 5 ~ 1 / 10 ) f SW
Use the following equation to calculate R2:
R2
VOSC f O
R1
VIN
f LC
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3. Place the first zero fZ1 before the output LC filter double pole frequency fLC.
f Z 1 0.75 f LC
NEW PRODUCT
Calculate the C2 by the equation:
C2
1
2 R 2 f LC 0.75
4. Set the pole at the ESR zero frequency fESR:
f P1 f ESR
Calculate the C1 by the following equation:
C1
C2
2 R 2 C 2 f ESR 1
5. Set the second pole fP2 at the half of the switching frequency and also set the second zero f Z2 at the output LC filter double pole fLC. The
compensation gain should not exceed the error amplifier open loop gain. Check the compensation gain at fP2 with the capabilities of the error
amplifier.
f P 2 0.5 f SW
f Z 2 f LC
Combine the two equations will get the following component calculations:
R3
R1
f SW
1
2 f LC
C3
1
R3 f SW
Figure 15. Converter Gain and Frequency
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14. Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as:
D VOUT / VIN
NEW PRODUCT
For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple current, ΔI P-P, and affects the load transient
response. Higher inductor value reduces the output capacitors’ ripple current and induces lower output ripple voltage. The ripple current can be
approximated by:
I P P
VIN 2VOUT VOUT
f SW L
VIN
Where fSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s
ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the
expense of higher ripple current. Increasing the switching frequency (f SW ) also reduces the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A
good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been
chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially
core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage.
15. Output Capacitor Selection
Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting output capacitors.
Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR
capacitors is recommended for switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the
output voltage ripple includes the capacitance voltage drop ΔV COUT and ESR voltage drop ΔVESR caused by the AC peak-to-peak sum of the
inductor’s current. The ripple voltage of output capacitors can be represented by:
VCOUT
I P P
8 COUT f SW
VESR I P P RESR
These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled
to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors are
needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for
bypassing the noise is also recommended, and the voltage rating of the output capacitors must be considered too.
To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load
step change.
For getting same load transient response, the output capacitance of two-phase converter only needs to be around half of output capacitance of
single-phase converter.
Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current
specified on the capacitors in order to prevent the capacitor from overheating.
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16. Input Capacitor Selection
NEW PRODUCT
Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET
turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of lowside MOSFET.
The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk
capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For twophase converter, the RMS current of the bulk input capacitor is roughly calculated as the following equation:
I RMS
I OUT
2 D (1 2 D)
2
For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tantalum capacitors can be used, but
caution must be exercised with regard to the capacitor surge current rating.
17. MOSFET Selection
The AP3598A requires two N-Channel power MOSFETs on each phase. These should be selected based upon R DS(ON), gate supply requirements
and thermal management requirements.
In high current applications, the MOSFET power dissipation, package selection, and heatsink are the dominant design factors. The power
dissipation includes two loss components: conduction loss and switching loss.
The conduction losses are the largest component of power dissipation for both the high-side and the low-side MOSFETs. These losses are
distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since
the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous
rectifier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due to the reverse-recovery
of the low-side MOSFET body diode. The gate-charge losses are dissipated by AP3598A and don’t heat the MOSFETs. However, large gatecharge increases the switching interval t SW, which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their
maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance
specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
For the high-side and low-side MOSFETs, the losses are approximately given by the following equations:
PHIGH-SIDE=IOUT2×(1+TC) ×RDS(ON)×D+ 0.5×IOUT×VIN×tSW×fSW
PLOW-SIDE=IOUT2×(1+TC)×(RDS(ON))×(1-D)
Where IOUT is the load current, TC is the temperature dependency of RDS(ON), fSW is the switching frequency, tSW is the switching interval, D is the
duty cycle.
Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, t SW, is
the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET.
18. Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance
and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is
carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting impedances and the magnitude of voltage spike.
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NEW PRODUCT
Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The
best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less
noise. Noisy traces beneath the IC are not recommended. Figure 16 illustrates the layout, with bold lines indicating high current paths; these
traces must be short and wide. Components along the bold lines should be placed close together. Below is a checklist for your layout:
1. Keep the switching nodes (HGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast
moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses
traces on any layer.
2. The signals going through theses traces have both high dv/dt and high dI/dt with high peak charging and discharging current. The traces from
the gate drivers to the MOSFETs (HGATEx and LGATEx) should be short and wide.
3. Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide
layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs
(VIN and PHASEx nodes) can get better heat sinking.
4. For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid
the noise interference, the current sensing trace should be away from the noisy switching nodes.
5. Decoupling capacitors, the resistor-divider, and the boot capacitor should be close to their pins. (For example, place the decoupling ceramic
capacitor as close as possible to the drain of the high-side MOSFET). The input bulk capacitors should be close to the drain of the high-side
MOSFET, and the output bulk capacitors should be close to the loads.
6. The input capacitor’s ground should be close to the grounds of the output capacitors and the low-side MOSFET.
7. Locate the resistor-divider close to the VREF and REFIN pins to minimize the high impedance trace. In addition, VSNS pin traces can’t be close
to the switching signal traces (HGATEx, LGATEx, BOOTx, and PHASEx).
AP3598A
Figure 16. The Layout of AP3598A
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Ordering Information
AP3598A XX XX – XX
Package
Packing
RoHS/Green
FN : U-QFN4040-24
TR : Tape & Reel
G1 : Green
NEW PRODUCT
Product Name
Package
Temperature Range
U-QFN4040-24
-40 to +85C
Part Number
AP3598AFNTR-G1
Marking ID
B3F
Packing
5000/Tape & Reel
Marking Information
(Top View)
First Line: Logo and Marking ID
Second and Third Lines: Date Code
Y: Year
WW: Work Week of Molding
M: Assembly House Code
th
th
XX: 7 and 8 Digits of Batch No.
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Package Outline Dimensions (All dimensions in mm(inch).)
(1)
Package Type: U-QFN4040-24 (Type B)
0.500(0.020)
NEW PRODUCT
3.950(0. 156)
4.050(0.159)
0.630(0.025)
TYP
TYP
N24 PIN # 1 IDENTIFICATION
N19
N1
Pin 1 Mark
3.950(0. 156)
4.050(0. 159)
2.650(0.104)
2.750(0.108)
N13
0.350(0.014)
0.450(0.018)
N7
0.190(0. 007)
0.290(0. 011)
2.650(0.104)
2.750(0.108)
0.000(0.000)
0.050(0.002)
0.550(0.022)
0.650(0.026)
AP3598A
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0.150(0.006)
TYP
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© Diodes Incorporated
A Product Line of
Diodes Incorporated
AP3598A
Suggested Pad Layout
(1)
Package Type: U-QFN4040-24 (Type B)
X
NEW PRODUCT
E
Y2
E
Y1
Y
Y3
X2
X1
Dimensions
X=Y1
(mm)/(inch)
Y
(mm)/(inch)
X1
(mm)/(inch)
Y2
(mm)/(inch)
Value
2.840/0.112
4.300/0.169
0.340/0.013
0.600/0.024
Dimensions
X2=Y3
(mm)/(inch)
E
(mm)/(inch)
–
–
Value
2.800/0.110
0.500/0.020
–
–
AP3598A
Document number: DS37261 Rev. 2 - 2
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www.diodes.com
November 2014
© Diodes Incorporated
A Product Line of
Diodes Incorporated
AP3598A
IMPORTANT NOTICE
NEW PRODUCT
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2014, Diodes Incorporated
www.diodes.com
AP3598A
Document number: DS37261 Rev. 2 - 2
28 of 28
www.diodes.com
November 2014
© Diodes Incorporated