APW8733 Dual-Phase COT Buck PWM Controller with Dynamic Voltage Features General Description • High Input Battery Voltages Range from 1.8V to The APW8733 is a dual-phase PWM control IC which 25V Input Power provides a precision voltage regulation system for advanced graphic card and motherboard applications. The • Multiform Purpose Input Voltage Collocation: VCC integration of dual-phase power MOSFET drivers into the controller IC and reduces the number of external parts for = 5V / VIN = 5.5V ~ 19V for NB MXM application • Built in VREF voltage = 2.0V +1% with all a cost and space saving power management solution. temperature range • External reference input with PWM VID Dynamic The APW8733 uses a constant on time architecture voltage control control, and results in excellent transient response and accurate DC voltage output in either PFM or PWM Mode. • Integrated Bootstrap Forward P-CH MOSFET • Built in Adjustable Frequency by TON : 100KHz ~ In Pulse Frequency Mode (PFM), the APW8733 provides very high efficiency over light to heavy loads with loading 800KHz range • modulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise Built in Constant On Time PWM Control with Current Sharing Operation • requirements. The device uses the voltage across the low side R DS(ON) for current sensing achieves high Built in External Soft-Start & Soft-Stop functions for output voltage • efficiency. The device integrates adjustable load line voltage positioning (droop) and adopts low side RDS(ON) for Support Single and Two phases PWM Control by channel-current balance. The APW8733 also implement a VID control operation in which the feedback voltage is LGATE2 & PSI voltage setting • Built in Programmable OCP function by Sensing regulated and tracks external input reference voltage. This controller protection features include over-temperature Low Side MOSFET • Built in UVP (50%), OVP(145%) & Thermal (OTP), over-voltage (OVP), under-voltage (UVP) and overcurrent protections (OCP). The device also provides a Shutdown functions on PWM Channel • Built in PGOOD indicator for output voltage • Built in POR Control Scheme Implemented at 4. power-on-reset function and a external programmable soft-start to prevent wrong operation and limit the input 25V ~ 4.45V range • Shutdown Control by EN using an External MOSFET • TQFN 3x3-20 Package surge current during power-on or start-up. The APW8733 is available in TQFN 3x3-20 packages. Applications • VGA ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 1 www.anpec.com.tw APW8733 Simplified Application Circuit 5.0V VREF REFIN VIN VCC PSI UGATE1 VOUT REFADJ LGATE1 CLK VID OUT VCC PGOOD UGATE2 VSNS LGATE2 Ordering and Marking Information Package Code QB: TQFN3x3-20 APW8733 Operating Ambient Temperature Range I : -40 to 85oC Assembly Material Handling Code Temperature Range Package Code APW8733 QB: APW 8733 XXXXX Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 2 www.anpec.com.tw APW8733 Pin Configuration PHASE1 LGATE1 VCC LGATE2 PHASE2 20 19 18 17 16 BOOT1 1 15 BOOT2 UGATE1 2 14 UGATE2 EN 3 PSI 4 VID 5 (Exposed Pad) GND 13 PGOOD 12 IOFS 11 VSNS 6 7 8 9 10 REFADJ REFIN VREF TON GNDSNS TQFN3x3-20 Top View = Thermal Pad (connected to GND plane for better heat dissipation) Absolute Maximum Ratings (Note 1,2) Symbol VCC VBOOT1/2 Parameter Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V BOOT1/2 to PHASE1/2 Voltage -0.3 ~ 7 V BOOT1/2 to GND Voltage -0.3 ~ 44 V > 400ns -0.3 ~ VBOOT1/2 + 0.3 V < 400ns -5 ~ VBOOT1/2 + 0.3 V > 400ns -0.3 ~ VCC + 0.3 V < 400ns -5 ~ VCC + 0.3 V > 400ns -1 ~ 28 V < 400ns -5 ~ 35 V EN, PSI, VID, REFADJ, REFIN, VREF, TON, GNDSNS, VSNS, IOFS and PGOOD to GND Voltage -0.3 ~ VCC + 0.3 V PD Power Dissipation Internally Limited TJ Maximum Junction Temperature VUGATE1/2 UGATE1/2 to PHASE1/2 Voltage VLAGTE1/2 LGATE1/2 to GND Voltage VPHASE1/2 PHASE1/2 to GND Voltage W 150 o C TSTG Storage Temperature -65 ~ 150 o TSDR Maximum Lead Soldering Temperature (10 Seconds) 300 o VESD Minimum ESD Rating (Human Body Mode) ±2 C C kV Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: The device is ESD sensitive. Handling precautions are recommended. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 3 www.anpec.com.tw APW8733 Thermal Characteristics (Note 3) Symbol θJA Parameter Junction-to-Ambient Resistance in free air θJC Typical Value (Note3) TQFN3x3-20 Junction-to-Case Resistance TQFN3x3-20 Unit 60 o 8 o C/W C/W Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 4) Symbol VIN Parameter Range Unit Converter Input Voltage 1.8 ~ 25 V VCC VCC Supply Voltage (VCC to GND) 4.5 ~ 5.5 V VOUT VOUT to GND 0.2 ~ 4 V IOUT Converter Output Current 0 ~ 40 TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o A C C Note 4: Refer to the typical application circuit. Electrical Characteristics Refer to Figure. 1 in the “Typical Application Circuits”. These specifications apply over VIN = 12V, VCC = 5V, TA = 25oC, unless otherwise noted. Typical values are at TA = 25oC. Symbol Parameter Test Conditions APW8733 Unit Min Typ Max 4.5 - 5.5 V SUPPLY CURRENT Vcc IVCC1 IVCC2 IVCC_SD VCC Supply Voltage Range VCC Supply Current EN = high, VSNS > VREFIN = 1V, PSI = high, RLG2SET = 4K Phase1 and Phase2 are both non-switching. - 500 700 µA VCC Supply Current EN = high, VSNS > VREFIN = 1V, PSI = high, RLG2SET = 2K Phase1 is non-switching. Phase2 is shutdown. - 300 500 µA VCC Shutdown Current No switching, EN = GND 3 10 µA 4.25 4.35 4.45 V - 0.1 - V 189 210 231 ns POWER ON RESET (POR) VPOR POR Threshold of VCC VPOR_HYST POR Hysteresis PWM FREQUENCY SETTING TON On Time VIN=19V, VOUT=1V, RTON=1MΩ TON(MIN) Minimum On Time Over all temperature & VCC 80 110 140 ns TOFF(MIN) Minimum Off Time VREFIN = 1V, VSNS = 0.9V, VPHASE = -0.1V 200 300 400 ns BOOSTSTRAP SWITCH VF Forward Voltage VCC - VBOOT1/2-GND, IF = 10mA - 0.3 0.4 V IR Reverse Leakage current VBOOT1/2-GND = 30V, VPHASE1/2 = 25V, VCC=5V - 0.2 0.5 µA Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 4 www.anpec.com.tw APW8733 Electrical Characteristics Refer to Figure. 1 in the “Typical Application Circuits”. These specifications apply over VIN = 12V, VCC = 5V, TA = 25oC, unless otherwise noted. Typical values are at TA = 25oC. S ymbol Parame ter APW 8733 Test Conditions Unit Min Typ Max CHIP ENABLE VENH Ch ip Enab le Thr eshold EN Risin g 1.2 - - V V ENL Ch ip Shutdown Threshol d EN Fa lling - - 0.6 V EN_LCD L eakage Curre nt VCC = E N = 5V - 0 .1 1 µA PGO OD L eakage curren t VPGOOD = 5V - 0 .1 1.0 µA PGO OD o utp ut low vo lta ge I PGOOD _SIN K = 4mA 0 .5 1.0 V PGO OD d elay time EN goes high to PGOO D go es hi gh - 30 0 350 us PGO OD Disabl e Deb ounce time VSNS be lows the Hysteresis o f 85%VREFIN to P GOOD go es low - 20 - us POWER GOOD INDICATOR POWER SAVING MO DE V PSI_ H PSI Hig h Thre sh old Volta ge VPSI Rising 0.9 1 1.1 V VPSI_L PSI Low Thre sh old Vo lta ge VPSI Falli ng 0.54 0 .6 6.6 V V LG2 _1 VLG2_1 Thresho ld Vo ltag e (Note5) 0.54 0 .6 0 .66 V V LG2 _2 VLG2_2 Thresho ld Vo ltag e (Note5) 0 .9 675 1.07 5 1.182 5 V V LG2 _3 VLG2_3 Thresho ld Vo ltag e (Note5) 1.62 1 .8 1 .98 V Two-Pha se with PWM to Sing le-Ph ase with PFM debo unce time - 30 0 - us Two-Pha se with PWM to Sing le-Ph ase with PWM debo unce time - 30 0 - us Two-Pha se with PWM to Sing le-Ph ase with Ul tra -so nic PFM de boun ce time - 30 0 - us 25 30 35 kHz IL G2SET Switchi ng Fr equen cy of Ul tra -so nic PFM EN = high, PSI = low, R LG2SET = 4K Mo de Setting Current Sou rce from LGATE2 Te rminals 230 24 0 250 µA 1.98 2.00 2 .02 V REFE RE NCE VO LTAGE VR EF Re fe rence Volta ge Accuracy I REF=100 uA, T A= -20 OC ~ 85O C I REF VREF Maximum Output Cu rrent VREF = GND - 5 - mA Re fe rence Volta ge Load Re gulation I REF=0~2mA -5 - 5 mV ΔVR EF VREF Discharg e Resista nce VREFIN O perating Rang e RE FIN Inp ut Le akage Curren t Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 5 - - 100 Ω 0.2 - 2 V - - 0.1 µA www.anpec.com.tw APW8733 Electrical Characteristics Refer to Figure. 1 in the “Typical Application Circuits”. These specifications apply over VIN = 12V, VCC = 5V, TA = 25oC, unless otherwise noted. Typical values are at TA = 25oC. S ymbol Parame ter APW 8733 Test Conditions Unit Min Typ Max - 20 - SOFT-STOP RSTOP Soft Sto p Discharg e Resistance VSNS to GND Resistan ce Ω VID CONTROL INPUT VIH Logic High Th reshold Le vel 1.2 - - V VIL Logic Low Th reshold Le vel - - 0.6 V R REFADJ IR EFADJ VID Input Leakage Curr ent VID = 3 .3V - - 1 µA On Resistance of RE FA DJ MO SFET VID = High - 20 - Ω Leakag e Cur rent o f REFADJ Pin VREFADJ = 2V, VID = GND - - 0.1 µA REFADJ DRIV ING TR RE FADJ Rising Time With 2 0pF L oad - 5 10 ns TF RE FADJ Fal ling Time With 2 0pF L oad - 5 10 ns Ri sin g and Falling Ed ge Delay |T R-T F | -0.5 - 0.5 ns T PDR Ri sin g P ropag ation Delay 50% VID to 50%V REFADJ wi th 20 pF Lo ad - 10 - ns T PDF Fa lling Pro pagation Dela y 50% VID to 50%V REFADJ wi th 20 pF Lo ad - 10 - ns Propa gation Delay Error |T PDR- TPD F| -0.5 - 0.5 ns - 27 - ns VPHASE1- GND -5 - 5 mV △ T PD TU Un it Pu lse Width ZERO CURRE NT DETECT VZC Ze ro Cu rrent De te ct PHASE CURRE NT SENSE gm Tr ans-condu ctance Note5 - 1 .0 - mA/V V OFFSET GM A mplifier Offset Note5 -5 - 5 uV 100 kΩ from IOFS to V RE F 1.425 1 .5 1.575 V 100 kΩ from IOFS to G ND 0.475 0 .5 0.525 V VIOFS IO FS Voltage GATE DRIV ER R UG_SR C Up per Sid e Gate Sourcing I UGATE=100mA Sour cin g - 2 .0 4.0 Ω RU G_ SN K Up per Sid e Gate Sinking I UGATE=100mA Sinkin g - 1 .5 3.0 Ω R LG_SRC Low S ide Ga te So urcing I LGATE=100m A Sou rci ng - 2 .0 4.0 Ω Low S ide Ga te Sin kin g I LGATE=100m A Sinkin g R LG_SNK T DT De ad-time I VSN S VSNS Input Bias Cur rent VSNS = 2V VSNS Disch arge Resistance Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 6 - 1 .0 2.0 Ω - 30 - ns -0.5 - 0.5 µA - - 20 Ω www.anpec.com.tw APW8733 Electrical Characteristics Refer to Figure. 1 in the “Typical Application Circuits”. These specifications apply over VIN = 12V, VCC = 5V, TA = 25oC, unless otherwise noted. Typical values are at TA = 25oC. S ymbol Parame ter APW 8733 Test Conditions Unit Min Typ Max 140 14 5 150 % - 2 - us 40 50 60 % - 2 - us 110 12 0 130 µA PROTECTION Over Vo lta ge Protecti on (OVP ) VSNS-GNDSNS/VR EFIN-GND OVP Debo unce time Un der Voltage Protection (UVP) VSNS-GND/VR EFIN-GN D UV P De bounce time IOCSET OCP Settin g Cu rrent Sou rce from LGATE1 Te rminals OCP De boun ce time Ma ximu m VOCSET Thresho ld - 2 - us 0.55 0 .6 - V OCP DA C Sa mp le De lay Time (Note5) - 50 - us OCP DA C Maximum Sample Time (Note5) - 70 - us Over Temp erature Pro tection (OTP) - 15 0 - o Over Temp erature Hysteresis - 30 - o C C Note 5: Guarantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 7 www.anpec.com.tw APW8733 Pin Description PIN NAME FUNCTION 1 BOOT1 Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT1 range from 0.1µF to 1µF. Ensure that CBOOT1 is placed near the IC. 2 UGATE1 Upper Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 3 EN Enable input. 4 PSI Power Saving Mode. Connect a resistor from PSI to GND to set the power saving mode threshold current level. Connect this pin to VREF and RLG2SET >= 4K for always two phases operation. Short this pin to ground for always single-phase operation. (refer to Table.1) 5 VID VID Input. This pin is used to adjust reference voltage. 6 REFADJ 7 REFIN External Reference Input. This is input pin of external reference voltage. Connect a voltage divider from VREF to REFIN to GND to set the reference voltage. 8 VREF Reference Voltage Output. This is the output pin of high precision 2V reference voltage. Bypass this pin with a 1uF ceramic capacitor to GND. 9 TON The Pin is Allowed to Adjust the Switching Frequency. Connect a resistor RTON from TON pin to VIN. 10 GNDSNS 11 VSNS Feedback Voltage. Output Voltage Feedback Pin. This pin is connected to the output voltage. The PGOOD, UVP, and OVP circuits detect this signal to report output voltage status. 12 IOFS Current Balance Adjustment. Connect a resistor from this pin to VREF or GND to adjust the current sharing. 13 PGOOD Open drain power good output. 14 UGATE2 Upper Gate Driver Output for channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 15 BOOT2 Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT2 range from 0.1μF to 1µF. Ensure that CBOOT2 is placed near the IC. 16 PHASE2 Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 17 LGATE2 Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 18 VCC 19 LGATE1 Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 20 PHASE1 Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Exposed Pad GND Reference adjustment output. GND Sense. Negative node of the remote voltage sense. Supply Voltage. This pin provides current for internal control circuit. Bypass this pin with a minimum 1uF ceramic capacitor next to the IC. Ground. Tie this pin to the ground island/plane through the lowest impedance connection available. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 8 www.anpec.com.tw APW8733 Block Diagram VREF EN VCC Internal Regulator Power On Reset IOFS 145%VREFIN PGOOD VSNS VSNS VID 85%VREFIN PHASE1 PHASE2 REFADJ OTP TJ > 150oC Current Balance VSNS TON VSNS1 VSNS2 Comparator On-time Generator VSNS GNDSNS + Power Saving Setting EN REFIN BOOT1 VCC BOOT2 VCC Logic Control UGATE1 PSI Logic Control UGATE2 PHASE1 PHASE2 ILG2SET IOCSET VCC VCC LGATE1 Over Current Protection S/H Over Voltage Protection PHASE1 PHASE2 Under Voltage Protection LGATE2 Zero Crossing Detector GND Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 9 www.anpec.com.tw APW8733 Typical Application Circuit 33k PSI VCC 2.2µF 2R2 TON BOOT1 100k VCC PGOOD EN 270µFx2 VOUT PHASE1 0.8µH APM3106 10µFx2 820µFx3 ROCSET (Option ) IOFS 51k VREF BOOT2 UGATE2 0.1µF 10µFx2 APM3109 PHASE2 1k REFIN 1k VIN =12V 10µFx2 APM3109 LGATE1 1uF 1M 0.1µF UGATE1 5V 8.2k REFADJ LGATE2 1uF 100R 0.8µH APM3106 0R RLG2SET VID VSNS GNDSNS GND Figure.1 Typical Application Circuit Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 10 www.anpec.com.tw APW8733 Function Description Constant-On-Time PWM Controller with Input Feed-For- Where FSW is the nominal switching frequency of the con- ward verter in PWM mode. The load current at handoff from PFM to PWM mode is given by: The constant-on-time control architecture is a pseudo fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resis- TLOAD(PFM − PWM) = tor so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time is = controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- 1 VOUT − VOUT × × TON − PFM 2 L VIN − VOUT 1 VOUT × × 2L FSW VIN Forced-PWM Mode tional to the input voltage and directly proportional to the output voltage. In PWM operation, the high-side switch The Forced-PW M mode disables the zero-crossing comparator, which truncates the low-side switch on-time on-time is determined by a switching frequency control circuit in the on-time generator block. The switching fre- at the inductor current zero crossing. This causes the low-side gate-drive waveform to become the complement quency control circuit senses the switching frequency of the high-side switch and keeps regulating it at a constant of the high-side gate-drive waveform. This in turn causes the inductor current to reverse at light loads while UGATE frequency in PWM mode. The design improves the frequency variation and is more outstanding than a conven- maintains a duty factor of VOUT/VIN. The benefit of ForcedPWM mode is to keep the switching frequency fairly tional constant-on-time controller, which has large switching frequency variation over input voltage, output current, constant. The Forced-PWM mode is most useful for reducing audio frequency noise, improving load-transient and temperature. Both in PFM and PWM, the on-time response, and providing sink-current capability for dy- generator, which senses input voltage on TON pin, provides very fast on-time response to input line transients. namic output voltage adjustment. Another one-shot sets a minimum off-time (typical: 300ns). The on-time one-shot is triggered if the error com- VCC Power-On-Reset (POR) The Power-On-Reset (POR) circuit compares the input parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- voltage at VCC with the POR threshold (4.35V rising, typical) to ensure the input voltage is high enough for shot has timed out. Pulse-Frequency Modulation (PFM) reliable operation. The 0.1V (typ.) hysteresis prevents supply transients from causing a restart. Once the input In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This voltage exceeds the POR rising threshold, startup begins. When the input voltage falls below the POR falling switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero threshold, the controller turns off the converter. crossing. This mechanism causes the threshold between PFM and PWM operation to coincide with the boundary VREF This is the output pin of high precision 2V reference between continuous and discontinuous inductor-current operation (also known as the critical conduction point). voltage. Bypass this pin with a 1uF ceramic capacitor to GND. The VREF must have capability to drive 5mA output The on-time of PFM is given by: TON − PFM = current. 1 VOUT × FSW VIN Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 11 www.anpec.com.tw APW8733 Function Description (cont.) Soft-start and Soft-stop After the VCC voltage exceeds the POR voltage threshold VREF and the EN threshold exceeds 1.6V, the device initials a start-up process and then ramps up the output voltage to External Control (GPU Standby mode) the setting of output voltage. The external soft-start circuit is as shown in Figure. 2. The REFIN voltage is divided by VID(PWM) the resistor R1 and R2. The soft-start duration is given by: GPU Standby VOUT VBOOT VBOOT VSTANDBY REFIN TSS = 5τ Where τ = [ (R1xR2) / (R1+R2) ] x CADJ Figure. 3 Timing Diagram Since the VREFIN soft-start, to prevent PGOOD abnormal Over Current Protection (OCP) trigger during soft-start. For preventing wrong behavior or trigger some protections during soft start period, sug- A resistor (ROCSET), connected from the LGATE1 to GND, gested the CADJ capacitance must be limited under 10nF and resistors R1 plus R2 is lower than 10kΩ. Moreover, programs the over-current trip level. Before the IC initiates a start-up process, an internal current source, IOCSET consider the power sequence issue, suggested the VREFIN established time is within 100µs(Typ.).After 300µs which (120µA typical), flowing through the ROCSET develops a voltage (VROCSET) across the ROCSET. The device holds VOCP EN goes high, the PGOOD is enabled. In the events of under-voltage, over-voltage, over-current, or shutdown, and stops the current source, I OCSET, during normal operation. When the voltage across the low-side MOSFET the chip enables the soft-stop function. The soft-stop function discharges the output voltages to the GND through exceeds the VOCP, the IC turns off both high-side and lowside MOSFETs. The APW8733 has an internal OCP volt- an internal 20Ω switch. age (VOCP_MAX), and the value is 0.6V typical. When the ROCSET x IOCSET is exceeds 0.6V or the ROCSET is floating or VID not connected, the over current threshold will be the internal default value 0.6V. The VID pin adjusts from VBOOT to VOUT should be normal (Band-Width is large enough). The soft-start time from The threshold of the valley inductor current is therefore VBOOT to VOUT depend on R3 & CADJ, and the output ripple of VREFIN depend on CADJ & VID frequency. R1 R2 R3 CADJ PWM given by: IOCSET × ROCSET RDS( ON )(LOW − Side ) VREF IOCP = REFIN IOCP × ROCSET = IL1 × RDS( ON) _ LG1 + IL 2 × RDS( ON) _ LG2 ≈ IOUT × RDS(ON) REFADJ VID Buffer GND Figure.2 VID internal circuit. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 12 www.anpec.com.tw APW8733 Function Description (cont.) For the over-current is never occurred in the normal operating load range; the variation of all parameters in the Rx PHASE1 above equation should be considered: - The RDS(ON) of low-side MOSFET is varied by temperature and gate to source voltage. Users should determine the maximum R DS(ON) by using the manufacturer’s datasheet. VOFFSET ISEN1 ISEN2 Sample & Hold ISEN1- ISEN2 Rx VSNS1 Current Balance VSNS2 PHASE2 - The minimum I OCSET (120µA) and minimum R OCSET should be used in the above equation. VOFFSET - Note that the IOCP is the current flow through the lowside MOSFET; IOCP must be greater than valley inductor Figure. 4 Illustration of Current Balance Circuit current which is output current minus the half of inductor ripple current. LOCP > IOUT − VSNS Offset Current Adjust The APW8733 integrated IOFS allows the offset current ∆I 2 to adjust phase current. The IOFS pin voltage is nominal 0.5V when connecting a resistor to GND and 1.5V when Where ∆I = output inductor ropple current connecting a resistor to VREF. Connecting a resistor from IOFS pin to GND generate a current source as: Current Sharing The APW8733 extracts phase currents for current balance by parasitic on-resistance of the lower switches when IOFS = 0.5V / RIOFS turned on as shown in Figure. 4. The GM amplifier senses the voltage drop across the lower switch and converts it This current is added to phase1 current signal ISEN1 for current balance. Consequently, phase2 will share more into current signal each time it turns on. The sampled and held current is expressed as: percentage of output current. Connecting a resistor from IOFS pin to VREF generates a current source as: ISENx=Gm x ∆V = (GND-VPHASE) / RX + VOFFSET / RX IOFS = (VREF - 1.5V) / RIOFS =ILX x RDS(ON) / RX + VOFFSET / RX This current is added to phase2 current signal ISEN2 for current balance. Consequently, phase1 will share more percentage of output current. The differential current of the current sharing control circuit (ISEN1-ISEN2) is used to generate two current parts, I1 and I2. The VSNS1 and VSNS2 will increase or decrease because of these two currents. For example, when ISEN1 > Automatic Phase Reduction (PSI) The APW8733 features automatic phase reduction that turns off phase2 driver signal at light load condition and ISEN2, the VSNS1 will decrease and the VSNS2 will increase. Therefore, the on-time of PWM1 will decrease and the on- reduces both switching and conduction losses. The automatic phase reduction maintains high power conver- time of PWM2 will increase. Then, the device will reduce IL1 current and increase IL2 current for current sharing, vice sion efficiency over the output current range. The output current is sensed and mirrored to PSI pin as: verse. VPSI = [( IL1 x RDS(ON)_LG1 + IL2 x RDS(ON)_LG2 ) / 800] x RPSI VPSI ~= ( IOUT x RDS(ON) / 800 ) x RPSI Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 13 www.anpec.com.tw APW8733 Function Description (cont.) A resistor (RLG2SET), connected from the L GATE2 to GND, programs the VLG2 voltage. Before the IC initiates a start- Power-Good Output up process, an internal current source, I LG2SET (240µA typical), flowing through the RLG2SET develops a voltage parator continuously monitors the output voltage. PGOOD is actively held low in shutdown, and standby. When PWM (VLG2) across the RLG2SET. The device holds VLG2 and stops the current source, ILG2SET, during normal operation. The converter’s output voltage is greater than 85% (typ.) of its target value, the internal open-drain device will be pulled VLG2 is therefore given by: low and the PGOOD will go high. The When the output voltage VOUT outruns 145% (typ.) or falls down 85% (typ.) VLG2SET = ILG2SET x RLG2SET of the target voltage, PGOOD signal will be pulled low and latched immediately. PGOOD is an open-drain output and the PGOOD com- Noted that, the setting time must be ready with 120µs (Typ.) for correct mode setting in different output power Over-Temperature Protection (OTP) The over-temperature circuit limits the junction tempera- MOSFET application.Select case1 to set the RLG2SET is no connected. Select case2 to set the VLG2SET which is ranged ture of the APW8733. When the junction temperature exceeds 150oC, a thermal sensor pulls UGTAE and LGATE between VLG2_3(1.8V) and VLG2_2(1.075V). Select case3 to set the VLG2SET which is ranged between VLG2_2(1.075V) low, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and and VLG2_1(0.6V). Select case3 to set the VLG2SET which is lower than VLG2_1(0.6V). regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC The APW8733 operation mode is as follows: hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions, in- Table.1 creasing the lifetime of the device. Case 1 2 3 4 RLG2SET VPSI > 1 NC 5.6k B A 3.3k 1.8k VPSI < 0.6 Debounce Time (us) C D E F AàB BàA 300 0 AàC CàA 300 0 AàD DàA 300 0 EàF FàE 0 0 Over Voltage Protection (OVP) The over-voltage protection (OVP) circuit monitors the VSNS (VSNS) voltage to prevent the output from overvoltage. When the VSNS rises above 145% (typ.) of the setting reference voltage, the APW8733 turns off highside and low-side MOSFETs, and through an internal 20Ω switch to sink the output voltage (VOUT). The converter shuts down and the output is latched to be floating after PGOOD goes high. Cycling the EN enable signal, VCC power-on-reset signal can reset the latch. The OVP func- Where: A: Two Phases with PWM tion is not latched before PGOOD goes high. B: Single Phase with PFM C: Single Phase with PWM D: Single Phase with Ultra-sonic PFM E: Single Phase with PWM F: Single Phase with PFM Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 14 www.anpec.com.tw APW8733 Function Description (cont.) Under Voltage Protection (UVP) Layout Consideration The under-voltage protection circuit monitors the voltage For all switching power supplies, the layout is an important step in the design; especially at high peak currents on VSNS (VSNS) by Under-Voltage (UV) comparator to protect the PWM converter against short-circuit conditions. and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty When the VSNS falls below the falling UVP threshold (50% of the setting reference voltage), a fault signal is gener- cycle jitter. 1. The input capacitor should be placed close to the VIN/ ated and the device turns off high-side and low-side MOSFETs. The converter shuts down and the output is VCC and GND. Connecting the capacitor and VIN/VCC/ GND with short and wide trace without any via holes for latched to be floating after PGOOD goes high. Cycling the EN enable signal, VCC power-on-reset signal can reset good input voltage filtering. The distance between VIN/ VCC and GND to capacitor less than 2mm respectively is the latch. The UVP function doesn’t active before PGOOD goes high. recommended. 2. To minimize copper trace connections that can inject Programming the On-Time Control and PWM Switching Frequency noise into the system, the inductor should be placed as close as possible to the PHASE1/PHASE2 pin to mini- The APW8733 does not use a clock signal to produce mize the noise coupling into other circuits. 3. The output capacitor should be place closed to con- PWM. The device uses the constant-on-time control architecture to produce pseudo-fixed frequency with input verter VOUT and GND. 4. Since the feedback pin and network is a high imped- voltage feed-forward. The on-time pulse width is proportional to output voltage VOUT and inverses proportional to ance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback net- input voltage VIN. In PWM, the on-time calculation is written as below: TON = 3.85 × 10 −12 × RTON × work should be shielded with a ground plane or trace to minimize noise coupling into this circuit. VOUT VIN − 0.5 Where: RTON is the resistor connected from TON pin to VIN. Furthermore, the approximate PWM switching frequency is written as: TON = D VOUT / VIN => FSW = FSW TON Where: FSW is the PWM switching frequency. APW8733 doesn’t have VIN pin to calculate on-time pulse width. Therefore, monitoring VTON voltage as input voltage to calculate ontime. And then, use the relationship between on-time and duty cycle to obtain the switching frequency. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 15 www.anpec.com.tw APW8733 Package Information TQFN3x3-20 D E b A Pin 1 A1 A3 D2 NX aaa C L K E2 Pin 1 Corner e S Y M B O L TQFN3x3-20 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.25 0.006 0.010 A3 0.20 REF 0.008 REF b 0.15 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 0.50 0.012 e 0.40 BSC L 0.30 K 0.20 0.016 BSC 0.008 0.08 aaa 0.020 0.003 Note : 1. Followed from JEDEC MO-220 WEEE Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 16 www.anpec.com.tw APW8733 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN3x3-20 A H T1 C d D 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.00±0.20 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type TQFN3x3-20 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 Quantity 3000 17 www.anpec.com.tw APW8733 Taping Direction Information TQFN3x3-20 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 18 www.anpec.com.tw APW8733 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8733 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2016 20 www.anpec.com.tw