Simple cell balancer EDLC cell balance LSI BD14000EFV-C evaluation board BD14000EFV-EVK-001 Summary BD14000EFV-EVK-001 realizes stand-alone cell balance of 4-6 cell series EDLC using EDLC cell balance LSI (BD14000EFV-C). The cell balance current can be set by shunt resistance. In addition, the cell balance voltage is setable, too. Performance specifications (this is a representative figure and characteristic is not guaranteed) VIN = 15V, unless otherwise specified Parameter Input voltage range Cell balance current Min Typ 8.0 100 Max Units 24 V mA Conditions Vcn-Vcn-1 = 2.5V Cell balance detection voltage setting ： It is setable at VCB = 2.4-3.1V (0.1V step) Overvoltage detection voltage setting 1 ： It is setable at VOVLO1 = VCB+0.15V or 0.25V Overvoltage detection voltage setting 2 ： It is setable at VOVLO2 = VCB+0.30V or 0.50V www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 1/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 Operating procedure 1. Necessary apparatus (1) EDLC from 4 cell to 6 cell (2) The constant current power supply which is available for voltage upper limit setting (3) Monitor with the oscilloscope or DC voltmeter 2. Connection of an apparatus (1) Connect EDLC to a board by soldering. (2) Connect a constant current power supply to plus side of the high-end cell of EDLC and minus side of the last cell and set a charge current and a voltage upper limit level. (3) Set the detection voltage by VSET0-2,OVLOSEL pin setting. (please set it in either H/L by all means.) (4) Set ENIN pin setting in 'H' to turn on this LSI. (5) Turn on a constant current source and do charge ⇔ discharge. When cell voltage is not balanced, cell balance can be realized by repeating charge and discharge several times. (6) The operation can be checked by monitoring the current between each cell and a flag output terminal (Dn, OVLO1,2, OK). (7) At a end time of evaluation, please completely discharge EDLC by a constant current source. ＊ The ENIN,VSET01,2,OVLOSEL setting, please connect a monitor pin to H:VREG/L:VSS. It is available to use 2 point of contact switches for the terminal logic’s control. In that case, please implement 2 point of contact switches at the parts list. discharge charge VREG output pin Flag output pins ENIN input pin OVLOSEL input pin EDLC Constant current power source EDLC EDLC EDLC Parts implementing area for LSI stack application EDLC EDLC BD14000EFV-EVK-001 VSET0～2 input pins Figure 1. connection image figure www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 2/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 Board circuit diagram VCC = 8.0V - 24V ①:DTA115EUA (digital transistor) ②:DTC115EUA (digital transistor) ③:2SA1576S (PNP transistor) VCC JVCC VCC 30 C6 CVCC JC6 CELL6 1 C6 2 D6 OV1_U C_C6 OV2_U VREG D6 RD6 JD6 VREG 29 VREG VREG VREG CVREG S6 28 JC5 CELL5 4 C5 C_C5 VO_OVLO2 27 D5 RD5 JD5 5 D5 Q1 Q3 ① ① to VO_OVLO2 VO_OVLO1 to VO_OVLO1 C5 VO_OVLO1 JOVLO1 VO_OVLO2 JOVLO2 VO_OK ROK S6 ROVLO2 3 ROVLO1 CAP6 J1 ② J2 J3 ② Q4 J4 26 VO_OK Q2 VREG JOK S5 CAP5 OV1_D 6 OV2_D SWENIN S5 ENIN C4 ENIN VSS 25 JC4 CELL4 VSS JENIN 7 C4 VREG BD14000EFV-C STEST0 C_C4 TEST0 D4 OK_U TEST0 JD4 8 24 to VO_OK RD4 Q5 ① JTEST0 D4 SWOVSEL S4 CAP4 OV_SEL OVLO_SEL 9 23 J5 VREG S4 R6_1 JOVSEL Q6 C3 SWSET0 JC3 CELL3 Pkg: HTSSOP-B30 10 C3 J6 VSET0 R8 VSET0 22 R6_2 JSET0 C_C3 OK_M ③ D3 RD3 JD3 ② Q7 SWSET1 11 VSET1 D3 VSET1 21 VSET2 20 S3 Q8 ② JSET1 CAP3 12 SWSET2 S3 VSET2 C2 JC2 CELL2 J8 JSET2 13 OK_D Need the VSS LAND under the SMT LSI. C_C2 D2 RD2 VSS C2 JD2 VSS VSS VSS VSS VSS 14 VREG EN_U ① D2 VSS 19 VSS S2 CAP2 S1 15 Q9 S2 S1 18 D1 17 D1 to ENIN J9 CAP1 C1 ENIN J10 JD1 RD1 CELL1 Q10 C1 16 C_C1 JC1 EN_D ② VSS Figure 2. BD14000EFV-EVK-001 board circuit diagram Parts list No. parts name symbol count[pcs] 1 2 3 4 5 6 7 LSI shant R capasitor capasitor capasitor capasitor pullup R LSI RD1,2,3,4,5,6 CAP1,2,3,4,5,6 C_C1,2,3,4,5,6 CVCC CVREG ROVLO1,2,ROK 1 6 0 1 1 1 3 8 switch SWENIN,OVSEL,SET0,1,2 0 9 switch SWTEST0 0 10 pullup R R6_1,R6_2,R8 0 11 12 13 14 15 16 17 18 19 digital Tr(PNP) digital Tr(NPN) PNP Tr pins pins pins pins pins pins Q1,3,5,9 Q2,4,7,8,10 Q6 VREG,VCC VSS(x5) C1-6,CELL1-6 D1-6,VO_OK,VO_OVLO1-2 VSET0-2, OVLO_SEL,ENIN S1-6,TEST0 OV1-2_U,OV1-2_D,OK_U,OK_D,OD_M, EN_U,EN_D,ENIN JC1-6,JD1-6,JSET0-2,JOVSEL,JTEST0, JENIN,JOK,JOVLO1-2,JVCC J1-6,J8-10 0 0 0 2 5 12 9 12 0 20 pins 21 jumper 22 jumper www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. value Description LSI 24Ω 0.1uF 1uF 1uF 100kΩ EDLC cell balance LSI 1W,200V,F（±1.0%) not installed for EDLC connection 50V,R,±10% 50V,X7R,±10% 16V,X7R,±10% 1/16W,50V,F(±1%) 2 pointed swichs are not installed. 2pole switch If needed, please install them. 2pole switch not installed. TEST0 is connectted to VSS. 1/16W,50V,F(±1%) 100kΩ not installed. Using for LSI stacking. digital Tr(PNP) not installed. Using for LSI stacking. digital Tr(NPN) not installed. Using for LSI stacking. PNP Tr not installed. Using for LSI stacking. red pin. black pin. yellow pin. white pin. sky blue pin. not installed. If needed, please install them. Manufacturer Configuraton Manufacturer Parts Number [mmxmm] BD4000EFV-C ROHM HTSSOP-B30 LTR50 ROHM 5.0x2.5 GCM188R11H104KA42# MURATA 1.6x0.8 GCM21BR71H105KA01# MURATA 2.0x1.25 GCM188R71C105KA49# MURATA 1.6x0.8 MCR01 ROHM 1.0x0.5 ATE1D2M3-10-Z FUJISOKU ATE1D2M3-10-Z FUJISOKU 5.0x9.5 5.0x9.5 MCR01 ROHM 1.0x0.5 DTA115EUA DTC115EUA 2SA1576A - ROHM ROHM ROHM - 2.0x2.1 2.0x2.1 2.0x2.1 1.2φ 1.2φ 1.2φ 1.2φ 1.2φ 1.2φ 0 - not installed. Using for LSI stacking. - - 1.2φ 22 - connected. - - - 0 - not connected. - - - 3/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 Board layout Figure 3. Top layer silkscreen (Top view) Figure 4. Top layer layout (Top view). www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 4/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 Figure 5. Bottom layer silkscreen (Top view). Figure 6. Bottom layer layout (Top view). www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 5/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 About stack of this LSI When using the power storage element for connection of over 8 cells, series connection of this chip is possible. Enable control (ENIN pin control) and various flag output (VO_OVLO1, VO_OVLO2, the VO_OK pin output) are also available in the series connection by using the following application circuit. A：top LSI B：middle LSI C：bottom LSI Figure 7. LSI stack application circuit example www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 6/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 Board connection diagrams in Top and Middle, Bottom layer are showed in the following. Because the parts for the LSI stack are nonimplement, please implement parts depending on a use. ①:DTA115EUAFRA (digital transistor,UMT3) ②:DTC115EUAFRA (digital transistor,UMT3) ③:2SA1576AFRA (PNP transistor,UMT3) (***EUA : standard) (***EUAFRA: for Automotive) VCC JVCC VCC 30 C6 CVCC JC6 CELL6 1 open open OV1_U OV2_U C6 C_C6 VREG D6 RD6 JD6 VREG VO_OVLO1 open JOVLO1 VO_OVLO2 open JOVLO2 VO_OK open 28 CELL5 4 C5 5 D5 C_C5 VO_OVLO2 27 D5 RD5 JD5 ① to VO_OVLO2 VO_OVLO1 VREG Q3 ① to VO_OVLO1 C5 JC5 VREG Q1 ROK CVREG S6 CAP6 ROVLO2No need S6 29 No need D6 3 VREG ROVLO1No need 2 J1 short ② open J2 J3 ② short Q4 open J4 26 VO_OK Q2 VREG JOK S5 CAP5 OV1_D 6 ENIN C4 ENIN open 7 C4 8 D4 9 S4 VREG open STEST0 Q5 ① TEST0 D4 OK_U JTEST0 S4 SWOVSEL CAP4 OV_SEL OVLO_SEL 23 No need 24 to VO_OK TEST0 JD4 short J5 VREG R6_1 JOVSEL SWSET0 J6 VSET0 R8 22 JSET0 C_C3 D3 RD3 JD3 SWSET1 11 D3 12 S3 13 C2 R6_2 ③ VSET1 VSET1 ② Q7 OK_M No need Q8 ② 21 S3 JSET1 CAP3 open No need VSET0 No need C3 No need 10 short Q6 Pkg: HTSSOP-B30 C3 JC3 CELL3 No need VSS JENIN C_C4 RD4 Output to OV2_U pin on bottom layer VSS 25 BD14000EFV-C JC4 CELL4 OV2_D No need Output to OV1_U pin on bottom layer SWENIN S5 SWSET2 open VSET2 No need C2 VSET2 20 JC2 CELL2 J8 JSET2 Output to OK_U pin on bottom layer VSS OK_D C_C2 D2 RD2 JD2 VSS VSS VSS VSS VSS 14 open VREG EN_U ① D2 VSS 19 VSS S2 Connect to CELL6 pin on bottom layer S1 15 Q9 S2 S1 18 D1 to ENIN J9 CAP1 D1 short CAP2 17 C1 ENIN open J10 JD1 RD1 CELL1 Q10 C1 16 C_C1 JC1 EN_D No need Input from EN_U pin on bottom layer ② VSS Figure 8. Top LSI board connection diagram ①:DTA115EUAFRA (digital transistor,UMT3) ②:DTC115EUAFRA (digital transistor,UMT3) ③:2SA1576AFRA (PNP transistor,UMT3) (***EUA : standard) (***EUAFRA: for Automotive) VCC JVCC Connect to VSS pin on upper layer VCC 30 C6 CVCC Input from OV1_D pin on upper layer JC6 CELL6 1 Input from OV2_D pin on upper layer C6 OV1_U C_C6 OV2_U VREG D6 RD6 JD6 29 S6 VO_OVLO1 28 JC5 CELL5 4 C5 C_C5 VO_OVLO2 27 D5 RD5 JD5 5 D5 6 S5 VO_OVLO1 open JOVLO1 VO_OVLO2 open JOVLO2 VO_OK open VREG Q1 Q3 ① ① to VO_OVLO2 3 C5 to VO_OVLO1 S6 CAP6 VREG ROK CVREG ROVLO2No need VREG No need VREG D6 ROVLO1No need 2 J1 short ② short J2 J3 ② short Q4 short J4 26 VO_OK Q2 VREG JOK S5 CAP5 OV1_D C4 ENIN open 7 VREG C4 STEST0 Input from OK_D pin on upper layer Q5 ① TEST0 D4 OK_U 24 to VO_OK TEST0 JD4 JTEST0 8 D4 SWOVSEL S4 CAP4 OV_SEL 23 S4 short 100kΩ J5 VREG open OVLO_SEL 9 JOVSEL Pkg: HTSSOP-B30 C3 R6_1 Q6 SWSET0 JC3 CELL3 VSS JENIN C_C4 RD4 OV2_D Output to OV2_U pin on bottom layer VSS 25 BD14000EFV-C JC4 CELL4 Output to OV1_U pin on bottom layer SWENIN ENIN J6 VSET0 R8 100kΩ C3 VSET0 22 R6_2 JSET0 C_C3 ③ D3 RD3 JD3 ② Q7 SWSET1 11 D3 12 S3 13 C2 VSET1 VSET1 Q8 ② JSET1 SWSET2 VSET2 C2 VSET2 open 20 JC2 CELL2 J8 JSET2 Output to OK_U pin on bottom layer VSS OK_D Output to EN_D pin on upper layer C_C2 D2 JD2 VSS 14 VREG EN_U ① VSS 19 VSS S2 S1 15 Connect to CELL6 pin on bottom layer Q9 S2 S1 18 D1 17 D1 C1 to ENIN J9 CAP1 ENIN J10 short CAP2 VSS VSS VSS VSS D2 short RD2 OK_M No need 21 S3 CAP3 open No need 10 JD1 RD1 CELL1 Q10 C1 16 C_C1 JC1 EN_D Input from EN_U pin on bottom layer ② VSS Figure 9. Middle LSI board connection diagram www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 7/8 2014.10.20 Rev.001 BD14000EFV-EVK-001 ①:DTA115EUAFRA (digital transistor,UMT3) ②:DTC115EUAFRA (digital transistor,UMT3) ③:2SA1576AFRA (PNP transistor,UMT3) (***EUA : standard) (***EUAFRA: for Automotive) VCC JVCC Connect to VSS pin on upper layer VCC 30 C6 CVCC Input from OV1_D pin on upper layer JC6 CELL6 1 Input from OV2_D pin on upper layer C6 OV1_U C_C6 OV2_U VREG D6 RD6 JD6 29 C5 VO_OVLO1 28 JC5 CELL5 4 C5 C_C5 VO_OVLO2 27 D5 RD5 JD5 5 D5 ★monitor VO_OVLO1 short ★monitor JOVLO1 VO_OVLO2 short JOVLO2 VO_OK open Q1 No need VREG Q3 No need ① ① to VO_OVLO2 S6 to VO_OVLO1 3 VREG ROK CVREG S6 CAP6 ROVLO2No need VREG 100kΩ VREG D6 ROVLO1100kΩ 2 J1 short ② short J2 J3 ② short Q4 short J4 26 VO_OK 6 S5 C4 ENIN 7 VSS JENIN VREG STEST0 Q5 ① Input from OK_D pin on upper layer TEST0 D4 OK_U 24 to VO_OK TEST0 JD4 JTEST0 8 D4 SWOVSEL S4 CAP4 OV_SEL 23 S4 short 100kΩ J5 VREG open OVLO_SEL 9 JOVSEL Pkg: HTSSOP-B30 C3 R6_1 Q6 SWSET0 JC3 CELL3 open OV2_D VSS C4 C_C4 RD4 open OV1_D SWENIN 25 BD14000EFV-C JC4 CELL4 Q2 VREG JOK ★enable control ENIN short S5 CAP5 100kΩ J6 VSET0 R8 ★monitor OK_M 100kΩ 10 C3 VSET0 22 R6_2 JSET0 C_C3 ③ D3 RD3 JD3 ② Q7 SWSET1 11 D3 12 S3 VSET1 VSET1 Q8 ② 21 S3 JSET1 CAP3 SWSET2 short VSET2 C2 VSET2 20 JC2 CELL2 J8 JSET2 open 13 OK_D D2 RD2 JD2 VSS 14 D2 15 S2 VSS VSS C2 Output to EN_D pin on upper layer C_C2 VSS VSS VSS VSS VREG EN_U ① No need VSS 19 VSS S2 CAP2 S1 Q9 18 D1 17 C1 ENIN J10 short CAP1 D1 to ENIN J9 open S1 JD1 RD1 CELL1 Q10 C1 16 C_C1 JC1 EN_D ② open VSS Figure 10. Bottom LSI board connection diagram About a 4-6 cell application circuit When using the power storage element with 4 cells and 5cells, please connect all the unused pins to the Cn pin where n is the number of actual cells in series. This chip can respond to 4 to 6 cells, but cannot respond to 3cells or fewer than 3 cells. 6 cell 5 cell (shunt an unused pin on C5 pin) 4 cell (shunt an unused pin on C4 pin) Figure 11. 4-6 cell application circuit example www.rohm.co.jp © 2014 ROHM Co., Ltd. All rights reserved. 8/8 2014.10.20 Rev.001