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Data eet
Datasheet
Po
ower Mana
agement IC for Auto
omotive M
Microcontrroller
Buck-B
B
Boost Switch
S
hing R
Regula
ator + LDO +
Step-do
S
own Switch
S
ing Re
egulattor + Reset
R
+
Watch
W
Dog Timer
T
BD39001EK
B
KV-C
Ge
eneral Descrription
Key
y Specificatio
ons
BD39001EKV-C is a power management IC w
with
oller (DC / DC
C1),
buck-boostt switching regulator contro
secondary step-down sw
witching regulator (DC / DC
C2),
LDO, reset and WDT.
The BD390
001EKV-C inccludes protection circuits, ssuch
as Under vo
oltage, Over voltage,
v
Over current and TS
SD.
■
■
■
Fe
eatures
Automa
atically controlled buck-boos
st switching
regulato
or with 40 V ra
ated VCC, DC / DC2 and LD O
input
3.3 V fixxed output seccondary step-down switchin
ng
regulato
or with built-in FET
5 V fixe
ed output seco
ondary LDO
Configu
urable Sequen
nce control
Over Current protectiion
DC / DC
C1: Adjustable
e voltage with external resisstors
DC / DC
C2: Integrated
d
LDO: In
ntegrated
Over vo
oltage / Underr voltage detec
ction
Reset fo
or LDO, DC / DC2 and WDT
T
Window
w Watchdog Timer
HTQFP
P48V package
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Input voltage
e range
4.0 V to 30 V
(Sttartup voltagee needs to be
e above 4.5V
V.)
Output voltage
DC1 FB Voltage
0.8 V
Buck--Boost DC / D
Secon
ndary DC / DC
C2
3.3 V
Secon
ndary LDO
5.0 V
Reference voltage accuraacy
Buck--Boost DC / D
DC1 FB Voltage
±2 %
Secon
ndary DC / DC
C2
±2 %
Secon
ndary LDO
±2 %
Oscillation frrequency
200
2 to 550 kH
Hz
Max output current
c
Secon
ndary Buck DC
C / DC2
900 mA
A
Secon
ndary LDO
600 mA
A
Stand-by Cu
urrent
0 μA (Typ
p)
Operating te
emperature rannge
-4
40 °C to 125 °C
C
AEC-Q100 Qualified
Q
Package
HTQFP48V
W (Typ) × D (T
Typ) × H (Maxx)
9.000 mm × 9.00 mm × 1.00 mm
m
Ap
pplications
Microco
ontroller for Au
utomotive
■
cation Circuit
Typical Applic
Simplified Circcuit1
Simplified Circuit2
VCC
EN1
CL
VREG
VO1
OUTH
RT
VL
SS1
VDD
FB1
OUTL
COMP1
VO2
PGND1
SS2
VS2
FB2
SW2
COMP2
VO1
VO1
VO2
PGND2
EN2
VO3
VS3
CT
VO3
EN3
SEQ2
RST2#
SEQ3
RST3#
ENWD
RSTWD#
PG1
CLK
PG2
RTW
SEL_UVLO
GND
PG3
Buck-Boost Switching
S
Reg
gulator
+ Secondarry Switching Regulator
R
+ Secondarry LDO
Product structure
e: Silicon mono
olithic integrated circuit
○P
ww
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© 2014
2
ROHM Co
o., Ltd. All rights reserved.
TSZ
Z22111・14・0
001
Buck Switching R
Regulator
+ Secondary
S
Sw
witching Regulator
+ Secondary
S
LD O
○Thiss product is not designed for pro
otection againstt radioactive ray
ys
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TSZ002201-0T3T0
0AM00120-1
1-2
Apr.7.2014 Rev.00
01
Datasheet
BD39001EKV-C
Pin Configuration
25 EN1
26 T4
27 VREG
28 SS1
29 COMP1
30 FB1
31 RT
32 GND
33 RST2#
34 RST3#
35 RSTWD#
36 CT
(TOP VIEW)
COMP2
12
13
SS2
SEL_UVLO 48
11
FB2
10
14
PGND2
VDD
T3 47
PGND2
OUTL
15
9
16
PG1 46
NC
PG2 45
8
PGND1
7
17
SW2
NC
PG3 44
SW2
VL
18
6
19
SEQ2 43
NC
SEQ3 42
5
NC
4
20
VS2
OUTH
EN2 41
VS2
NC
21
3
22
EN3 40
VS3
ENWD 39
2
CL
1
VCC
23
NC
24
CLK 38
VO3
RTW 37
Pin Description
Pin No.
Symbol
Function
Pin No.
1
2
VO3
5 V Output
25
N.C.
Not connected
26
3
VS3
Supply Voltage Input for LDO
27
4
VS2
Supply Voltage Input for DC / DC2
5
VS2
Supply Voltage Input for DC / DC2
Symbol
Function
EN1
Output ON / OFF
T4
(Note 1)
Test pin
VREG
Internal power supply
28
SS1
Soft start time setting for DC / DC1
29
COMP1
Error-amp output for DC / DC1
6
N.C.
Not connected
30
FB1
Feedback for DC / DC1
7
SW2
DC / DC2 SW pin
31
RT
Frequency setting
8
32
GND
Ground
SW2
DC / DC2 SW pin
9
N.C.
Not connected
33
RST2#
Reset Output for DC / DC2
10
PGND2
Power Ground
34
RST3#
Reset Output for LDO
11
PGND2
Power Ground
35
RSTWD#
Reset Output for WDT
12
SS2
Soft start time setting for DC / DC2
36
CT
Reset Delay
13
COMP2
Error-amp output for DC / DC2
37
RTW
Frequency setting for WDT
14
FB2
Feedback for DC / DC2
38
CLK
Clock input
15
VDD
N-channel MOSFET drive supply
39
ENWD
WDT ON / OFF
16
OUTL
N-channel MOSFET drive
40
EN3
Output ON / OFF for LDO
17
PGND1
Power Ground
41
EN2
Output ON / OFF for DC / DC2
18
N.C.
Not connected
42
SEQ3
Sequence setting for LDO
19
VL
Pch FET gate clamp for DC / DC1
43
SEQ2
Sequence setting for DC / DC2
20
N.C.
Not connected
44
PG3
Power good output for LDO
21
OUTH
N-channel MOSFET drive
45
PG2
Power good output for DC / DC2
22
N.C.
Not connected
Overcurrent detection setting
for DC / DC1
Supply Voltage Input
46
PG1
Power good output for DC / DC1
23
24
(Note 1)
CL
VCC
47
48
T3
(Note 1)
SEL_UVLO
Test pin
Select Pin for VCC UVLO
Short with GND
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TSZ22111・15・001
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TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Block Diagram
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TSZ22111・15・001
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TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
Limits
Unit
VCC Voltage
(Note 1)
VCC
40
V
VS2 Voltage
(Note 1)
VS2
40
V
VS3 Voltage
(Note 1)
VS3
40
V
CL Voltage
VCL
VCC
V
EN1 Voltage
VEN1
VCC
V
VREG Voltage
VREG
7
V
VDD Voltage
VDD
7
V
VSS1, VSS2
VREG
V
RST2#, RST3#, RSTWD#
VRST2#, VRST3#, VRSTWD#
7
V
CLK, RTW, CT, ENWD
VCLK, VRTW, VCT, VENWD
7
V
VPG1, VPG2, VPG3
7
V
VEN2, VEN3
VREG
V
VSEQ2, VSEQ3
7
V
Pd
5.0
W
Tstg
-55 to +150
°C
Tjmax
150
°C
SS1, SS2 Voltage
PG1, PG2, PG3
EN2, EN3
SEQ2, SEQ3
Power Dissipation
(Note 2)
Storage Temperature Range
Junction Temperature
(Note 1) Pd should not be exceeded.
(Note 2) If mounted on a standard ROHM 4 layer PCB (copper foil area: 70 mm × 70 mm) (Standard ROHM PCB size: 70mm × 70 mm ×1.6mm)
Reduce by 9.6 mW / °C (Ta ≥ 25 °C)
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open
circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the
IC is operated over the absolute maximum ratings.
Recommended Operating Rating
Maximum ratings
Parameter
Symbol
Unit
Min
Max
VCC (Buck Boost mode)
4 (Note 1)
30
V
VCC (Buck mode)
6
30
V
VS2
5
10
V
VS3
5
10
V
FOSC
200
550
kHz
WDT Oscillation Frequency
FOSCW
50
250
kHz
OUTH Current Ability
IOUTH
-
1.5
A
OUTL Current Ability
IOUTL
-
1.5
A
SW2 Current Ability
ISW2
-
900 (Note 2)
mA
VO3 Current Ability
IVO3
-
600 (Note 2)
mA
Operating Temperature Range
Topr
-40
+125
°C
Voltage Power Supply
Oscillation Frequency
(Note 1) Initial startup is over 4.5 V
(Note 2) Pd should not be exceeded.
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TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Electrical Characteristic
(Unless otherwise specified: -40 °C ≤ Ta ≤ +125 °C, 4 V ≤ VCC ≤ 30 V, 5 V ≤ VS2 ≤ 10 V, 5 V ≤ VS3 ≤ 10 V)
Limits
Parameter
Symbol
Unit
Min
Typ
Max
Condition
All
Standby Current 1
IST1
-
0
10
μA
Ta = 25 °C
Standby Current 2
IST2
-
-
30
μA
Ta = 125 °C
Circuit Current
IVCC
5
8
12
mA
RT = 33 kΩ, FB1 = 1.0 V
Oscillation Frequency
FOSC
315
350
385
kHz
RT = 33 kΩ
VREG Output Voltage
VREG
3.0
3.5
4.0
V
VDD Output Voltage
VDD
4.5
5
5.5
V
VCC = 12 V
UVLO_VCC Detection Voltage 1
VUVLOVCC1
3.30
3.60
3.90
V
SEL_UVLO = OPEN
UVLO Hysteresis Voltage 1
VUVVCCHYS1
200
400
600
mV
SEL_UVLO = OPEN
UVLO_VCC Detection Voltage 2
VUVLOVCC2
5.27
5.58
5.89
V
SEL_UVLO = GND
UVLO_VCC Release Voltage 2
VUVVCCRE2
5.35
5.67
6.0
V
SEL_UVLO = GND
UVLO Hysteresis Voltage 2
VUVVCCHYS2
50
75
-
mV
SEL_UVLO = GND
EN1 L Threshold
VEN1L
-
-
0.5
V
EN1 H Threshold
VEN1H
2.5
-
-
V
EN1 Input Resistance
REN1
180
375
570
kΩ
SEL_UVLO Threshold
VSEL_UVLO
-
VREG / 2
-
V
SEL_UVLO Output Current
ISEL_UVLO
5
14
23
μA
SEL_UVLO = 0 V
VREF08
0.784
0.800
0.816
V
FB1 = COMP1
FB1 Input Bias Current
IFB1
-1
0
+1
μA
FB1 = 0.8 V
Soft Start Quick Charge Current
ISS0
55
110
165
μA
Soft Start Charge Current
ISS1
5
10
15
μA
Soft Start selected Voltage
VSS0
0.3
0.7
1.5
V
-
V
DC / DC1
VCC = 5 V
(Buck - Boost DC / DC Controller)
FB1 Voltage
Soft Start End Voltage 1
VSS1
-
VSS0+
VREF08
Soft Start Cramp Voltage
VSSCL1
2.2
2.8
3.3
V
SS1 = open
VL
8
10
12
V
VCC ≥ 12 V VCC - VL
Hi - Side OUTH ON - Resistance
RONHH
-
1.7
-
Ω
VCC = 12 V OUTH - VCC
Lo - Side OUTH ON - Resistance1
RONHL1
-
3
-
Ω
VCC = 12 V OUTH - VL
Lo - Side OUTH ON - Resistance2
RONHL2
-
-
30
Ω
VCC = 4 V OUTH - PGND
Hi - Side OUTL ON - Resistance
RONLH
-
18
-
Ω
VCC = 12 V
Lo - Side OUTL ON - Resistance
RONLL
-
22
-
Ω
VCC = 12 V
Over current detection CL voltage (Low)
VCL_L
86
100
114
mV
VCC - CL Voltage, VCC = 12 V
Over current detection CL voltage (High)
VCL_H
172
200
228
mV
VCC - CL Voltage, VCC = 12 V
TON
-
92
-
%
VCC - VL Voltage
Maximum ON Duty (OUTL)
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TSZ22111・15・001
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FOSC = 600 kHz
TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Electrical Characteristic - Continued
Limits
Parameter
Symbol
Unit
Condition
Min
Typ
Max
VO2
3.23
3.30
3.37
V
Under voltage detection voltage
VRST2
3.00
3.07
3.14
V
Under voltage hysteresis voltage
VRSTH2
20
-
80
mV
Soft Start Charge Current
ISS2
5
10
15
μA
Soft Start end voltage 2
VSS2
0.6
0.8
1.0
V
SW2 ON - Resistance H
RONH2
-
0.3
0.6
Ω
SW2 ON - Resistance L
RONL2
-
0.3
0.6
Ω
EN2 Threshold Voltage
VEN2
0.6
0.8
1.0
V
EN2 Charge Current
IEN2
4
8
12
μA
UVLO_VS2 Detection Voltage
VUVLOVS2
3.5
3.9
4.3
V
UVLO_VS2 Hysteresis Voltage
VUVVS2HYS
0.2
0.35
0.5
V
VO3
4.90
5.00
5.10
V
6.0 V ≤ VS3 ≤ 10 V,
5 mA ≤ IVO3 ≤ 600 mA
Drop Voltage
ΔVO3
-
-
0.6
V
VS3 = 4.65 V, IVO3 = 600 mA
Under voltage detection voltage
VRST3
4.50
4.625
4.75
V
Under voltage hysteresis voltage
VRSTH3
30
-
150
mV
VCC UVLO - LDO LVD
difference voltage
ΔVLVD3
0.7
0.9
1.5
V
EN3 Threshold Voltage
VEN3
0.6
0.8
1.0
V
EN3 Charge Current
IEN3
4
8
12
μA
UVLO_VS3 Detection Voltage
VUVLOVS3
3.5
3.9
4.3
V
UVLO_VS3 Hysteresis Voltage
VUVVS3HYS
0.2
0.35
0.5
V
VOVVS
12.5
14
15.5
V
DC / DC2
(Secondary DC / DC)
Output Voltage 2
LDO
SS2 = 0.2 V
EN2 = 0.2 V
(5.0 V Output LDO)
Output Voltage 3
VS3 Over voltage detection voltage
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VULOVVCC2 - VRST3
EN3 = 0.2 V
TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Electrical Characteristic - Continued
Parameter
Symbol
Limits
Min
Typ
Max
Unit
Condition
RST2#, RST3#, RSTWD#
CT = 0.47 μF
Reset Delay Time
tRST
30
56
160
ms
Reset L Voltage 1
VRSTL1
-
-
0.25
V
VO3 = 1.0 V, IRST = 100 μA
Reset L Voltage 2
VRSTL2
-
-
0.4
V
IRST = 1 mA
tPHL
-
-
5
µs
RST# pull up resistance 4.7 kΩ
kHz
Reset Response Time
WDT Oscillation Frequency
FOSCW
75
100
125
512
FOSCW
6655
FOSCW
128
FOSCW
517
FOSCW
6675
FOSCW
133
FOSCW
0.8
V
WDT Reset Time
tWRES
507
FOSCW
6635
FOSCW
123
FOSCW
CLK L Threshold
VCLKL
-
-
CLK FAST NG Threshold
tWF
CLK SLOW NG Threshold
tWS
CLK H Threshold
RTW = 51 kΩ
s
s
s
VCLKH
2.0
-
-
V
ENWD L Threshold
VENWDL
-
-
0.8
V
ENWD H Threshold
VENWDH
2.0
-
-
V
RSTWD ON Resistance
RRSTWD
50
100
200
Ω
IRSTWD = 100 μA
PG1, PG2, PG3
0.5
1.0
2.0
kΩ
PG1 Under Voltage Detection voltage
RPG1
RPG2
RPG3
VLVPG1
0.62
0.67
0.72
V
FB1 Voltage
PG1 Under Voltage Hysteresis
VLVPH1
20
-
100
mV
FB1 Voltage
PG1 Over Voltage Detection Voltage
VOVPG1
0.88
0.94
1.00
V
FB1 Voltage
PG1 Over Voltage Hysteresis
VOVPH1
20
-
100
mV
FB1 Voltage
PG2 Under Voltage Detection Voltage
VLVPG2
3.00
3.07
3.14
V
FB2 Voltage
PG2 Under Voltage Hysteresis
VLVPH2
20
-
80
mV
FB2 Voltage
PG2 Over Voltage Detection Voltage
VOVPG2
3.45
3.53
3.60
V
FB2 Voltage
PG2 Over Voltage Hysteresis
VOVPH2
20
-
80
mV
FB2 Voltage
PG3 Under Voltage Detection Voltage
VLVPG3
4.50
4.625
4.75
V
VO3 Voltage
PG3 Under Voltage Hysteresis
VLVPH3
30
-
150
mV
VO3 Voltage
PG3 Over Voltage Detection Voltage
VOVPG3
5.25
5.38
5.50
V
VO3 Voltage
PG3 Over Voltage Hysteresis
VOVPH3
30
-
150
mV
VO3 Voltage
SEQ2 ON Resistance
RSEQ2
0.5
1.0
2.0
kΩ
ISEQ2 = 100 μA
SEQ3 ON Resistance
RSEQ3
0.5
1.0
2.0
kΩ
ISEQ3 = 100 μA
PG ON - Resistance
SEQ 2, SEQ 3
Reset response time (tPHL)
UVLO, RST# Delay time
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FB2, RST2# Delay time
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VO3, RST3# Delay time
TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Typical Performance Curves
10
12.00
11.00
Circuit Current: ICC [mA]
Stundby Current: Istb [μA]
8
6
4
10.00
9.00
8.00
7.00
2
6.00
0
5.00
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 1. Standby Current vs. Temperature
Figure 2. Circuit Current vs. Temperature
3.37
0.810
3.35
Output Voltage2: VO2 [V]
0.805
FB1 Voltage 1: VREF08 [V]
-10
20
50
80
110
Ambient Temperature: Ta [°C]
0.800
0.795
0.790
0.785
3.33
3.31
3.29
3.27
3.25
3.23
0.780
-40
-40
-10
20
50
80
110
Ambient Temperature: Ta [°C]
Figure 3. FB1 Voltage vs. Temperature
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TSZ22111・15・001
-10
20
50
80
110
Ambient Temperature: Ta [°C]
Figure 4. Output Voltage2 vs. Temperature
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Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Typical Performance Curves - Continued
5.1
385
5.1
Frequency: FOSC [kHz]
Output Voltage3: VO3 [V]
375
5.0
5.0
365
355
345
335
325
4.9
315
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 5. Output Voltage3 vs. Temperature
110
Figure 6. Frequency vs. Temperature
2.5
125
115
EN1 Threshold: EN1 [V]
WDT Frequency: FOSCW [kHz]
-10
20
50
80
Ambient Temperature: Ta [°C]
105
95
2.0
1.5
1.0
85
0.5
75
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
-40
110
Figure 7. WDT Frequency vs. Temperature
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TSZ22111・15・001
-10
20
50
80
Ambient Temperature: Ta [°C]
110
Figure 8. EN1 Threshold vs. Temperature
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TSZ02201-0T3T0AM00120-1-2
Apr.7.2014 Rev.001
Datasheet
BD39001EKV-C
Typical Performance Curves - Continued
VCC UVLO Threshold Voltage2: VUVLOVCC2 [V]
VCC UVLO Threshold Voltage1: VUVLOVCC1 [V]
3.9
3.8
3.7
3.6
3.5
3.4
5.77
5.72
5.67
5.62
5.57
5.52
5.47
5.42
5.37
3.3
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
-40
110
Figure 9. VCC UVLO Threshold Voltage1
vs. Temperature
Figure 10. VCC UVLO Threshold Voltage2
vs. Temperature
3.14
4.8
3.12
Under Voltage Detection3: VRST3 [V]
Under Voltage Detection2: VRST2 [V]
-10
20
50
80
110
Ambient Temperature: Ta [°C]
3.1
3.08
3.06
3.04
3.02
3
4.7
4.7
4.6
4.6
4.5
-40
-10
20
50
80
110
Ambient Temperature: Ta [°C]
-40
Figure 11. Under Voltage Detection2
vs. Temperature
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TSZ22111・15・001
-10
20
50
80
Ambient Temperature: Ta [°C]
110
Figure 12. Under Voltage Detection3
vs. Temperature
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BD39001EKV-C
Typical Performance Curves - Continued
4.5
OUTH Low RON1 RONHL1 [ohm]
OUTH High RON RONHH [ohm]
2.5
2.0
1.5
1.0
4
3.5
3
2.5
2
0.5
1.5
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
23
22.0
22
21.0
21
20
19
110
Figure 14. OUTH Low RON1 vs. Temperature
OUTL Low RON: RONLL [ohm]
OUTL High RON: VONLH [ohm]
Figure 13. OUTH High RON vs. Temperature
-10
20
50
80
Ambient Temperature: Ta [°C]
18
20.0
19.0
18.0
17.0
17
16.0
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 15. OUTL High RON vs. Temperature
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20
50
80
110
Ambient Temperature: Ta [°C]
Figure 16. OUTL Low RON vs. Temperature
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0.6
0.6
0.5
0.5
SW2 Low RON: RONL2 [ohm]
SW2 High RON: RONH2 [ohm]
Typical Performance Curves - Continued
0.4
0.3
0.2
0.4
0.3
0.2
0.1
0.1
-40
-10
20
50
80
Ambient Temperature: Ta [°C]
110
-40
Figure 17. SW2 High RON vs. Temperature
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20
50
80
Ambient Temperature: Ta [°C]
110
Figure 18. SW2 Low RON vs. Temperature
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BD39001EKV-C
Description of Blocks
■
Under Voltage Lockout circuit (VCC_UVLO)
This is a Low Voltage Error Prevention Circuit.
In case of SEL_UVLO = OPEN, if the VCC drops below 3.6 V (Typ), the VCC_UVsLO is activated and the output circuit
shuts down. In case of SEL_UVLO = GND, if the VCC drops below 5.58 V (Typ), the VCC_UVLO is activated and the
output circuit shuts down.
■
Thermal Shut Down (TSD)
The TSD protects the device from overheating.
If the chip temperature (Tj) reaches 175 °C (Typ), the circuit shuts down
„
Over Voltage Detection (OVD)
If DC / DC1, DC / DC2 and LDO output voltage exceed OVD, each PGOOD Pin turns Low.
DC / DC1 OVD monitors FB1 voltage, DC / DC2 OVD monitors FB2 voltage and LDO OVD monitors VO3 voltage.
PGOOD pin is an open drain output. And the pull up resistor should be connected to PGOOD for using this function.
„
Low Voltage Detection (LVD)
If DC / DC1, DC / DC2 and LDO output voltage below LVD, each PGOOD Pin turns Low.
DC / DC1 LVD monitors FB1 voltage, DC / DC2 LVD monitors FB2 voltage and LDO LVD monitors VO3 voltage.
PGOOD pin is an open drain output, and the pull up resistor should be connected to PGOOD for using this function.
■
Under Voltage Lockout (VS_UVLO)
VS_UVLO prevents Error function at low VS voltage.
If the VS2 or VS3 drops below 3.9 V (Typ), the VS_UVLO is activated and the DC / DC2 or LDO is turned off.
■
Over Current Protection (OCP1_L, OCP1_H)
DC / DC1 has two levels over current protection with different control system as shown below.
1) OCP1 low level operations
In case the voltage between VCC and CL exceeds 100 mV (Typ), OCP1 (low level operation) is activated and the
switching pulse width of OUTH and the switching pulse width of OUTL are limited. Also, if this pulse limited status
continues during 256 clock times where the FB1 pin voltage drops below the under voltage detection level, the soft
start pin capacitor is discharged and the output is turned OFF during 8192 clock times.
During the 8192 clock in which the output is turned OFF, the logic of OUTH and OUTL pin changes as follows;
OUTH = H and OUTL = H. After the 8192 clock the chip returns to normal operations and the soft start pin is
recharged.
2) OCP1 high level operations
In case the inter VCC - CL pin voltage exceeds 200 mV (Typ), the chip goes into OCP1 high level operations, the
soft start pin capacitor is discharged and the output is turned OFF for 8192 clk. During the 8192 clock in which the
output is turned OFF, the logic of OUTH and OUTL pin changes as follows; OUTH = H and OUTL = H. After the
8192 clock the chip returns to normal operations and the soft start pin is recharged.
OCP LOW level operation
CL
OVP
UVP
OCP H level operation
OCP LOW level operation
FB1
VO1
ISW
PG1
SS1
Discharge SS
256clk
Discharge SS
8192clk
8192clk
OUTH
OUTL
OUTH=H,OUTL=H
fix to logic
Normal operation
Output pulse is limited
OUTH=H,OUTL=H
fix to logic
Normal operation
Figure 19. Timing chart for DC / DC1 protection
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・DC / DC2
If output current of SW2 exceeds OCP, SW2 ON duty is limited and the output voltage is lowered.
If FB2 voltage is below SCP and after 256 clk (Typ), DC / DC2 is turned off. After 256 clk (Typ), DC / DC2 returns to
normal operation.
Figure 20. DC / DC2 Over current protection
・If the output current of LDO exceed OCP, the output current is limited and the output voltage is lowered.
■
Over Voltage Protection (VS3 OVP)
・In case the VS3 voltage exceeds 14 V (Typ), the chip goes into VS3 OVP, the SS1 capacitor is discharged and the
output is turned OFF for 8192 clock. During the 8192 clock in which the output is turned OFF, the logic of OUTH and
OUTL changes as follows; OUTH = H and OUTL = H. After the 8192 clock the chip returns to normal operations and
the SS1 is recharged.
VCC
14V
VO1 x
VS3
(=VO1)
0.94
V
0.8
8192clk
VO1 x
0.67
V
0.8
PG1
SS1
Discharge SS
OUTH
OUTL
OUTH=H,OUTL=H
fix to logic
Normal operation
HSW
EN2
EN3
All numerical values are Typical.
Figure 21. VS3 Over voltage protection
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RST#, RSTWD# pin
In case of ENWD = L, RSTWD# voltage is pull up voltage.
In case of ENWD = H, WDT operation starts. If WDT is in abnormal condition, RSTWD# outputs ‘L’.
If VO2 or VO3 voltage is below the LVD, reset voltage (RST#) output is low.
If both of VO2 and VO3 exceed the reset release voltage, CT is charged. After tPOR, reset voltage outputs high.
VO2 abnormal
detection
RST2#
VS2 UVLO
EN2
VO3 abnormal
detection
RST3#
VS3 UVLO
EN3
VCC UVLO
TSD
RSTWD#
WDT abnormal
detection
ENWD
Figure 22. RST#, RSTWD# Logic Circuit
Figure 23. RST2#, RST3# Timing Chart
Figure 24. Timing chart (detection of LVD between reset)
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„
Oscillator for Watch Dog Timer (FOSCW)
This block creates a reference frequency of the Watch Dog Timer. The oscillation frequency is determined by the RTW
resistance. The oscillation frequency can be set in the range of 50 kHz to 250 kHz.
„
WATCH DOG TIMER
Microcontroller (μC) operation is monitored with CLK pin. Window watch dog timer is included to enhance the
assurance of the system. WDT starts operating when ENWD becomes high. CLK pin voltage must be Low when
ENWD switches to High.
WDT monitors both edges of CLK pin (rising edge and falling edge). If width of both edges are shorter than Fast NG or
longer than Slow NG, RSTWD turns low for a WDT reset time (tWRES). Since the width of Fast NG and Slow NG depends
on a number of FOSCW, Fast NG and Slow NG are variable by frequency of FOSCW. If FOSCW is unusual (ex. RTW is short
to ground), RSTWD turns low. In case of using RSTWD, pull-up resister is needed because RSTWD is an open drain.
POR=Low or ENWD=Low
OSC_WDT Error detection
WDT_CLK Error
detection release
Standby
MODE
OSC_WDT ERR
Detect
“RSTWD=Low”
er OS
ro C_
rd W
et D
ec T
tio
n
“RSTWD=High”
or
o w ow
=L L
R D=
PO NW
E
Nomal
MODE
“RSTWD=High”
Fast NG or Slow NG detection
RSTWD Low range > tWRES
μC Error not detect
(Fast NG, Slow NG not detect)
μC ERR
Detect
“RSTWD=Low”
RSTWD Low range < tWRES
Figure 25. Witch Dog Timer State Change Diagram (WDT FSM)
(2)
WDT_FSM
Stop
Standby (1)
Normal (2)
(3)
(2)
(3)
(2)
(1)
(2)
(4)
(3)
(2)
(1)
UVLO
VCC
VREG
VO3
(5)
(5)
ENWD
Slow NG
ｔWRES
ｔWRES
ｔWRES
In case of pull up to 5V LDO
RSTWD#
Fast NG
Fast NG
CLK
WDT_CLK
(1): Standby Mode, (2): Normal Mode, (3): Microcontroller Error Detect, (4): OSC_WDT Error Detect (See Figure 25 WDT FSM)
(5): When ENWD is changed Low to High, it is necessary that CLK is Low.
Figure 26. WDT Timing Chart
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External Components Selection
VO1
RFB1B
RFB1C
CFB1
RFB1A
FB1
VCC
CCO1A
CCO1B
RCLA
CL
COMP1
RCO1
CVCCA
CCL
RCLB
CVCCB
CVL
VL
PGND2
OUTH
L1
SW1
CVO1
OUTL
COMP2
VO1
RCO2
CCO2
VS2
CVS2
VDD
CVDD
SW2
L2
CVO2
PGND1
VO2
Figure 27. Application Example 1
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(1)
Buck mode (VCC>>VO1)
In case the input voltage is high compared to the output voltage, the
chip will go into buck mode, resulting OUTH to repeatedly switch
between H and L and that the OUTL will go to L (= OFF).
This operation is the same as that of standard step-down switching
regulators.
Shown below are the OUTH and OUTL waveforms on the right.
ON duty of PMOS (Dpon), VCC and VO1 are shown in the following
equation.
VCC
(eq. 1)
Figure 28
(2) Buck-Boost mode (VCC ≈ VO1)
In case the input voltage is close to the output voltage, the chip will go into buck-boost mode, resulting both the OUTH
and OUTL to repeatedly switch between H and L. Concerning the OUTH, OUTL timing, the chip internally controls
where the following sequence is upheld; when OUTH: H Æ L, OUTL: H Æ L.
Shown below are the OUTH and OUTL waveforms.
①
②
VCC > VO1
VCC < VO1
Figure 29
Figure 30
*The timing excludes the SW delay
The relationship between ON duty of PMOS (Dpon), ON duty of NMOS (Dnon), VCC and VO1 is shown in the following
equation.
(
(eq. 2)
)
The calculation formula of Dpon and Dnon are shown in Page 17.
(3) Boost mode (VCC << VO1)
In case the input voltage is low compared to the output voltage, the chip will
go into boost mode, resulting OUTH to go to L (= ON) and OUTL will
repeatedly switch between H and L. This operation is the same as that of
standard step-up switching regulators.
Max duty of OUTL is limited by internal circuit.
ON duty of NMOS (Dnon), VCC and VO1 are shown in the following
equation.
(1
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BD39001EKV-C
(4) Voltage for Mode Switching and Duty Control
In the event of mode switching from Boost to Buck-Boost or vice versa, mode switching input voltage is dependent on output
voltage, the gain of inverting amplifier and the cross duty. The general description is shown below.
The duty of OUTH is controlled by output of error amp (COMP1) and SLOPE voltage.
Also, OUTL duty is controlled by the output voltage of the inverting amplifier in chip (BOOSTCOMP) and SLOPE voltage.
In case VCC = VO1, COMP1 voltage becomes equal to BOOSTCOMP voltage, and switching control timing of OUTH and
OUTL becomes identical accordingly.
VCC = Vo1
(Typ)
COMP1
100%
Cross duty
85 %(Typ)
SLOPE
0%
BOOSTCOMP
Buck
Boost
Buck-Boost
Figure 32. Buck-Boost operation controlled by COMP1, BOOSTCOMP and SLOPE voltage
ON duty of PMOS in this condition is called the cross duty (Dx = 0.85, Typ). Dpon and Dnon can be calculated by the following
equation, assuming the gain of the inverting amplifier as A (1.5, Typ).
1
(
1.5
)
1.125
(Note 1)
(eq. 4)
From eq.3, eq.4 and Dpon = 1, the input voltage at transition between buck - boost and boost mode is calculated as follows;
(1
)
0.625
(Note 1)
(eq. 5)
Also, from eq.1, eq.4 and Dnon = 0, the input voltage at transition between buck - boost and buck mode is calculated as
follows;
(
)
1.333
(Note 1)
88
87
(Note 1) A = 1.5 (Typ), Dx = 0.85 (Typ)
86
Cross duty [%]
Be sure to confirm Dx and A value under the actual application because
these parameters vary depending on conditions of use and external
components selected.
Dx varies with oscillating frequency shown in Figure 33.
In addition, ‘A’ value can be calculated by Dnon / Dpon.
85
84
83
PMOS: RSD080P05
NMOS: RSD150N06
82
81
0
100 200 300 400 500 600 700 800
Oscillating frequency [kHz]
Figure 33. Cross duty vs. frequency
characteristics
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1.
Setting the output L1, L2 value (DC / DC1, DC / DC 2)
It is necessary to use LC filter. The use of big inductor helps lower the inductor ripple current and output ripple voltage, even
though cost is higher and size is bigger.
The inductance is shown in the following equation.
The coil value significantly influences the output ripple current. Thus, as seen bellow, the larger the coil is and the higher the
switching frequency is, the lower the ripple current is. The optimal output ripple current setting is 30 % of maximum current.
・DC / DC1 (at Buck - Boost)
Buck mode
Buck-Boost mode
VCC < VO1
VCC > VO1
∆
(
)
(
∆
1
Boost mode
)
)
(
∆
1
∆
1
(
)
1
_
ΔIL: Ripple current, I L: Average coil current, f: Oscillating frequency
PMOS ON
Dpon:
Dnoff:
(1
NMOS OFF
(1
)/(
2.13
/(
)
2.13
–
)
1.5
)
1.5
(
(
)
)
・DC / DC1 (at Buck)
∆
(
)
(
)
1
(VCC (MAX): Maximum input voltage, ΔIL1: Inductor ripple current, VO1: Output voltage 1, fSW: Oscillating frequency)
・DC / DC2 (at Boost)
∆
(
)
(
)
2
(VS2 (MAX): Maximum input voltage, ΔIL2: Inductor ripple current, VO2: Output voltage 2, fSW: Oscillating frequency)
An output current in excess of the coil current rating will cause magnetic saturation to the coil and decrease efficiency.
The following equation shows the peak current ILMAX assuming the efficiency as η.
It is recommended to secure sufficient margin to ensure that the peak current does not exceed the coil current rating.
1
η
Δ
2
Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
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When load current is low, DC / DC1 operates discontinuously so set ΔIL in a way it operates continuously (IL1 keeps
continuously flowing).
The condition of continuous operation is shown in the following equation.
・DC / DC1
(
)
2
1
(IO1: Load current)
SW1
SW1
IO1
ΔIL1
IO1
Figure 34. Continuous operation
Figure 35. Discontinuous operation
IOLIMIT
IO1
Figure 36. Over current detection
Shielded type inductor (closed magnetic circuit) is recommended. Open magnetic circuit type inductor can be used for low
cost applications if noise is not of concern. But in this case, there is magnetic field radiation between the parts and thus
keep enough spacing between the parts.
For ferrite core inductor type, please note that magnetic saturation may occur. Saturation needs to be avoided at all times.
Precautions must be taken into account on the given provisions of the current rating because it differs according to each
manufacturer.
Please confirm the rated current at the maximum ambient temperature of the application to the coil manufacturer.
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2.
Setting the output capacitor CVO1, CVO2 value (DC / DC1, DC / DC 2)
The maximum output current is limited by the over current protect operation current as shown in below equation.
(
)
(
)
2
IO (MAX): Maximum output current, ILIMIT (MIN): Minimum over current protect operation level (0.9 A) (1ch is external set)
When the ΔIL is low, the Inductor core loss (iron loss), the loss due to ESR of the output capacitor and the ΔVPP will
become low. ΔVPP is expressed as follows:
Buck mode
Boost mode
∆
8
(ESR: Output capacitor equivalence series resistance, CO: Output capacitor volume)
By using small ESR capacitor, ΔVPP voltage level can be lowered. The benefit of ceramics capacitor is low ESR and small
form factor.
The frequency characteristic of ESR from the datasheet of the manufacturer should be confirmed. Choose the ceramic
capacitor which exhibits low ESR in the switching frequency range that is used On the other hand, DC biasing
characteristics of the ceramic capacitor is significant so it needs to be carefully examined. For the voltage rating of the
ceramic capacitor, twice or more than the maximum output voltage is usually required. By selecting these high voltages
rating, it is possible to reduce the influence of DC bias characteristics. Moreover, in order to maintain good temperature
characteristics, the one with the characteristic of X7R or better, is recommended.
Because the voltage rating of ceramic capacitor is low, the selection becomes difficult in the application with high output
voltage. In that case, select electrolytic capacitor.
When using electrolytic capacitors, the voltage rating should be 1.2 times or more than the output voltage. Electrolytic
capacitors have a high voltage rating, large capacity, small amount of DC biasing characteristic, and are generally
inexpensive. Because typical failure mode is OPEN, it is effective to use electrolytic capacitor for applications where high
reliability is required such as automotive. On the other hand, disadvantages are relatively high ESR and capacitance value
drop at low temperatures. In this case, please take note that ΔVPP may increase at low temperature conditions. Moreover,
consider the lifetime characteristic of this capacitor.
The tantalum capacitor and the conductive polymer capacitor have good temperature characteristics, unlike an electrolytic
capacitor. These capacitors have small amount of DC biasing characteristic like the electrolytic capacitor. For the voltage
rating of the tantalum capacitor, twice or more than the maximum output voltage is usually required. For the voltage rating
of the conductive polymer capacitor, 1.5 times or more than the maximum output voltage is usually required. The demerits
of tantalum capacitor and conductive polymer capacitor are that a fault mode is “short” and voltages rating is low. Also the
conductive polymer capacitor is expensive. For these reason, these capacitors are not used for automotive applications,
because of its high reliability requirements.
Output capacitors are rated in ripple current. The RMS values of the ripple electric current obtained in the next expression
must not exceed the ratings of ripple electric current.
∆
(
)
√12
(ICVO (RMS): Output ripple current RMS value)
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When it comes to the capacitance CO, the value needs to be less than the value calculated by the equations below.
・DC / DC 1
(
0.5
(
(
)
(
))
0.4
(
(
)
(
)
)
・DC / DC 2
(
)
(ILIMIT (MIN): Minimum over current protect operation current (1ch is external set). 2ch = 0.9 A.
Soft start Min time DC / DC1: 0.5 ms, DC / DC2: 0.4 ms)
Boot failure may occur if the capacitance value exceeds the limits explained above. If the capacitance value is extremely
large, over-current protection may be activated by the inrush current at startup, and the output may not start.
Please confirm this on the actual circuit.
Capacitance values are critical parameter to determine the LC oscillation frequency. Transient response and loop stability
are dependent on the CVO. Please select after confirming the setting of the phase compensation circuit.
4.
Setting the input capacitor CVCCA / CVCCB, CVS2 value (VCC, VS2)
Input capacitors reduce the power output impedance that is connected to VCC. Two types of capacitors are needed for
input capacitor, i.e., decoupling capacitor CVCCB and bulk capacitor CVCCA. The decoupling capacitors of VCC and VS2
need to be 1 μF to 10 μF ceramics. The ceramic capacitors are most effective when placed as close to VCC and VS2
as possible. At VCC, the ceramic capacitors need to be placed between VCC and GND and close to PMOS and the
ground of schottky barrier diode. At VS2, the ceramic capacitor needs to be placed between VS2 and GND. Voltage
rating is recommended to be more than 1.2 times the maximum input voltage and twice the normal input voltage.
The bulk capacitor prevents line voltage drop and serves as a backup power supply to maintain the input voltage. The
low ESR electrolytic capacitor with large capacitance is suitable for the bulk capacitor. It is necessary to select the
capacitance value which best fits to each application. In case impedance of input side is high such as long wiring
between the power supply and VCC, input voltage gets unstable when output impedance of the power supply
increases resulting in oscillation or degraded ripple rejection characteristics. Large capacitor is needed in this case. It
is necessary to verify that the output does not turn off in the event of Vcc drop due to transient in the actual circuit.
Make sure not to exceed the rated ripple current of the capacitor in this case. The RMS of the input ripple current can
be obtained from the following equation.
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・DC / DC 1
VCC
(
(
)
CVCCB
)
OUTH
L1
(ICVCCB (RMS): Input ripple current RMS value)
VO1
CVO1
Figure 37. VCC pin
・DC / DC 2
(
(
)
VS2
)
VS2
(ICVS2 (RMS): Input ripple current RMS value)
CVS2
SW2
L2
VO2
CVO2
Figure 38. VS2 pin
In automotive and other applications requiring high reliability, it is recommended that capacitors are connected in parallel
to reduce the risk of electrolytic capacitors drying out. In case of ceramic capacitors, it is recommended make it two in
series and two in parallel structures to reduce the risk of destruction due to short circuit event. Currently capacitors
containing two in series or two in parallel in one package are available in the market so please contact suppliers.
5.
Setting the input capacitor CVS3 value
Place a capacitor which is greater than 0.1 µF between VS3 and GND. Select the capacitor considering filter circuit for
power supply and VS3. Since the capacitance value is dependent on the board layout and pattern, secure enough margin
when selecting the capacitor. Capacitors that have good voltage and temperature characteristics are recommended.
6.
Setting the output capacitor CVREG value
Place a capacitor between the VREG pin and GND to avoid oscillation. 0.47 μF or greater capacitance is recommended.
CVREG can be electrolytic capacitor or ceramic capacitor. Secure the capacitance of 0.47 μF or greater in the voltage and
temperature range in actual operating conditions. The change in capacitance value by temperature may cause oscillation.
Select the capacitors which have good temperature characteristics (X7R or better), good DC bias characteristics with high
voltage rating. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
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7.
Setting the output capacitor CVDD value
Place a capacitor between VDD and GND. The capacitance needs to be 0.01 µF or greater (OUTL = open) and1 µF or
greater (OUTL in use). CVDD can be electrolytic or ceramic. Secure high enough capacitance in the voltage and
temperature range in actual operating conditions. The change in capacitance value by temperature may cause oscillation.
Select the capacitors which have good temperature characteristics (X7R or better), good DC bias characteristics with high
voltage rating. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
8.
Setting the internal drive circuit supply capacitor CVL value
Add the capacitor greater than 0.1 µF between VCC and VL. Select the capacitor considering the filter circuit for power
supply and VL. Since the capacitance value is dependent on the board layout and pattern, secure enough margin when
selecting the capacitor.
9.
Setting output voltage (VO1)
VO2 and VO3 are fixed output while VO1 is adjustable.
VO1 output voltage is determined by the following equation.
0.8
Please set feedback resistor RFB1B below 30 kΩ to reduce the error margin by the bias current. In addition, since power
efficiency is reduced when RFB1A + RFB1B is small, please set the current flowing through the feedback resistor small
enough as compared to the output current IO1.
10. Selection of the MOSFET (M1, M2)
In case of Buck-Boost DC / DC, DC / DC1 needs 2 external MOSFET (PMOS = M1 and NMOS = M2). In case of Buck DC
/ DC, DC / DC1 needs 1 external MOSFET (PMOS). Key parameters in choosing MOSFET are voltage and current rating.
Figure 39. Select MOSFET
(ⅰ) PMOS
o Vds maximum rating > VCC
o Vgs maximum rating > Lower value of 13 V or VCC
* The voltage between VCC - VL is kept at 10 V (Typ), 12 V (Max).
VL become 0 V when VCC become less than 10.3 V (Typ)
o Allowable current > coil peak current ILMAX
* A value above the over current protection setting is recommended.
* Choosing a low ON Resistance FET results in high efficiency.
(ⅱ) NMOS
o Vds maximum rating > VO
o Vgs maximum rating > VDD
o Allowable current > Coil peak current ILMAX
* A value above the over current protection setting is recommended.
* Choosing a low ON Resistance FET results in high efficiency.
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11. Selection of the schottky barrier diode
The diode needs to be low Vf and fast Trr. Key parameters in the diode selection are average rectified current and DC
reverse voltage. Average rectified current IF (AVG) can be obtained from the following equation:
(
I
)
(
(
)
)
(
)
(IF (AVG): Average rectified current)
The absolute maximum rating of the average rectified current needs to be 1.2 times or greater than the IF (AVG).
The absolute maximum rating of the DC reverse voltage needs to be 1.2 times or greater than the maximum input voltage.
The diode power loss can be obtained by the following equation:
(
(
)
)
(
)
(VF: Forward voltage of IO1 (MAX))
Selecting a diode that has low forward voltage and fast reverse recovery time will help achieve a high efficiency. Select a
diode with 0.6 V or lower forward voltage. The use of the diode greater than 0.6 V forward voltage may cause inner
element destruction so care has to be taken. The reverse recovery time of the schottky barrier diode is so short and thus
its switching loss is ignorable. If the diode needs to withstand the event of output short-circuit, absolute maximum ratings
and power dissipation need to be even higher. The maximum rated current needs to be approximately 1.5 times of the
over current detection value. The diode power loss at the event of output short-circuit can be obtained by the following
equation.
(
)
(
)
(ILIMIT (MAX): VO1 Maximum over current protect operation current)
12. Setting the oscillation frequency (DC / DC1, DC / DC2)
The internal oscillation frequency can be set by changing the resistance value connected to RT pin. Frequency can be set
in the range of 250 kHz to 600 kHz. The following table shows the resistance value and its corresponding oscillation
frequency. Switching may stop if the oscillation frequency is set outside of the recommended frequency range and thus
normal operation is not guaranteed in such case.
OSCILLATING FREQUENCY: FOSC [kHz]
RT vs FOSC
800
RT [kΩ]
FOSC [kHz]
700
16
697
600
20
564
500
27
424
33
350
39
298
47
250
56
211
68
175
400
300
200
100
0
0
20
40
60
80
OSCILLATING FREQUENCY SETTING
RESISTANCE: RRT [kΩ]
Figure 40. RT resistance vs. oscillation frequency
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*The oscillation frequency graph is typical. A certain
variation exists in actual usage.
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13. Setting the phase compensation circuit (DC / DC1)
Circuit stability and transient response characteristics are determined by phase compensation. In order to get negative
feedback stability, set phase lag when gain 1 (0 dB) equal to or less than 135 ˚ (greater than 45 ˚ phase margin).
Good frequency response can be realized by setting higher zero crossing frequency fc (frequency at 0 dB gain) of the
total gain. However, speed and stability are in trade-off relationship. Moreover, DC / DC converter application is sampled
by switching frequency and the gain of the switching frequency needs to be suppressed. In order to do so, zero crossing
frequency needs to be set equal to or lower than 1 / 10 of the switching frequency.
To improve the responsiveness, switching frequency needs to be raised. It is recommended to draw a Bode plot using
the transfer function of control loop in order to get a frequency response necessary. Please confirm the frequency
characteristics of the total gain by combining the below three transfer functions.
･･･ (a)
･･･ (b)
･･･ (c)
∆
(GLC: transfer function of LC resonance, GFB: transfer function of phase compensation,
GPWM: transfer function of PWM, ΔVRAMP: 0.4 V, Q: LC quality factor)
Since DC / DC1 of the BD39001EKV-C is voltage mode, it is possible to add 2-pole and 2-zero compensation as follows.
The frequency of zero and pole is determined by the following equations:
Figure 41. Phase compensation circuit (DC / DC1)
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(
･･･ (d)
)
･･･ (e)
･･･ (f)
(
･･･ (g)
)
･･･ (h)
f
･･･ (i)
(DCR: Inductor DC resistance, RO: Load resistance, RON: MOS FET ON resistance)
The frequency characteristics are optimized by placing pole and zero at most appropriate frequencies. The estimate is as
follows.
0.2
･･･ (j)
0.5
2
5
･･･ (k)
0.5
･･･ (l)
･･･ (m)
The phase compensation set as explained can cancel out the second order lag (-180 ˚) caused by LC resonance.
If fESR is positioned higher than DC / DC switching frequency such as using low ESR ceramic for output cap, fP2 is not
necessary.
If LC filter Q (quality factor) is high, the gain has peak and phase rotates too fast resulting in not enough phase margin. In
such case, set fZ1 and fZ2 as close to fLC as possible. Q (quality factor) is calculated by following equation:
Q
(
)
･･･ (n)
･･･ (o)
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14. Phase compensation circuit (DC / DC2)
DC / DC2 is current mode control and is 2-pole and 1-zero system. It has two poles formed by error amp and output load
and one zero added by phase compensation. The appropriate pole point and zero point placement results in good
transient response and stability. Generic Bode plot of DC / DC converters is shown below. At point (a), gain starts falling
due to the pole formed by output impedance of error amp and CCO2 capacitance. After that, in order to cancel out the
pole formed by output load, insert zero formed by RCO2 and CCO2 and offset the fluctuation of gain and phase before
reaching out to point (b).
(a)
A
Gain [dB]
GBW (b)
0
F[kHz]
FCRS
PHASE[deg]
0
-90°
-90
Phase margin
-180°
-180
F[kHz]
Figure 42. Phase compensation level
External component values are determined in this way. The RCO2 determines the cross over frequency FCRS, i.e., the
frequency at which DC / DC total gain falls down to 0 dB. When FCRS is set high, good transient response is expected
but stability is sacrificed on the other hand. When FCRS is set low, good stability is expected but transient response is
sacrificed on the other hand.
In this example, component value is set in a way FCRS is 1 / 5 to 1 / 10 of the switching frequency.
(i) RCO2 for Phase compensation
Phase compensation resistor RCMP can be obtained by the following equation.
2
0.8
(Ω)
VO2: Output voltage, FCRS: Cross over frequency, CVO2: Output capacitor, VFB2: Feedback reference voltage (0.8 V (Typ)),
GMP: Current sense gain (16.7 A / V (Typ)), GMA: Error amp trans-conductance (220 uA / V (Typ))
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(ii) CCO2 for Phase compensation
Phase compensation capacitor CCO2 can be obtained by the following equation.
(F)
DCR
SW2
L2
VO2
CVO2
RVO2
CFB2
RFB2B
COMP2
FB2
RCO2
RFB2A
ERRAMP
0.8V
CCO2
Figure 43. Phase compensation circuit (DC / DC2)
However these are simple equation and thus adjustment of the value using the actual product may be necessary for
optimization. Also compensation characteristics are influenced by PCB layout and load conditions and thus thorough
evaluation using the production intent unit is recommended.
15. Phase compensation circuit (DC / DC1, DC / DC2)
The way to start designing phase compensation circuit is as explained. Create a Bode plot and check if targeted frequency
characteristics are met. The frequency characteristics pretty much fluctuate depending on PCB layout, type of
components used and operating conditions. For instance, using electrolytic capacitor for output stability may cause the
shift of LC resonance resulting in oscillation due to the capacitance drop at low temp and relevant ESR increase. For
phase compensation, temperature compensating type capacitor is recommended. Make sure to check stability and
responsiveness in actual product.
Frequency characteristics are checked by gain phase analyzer or FRA. Ask each vendor for measurement method. Even
you such measurement equipment is unavailable, phase margin can be estimated from transient load response. Monitor
how the output waveform fluctuates when changing from no load to maximum load. If the output fluctuation is significant,
response time is slow. If the ringing is frequent, phase margin is not enough. Twice or less ringing is appropriate. The
phase margin however cannot be quantified in this check method.
Output load
Maximum load
0
Phase margin: little
Output voltage
Phase margin: good
t
Figure 44. Load response
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16. Phase compensation circuit (LDO3)
VO3 pin capacitor
The capacitor must be added between VO3 pin and GND in order to stop from having it Oscillated and the recommended
Capacitance value is more than 10uF. In accordance to graph shown in below, either Electrolytic or Ceramic Capacitor can
be used. Please ensure to select the Capacitor higher than 10uF in the range of voltage and temperature to be used at.
There is possibility of oscillation when capacitance value changes due to change of temperature. When selecting a
ceramic capacitor, X7R or higher is recommended which is good in temperature characteristic and has excellent DC bias
characteristic. In case significant voltage swing and load transient are expected, make sure to carry out thorough
evaluation before making a decision on the capacitance value.
○Condition
VCC = 12 V
VS3 = 6.5 V
0 mA ≤ IO3 ≤ 600 mA
10 µF ≤ CVO3 ≤ 100 µF
CVO3 VS. ESR
100
ESR[ohm]
10
1
0.1
0.01
10
22
33
47
68
100
CVO3 [uF]
Figure 45. Output capacitor value CVO3 vs Output capacitor ESR
VO3
CVO3
ESR
IO3
Figure 46. Output capacitor and ESR measurement circuit
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17. Provision of Capacitor connected to CL terminal
The capacitor (CCL) and resistor (RCLB) connected to CL pin are the CR noise filter for preventing OCP error detection.
For the constant setting of filter, since noise depends on
circuit and board pattern, there is no fixed rule. But, please
try reducing cut-off frequency of CR filter without
deteriorating ON pulse waveform that requires detecting
current sense.
Pulse width≈ (VO1 / VCC)・ (1 / FOSC)
(The rough estimate setting is RCLB = several tens ohm, CCL
= several thousand pF)
CCL
CL
RCLA
VCC
RCLB
OUTH
Figure 47. CL pin filter circuit
18. Soft Start setting
The soft start function is necessary to prevent inrush of coil current and output voltage overshoot at start up.
Setting of soft start time is shown in the following equation.
・DC / DC1
・DC / DC2
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19. Setting the CT power on reset time
Power reset setting time can be set by the capacitor connected to CT
Capacitance can be chosen from 0.01 μF to 1 μF range or have CT terminal OPEN.
If setting is made out of its range, chattering may occur at Reset output.
CT operation is changed by the time of error detection. See page 13, Figure 14 for detail.
(1) CT pin starts 0 V
Power ON Reset Time: POR[ms]
CT vs POR
200
CT [μF]
0.001
POR [ms]
0.167
180
0.0082
1.09
160
140
120
100
80
0.01
1.62
0.022
3.46
0.033
5.24
0.047
7.64
0.068
10.8
0.1
16
0.22
36.2
40
0.47
76.8
20
1
159
2.2
360
10
1810
200
CT [μF]
0.001
POR [ms]
0.16
180
0.0082
0.826
160
0.01
1.452
140
0.022
2.51
0.033
3.93
0.047
5.82
0.068
7.9
0.1
14.12
0.22
26.7
60
0
0
0.3
0.6
0.9
POR SETTING CAPACITOR:
CCT[μF]
Figure 48. Power ON Reset time1 (CT = 0 V to 0.8 V (Typ))
(2) CT pin starts 0.2 V
Power ON Reset Time: tRST[ms]
CT vs tRST
120
100
80
60
40
0.47
57.2
1
114.4
2.2
244
10
1240
20
0
0
0.3
0.6
0.9
POR SETTING CAPACITOR:
CCT[μF]
Figure 49. Power ON Reset time2 (CT = 0.2 V (Typ) to 0.8 V (Typ))
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20. Setting the WDT oscillation frequency
WDT oscillation frequency can be set by resistance value connected to RTW. Possible setting range is 50 kHz to 250 kHz and the
relation between resistance value and oscillation frequency is decided as shown below.
It is possible that the switching stops at outside these range and its operation is not guaranteed.
WDTOSCILLATING FREQUENCY: FOSCW [kHz]
RTW vs FOSC
RTW [kΩ]
12
18
22
27
33
47
51
62
75
82
100
120
150
450
400
350
300
250
200
150
100
50
0
0
40
80
120
160
FOSCW [kHz]
393
268
221
182
151
108
100
83
69
64
53
45
36
OSCILLATING FREQUENCY SETTING
RESISTANCE: RRTW [kΩ]
*This oscillation frequency graph is typical value
Tolerance needs to be put into consideration.
Figure 50. WDT oscillation frequency characteristics
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21. Recommend value of external pull - up resistance
PG pin ON resistance (PPUPG)
Min = 0.5 kΩ, Typ = 1.0 kΩ, Max = 2.0 kΩ
(V)
Please set the Resistance value considering H threshold of
PG pin.
Figure 51.
22. Provision of EN1 pull -up resistance
Because "H" threshold of EN1 is Min 2.5 V, please design as the below equation is able to work.
2.5
VCC
(V)
REN1A
EN
(188 kΩ ≤ REN1B ≤ 750 kΩ)
REN1B
Figure 52
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Application Examples
*There are many factors (Board layout, variation of the part, etc.) that can affect the characteristics.
Please verify and confirm using practical applications.
*No connection (N.C) pin should not be connected to any other lines.
*Be sure to connect the TEST pin to ground.
* If EN1 pin is connected to VCC pin, please insert resistance between the pins.
Figure 53. Application Example 2 (DC / DC1 Buck - Boost)
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Application Examples - Continued
*There are many factors (Board layout, variation of the part, etc.) that can affect the characteristics.
Please verify and confirm using practical applications.
*No connection (N.C) pin should not be connected to any other lines.
*Be sure to connect the TEST pin to ground.
* If EN1 pin is connected to VCC pin, please insert resistance between the pins.
REN1A
CVCCA
VCC
CVCCB
EN1
CL
VERG
power gnd
CVL
CCL
RCLA
RCLB
OUTH
M1
CVREG
RT
VO1
RFB1C
RFB1B
CSS1
CFB1
CCO1A
RFB1A
VL
RRT
SS1
VDD
FB1
OUTL
L1
CVDD
D1A
CCO1B
RCO1
VO1
D1B
CVO1B
CVO1A
power gnd
COMP1
PGND1
power gnd
VO2
CSS2
SS2
VS2
CVS2
FB2
SW2
L2
VO2
power gnd
CVO2
power gnd
COMP2
PGND2
RCO2
CCO2
VO1
VO3
power gnd
EN2
VO3
CVO3
CT
VS3
CVS3
power gnd
power gnd
CCT
RRST2
RRST3
RRSTW
RPUPG1
RPUPG2
RPUPG3
EN3
SEQ2
RST2#
SEQ3
RST3#
ENWD
RSTWD#
CLK
PG1
RTW
PG2
RRTW
SEL_UVLO
PG3
GND
Figure 54. Application Example 3 (DC / DC1 Buck)
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Example of Constant Setting (DC / DC1 Buck Mode)
Name
Value
Parts No.
Size Code
Maker
IC
-
-
BD39001EKV-C
10 × 10 mm
ROHM
REN
150
kohm
MCR03
1608
ROHM
RRT
27
kohm
MCR03
1608
ROHM
RFB1A
10
kohm
MCR03
1608
ROHM
Note
RFB1B
68
kohm
MCR03
1608
ROHM
RFB1C
1.6
kohm
MCR03
1608
ROHM
At Buck-Boost: 0.1 kohm
RCO1
36
kohm
MCR03
1608
ROHM
At Buck-Boost: 4.7 kohm
RCO2
20
kohm
MCR03
1608
ROHM
RRTW
47
kohm
MCR03
1608
ROHM
RCLA
110
mohm
MCR10
2012
ROHM
RCLB
110
mohm
MCR10
2012
ROHM
RRST2
10
kohm
MCR03
1608
ROHM
RRST3
10
kohm
MCR03
1608
ROHM
RRSTW
10
kohm
MCR03
1608
ROHM
RPUPG1
10
kohm
MCR03
1608
ROHM
RPUPG2
10
kohm
MCR03
1608
ROHM
RPUPG3
10
kohm
MCR03
1608
ROHM
CVCCA
47
µF
Electrolytic capacitor
-
-
CVCCB
2.2
µF
GCM31CR71H225KA40
1608
murata
CVREG
1
µF
GCM188R71C105KA49
1608
murata
CVDD
0.1
µF
GCM188R11H104KA42
1608
murata
CSS1
0.033
µF
GCM188R11H333KA40
1608
murata
CSS2
0.047
µF
GCM188R11H473KA40
1608
murata
CCO1A
2200
pF
GCM188R11H222KA01
1608
murata
At Buck-Boost: 47000 pF
At Buck-Boost: 100 pF
CCO1B
33
pF
GCM188R11H330KA01
1608
murata
CCO2
2200
pF
GCM188R11H222KA01
1608
murata
CVS3
1
µF
GCM188R71C105KA49
1608
murata
At Buck-Boost: 1 µF
CCL
0.1
µF
GCM188R11H104KA42
1608
murata
CVL
0.1
µF
GCM188R11H104KA42
1608
murata
CVO1A
100
µF
Electrolytic capacitor
-
-
At Buck-Boost: 47 μF
CVO1B
OPEN
-
-
-
At Buck-Boost: 44 μF
CVS2
4.7
µF
GCM21BR71C475KA67
2012
murata
CVO2
100
µF
Electrolytic capacitor
-
-
CVO3
100
µF
Electrolytic capacitor
-
-
CCT
0.1
µF
GCM188R11H104KA42
1608
murata
L1
47
µH
SLF12565T-470M2R4-H
12.5 × 12.5 mm
TDK
µH
SLF7045T-100M1R8-H
7 × 7 mm
L2
10
D1A
SBD
RB050L-40
ROHM
TDK
D1B
SBD
RB050L-40
ROHM
M1
pchFET
RSD046P05
ROHM
M2
nchFET
RSD080N06
ROHM
Only Buck-Boost
Only Buck-Boost
Notes for pattern layout of PCB
1)
2)
3)
4)
5)
6)
Design the wirings shown in bold line as short as possible.
Place the input ceramic capacitor CVCCB as close to M1 as possible.
Place the RRT and RRTW as close to GND pin as possible.
Place the RFB1A and RFB1B as close to FB1 pin as possible and provide the shortest wiring from FB1 pin.
Place the RFB1A, RFB1B and FB2 as far away from L1 and L2 as possible.
Separate power GND and signal GND so that SW noise doesn’t affect the signal GND.
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Sequence function
DC / DC2 and LDO output sequence can be set with EN2, EN3, SEQ2 and SEQ3 pin.
Ex. 1) EN2, EN3, SEQ2 and SEQ3 pins are open
DC / DC1→LDO and DC / DC2 start at once.
Figure 55. Start sequence example 1
Ex. 2) Condenser connects to EN pin
VCC
EN2
EN1
DC / DC2
CEN2
SS1
Soft Start
EN3
VS_UVLO
VO1(VS2, VS3)
LDO
SEQ2
EN2
Soft Start
LVD2
（DC / DC2)
SS2
VO2
LVD2 Release voltage
EN3
SEQ3
LVD3
（LDO)
LVD3 Release voltage
VO3
CT
ｔRST
RST
Figure 56. Start sequence example 2
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Power Dissipation
Maximum Junction Temperature Tj is 150 °C. If the junction temperature reaches 175 °C or higher, the circuit will be shut
down. Please make sure that the junction temperature must not exceed 150C at all time.
For thermal design, be sure to operate the IC within the following conditions.
(Since the temperatures described hereunder are all guaranteed temperatures, take margin into account.)
1. Ambient temperature Ta is less than 125 °C.
2. Tj is less than 150 °C.
Temperature Tj can be calculated by two ways as below.
1. To obtain Tj from the IC surface temperature Tc in actual use
2. To obtain Tj from the ambient temperature Ta
The heat loss of the IC (PTOTAL) is calculated by the equation below.
・DC / DC1 (at Buck)
2
2
・DC / DC2
– Toff2
(
(
2
2
2
)
2
2
/2)
I
f)
・LDO
(
–
)
・DC / DC1
①
②
(
)
2
Figure 57. SW1 Wave form
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BD39001EKV-C
・DC / DC2
Figure 58. SW2 wave and circuit
③The loss of ON Duty
④The loss of OFF Duty
⑤The loss of OFF / OFF
⑥The loss of Tr2
Tr2
⑦The loss of Tf2
Tf2
–
Vf
(Toff2
f)
RONH1: ON resistor of external Pch-PowTr
RONH2: ON resistor of internal Pch-PowTr
RONL2: ON resistor of internal Nch-PowTr
VO1: DC / DC1 output voltage
VO2: DC / DC2 output voltage
VO3: LDO output voltage
VCC: Input voltage (VS2 = VO1, VS3 = VO1)
Io1: DC / DC1 output current
Io2: DC / DC2 output current
Io3: LDO output current
ICC: circuit current (see page 5)
Tr1: Switching rise time (About15 ns)
Tr2: Switching rise time (About15 ns)
Tf1: Switching fall time (About 35 ns)
Tf2: Switching fall time (About15 ns)
Toff2: DC / DC2 dead time (About 65 ns)
f: Oscillation frequency
See the thermal derating characteristics (Figure 59) if the device used over the ambient temperature Ta = 25 °C.
The characteristics of IC largely depend on temperature, and IC must be used at maximum junction temperature (Tjmax) or
lower. Even if the ambient temperature is 25 °C, there is a possibility junction temperature gets high as consequence of input
voltage and load current. IC must be used within power dissipation Pd.
Thermal resistance value θja is varied by the number of the layer and copper foil area of the PCB.
See Figure 59 for the thermal design.
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Thermal Derating Characteristics
Power Dissipation : Pd （W)
6
IC mounted on ROHM standard board
・Board size: 70 mm × 70 mm × 1.6 mm
・PCB and back metal are connected by soldering
④5.00 W
5
①1 layer board 70 × 70 × 1.6 mm (copper foil area 0 mm × 0 mm)
②2 layer board 70 × 70 × 1.6 mm (copper foil 15 mm × 15 mm)
③2 layer board 70 × 70 × 1.6 mm (copper foil 70 mm × 70 mm)
④4 layer board 70 × 70 × 1.6 mm (copper foil 70 mm × 70 mm)
③3.60 W
4
3
②1.80 W
Board①: θja = 89.3 °C / W
Board②: θja = 69.4 °C / W
Board③: θja = 34.7 °C / W
Board④: θja = 25.0 °C / W
2
①1.40 W
1
0
0
25
50
75
100
125
150
Ambient Temperature: Ta(℃)
Figure 59. Package data of HTQFP48V (Reference data)
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BD39001EKV-C
I / O Equivalence Circuit
1. VO3
3. VS3
4, 5. VS2
VS3
LDO
Circuit
GND
7, 8. SW2
10, 11. PGND2
12. SS2
VREG
VS2
PGND2
SS
SW2
GND
PGND2
GND
13. COMP2
14. FB2
15. VDD
VREG
VCC
FB
VDD
PGND1
GND
16. OUTL
17. PGND1
19. VL
VCC
VDD
PGND1
VL
DC / DC1
Driver Circuit
OUTL
GND
PGND1
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BD39001EKV-C
I / O Equivalence Circuit - Continued
21. OUTH
23. CL
VCC
OUTH
24. VCC
VCC
VCC
CL
CL
GND
GND
VL
PGND1
25. EN1
26. T4
27. VREG
28. SS1
29. COMP1
30. FB1
31. RT
33, 34
RST2#, RST3#
35. RSTWD#
VCC
VREG
EN1
T4
GND
GND
VCC
SS1
GND
VREG
RSTWD
RT
GND
GND
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BD39001EKV-C
I / O Equivalence Circuit - Continued
36. CT
LDO_PREREG
37. RTW
38. CLK
40. EN3
41. EN2
VREG
CT
RTW
GND
GND
39. ENWD
VREG
VREG
EN3
EN2
GND
GND
42, 43, 44, 45, 46
SEQ3, SEQ2, PG3, PG2, PG1
PG1
PG2
PG3
SEQ2
SEQ3
GND
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47. T3
48. SEL_UVLO
VREG
T3
GND
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BD39001EKV-C
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Please make sure to have protection against
reverse polarity, such as putting an external diode between the power supply and the IC’s power supply pins.
2.
Power Supply Lines
Power supply line must be low impedance on the PCB. The power supply of digital and analog must be separated
(even if the electrical potentials are the same) to prevent analog circuit from having digital noise by common
impedance of line pattern (ground line must be designed in the same way)
Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on
the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that ground pin must have the lowest electrical potential at all time even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately, but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground voltage caused by large currents. Also ensure that the ground traces of external components do not cause
variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded, the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd is specified at the condition of
70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board
size or copper area to prevent the IC from exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the specified characteristics can be approximately obtained. The
electrical characteristics are guaranteed under the specified conditions.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
protect IC from static discharge damage, ground the IC during assembly and use similar precautions during transport
and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Make sure that there is nothing between the pins, such as no metal particles, no water droplets (in very humid
environment) and unintentional solder bridge deposited.
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BD39001EKV-C
Operational Notes – continued
10.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If input pins left unconnected, the electric field from the outside can easily charge it. The
small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation
of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.
Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower
than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power
supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have
voltages within the values specified in the electrical characteristics of this IC.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant with the consideration of the capacitance charge
with temperature and the decrease in nominal capacitance due to DC bias and others.
13. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. If however the rating is exceeded for a continued period of time, the junction
temperature (Tj) rises, and TSD activated, which turns off all output pins. When the Tj falls below the TSD threshold,
the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings. Under no circumstances,
TSD circuit should not be used for any purpose other than protecting the IC from exceeding the maximum rating.
14. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is designed to avoid IC damaged from sudden and unexpected incidents, so should not be used in
applications characterized by continuous operation or transitioning of the protection circuit.
15. Power input at shutdown
If VCC starts up in rapid period of time at shutdown (EN1 = OFF), VREG voltage may be output, which causes the IC to
malfunction. Therefore, set the VCC rise time at 40V/ms or shorter.
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16. Reverse Polarity and Surge voltage
z
If the VCC and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended.
z
If the VS2 and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended.
z
If the VS3 and pin potential are reversed, internal circuit or element may be damaged (example: VCC is shorted to
GND while external capacitor changed) Putting diode for reverse protection in series of VCC or putting bypass diode
between VCC is recommended
VS3
z
Applying positive surge to the VCC
If there is apossibility a surge exceeding the rating be applied to VCC, please put a power zener diode between VCC
and GND.
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z
Applying negative surge to the VCC
If there is a possibility VCC gets lower than GND, please put a schottky diode between VCC and GND.
z
Protection Diode
If there is a possibility large inductive load is connected to the output pin (VO2 or VO3) resulting in back-EMF at time
of startup and shutdown, a protection diode should be placed as shown in the figure below.
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Datashe
Datasheet
eet
BD
D39001EK
KV-C
Ph
hysical Dime
ension, Tape
e and Reel Information
Package
P
Na
ame
ww
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2
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o., Ltd. All rights reserved.
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Z22111・15・0
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HT
TQFP48V
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Z02201-0T3T
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BD39001EKV-C
Ordering Information
B
D
3
9
0
Part Number
0
1
E
K
Package
EKV: HTQFP48V
V
-
For in-vehicle
C
E2
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
HTQFP48V (TOP VIEW)
Part Number Marking
BD39001
LOT Number
1PIN MARK
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Revision History
Date
Revision
2014.Apr.7
001
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice – SS
© 2013 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice – SS
© 2013 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001