PIC10(L)F320/322 6/8-Pin Flash-Based, 8-Bit Microcontrollers High-Performance RISC CPU Low-Power Features (PIC10LF320/322) • Only 35 Instructions to Learn: - All single-cycle instructions, except branches • Operating Speed: - DC – 16 MHz clock input - DC – 250 ns instruction cycle • Up to 512 Words of Flash Program Memory • 64 Bytes Data Memory • Eight-level Deep Hardware Stack • Interrupt Capability • Processor Self-Write/Read access to Program Memory • Pinout Compatible to other 6-Pin PIC10FXXX Microcontrollers • Standby Current: - 20 nA @ 1.8V, typical • Operating Current: - 25 A @ 1 MHz, 1.8V, typical • Watchdog Timer Current: - 500 nA @ 1.8V, typical Special Microcontroller Features • Low-Power 16 MHz Internal Oscillator: - Software selectable frequency range from 16 MHz to 31 kHz - Factory calibrated to 1%, typical • Wide Operating Range: - 1.8V to 3.6V (PIC10LF320/322) - 2.3V to 5.5V (PIC10F320/322) • Power-On Reset (POR) • Power-up Timer (PWRT) • Brown-Out Reset (BOR) • Ultra Low-Power Sleep Regulator • Extended Watchdog Timer (WDT) • Programmable Code Protection • Power-Saving Sleep mode • Selectable Oscillator Options (EC mode or Internal Oscillator) • In-Circuit Serial Programming™ (ICSP™) (via Two Pins) • In-Circuit Debugger Support • Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V (‘F’ variant only) Output Levels • Integrated Temperature Indicator • 40-year Flash Data Retention 2011-2015 Microchip Technology Inc. Peripheral Features • Four I/O Pins: - One input-only pin - High current sink/source for LED drivers - Individually selectable weak pull-ups - Interrupt-on-Change • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two PWM modules: - 10-bit PWM, max. frequency 16 kHz - Combined to single 2-phase output • A/D Converter: - 8-bit resolution with 3 channels • Configurable Logic Cell (CLC): - 8 selectable input source signals - Two inputs per module - Software selectable logic functions including: AND/OR/XOR/D Flop/D Latch/SR/JK - External or internal inputs/outputs - Operation while in Sleep • Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - Linear frequency control - High-speed clock input - Selectable Output modes - Fixed Duty Cycle (FDC) - Pulse Frequency (PF) mode • Complementary Waveform Generator (CWG): - Selectable falling and rising edge dead-band control - Polarity control - Two auto-shutdown sources - Multiple input sources: PWM, CLC, NCO DS40001585C-page 1 PIC10(L)F320/322 Data Sheet Index: 1: DS40001585 Note: Debug(1) XLP PIC10(L)F320 (1) 256 64 4 3 2 2 1 1 1 PIC10(L)F322 (1) 512 64 4 3 2 2 1 1 1 Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header; E - Emulation, Available using Emulation Header. 2: One pin is input-only. Numerically Controlled Oscillator (NCO) Fixed Voltage Reference (FVR) Configurable Logic Cell (CLC) Complementary Wave Generator (CWG) PWM Timers (8-Bit) 8-Bit ADC (ch) I/O’s(2) Data SRAM (bytes) Program Memory Flash (words) Device Data Sheet Index PIC10(L)F320/322 Family Types 1 1 H H N N PIC10(L)F320/322 Data Sheet, 6/8 Pin High Performance, Flash Microcontrollers. For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001585C-page 2 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 1: 6-PIN DIAGRAM, PIC10(L)F320/322 SOT-23 ICSPDAT/RA0 1 PIC10(L)F320 PIC10(L)F322 VSS 2 ICSPCLK/RA1 3 FIGURE 2: 6 RA3/MCLR/VPP 5 VDD 4 RA2 8-PIN DIAGRAM, PIC10(L)F320/322 PDIP, DFN N/C 1 RA2 3 ICSPCLK/RA1 4 TABLE 1: I/O 8 RA3/MCLR/VPP PIC10(L)F320 PIC10(L)F322 VDD 2 7 VSS 6 N/C 5 RA0/ICSPDAT 6 AND 8-PIN ALLOCATION TABLE, PIC10(L)F320/322 6-Pin 8-Pin Analog Timer PWM Interrupts Pull-ups CWG NCO CLC Basic ICSP RA0 1 5 AN0 — PWM1 IOC0 Y CWG1A — CLC1IN0 — ICSPDAT RA1 3 4 AN1 — PWM2 IOC1 Y CWG1B NCO1CLK CLC1 CLKIN ICSPCLK RA2 4 3 AN2 T0CKI — INT/IOC2 Y CWG1FLT NCO1 CLC1IN1 CLKR RA3 6 8 — — — IOC3 Y — — — MCLR VPP N/C — 1 — — — — — — — — — — N/C — 6 — — — — — — — — — — VDD 5 2 — — — — — — — — VDD — VSS 2 7 — — — — — — — — VSS — 2011-2015 Microchip Technology Inc. DS40001585C-page 3 PIC10(L)F320/322 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 6 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Device Configuration .................................................................................................................................................................. 19 4.0 Oscillator Module........................................................................................................................................................................ 24 5.0 Resets ........................................................................................................................................................................................ 28 6.0 Interrupts .................................................................................................................................................................................... 35 7.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 44 8.0 Watchdog Timer ......................................................................................................................................................................... 46 9.0 Flash Program Memory Control ................................................................................................................................................. 50 10.0 I/O Port ....................................................................................................................................................................................... 67 11.0 Interrupt-On-Change .................................................................................................................................................................. 73 12.0 Fixed Voltage Reference (FVR) ................................................................................................................................................. 77 13.0 Internal Voltage Regulator (IVR) ................................................................................................................................................ 79 14.0 Temperature Indicator Module ................................................................................................................................................... 81 15.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 83 16.0 Timer0 Module ........................................................................................................................................................................... 93 17.0 Timer2 Module ........................................................................................................................................................................... 96 18.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................... 98 19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 104 20.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 119 21.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 129 22.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 144 23.0 Instruction Set Summary .......................................................................................................................................................... 147 24.0 Electrical Specifications............................................................................................................................................................ 156 25.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 176 26.0 Development Support............................................................................................................................................................... 177 27.0 Packaging Information.............................................................................................................................................................. 181 Appendix A: Data Sheet Revision History.......................................................................................................................................... 189 DS40001585C-page 4 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011-2015 Microchip Technology Inc. DS40001585C-page 5 PIC10(L)F320/322 1.0 DEVICE OVERVIEW The PIC10(L)F320/322 are described within this data sheet. They are available in 6/8-pin packages. Figure 1-1 shows a block diagram of the PIC10(L)F320/322 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC10(L)F322 DEVICE PERIPHERAL SUMMARY PIC10(L)F320 TABLE 1-1: Analog-to-Digital Converter (ADC) ● ● Configurable Logic Cell (CLC) ● ● Complementary Wave Generator (CWG) ● ● Fixed Voltage Reference (FVR) ● ● Numerically Controlled Oscillator (NCO) ● ● Temperature Indicator ● ● PWM1 ● ● PWM2 ● ● Timer0 ● ● Timer2 ● ● PWM Modules Timers DS40001585C-page 6 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 1-1: PIC10(L)F320/322 BLOCK DIAGRAM Program Flash Memory RAM CLKR PORTA Timing Generation CLKIN CPU INTRC Oscillator Figure 2-1 MCLR Timer0 Temp. Indicator Note 1: ADC 8-Bit Timer2 FVR PWM1 PWM2 NCO CLC CWG See applicable chapters for more information on peripherals. 2011-2015 Microchip Technology Inc. DS40001585C-page 7 PIC10(L)F320/322 TABLE 1-2: PIC10(L)F320/322 PINOUT DESCRIPTION Name RA0/PWM1/CLC1IN0/CWG1A/ AN0/ICSPDAT RA1/PWM2/CLC1/CWG1B/AN1/ CLKIN/ICSPCLK/NCO1CLK RA2/INT/T0CKI/NCO1/CLC1IN1/ CLKR/AN2/CWG1FLT RA3/MCLR/VPP Function Input Type RA0 TTL PWM1 — CLC1IN0 ST CWG1A — Output Type Description CMOS General purpose I/O with IOC and WPU. CMOS PWM output. — CLC input. CMOS CWG primary output. AN0 AN ICSPDAT ST CMOS ICSP™ Data I/O. — A/D Channel input. CMOS General purpose I/O with IOC and WPU. RA1 TTL PWM2 — CMOS PWM output. CLC1 — CMOS CLC output. CWG1B — CMOS CWG complementary output. AN1 AN — A/D Channel input. CLKIN ST — External Clock input (EC mode). ICSPCLK ST — ICSP™ Programming Clock. NCO1CLK ST — Numerical Controlled Oscillator external clock input. RA2 TTL INT ST — External interrupt. T0CKI ST — Timer0 clock input. NCO1 — CLC1IN1 ST CLKR — AN2 AN — A/D Channel input. CWG1FLT ST — Complementary Waveform Generator Fault 1 source input. General purpose input. CMOS General purpose I/O with IOC and WPU. CMOS Numerically Controlled Oscillator output. — CLC input. CMOS Clock Reference output. RA3 TTL — MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output TTL = CMOS input with TTL levels HV = High Voltage DS40001585C-page 8 CMOS = CMOS compatible input or output ST = CMOS input with Schmitt Trigger levels 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 2.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Word - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 2.1 Program Memory Organization The mid-range core has a 13-bit program counter capable of addressing 8K x 14 program memory space. This device family only implements up to 512 words of the 8K program memory space. Table 2-1 shows the memory sizes implemented for the PIC10(L)F320/322 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, and 2-2). The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing TABLE 2-1: DEVICE SIZES AND ADDRESSES Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range (1) PIC10(L)F320 256 00FFh 0F80h-00FFh PIC10(L)F322 512 01FFh 1F80h-01FFh Device Note 1: High-endurance Flash applies to low byte of each address in the range. 2011-2015 Microchip Technology Inc. DS40001585C-page 9 PIC10(L)F320/322 FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR PIC10(L)F320 FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR PIC10(L)F322 PC<12:0> PC<12:0> CALL, RETURN, RETLW RETFIE CALL RETURN, RETLW RETFIE 13 13 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h On-chip Program Memory Page 0 Rollover to Page 0 Wraps to Page 0 00FFh 0100h On-chip Program Memory Page 0 Wraps to Page 0 Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 DS40001585C-page 10 FFFh Rollover to Page 0 01FFh 0200h FFFh 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 2.2 Data Memory Organization The data memory is in one bank, which contains the General Purpose Registers (GPR) and the Special Function Registers (SFR). The RP<1:0> bits of the STATUS register are the bank select bits. RP1 0 RP0 0 Bank 0 is selected The bank extends up to 7Fh (128 bytes). The lower locations of the bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as Static RAM. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC10(L)F320/322. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-3). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. 2011-2015 Microchip Technology Inc. DS40001585C-page 11 PIC10(L)F320/322 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (see Section 23.0 “Instruction Set Summary”). Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC10(L)F320 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. DS40001585C-page 12 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 2-1: STATUS: STATUS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R-1/q R-1/q R/W-x/u R/W-x/u R/W-x/u IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 IRP: Reserved(2) bit 6-5 RP<1:0>: Reserved(2) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2: Maintain as ‘0’. 2011-2015 Microchip Technology Inc. DS40001585C-page 13 PIC10(L)F320/322 2.2.3 DEVICE MEMORY MAPS The memory maps for PIC10(L)F320/322 are as shown in Table 2-2. TABLE 2-2: PIC10(L)F320/322 MEMORY MAP (BANK 0) INDF(*) 00h PMADRL 20h TMR0 01h PMADRH 21h PCL 02h PMDATL 22h STATUS 03h PMDATH 23h FSR 04h PMCON1 24h PORTA 05h PMCON2 25h TRISA 06h CLKRCON 26h LATA 07h NCO1ACCL 27h ANSELA 08h NCO1ACCH 28h WPUA 09h NCO1ACCU 29h PCLATH 0Ah NCO1INCL 2Ah INTCON 0Bh NCO1INCH 2Bh PIR1 0Ch Reserved 2Ch PIE1 0Dh NCO1CON 2Dh OPTION_REG 0Eh NCO1CLK 2Eh 2Fh PCON 0Fh Reserved OSCCON 10h WDTCON 30h TMR2 11h CLC1CON 31h PR2 12h CLC1SEL1 32h T2CON 13h CLC1SEL2 33h PWM1DCL 14h CLC1POL 34h PWM1DCH 15h CLC1GLS0 35h PWM1CON 16h CLC1GLS1 36h PWM2DCL 17h CLC1GLS2 37h PWM2DCH 18h CLC1GLS3 38h PWM2CON 19h CWG1CON0 39h IOCAP 1Ah CWG1CON1 3Ah IOCAN 1Bh CWG1CON2 3Bh IOCAF 1Ch CWG1DBR 3Ch FVRCON 1Dh CWG1DBF 3Dh ADRES 1Eh VREGCON 3Eh 1Fh BORCON 3Fh ADCON Legend: * 40h 60h General Purpose Registers General Purpose Registers 32 Bytes 32 Bytes 5Fh 7Fh = Unimplemented data memory locations, read as ‘0’. = Not a physical register. DS40001585C-page 14 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 2-3: Address SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS 0001 1xxx 000q quuu 04h FSR 05h PORTA — — — — RA3 RA2 RA1 RA0 06h TRISA — — — — —(1) TRISA2 TRISA1 TRISA0 ---- 1111 ---- 1111 07h LATA — — — — — LATA2 LATA1 LATA0 ---- -xxx ---- -uuu 08h ANSELA — — — — — ANSA2 ANSA1 ANSA0 ---- -111 ---- -111 09h WPUA — — — — WPUA3 WPUA2 WPUA1 WPUA0 ---- 1111 ---- 1111 0Ah PCLATH — — — — — — — PCLH0 ---- ---0 ---- ---0 0Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 000u 0Ch PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — -0-0 0-0- -0-0 0-0- 0Dh PIE1 — TMR2IE — 0Eh OPTION_REG IRP RP1 RP0 — ADIE — NCO1IE CLC1IE WPUEN INTEDG T0CS T0SE PSA — — — PCON — 10h OSCCON — 11h TMR2 12h PR2 13h T2CON 14h PWM1DCL 15h PWM1DCH 16h PWM1CON 17h PWM2DCL 18h PWM2DCH 19h PWM2CON 1Ah IOCAP — — — 1Bh IOCAN — — 1Ch IOCAF — — 1Dh FVRCON FVREN FVRRDY 1Eh ADRES ADCON Legend: Note 1: PD Z DC C Indirect Data Memory Address Pointer 0Fh 1Fh TO — — POR BOR ---- --qq ---- --uu LFIOFR HFIOFS -110 0-00 -110 0-00 Timer2 Module Register 0000 0000 0000 0000 Timer2 Period Register 1111 1111 1111 1111 T2CKPS<1:0> -000 0000 -000 0000 — xx-- ---- uu-- ---- — TMR2ON — — — — uuuu uuuu — — — 0000 ---- 0000 ---- — — — — xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu — — — — 0000 ---- 0000 ---- — IOCAP3 IOCAP2 IOCAP1 IOCAP0 ---- 0000 ---- 0000 — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 ---- 0000 ---- 0000 — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 ---- 0000 ---- 0000 TSEN TSRNG — — 0x00 --00 0x00 --00 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 PWM2OE PWM2OUT PWM2POL ADFVR<1:0> A/D Result Register ADCS<2:0> xxxx xxxx — PWM2DCH<7:0> PWM2EN -0-0 0-0uuuu uuuu — PWM1OE PWM1OUT PWM1POL PWM2DCL<1:0> -0-0 0-01111 1111 — PWM1DCH<7:0> PWM1EN ---- uuuu — TOUTPS<3:0> PWM1DCL<1:0> uuuu uuuu ---- xxxx HFIOFR IRCF<2:0> — PS<2:0> xxxx xxxx CHS<2:0> GO/ DONE ADON x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. 2011-2015 Microchip Technology Inc. DS40001585C-page 15 PIC10(L)F320/322 TABLE 2-3: Address SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 — — — — Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets 0000 0000 0000 0000 — — PMADR8 ---- ---0 ---- ---0 Bank 0 (Continued) 20h PMADRL 21h PMADRH PMADR<7:0> 22h PMDATL 23h PMDATH — — 24h PMCON1 — CFGS 25h PMCON2 26h CLKRCON — PMDAT<7:0> PMDAT<13:8> LWLO FREE WRERR WREN WR RD Program Memory Control Register 2 (not a physical register) — CLKROE — — — — — — xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu 1000 0000 1000 q000 0000 0000 0000 0000 -0-- ---- -0-- ---- 27h NCO1ACCL NCO1 Accumulator <7:0> 0000 0000 0000 0000 28h NCO1ACCH NCO1 Accumulator <15:8> 0000 0000 0000 0000 29h NCO1ACCU 2Ah NCO1INCL 2Bh NCO1INCH 2Ch — 2Dh NCO1CON 2Eh NCO1CLK 2Fh — NCO1 Accumulator <19..16> ---- 0000 ---- 0000 NCO1 Increment <7:0> 0000 0001 0000 0001 NCO1 Increment <15:8> 0000 0000 0000 0000 Unimplemented N1EN N1OE N1OUT N1POL — N1PWS<2:0> Reserved 30h — — — — — N1PFM N1CKS<1:0> Reserved WDTCON — — 31h CLC1CON LC1EN LC1OE 32h CLC1SEL0 — 33h CLC1SEL1 — 34h CLC1POL LC1POL WDTPS<4:0> SWDTEN — — 0000 ---0 00x0 ---0 000- --00 000- --00 xxxx xxxx uuuu uuuu --01 0110 --01 0110 LC1INTN LC1MODE<2:0> 00x0 -000 00x0 -000 LC1D2S<2:0> — LC1D1S<2:0> -xxx -xxx -uuu -uuu LC1D4S<2:0> — LC1D3S<2:0> -xxx -xxx -uuu -uuu LC1OUT LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu 38h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D1N xxxx xxxx uuuu uuuu 39h CWG1CON0 35h 36h 37h G1EN — G1OEB G1ASDLB<1:0> — LC1INTP G1OEA — G1POLB G1ASDLA<1:0> LC1G4POL LC1G3POL LC1G4D2N LC1G4D1T G1POLA — — — — — — G1CS0 3Ah CWG1CON1 3Bh CWG1CON2 G1ASE G1ARSEN 3Ch CWG1DBR — — 3Dh CWG1DBF — — 3Eh VREGCON — — — — — — VREGPM1 3Fh BORCON SBOREN BORFS — — — — — Legend: Note 1: — — G1IS<1:0> 0000 0--0 0000 0--0 xxxx --xx uuuu --uu G1ASDCLC1 G1ASDFLT xx-- --xx uu-- --uu CWG1DBR<5:0> --xx xxxx --uu uuuu CWG1DBF<5:0> --xx xxxx --uu uuuu Reserved ---- --01 ---- --01 BORRDY 10-- ---q uu-- ---u x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. DS40001585C-page 16 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC All devices have an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate Stack Overflow or Stack Underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. 8 PCLATH<4:0> 5 Instruction with PCL as Destination ALU Result PCLATH PCH 12 11 10 PCL 8 0 7 PC GOTO, CALL 2 PCLATH<4:3> 11 OPCODE <10:0> PCLATH 2.3.1 STACK MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper five bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower eight bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. 2.4 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-4. A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x40 FSR INDF FSR FSR,7 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). 2011-2015 Microchip Technology Inc. DS40001585C-page 17 PIC10(L)F320/322 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322 Direct Addressing 6 From Opcode Indirect Addressing 0 7 File Select Register 0 Location Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. DS40001585C-page 18 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 3.0 DEVICE CONFIGURATION Device configuration consists of Configuration Word and Device ID. 3.1 Configuration Word There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word at 2007h. 2011-2015 Microchip Technology Inc. DS40001585C-page 19 PIC10(L)F320/322 3.2 Register Definitions: Configuration Word REGISTER 3-1: CONFIG: CONFIGURATION WORD U-1 R/P-1/1 — R/P-1/1 WRT<1:0> R/P-1/1 R/P-1/1 R/P-1/1 BORV LPBOR LVP bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE bit 8 R/P-1/1 R/P-1/1 R/P-1/1 WDTE<1:0> R/P-1/1 BOREN<1:0> bit 7 R/P-1/1 FOSC bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit bit 13 Unimplemented: Read as ‘1’ bit 12-11 WRT<1:0>: Flash Memory Self-Write Protection bits 256 W Flash memory: PIC10(L)F320: 11 =Write protection off 10 =000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control 01 =000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control 00 =000h to 0FFh write-protected, no addresses may be modified by PMCON control 512 W Flash memory: PIC10(L)F322: 11 =Write protection off 10 =000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control 01 =000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control 00 =000h to 1FFh write-protected, no addresses may be modified by PMCON control bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage (VBOR), low trip point selected. 0 = Brown-out Reset voltage (VBOR), high trip point selected. bit 9 LPBOR: Low-Power Brown-out Reset Enable bit 1 = Low-power Brown-out Reset is enabled 0 = Low-power Brown-out Reset is disabled bit 8 LVP: Low-Voltage Programming Enable bit 1 = Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR. 0 = High Voltage on MCLR/VPP must be used for programming bit 7 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA3 bit. Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. Once enabled, code-protect can only be disabled by bulk erasing the device. See VBOR parameter for specific trip point voltages. DS40001585C-page 20 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 3-1: CONFIG: CONFIGURATION WORD (CONTINUED) bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset enabled; SBOREN bit is ignored 10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = Brown-out Reset controlled by the SBOREN bit in the BORCON register 00 = Brown-out Reset disabled; SBOREN bit is ignored bit 0 FOSC: Oscillator Selection bit 1 = EC on CLKIN pin 0 = INTOSC oscillator I/O function available on CLKIN pin Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. Once enabled, code-protect can only be disabled by bulk erasing the device. See VBOR parameter for specific trip point voltages. 2011-2015 Microchip Technology Inc. DS40001585C-page 21 PIC10(L)F320/322 3.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory protection are controlled independently. Internal access to the program memory and data memory are unaffected by any code protection setting. 3.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 3.4 “Write Protection” for more information. 3.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word define the size of the program memory block that is protected. 3.5 User ID Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 3.6 “Device ID and Revision ID” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC10(L)F320/322 Flash Memory Programming Specification” (DS41572). DS40001585C-page 22 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 3.6 Device ID and Revision ID The memory location 2006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 9.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 3.7 Register Definitions: Device and Revision REGISTER 3-2: DEVID: DEVICE ID REGISTER(1) R R R R R R DEV<8:3> bit 13 R R bit 8 R R R DEV<2:0> R R R REV<4:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-5 ‘0’ = Bit is cleared DEV<8:0>: Device ID bits DEVID<13:0> Values Device DEV<8:0> bit 4-0 REV<4:0> PIC10F320 10 1001 101 x xxxx PIC10LF320 10 1001 111 x xxxx PIC10F322 10 1001 100 x xxxx PIC10LF322 10 1001 110 x xxxx REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. 2011-2015 Microchip Technology Inc. DS40001585C-page 23 PIC10(L)F320/322 4.0 OSCILLATOR MODULE 4.1 Overview The system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software. The oscillator module has a variety of clock sources and selection features that allow it to be used in a range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module. FIGURE 4-1: Clock source modes are configured by the FOSC bit in Configuration Word (CONFIG). 1. 2. EC oscillator from CLKIN. INTOSC oscillator, CLKIN not enabled. PIC10(L)F320/322 CLOCK SOURCE BLOCK DIAGRAM IRCF<2:0> 3 HFINTOSC 16 MHz HFIOFR(1) HFIOFS(1) 111 110 101 100 011 010 250 kHz 31 kHz 001 000 MUX Divider LFINTOSC 31 kHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz INTOSC FOSC (Configuration Word) LFIOFR(1) 0 CLKIN MUX EC 1 System Clock (CPU and Peripherals) CLKR CLKROE Note 1: HFIOFR, HFIOFS and LFIOFR are Status bits in the OSCCON register. DS40001585C-page 24 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 4.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module, which has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. • The External Clock mode (EC) relies on an external signal for the clock source. The system clock can be selected between external or internal clock sources via the FOSC bit of the Configuration Word. 4.3 Internal Clock Modes The internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate all internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz (LFINTOSC). The HFINTOSC consists of a primary and secondary clock. The secondary clock starts first with rapid startup time, but low accuracy. The secondary clock ready signal is indicated with the HFIOFR bit of the OSCCON register. The primary clock follows with slower start-up time and higher accuracy. The primary clock is stable when the HFIOFS bit of the OSCCON register bit goes high. 4.3.1 4.3.2 FREQUENCY SELECT BITS (IRCF) The output of the 16 MHz HFINTOSC is connected to a divider and multiplexer (see Figure 4-1). The Internal Oscillator Frequency Select bits (IRCF) of the OSCCON register select the frequency output of the internal oscillator: • HFINTOSC - 16 MHz - 8 MHz (default after Reset) - 4 MHz - 2 MHz - 1 MHz - 500 kHz - 250 kHz • LFINTOSC - 31 kHz Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 8 MHz. The user can modify the IRCF bits to select a different frequency. There is no delay when switching between HFINTOSC frequencies with the IRCF bits. This is because the switch involves only a change to the frequency output divider. Start-up delay specifications are located Section 24.0 “Electrical Specifications”. in INTOSC MODE When the FOSC bit of the Configuration Word is cleared, the INTOSC mode is selected. When INTOSC is selected, CLKIN pin is available for general purpose I/O. See Section 3.0 “Device Configuration” for more information. 2011-2015 Microchip Technology Inc. DS40001585C-page 25 PIC10(L)F320/322 4.4 Register Definitions: Reference Clock Control REGISTER 4-1: CLKRCON – REFERENCE CLOCK CONTROL REGISTER U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 U-0 — CLKROE — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 CLKROE: Reference Clock Output Enable bit 1 = Reference Clock output (CLKR), regardless of TRIS 0 = Reference Clock output disabled bit 5-0 Unimplemented: Read as ‘0’ 4.5 Register Definitions: Oscillator Control REGISTER 4-2: U-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-1/1 — R/W-1/1 R/W-0/0 IRCF<2:0> R-0/0 U-0 R-0/0 R-0/0 HFIOFR — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: INTOSC (FOSC) Frequency Select bits 111 = 16 MHz 110 = 8 MHz (default value) 101 = 4 MHz 100 = 2 MHz 011 = 1 MHz 010 = 500 kHz 001 = 250 kHz 000 = 31 kHz (LFINTOSC) bit 3 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = 16 MHz Internal Oscillator (HFINTOSC) is ready 0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready bit 2 Unimplemented: Read as ‘0’ bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = 31 kHz Internal Oscillator (LFINTOSC) is ready 0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = 16 MHz Internal Oscillator (HFINTOSC) is stable 0 = 16 MHz Internal Oscillator (HFINTOSC) is not stable DS40001585C-page 26 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 4.6 External Clock Mode 4.6.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. TABLE 4-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 CLKRCON — CLKROE OSCCON — Legend: CONFIG Legend: Bit 4 — — Bit 3 IRCF<2:0> Bit 2 Bit 1 Bit 0 Register on Page — — — — 26 HFIOFR — LFIOFR HFIOFS 26 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by ECWG. TABLE 4-2: Name Bit 5 Bits SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — WRT<1:0> 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BORV LPBOR BOREN<1:0> Bit 8/0 LVP FOSC Register on Page 20 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. 2011-2015 Microchip Technology Inc. DS40001585C-page 27 PIC10(L)F320/322 5.0 RESETS There are multiple ways to reset this device: • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSP™ Programming Mode Exit MCLRE Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out Reset R LPBOR Reset PWRT Done PWRTE LFINTOSC BOR Active(1) Note 1: See Table 5-1 for BOR active conditions. DS40001585C-page 28 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 5.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Word. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Word. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 5-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Register 3-1. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 5-2 for more information. BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Device Operation upon: Release of POR/Wake- up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 5.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Word are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 5.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Word are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Word are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device startup is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 2011-2015 Microchip Technology Inc. DS40001585C-page 29 PIC10(L)F320/322 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. Register Definition: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Word = 01: 1 = BOR enabled 0 = BOR disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers Sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Word. DS40001585C-page 30 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 5.4 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.1 ENABLING LPBOR 5.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 8.0 “Watchdog Timer” for more information. 5.7 Programming Mode ICSP Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. 5.8 Power-Up Timer The LPBOR is controlled by the LPBOR bit of Configuration Word. When the device is erased, the LPBOR module defaults to enabled. The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 5.4.1.1 The Power-up Timer is controlled by the PWRTE bit of Configuration Word. LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal which goes to the PCON register and to the power control block. 5.5 The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE and the LVP bit of Configuration Word (Table 52). MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 5.5.1 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. MCLR TABLE 5-2: 5.9 Power-up Timer runs to completion (if enabled). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 4.0 “Oscillator Module” for more information. The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 5.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. 2011-2015 Microchip Technology Inc. DS40001585C-page 31 PIC10(L)F320/322 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001585C-page 32 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 5.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up from Sleep u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep TABLE 5-4: Condition RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1000 ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up from Sleep PC + 1 0000 0uuu ---- --uu Brown-out Reset 0000h 0001 1uuu ---- --u0 0001 0uuu ---- --uu Condition Interrupt Wake-up from Sleep PC + 1 (1) Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2011-2015 Microchip Technology Inc. DS40001585C-page 33 PIC10(L)F320/322 5.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-On Reset (POR) • Brown-Out Reset (BOR) The PCON register bits are shown in Register 5-2. 5.12 Register Definition: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W/HC-q/u R/W/HC-q/u — — — — — — POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 30 — — — — — — POR BOR 34 IRP RP1 RP0 TO PD Z DC C 13 — — SWDTEN 48 PCON STATUS WDTCON WDTPS<4:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. TABLE 5-6: Name CONFIG Bits SUMMARY OF CONFIGURATION WORD WITH RESETS Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — WRT<1:0> 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BORV LPBOR BOREN<1:0> Bit 8/0 LVP FOSC Register on Page 20 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Reset. DS40001585C-page 34 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 6.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Context Saving during Interrupts Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 6-1. FIGURE 6-1: INTERRUPT LOGIC Rev. 10-000010A 1/13/2014 TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> 2011-2015 Microchip Technology Inc. GIE DS40001585C-page 35 PIC10(L)F320/322 6.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 register) 6.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 6-2 and Section 6.3 “Interrupts During Sleep” for more details. The INTCON and PIR1 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001585C-page 36 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 6-2: INTERRUPT LATENCY INTOSC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC 2011-2015 Microchip Technology Inc. PC+2 NOP NOP DS40001585C-page 37 PIC10(L)F320/322 FIGURE 6-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 INTOSC CLKR (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 24.0 “Electrical Specifications”. 4: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001585C-page 38 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 6.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 7.0 “PowerDown Mode (Sleep)” for more details. 6.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. EXAMPLE 6-1: MOVWF SWAPF Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Table 1-2). This makes context save and restore operations simpler. The code shown in Example 6-1 can be used to: • • • • • Store the W register Store the STATUS register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register Note: These devices do not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. SAVING STATUS AND W REGISTERS IN RAM W_TEMP STATUS,W MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF 6.5 STATUS W_TEMP,F W_TEMP,W 2011-2015 Microchip Technology Inc. ;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register ;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W DS40001585C-page 39 PIC10(L)F320/322 6.6 Interrupt Control Registers REGISTER 6-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit 1 = Enables the interrupt-on-change interrupt 0 = Disables the interrupt-on-change interrupt bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001585C-page 40 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 6-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — ADIE — NCO1IE CLC1IE — TMR2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit 1 = Enables the NCO overflow interrupt 0 = Disables the NCO overflow interrupt bit 3 CLC1IE: Configurable Logic Block Interrupt Enable bit 1 = Enables the CLC interrupt 0 = Disables the CLC interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 Match interrupt 0 = Disables the TMR2 to PR2 Match interrupt bit 0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2011-2015 Microchip Technology Inc. DS40001585C-page 41 PIC10(L)F320/322 REGISTER 6-3: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — ADIF — NCO1IF CLC1IF — TMR2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed 0 = The A/D conversion is not complete bit 5 Unimplemented: Read as ‘0’ bit 4 NCO1IF: Numerically Controlled Oscillator Interrupt Flag bit 1 = NCO1 overflow occurred (must be cleared in software) 0 = No NCO1 overflow bit 3 CLC1IF: Configurable Logic Block Rising Edge Interrupt Flag bit 1 = CLC interrupt occurred (must be cleared in software) 0 = No CLC Interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match Note: The match must occur the number of times specified by the TMR2 postscaler (Register 17-1). bit 0 Unimplemented: Read as ‘0’ Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001585C-page 42 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 IOCAF — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 76 IOCAN — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 75 IOCAP — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 75 Name INTCON OPTION_REG WPUEN INTEDG T0CS T0SE PSA PIE1 — ADIE — NCO1IE CLC1IE — PS<2:0> TMR2IE — 95 41 PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — 42 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts. 2011-2015 Microchip Technology Inc. DS40001585C-page 43 PIC10(L)F320/322 7.0 POWER-DOWN MODE (SLEEP) 7.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. ADC is unaffected, if the dedicated FRC clock is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • • I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC CWG and NCO modules using HFINTOSC I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include the FVR module. See Section 12.0 “Fixed Voltage Reference (FVR)” for more information on these modules. DS40001585C-page 44 External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.10 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. The Complementary Waveform Generator (CWG) and the Numerically Controlled Oscillator (NCO) modules can utilize the HFINTOSC oscillator as their respective clock source. Under certain conditions, when the HFINTOSC is selected for use with the CWG or NCO modules, the HFINTOSC will remain active during Sleep. This will have a direct effect on the Sleep mode current. Please refer to 21.0 “Complementary Waveform Generator (CWG) Module” and 20.0 “Numerically Controlled Oscillator (NCO) Module” for more information. 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 7.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. FIGURE 7-1: Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 INTOSC T1OSC(2) CLKR Interrupt flag Interrupt Latency (1) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: PC PC + 1 Inst(PC) = Sleep PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) Inst(PC - 1) Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 STATUS IRP RP1 RP0 TO — — Legend: PC + 2 GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. Applicable only if the T1 Oscillator exists on this particular device. TABLE 7-1: WDTCON PC + 2 Bit 3 Bit 2 Bit 1 PD Z DC WDTPS<4:0> Bit 0 Register on Page C 13 SWDTEN 48 — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode. 2011-2015 Microchip Technology Inc. DS40001585C-page 45 PIC10(L)F320/322 8.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 8-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep DS40001585C-page 46 WDTPS<4:0> 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 8.1 Independent Clock Source 8.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 24.0 “Electrical Specifications” for the LFINTOSC tolerances. 8.2 Time-Out Period The WDTPS bits of the WDTCON register set the timeout period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 8.4 Clearing the WDT The WDT is cleared when any of the following conditions occur: WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word. See Table 8-1. When the WDTE bits of Configuration Word are set to ‘11’, the WDT is always on. • • • • • • WDT protection is active during Sleep. See Table 8-2 for more information. 8.2.2 8.5 8.2.1 WDT IS ALWAYS ON WDT IS OFF IN SLEEP When the WDTE bits of Configuration Word are set to ‘10’, the WDT is on, except in Sleep. WDT protection is not active during Sleep. 8.2.3 WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Word are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged by Sleep. See Table 8-1 for more details. TABLE 8-1: Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 2.0 “Memory Organization” and Register 2-1 for more information. WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode WDT Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X 01 0 00 TABLE 8-2: Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled X X Active Disabled Disabled WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Exit Sleep Change INTOSC divider (IRCF bits) 2011-2015 Microchip Technology Inc. Unaffected DS40001585C-page 47 PIC10(L)F320/322 8.6 Watchdog Control Register REGISTER 8-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS<4:0> R/W-0/0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. DS40001585C-page 48 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 8-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON — STATUS IRP RP1 — — WDTCON Bit 5 Bit 4 IRCF<2:0> RP0 TO Bit 3 Bit 2 Bit 1 Bit 0 Register on Page HFIOFR — LFIOFR HFIOFS 26 PD Z DC C 13 SWDTEN 48 WDTPS<4:0> Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 8-4: Name CONFIG Bits SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — WRT<1:0> 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BORV LPBOR BOREN<1:0> Bit 8/0 LVP FOSC Register on Page 20 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. 2011-2015 Microchip Technology Inc. DS40001585C-page 49 PIC10(L)F320/322 9.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 9-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/ erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Word) and write protection (WRT<1:0> bits in Configuration Word). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Word. 9.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 512 words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. DS40001585C-page 50 9.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 9.2 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 9-1 for Erase Row size and the number of write latches for Flash program memory. 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 9-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC10(L)F320 PIC10(L)F322 9.2.1 Row Erase (words) Write Latches (words) 16 16 READING THE FLASH PROGRAM MEMORY FIGURE 9-1: FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set. Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2011-2015 Microchip Technology Inc. DS40001585C-page 51 PIC10(L)F320/322 FIGURE 9-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 9-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; not required on devices with 1 Bank of SFRs ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 9-2) Ignored (Figure 9-2) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001585C-page 52 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 9.2.2 Note: FLASH MEMORY UNLOCK SEQUENCE A delay of at least 100 s is required after Power-On Reset (POR) before executing a Flash memory unlock sequence. The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • Row Erase • Load program memory write latches • Write of program memory write latches to program memory • Write of program memory write latches to User IDs The unlock sequence consists of the following steps: FIGURE 9-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 Initiate Write or Erase operation (WR = 1) 1. Write 55h to PMCON2 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 Instruction Fetched ignored NOP execution forced 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Instruction Fetched ignored NOP execution forced End Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2011-2015 Microchip Technology Inc. DS40001585C-page 53 PIC10(L)F320/322 9.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 9-2. After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FIGURE 9-4: FLASH PROGRAM MEMORY ERASE FLOWCHART Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence Figure 9-3 (FIGURE x-x) CPU stalls while ERASE operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation DS40001585C-page 54 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 EXAMPLE 9-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF PMCON1,WREN INTCON,GIE 2011-2015 Microchip Technology Inc. ; Disable ints so required sequences will execute properly ; not required on devices with 1 Bank of SFRs ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts DS40001585C-page 55 PIC10(L)F320/322 9.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 9-5 (row writes to program memory with 16 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper ten bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower five bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 9.2.2 “Flash Memory Unlock Sequence”). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 9.2.2 “Flash Memory Unlock Sequence”). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 9-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. DS40001585C-page 56 2011-2015 Microchip Technology Inc. BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 7 1 0 7 4 3 PMADRL PMADRH - - - - - - - r4 r3 r2 r1 r0 c3 c2 0 7 - c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 Program Memory Write Latches 4 14 Write Latch #0 00h PMADRL<3:0> 14 5 14 14 Write Latch #1 01h 14 Write Latch #14 Write Latch #15 0Eh 0Fh 14 14 14 PMADRH<0>: PMADRL<7:4> CFGS = 0 2011-2015 Microchip Technology Inc. Row Address Decode Row Addr Addr Addr Addr 000h 0000h 0001h 000Eh 000Fh 001h 0010h 0011h 001Eh 001Fh 002h 0020h 0021h 002Eh 002Fh 01Eh 01E0h 01E1h 01EEh 01EFh 01Fh 01F0h 01F1h 01FEh 01FFh Flash Program Memory 000h 2000h - 2003h USER ID 0 - 3 CFGS = 1 2004h - 2005h 2006h 2007h 2008h reserved DEVICEID REVID Configuration Word reserved Configuration Memory PIC10(L)F320/322 DS40001585C-page 57 FIGURE 9-5: PIC10(L)F320/322 FIGURE 9-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure9-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure9-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation DS40001585C-page 58 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 EXAMPLE 9-3: WRITING TO FLASH PROGRAM MEMORY ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '00') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory ; BANKSEL PMADRH MOVF ADDRH,W ;Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVF DATAADDR,W ;Load initial data address MOVWF FSR ; LOOP MOVF INDF,W ;Load first data byte into lower MOVWF PMDATL ; INCF FSR,F ;Next byte MOVF INDF,W ;Load second data byte into upper MOVWF PMDATH ; INCF FSR,F ; BANKSEL PMCON1 BSF PMCON1,WREN ;Enable writes BCF INTCON,GIE ;Disable interrupts (if using) BTFSC INTCON,GIE ;See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ;Start of required write sequence: MOVWF PMCON2 ;Write 55h MOVLW 0AAh ; MOVWF PMCON2 ;Write 0AAh BSF PMCON1,WR ;Set WR bit to begin write NOP ;Required to transfer data to the buffer NOP ;registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF PMCON1,WREN ;Disable writes BSF INTCON,GIE ;Enable interrupts (comment out if not using interrupts) BANKSEL PMADRL MOVF PMADRL, W INCF PMADRL,F ;Increment address ANDLW 0x03 ;Indicates when sixteen words have been programmed SUBLW 0x03 ;Change value for different size write blocks ;0x0F = 16 words ;0x0B = 12 words ;0x07 = 8 words ;0x03 = 4 words BTFSS STATUS,Z ;Exit on a match, GOTO LOOP ;Continue if more data needs to be written 2011-2015 Microchip Technology Inc. DS40001585C-page 59 PIC10(L)F320/322 9.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FIGURE 9-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure9-2 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure9-4 x.x) Figure Write Operation use RAM image (Figure9-5 x.x) Figure End Modify Operation DS40001585C-page 60 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 9.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Word can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<13> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 9-2. When read access is initiated on an address outside the parameters listed in Table 9-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. TABLE 9-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 2000h-2003h 2006h 2007h User IDs Device ID/Revision ID Configuration Word Yes Yes Yes Yes No No EXAMPLE 9-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; not required on devices with 1 Bank of SFRs ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 9-2) Ignored (See Figure 9-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2011-2015 Microchip Technology Inc. DS40001585C-page 61 PIC10(L)F320/322 9.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 9-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure Figure 9-2x.x) PMDAT = RAM image ? Yes No No Fail Verify Operation Last Word ? Yes End Verify Operation DS40001585C-page 62 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 9.6 Flash Program Memory Control Registers REGISTER 9-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDAT<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a Program Memory Read command. REGISTER 9-2: PMDATH: PROGRAM MEMORY DATA HIGH U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDAT<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a Program Memory Read command. 2011-2015 Microchip Technology Inc. DS40001585C-page 63 PIC10(L)F320/322 REGISTER 9-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Program Memory Read Address low bits REGISTER 9-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — PMADR8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 PMADR8: Program Memory Read Address High bit DS40001585C-page 64 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 9-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 — CFGS LWLO R/W/HC-0/0 R/W/HC-0/q(2) FREE WRERR R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs an write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read. Note 1: 2: 3: Unimplemented bit, read as ‘1’. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). 2011-2015 Microchip Technology Inc. DS40001585C-page 65 PIC10(L)F320/322 REGISTER 9-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 PMCON1 — CFGS LWLO FREE WRERR WREN WR RD 65 PMCON2 Program Memory Control Register 2 66 PMADRL PMADR<7:0> 64 — PMADRH — — — PMDATL — PMDATH Legend: CONFIG Legend: — — PMADR8 — 64 63 PMDAT<13:8> 63 — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module. TABLE 9-4: Name — PMDAT<7:0> Bits SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — WRT<1:0> 7:0 CP MCLR PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 BORV LPBOR BOREN<1:0> Bit 8/0 LVP FOSC Register on Page 20 — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. DS40001585C-page 66 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 10.0 I/O PORT FIGURE 10-1: Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. PORTA has three standard registers for its operation. These registers are: • TRISA register (data direction) • PORTA register (reads the levels on the pins of the device) • LATA register (output latch) Some ports may have one or more of the following additional registers. These registers are: • ANSELA (analog select) • WPUA (weak pull-up) I/O PORT OPERATION Read LATA D Write LATA Write PORTA TRISA Q CK VDD Data Register Data Bus I/O pin Read PORTA To peripherals ANSELA VSS The Data Latch (LATA register) is useful for readmodify-write operations on the value that the I/O pins are driving. A write operation to the LATA register has the same effect as a write to the corresponding PORTA register. A read of the LATA register reads of the values held in the I/O PORT latches, while a read of the PORTA register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELA register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. EXAMPLE 10-1: ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00000011' TRISA ;not required on devices ;Init PORTA ;not required on devices ; ;not required on devices ;digital I/O ;not required on devices ;Set RA<1:0> as inputs ;and set RA<2:3> as ;outputs 2011-2015 Microchip Technology Inc. with 1 Bank of SFRs with 1 Bank of SFRs with 1 Bank of SFRs with 1 Bank of SFRs DS40001585C-page 67 PIC10(L)F320/322 10.1 PORTA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 10-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 10-1 shows how to initialize PORTA. Reading the PORTA register (Register 10-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 10.1.3 Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 10-1. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table 10-1. TABLE 10-1: Function Priority(1) RA0 ICSPDAT CWG1A PWM1 RA0 RA1 CWG1B PWM2 CLC1 RA1 RA2 NCO1 CLKR RA2 RA3 None WEAK PULL-UPS Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA<3:0> enable or disable each pull-up (see Register 10-5). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION_REG register. 10.1.2 PORTA OUTPUT PRIORITY Pin Name The TRISA register (Register 10-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 10.1.1 PORTA FUNCTIONS AND OUTPUT PRIORITIES Note 1: Priority listed from highest to lowest. ANSELA REGISTER The ANSELA register (Register 10-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS40001585C-page 68 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 10.2 Register Definitions: PORTA REGISTER 10-1: PORTA: PORTA REGISTER U-0 U-0 U-0 U-0 R-x/x R/W-x/x R/W-x/x R/W-x/x — — — — RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RA<3:0>: PORTA I/O Value bits (RA3 is read-only) Note 1: Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register return actual I/O pin values. REGISTER 10-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 U-0 U-0 U-1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — —(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISA<2:0>: RA<2:0> Port I/O Tri-State Control bits 1 = Port output driver is disabled 0 = Port output driver is enabled Note 1: Unimplemented, read as ‘1’. 2011-2015 Microchip Technology Inc. DS40001585C-page 69 PIC10(L)F320/322 REGISTER 10-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits Note 1: Writes to PORTx are actually written to the corresponding LATx register. Reads from LATx register return register values, not I/O pin values. REGISTER 10-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — — — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled. 0 = Digital I/O. Pin is assigned to port or Digital special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin. DS40001585C-page 70 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 10-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WPUA<3:0>: Weak Pull-up PORTA Control bits 1 = Weak Pull-up enabled(1) 0 = Weak Pull-up disabled. Note 1: Enabling weak pull-ups also requires that the WPUEN bit of the OPTION_REG register be cleared (Register 16-1). 2011-2015 Microchip Technology Inc. DS40001585C-page 71 PIC10(L)F320/322 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — — — ANSA2 ANSA1 ANSA0 70 IOCAF — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 76 IOCAN — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 75 IOCAP — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 75 LATA — — — — — LATA2 LATA1 LATA0 70 PORTA — — — — RA3 RA2 RA1 RA0 69 (1) TRISA2 TRISA1 TRISA0 69 WPUA2 WPUA1 WPUA0 71 Name TRISA — — — — WPUA — — — — — WPUA3 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: Unimplemented, read as ‘1’. DS40001585C-page 72 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 11.0 INTERRUPT-ON-CHANGE The PORTA pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTA pin, or combination of PORTA pins, can be configured to generate an interrupt. The Interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 11-1 is a block diagram of the IOC module. 11.1 Enabling the Module To allow individual PORTA pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 11.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the interrupt-on-change pins of PORTA. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx bits. 11.4 Clearing Interrupt Flags The individual status flags, (IOCAFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 11-1: 11.2 Individual Pin Configuration For each PORTA pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCAPx bit of the IOCAP register is set. To enable a pin to detect a falling edge, the associated IOCANx bit of the IOCAN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, respectively. 2011-2015 Microchip Technology Inc. MOVLW XORWF ANDWF 11.5 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep. DS40001585C-page 73 PIC10(L)F320/322 FIGURE 11-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q D S Q To Data Bus IOCAFx CK CK Write IOCAFx R IOCIE R Q2 From all other IOCAFx individual pin detectors Q1 Q2 Q3 DS40001585C-page 74 IOC Interrupt to CPU Core Q1 Q1 Q2 Q2 Q3 Q3 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 11.6 Interrupt-On-Change Registers REGISTER 11-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’. bit 3-0 IOCAP<3:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge.( 1) 0 = Interrupt-on-Change disabled for the associated pin. Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1). REGISTER 11-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’. bit 3-0 IOCAN<3:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge.( 1) 0 = Interrupt-on-Change disabled for the associated pin. Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1). 2011-2015 Microchip Technology Inc. DS40001585C-page 75 PIC10(L)F320/322 REGISTER 11-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-4 Unimplemented: Read as ‘0’. bit 3-0 IOCAF<3:0>: Interrupt-on-Change PORTA Flag bits 1 = An enable change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx.( 1) 0 = No change was detected, or the user cleared the detected change. Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1). TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 IOCAF — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 76 IOCAN — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 75 IOCAP — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 75 TRISA — — — — —(1) TRISA2 TRISA1 TRISA0 69 Name INTCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. Note 1: Unimplemented, read as ‘1’. DS40001585C-page 76 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 12.0 FIXED VOLTAGE REFERENCE (FVR) 12.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through an independent programmable gain amplifier. The amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 15.0 “Analog-to-Digital Converter (ADC) Module” for additional information. • ADC input channel The FVR can be enabled by setting the FVREN bit of the FVRCON register. To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clearing the ADFVR<1:0> bits. 12.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 24.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 12-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 x1 x2 x4 FVR (To ADC Module) 1.024V Fixed Reference + FVREN - FVRRDY Any peripheral requiring the Fixed Reference (See Table 12-1) TABLE 12-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC BOR IVR Conditions Description FOSC = 1 EC on CLKIN pin. BOREN<1:0> = 11 BOR always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. All PIC10F320/322 devices, when VREGPM1 = 1 and not in Sleep The device runs off of the Power-Save mode regulator when in Sleep mode. 2011-2015 Microchip Technology Inc. DS40001585C-page 77 PIC10(L)F320/322 12.3 FVR Control Registers REGISTER 12-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q FVREN FVRRDY(1) R/W-0/0 TSEN (3) R/W-0/0 TSRNG (3) U-0 U-0 — — R/W-0/0 R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 Unimplemented: Read as ‘0 ‘ bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = ADC Fixed Voltage Reference Peripheral output is off. Note 1: 2: 3: FVRRDY indicates the true state of the FVR. Fixed Voltage Reference output cannot exceed VDD. See Section 14.0 “Temperature Indicator Module” for additional information. TABLE 12-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — Bit 1 Bit 0 ADFVR<1:0> Register on page 78 Legend: Shaded cells are not used with the Fixed Voltage Reference. DS40001585C-page 78 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 13.0 INTERNAL VOLTAGE REGULATOR (IVR) The Internal Voltage Regulator (IVR), which provides operation above 3.6V is available on: • PIC10F320 • PIC10F322 This circuit regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. When VDD approaches the regulated voltage, the IVR output automatically tracks the input voltage. The IVR operates in one of three power modes based on user configuration and peripheral selection. The operating power modes are: - High - Low - Power-Save Sleep mode Power modes are selected automatically depending on the device operation, as shown in Table 13-1. Tracking mode is selected automatically when VDD drops below the safe operating voltage of the core. IVR is disabled in Tracking mode, but will consume power. See Section 24.0 “Electrical Specifications” for more information. Note: TABLE 13-1: VREGPM1 Bit IVR POWER MODES - REGULATED Sleep Mode Memory Bias Power Mode EC Mode or INTOSC = 16 MHz (HP Bias) INTOSC = 1 to 8 MHz (MP Bias) INTOSC = 31 kHz to 500 kHz (LP Bias) 0 Yes Don’t Care No HFINTOSC 1 Yes No Peripherals Note 1: Forced to Low-Power mode by any of the following conditions: • BOR is enabled • HFINTOSC is an active peripheral source • Self-write is active • ADC is in an active conversion x No 2011-2015 Microchip Technology Inc. IVR Power Mode High Low Low Power Save(1) DS40001585C-page 79 PIC10(L)F320/322 REGISTER 13-1: U-0 — VREGCON: VOLTAGE REGULATOR CONTROL REGISTER U-0 — U-0 — bit 7 Legend: R = Readable bit u = Bit is unchanged ‘1’ = Bit is set W = Writable bit x = Bit is unknown ‘0’ = Bit is cleared U-0 — U-0 — U-0 — R/W-0/0 VREGPM1 R/W-1/1 Reserved bit 0 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM1: Voltage Regulator Power Mode Selection bit 1 = Power-Save Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up. 0 = Low-Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up. bit 0 Reserved: Maintain this bit set. DS40001585C-page 80 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev. 10-000069A 7/31/2013 VDD TSEN The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 14.1 TEMPERATURE CIRCUIT DIAGRAM TSRNG VOUT To ADC Temp. Indicator Circuit Operation Figure 14-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 14-1 describes the output characteristics of the temperature indicator. 14.2 Minimum Operating VDD vs. Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. High Range: VOUT = VDD - 4VT When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Low Range: VOUT = VDD - 2VT Table 14-1 shows the recommended minimum VDD vs. range setting. EQUATION 14-1: VOUT RANGES The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 12.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. TABLE 14-1: RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 14.3 Temperature Output The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 15.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON0 register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. 2011-2015 Microchip Technology Inc. 14.4 ADC Acquisition Time DS40001585C-page 81 PIC10(L)F320/322 TABLE 14-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — ADCON ADRES ADCS<2:0> CHS<2:0> A/D Result Register Bit 1 Bit 0 ADFVR<1:0> GO/ DONE ADON Register on Page 78 88 89 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the temperature indicator module. DS40001585C-page 82 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) converts an analog input signal to an 8-bit binary representation of that signal. This device uses three analog input channels, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates an 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure 15-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be internally generated. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. FIGURE 15-1: ADC SIMPLIFIED BLOCK DIAGRAM VREF- = Vss AN0 000 AN1 001 AN2 010 Reserved 011 Reserved Reserved 100 Temp Indicator 110 FVR 111 101 VREF+ = VDD ADC 8 GO/DONE ADRES ADON(1) CHS<2:0>(2) Note 1: 2: VSS When ADON = 0, all multiplexer inputs are disconnected. See ADCON register (Register 15-1) for detailed analog channel selection per device. 2011-2015 Microchip Technology Inc. DS40001585C-page 83 PIC10(L)F320/322 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • Port configuration Channel selection ADC conversion clock source Interrupt control 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 10.0 “I/O Port” for more information. Note: 15.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to five channel selections available: • AN<2:0> pins • Temperature Indicator • FVR (Fixed Voltage Reference) Output Refer to Section 12.0 “Fixed Voltage Reference (FVR)” and Section 14.0 “Temperature Indicator Module” for more information on these channel selections. 15.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON register (Register 15-1). There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal RC oscillator) The time to complete one bit conversion is defined as TAD. One full 8-bit conversion requires 9.5 TAD periods as shown in Figure 15-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 24.0 “Electrical Specifications” for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. The CHS bits of the ADCON register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 15.2 “ADC Operation” for more information. 15.1.3 ADC VOLTAGE REFERENCE There is no external voltage reference connections to the ADC. Only VDD can be used as a reference source. The FVR is only available as an input channel and not a VREF+ input to the ADC. DS40001585C-page 84 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 125 ns(1) 250 ns(1) 500 ns(1) 2.0 s FOSC/4 100 (1) 250 ns (1) FOSC/8 001 0.5 s(1) FOSC/16 101 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(2) 1.0 s 2.0 s 4.0 s 16.0 s(2) 010 2.0 s 4.0 s FOSC/64 110 4.0 s FRC x11 1.0-6.0 s(1,3) FOSC/32 Legend: Note 1: 2: 3: 500 ns 8.0 s 8.0 s 16.0 s (2) 1.0-6.0 s(1,3) 32.0 s(2) (2) 64.0 s(2) (2) 1.0-6.0 s(1,3) 1.0-6.0 s(1,3) Shaded cells are outside of recommended range. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 b2 b4 b5 b0 b7 b6 b1 b3 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRES is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 2011-2015 Microchip Technology Inc. DS40001585C-page 85 PIC10(L)F320/322 15.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. 15.2 15.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.5 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRES register with new conversion result 15.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRES register will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: 15.2.4 A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. DS40001585C-page 86 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 15.2.5 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.4 “A/D Acquisition Requirements”. 2011-2015 Microchip Technology Inc. DS40001585C-page 87 PIC10(L)F320/322 15.3 ADC Register Definitions The following registers are used to control the operation of the ADC. REGISTER 15-1: R/W-0/0 ADCON: A/D CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 ADCS<2:0> R/W-0/0 R/W-0/0 CHS<2:0> R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 4-2 CHS<2:0>: Analog Channel Select bits 111 = FVR (Fixed Voltage Reference) Buffer Output(2) 110 = Temperature Indicator(1) 101 = Reserved. No channel connected. 100 = Reserved. No channel connected. 011 = Reserved. No channel connected. 010 = AN2 001 = AN1 000 = AN0 bit 1 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (Setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete.) If this bit is cleared while a conversion is in progress, the conversion will stop and the results of the conversion up to this point will be transferred to the result registers, but the ADIF interrupt flag bit will not be set. If ADON = 0: 0 = A/D conversion not in progress bit 0 Note 1: 2: ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current See Section 14.0 “Temperature Indicator Module” for more information. See Section 12.0 “Fixed Voltage Reference (FVR)” for more information. DS40001585C-page 88 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 15-2: R/W-x/u ADRES: ADC RESULT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit result 2011-2015 Microchip Technology Inc. DS40001585C-page 89 PIC10(L)F320/322 15.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-3. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 15-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 15-1 may be used. This equation assumes that 1/2 LSb error is used (511 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C + Temperature - 25°C 0.05µs/°C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 – -------------------------n+1 2 –1 ;[1] VCHOLD charged to within 1/2 lsb –TC ---------- RC V AP P LI ED 1 – e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED – Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------n+1 2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD R IC + R SS + R S ln(1/511) = – 10pF 1k + 7k + 10k ln(0.001957) = 1.12 µs Therefore: T A CQ = 2µs + 1.12µs + 50°C- 25°C 0.05 µs/°C = 4.37µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS40001585C-page 90 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 15-3: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance RSS I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage Note 1: FIGURE 15-4: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Section 24.0 “Electrical Specifications”. ADC TRANSFER FUNCTION Full-Scale Range FFh FEh ADC Output Code FDh FCh FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB VREF- 2011-2015 Microchip Technology Inc. Zero-Scale Transition 1.5 LSB Full-Scale Transition VREF+ DS40001585C-page 91 PIC10(L)F320/322 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON Bit 6 Bit 5 Bit 4 ADCS<2:0> Bit 3 Bit 2 CHS<2:0> ADRES Bit 1 Bit 0 GO/DONE ADON ADRES<7:0> Register on Page 88 89 ANSELA — — — — — ANSA2 FVRCON FVREN FVRRDY TSEN TSRNG — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 PIE1 — ADIE — NCO1IE CLC1IE — TMR2IE — 41 PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — 42 TRISA — — — — — TRISA2 TRISA1 TRISA0 69 Legend: ANSA1 ANSA0 ADFVR<1:0> 70 78 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC module. DS40001585C-page 92 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 16.0 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow 16.1.2 The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 8-BIT COUNTER MODE Figure 16-1 is a block diagram of the Timer0 module. In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 16.1 8-Bit Counter mode using the T0CKI pin is selected by setting the T0CS bit in the OPTION_REG register to ‘1’. Timer0 Operation The rising or falling transition of the incrementing edge for the external input source is determined by the T0SE bit in the OPTION_REG register. The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 16.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit of the OPTION_REG register. FIGURE 16-1: BLOCK DIAGRAM OF THE TIMER0 PRESCALER FOSC/4 Data Bus 0 8 T0CKI 1 SYNC 2 TCY 1 TMR0 0 T0SE T0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow 8 PS<2:0> 2011-2015 Microchip Technology Inc. DS40001585C-page 93 PIC10(L)F320/322 16.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with Timer0. The prescaler assignment is controlled by the PSA bit of the OPTION_REG register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. 16.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 16.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 24.0 “Electrical Specifications”. DS40001585C-page 94 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 16-1: R/W-1/u WPUEN (1) OPTION_REG: OPTION REGISTER R/W-1/u R/W-1/u R/W-1/u R/W-1/u INTEDG T0CS T0SE PSA R/W-1/u R/W-1/u R/W-1/u PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit(1) 1 = Weak pull-ups are disabled 0 = Weak pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is inactive and has no effect on the Timer 0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Note 1: INTCON 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WPUEN does not disable the pull-up for the MCLR input when MCLR = 1. TABLE 16-1: Name TMR0 Rate SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 T0SE PSA OPTION_REG WPUEN INTEDG T0CS TMR0 TRISA PS<2:0> 95 Timer0 module Register — — — — — TRISA2 40 TRISA1 TRISA0 69 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. 2011-2015 Microchip Technology Inc. DS40001585C-page 95 PIC10(L)F320/322 17.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16, 1:64) • Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: See Figure 17-1 for a block diagram of Timer2. 17.1 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:64. The output of the prescaler is then used to increment the TMR2 register. • A write to TMR2 occurs. • A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented. The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 17-1: TIMER2 BLOCK DIAGRAM TMR2 Output FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 2 TMR2 Comparator Sets Flag bit TMR2IF Reset EQ Postscaler 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> DS40001585C-page 96 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 17-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 TOUTPS<3:0> R/W-0/0 TMR2ON R/W-0/0 T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 = Prescaler is 64 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1 TABLE 17-1: Name Bit 7 INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 PIE1 — ADIE — NCO1IE CLC1IE — TMR2IE — 41 PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — 42 PR2 Timer2 module Period Register TMR2 T2CON Legend: 96 Timer2 module Register — TOUTPS<3:0> 96 TMR2ON T2CKPS<1:0> 97 x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. 2011-2015 Microchip Technology Inc. DS40001585C-page 97 PIC10(L)F320/322 18.0 Figure 18-1 shows a simplified block diagram of PWM operation. PULSE-WIDTH MODULATION (PWM) MODULE Figure 18-2 shows a typical waveform of the PWM signal. The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: • • • • • PR2 T2CON PWMxDCH PWMxDCL PWMxCON FIGURE 18-1: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle registers PWMxDCL<7:6> PWMxDCH PWMxOUT to other peripherals: CLC and CWG Latched (Not visible to user) Output Enable (PWMxOE) TRIS Control R Comparator Q 0 PWMx S Q 1 TMR2 Module TMR2 (1) Output Polarity (PWMxPOL) Comparator PR2 Clear Timer, PWMx pin and latch Duty Cycle Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 18.1.9 “Setup for PWM Operation using PWMx Pins”. FIGURE 18-2: PWM OUTPUT Period Pulse Width TMR2 = 0 DS40001585C-page 98 TMR2 = PR2 TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 18.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 18.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2, the PWM output is never cleared (100% duty cycle). Note: The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches PR2. Care should be taken to update both registers before the timer match occurs. 18.1.2 PWM OUTPUT POLARITY The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. 18.1.3 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 18-1. EQUATION 18-1: When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) • The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 18.1.4 The Timer2 postscaler has no effect on the PWM operation. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. Equation 18-2 is used to calculate the PWM pulse width. Equation 18-3 is used to calculate the PWM duty cycle ratio. EQUATION 18-2: PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 18-3: DUTY CYCLE RATIO PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1 The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC 2011-2015 Microchip Technology Inc. DS40001585C-page 99 PIC10(L)F320/322 18.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 18-4. EQUATION 18-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse-width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 18-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz Timer Prescale (1, 4, 64) PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale (1, 4, 64) PR2 Value 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 18.1.6 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 18-2: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 18.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 4.0 “Oscillator Module” for additional details. 18.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. DS40001585C-page 100 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 18.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the PWMxOE bit of the PWMxCON register. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs. 2011-2015 Microchip Technology Inc. DS40001585C-page 101 PIC10(L)F320/322 18.2 PWM Register Definitions REGISTER 18-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN PWMxOE PWMxOUT PWMxPOL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 PWMxOE: PWM Module Output Enable bit 1 = Output to PWMx pin is enabled 0 = Output to PWMx pin is disabled bit 5 PWMxOUT: PWM Module Output Value bit bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low. 0 = PWM output is active-high. bit 3-0 Unimplemented: Read as ‘0’ DS40001585C-page 102 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 18-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register. REGISTER 18-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — PWMxDCL<7:6> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register. bit 5-0 Unimplemented: Read as ‘0’ TABLE 18-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — — — ANSA2 ANSA1 ANSA0 70 LATA — — — — — LATA2 LATA1 LATA0 70 PORTA — — — — RA3 RA2 RA1 RA0 69 PR2 PWM1CON Timer2 module Period Register PWM1EN PWM1OE PWM1OUT PWM1DCH PWM1DCL PWM2CON T2CON PWM1DCL<7:6> PWM2EN PWM2OE — — — 103 — — — — — — 103 PWM2POL — — — — 102 — — — 103 T2CKPS<1:0> 97 PWM2DCH<7:0> PWM2DCL<7:6> — — — — TOUTPS<3:0> 103 TMR2ON Timer2 module Register — — 102 PWM2OUT TMR2 TRISA — PWM1DCH<7:0> PWM2DCH PWM2DCL PWM1POL 96 — — — 96 TRISA2 TRISA1 TRISA0 69 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. 2011-2015 Microchip Technology Inc. DS40001585C-page 103 PIC10(L)F320/322 19.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell selects any combination of the eight input signals and through the use of configurable gates reduces the selected inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: • • • • Two I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. FIGURE 19-1: Refer to Figure 19-1 for a simplified diagram showing signal flow through the CLCx. Possible configurations include: • Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR • Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset CLCx SIMPLIFIED BLOCK DIAGRAM D CLCxIN[0] Q1 CLCxIN[1] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] See Figure 19-3 Input Data Selection Gates CLCxIN[2] LCxOUT LE LCxOE LCxEN lcxg1 Q TRIS Control lcxg2 Logic lcxg3 Function lcxq lcx_out CLCx lcxg4 LCxPOL LCxMODE<2:0> Interrupt det LCxINTP LCxINTN See Figure 19-2 sets CLCxIF flag Interrupt det DS40001585C-page 104 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 19.1 19.1.2 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity 19.1.1 DATA SELECTION There are eight signals available as inputs to the configurable logic. Four 8-input multiplexers are used to select the inputs to pass on to the next stage. Data inputs are selected with the CLCxSEL0 and CLCxSEL1 registers (Register 19-3 and Register 19-4, respectively). Data selection is through four multiplexers as indicated on the left side of Figure 19-2. Data inputs in the figure are identified by a generic numbered input name. Table 19-1 correlates the generic input name to the actual signal for each CLC module. The columns labeled lcxd1 through lcxd4 indicate the MUX output for the selected data input. D1S through D4S are abbreviations for the MUX select input codes: LCxD1S<2:0> through LCxD4S<2:0>, respectively. Selecting a data input in a column excludes all other inputs in that column. Note: Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. CLCx DATA INPUT SELECTION Data Input lcxd1 D1S lcxd2 D2S lcxd3 D3S lcxd4 D4S CLC 1 CLCxIN[0] 000 000 000 000 CLCx CLCxIN[1] 001 001 001 001 CLCxIN1 CLCxIN[2] 010 010 010 010 CLCxIN2 CLCxIN[3] 011 011 011 011 PWM1 CLCxIN[4] 100 100 100 100 PWM2 CLCxIN[5] 101 101 101 101 NCOx CLCxIN[6] 110 110 110 110 FOSC CLCxIN[7] 111 111 111 111 LFINTOSC Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/ NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 19-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 19-2: Data selections are undefined at power-up. TABLE 19-1: DATA GATING DATA GATING LOGIC CLCxGLS0 LCxGyPOL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • • • • Gate 1: CLCxGLS0 (Register 19-5) Gate 2: CLCxGLS1 (Register 19-6) Gate 3: CLCxGLS2 (Register 19-7) Gate 4: CLCxGLS3 (Register 19-8) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. Data gating is indicated in the right side of Figure 19-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 2011-2015 Microchip Technology Inc. DS40001585C-page 105 PIC10(L)F320/322 19.1.3 LOGIC FUNCTION There are eight available logic functions including: • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 19-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 19.1.4 OUTPUT POLARITY The last stage in the configurable logic cell is the output polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. DS40001585C-page 106 19.1.5 CLCX SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 19-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. • Select the gate output polarities with the LCxPOLy bits of the CLCxPOL register. • Select the desired logic function with the LCxMODE<2:0> bits of the CLCxCON register. • Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). • If driving the CLCx pin, set the LCxOE bit of the CLCxCON register and also clear the TRIS bit corresponding to that output. • If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register or falling event. - Set the CLCxIE bit of the associated PIE registers. - Set the GIE and PEIE bits of the INTCON register. • Enable the CLCx by setting the LCxEN bit of the CLCxCON register. 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 19.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: • LCxON bit of the CLCxCON register • CLCxIE bit of the associated PIE registers • LCxINTP bit of the CLCxCON register (for a rising edge detection) • LCxINTN bit of the CLCxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The CLCxIF bit of the associated PIR registers must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 19.3 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 19.4 Operation During Sleep The selection, gating, and logic functions are not affected by Sleep. Operation will continue provided that the source signals are also not affected by Sleep. 2011-2015 Microchip Technology Inc. DS40001585C-page 107 PIC10(L)F320/322 FIGURE 19-2: CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] INPUT DATA SELECTION AND GATING Data Selection 000 Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N 111 LCxD2G1T LCxD1S<2:0> LCxD2G1N CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] LCxD3G1T lcxd2T LCxD3G1N LCxD4G1T 111 LCxD4G1N 000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 111 lcxg3 LCxD3S<2:0> CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] LCxG1POL lcxd2N LCxD2S<2:0> CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] lcxg1 000 (Same as Data GATE 1) Data GATE 4 000 lcxg4 lcxd4T (Same as Data GATE 1) lcxd4N 111 LCxD4S<2:0> Note: DS40001585C-page 108 All controls are undefined at power-up. 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 19-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxq lcxg3 lcxg4 lcxg2 lcxq lcxg3 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxg1 lcxg4 K R lcxq lcxg2 D lcxg1 LE lcxg3 S lcxq Q R lcxg3 LCxMODE<2:0>= 110 2011-2015 Microchip Technology Inc. LCxMODE<2:0>= 111 DS40001585C-page 109 PIC10(L)F320/322 19.5 CLC Control Registers REGISTER 19-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 LCxEN LCxOE LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable Logic Cell is enabled and mixing input signals 0 = Configurable Logic Cell is disabled and has logic zero output bit 6 LCxOE: Configurable Logic Cell Output Enable bit 1 = Configurable Logic Cell port pin output enabled 0 = Configurable Logic Cell port pin output disabled bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire. bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on lcx_out 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on lcx_out 0 = CLCxIF will not be set bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K Flip-Flop with R 101 = Cell is 2-input D Flip-Flop with R 100 = Cell is 1-input D Flip-Flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR DS40001585C-page 110 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 19-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as ‘0’ bit 3 LCxG4POL: Gate 4 Output Polarity Control bit 1 = The output of gate 4 is inverted when applied to the logic cell 0 = The output of gate 4 is not inverted bit 2 LCxG3POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 1 LCxG2POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted 2011-2015 Microchip Technology Inc. DS40001585C-page 111 PIC10(L)F320/322 REGISTER 19-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u (1) — LCxD2S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u (1) LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111 = CLCxIN[7] is selected for lcxd2. 110 = CLCxIN[6] is selected for lcxd2. 101 = CLCxIN[5] is selected for lcxd2. 100 = CLCxIN[4] is selected for lcxd2. 011 = CLCxIN[3] is selected for lcxd2. 010 = CLCxIN[2] is selected for lcxd2. 001 = CLCxIN[1] is selected for lcxd2. 000 = CLCxIN[0] is selected for lcxd2. bit 3 Unimplemented: Read as ‘0’ bit 2-0 LCxD1S<2:0>: Input Data 1 Selection Control bits(1) 111 = CLCxIN[7] is selected for lcxd1. 110 = CLCxIN[6] is selected for lcxd1. 101 = CLCxIN[5] is selected for lcxd1. 100 = CLCxIN[4] is selected for lcxd1. 011 = CLCxIN[3] is selected for lcxd1. 010 = CLCxIN[2] is selected for lcxd1. 001 = CLCxIN[1] is selected for lcxd1. 000 = CLCxIN[0] is selected for lcxd1. Note 1: See Table 19-1 for signal names associated with inputs. DS40001585C-page 112 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 19-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u (1) — LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u (1) LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 111 = CLCxIN[7] is selected for lcxd4. 110 = CLCxIN[6] is selected for lcxd4. 101 = CLCxIN[5] is selected for lcxd4 100 = CLCxIN[4] is selected for lcxd4. 011 = CLCxIN[3] is selected for lcxd4. 010 = CLCxIN[2] is selected for lcxd4. 001 = CLCxIN[1] is selected for lcxd4. 000 = CLCxIN[0] is selected for lcxd4. bit 3 Unimplemented: Read as ‘0’ bit 2-0 LCxD3S<2:0>: Input Data 3 Selection Control bits(1) 111 = CLCxIN[7] is selected for lcxd3. 110 = CLCxIN[6] is selected for lcxd3. 101 = CLCxIN[5] is selected for lcxd3. 100 = CLCxIN[4] is selected for lcxd3. 011 = CLCxIN[3] is selected for lcxd3. 010 = CLCxIN[2] is selected for lcxd3. 001 = CLCxIN[1] is selected for lcxd3. 000 = CLCxIN[0] is selected for lcxd3. Note 1: See Table 19-1 for signal names associated with inputs. 2011-2015 Microchip Technology Inc. DS40001585C-page 113 PIC10(L)F320/322 REGISTER 19-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg1 0 = lcxd4T is not gated into lcxg1 bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg1 0 = lcxd4N is not gated into lcxg1 bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg1 0 = lcxd3T is not gated into lcxg1 bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg1 0 = lcxd3N is not gated into lcxg1 bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg1 0 = lcxd2T is not gated into lcxg1 bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg1 0 = lcxd2N is not gated into lcxg1 bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg1 0 = lcxd1T is not gated into lcxg1 bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg1 0 = lcxd1N is not gated into lcxg1 DS40001585C-page 114 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 19-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg2 0 = lcxd4T is not gated into lcxg2 bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg2 0 = lcxd4N is not gated into lcxg2 bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg2 0 = lcxd3T is not gated into lcxg2 bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg2 0 = lcxd3N is not gated into lcxg2 bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg2 0 = lcxd2T is not gated into lcxg2 bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg2 0 = lcxd2N is not gated into lcxg2 bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg2 0 = lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg2 0 = lcxd1N is not gated into lcxg2 2011-2015 Microchip Technology Inc. DS40001585C-page 115 PIC10(L)F320/322 REGISTER 19-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg3 0 = lcxd4T is not gated into lcxg3 bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg3 0 = lcxd4N is not gated into lcxg3 bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg3 0 = lcxd3T is not gated into lcxg3 bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg3 0 = lcxd3N is not gated into lcxg3 bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg3 0 = lcxd2T is not gated into lcxg3 bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg3 0 = lcxd2N is not gated into lcxg3 bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg3 0 = lcxd1T is not gated into lcxg3 bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg3 0 = lcxd1N is not gated into lcxg3 DS40001585C-page 116 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 19-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg4 0 = lcxd4T is not gated into lcxg4 bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg4 0 = lcxd4N is not gated into lcxg4 bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg4 0 = lcxd3T is not gated into lcxg4 bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg4 0 = lcxd3N is not gated into lcxg4 bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg4 0 = lcxd2T is not gated into lcxg4 bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg4 0 = lcxd2N is not gated into lcxg4 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg4 0 = lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg4 0 = lcxd1N is not gated into lcxg4 2011-2015 Microchip Technology Inc. DS40001585C-page 117 PIC10(L)F320/322 TABLE 19-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 LC1MODE<2:0> Register on Page CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 110 114 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 115 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 116 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 117 CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 111 CLC1SEL0 — LC1D2S<2:0> — LC1D1S<2:0> 112 CLC1SEL1 — LC1D4S<2:0> — LC1D3S<2:0> 113 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 40 PIE1 — ADIE — NCO1IE CLC1IE — TMR2IE — 41 PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — 42 TRISA — — — — — TRISA2 TRISA1 TRISA0 69 INTCON Legend: — = unimplemented read as ‘0’. Shaded cells are not used for CLC module. DS40001585C-page 118 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 20.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that requires frequency accuracy and fine resolution at a fixed duty cycle. Features of the NCOx include: • • • • • • • 16-bit increment function Fixed Duty Cycle (FDC) mode Pulse Frequency (PF) mode Output pulse width control Multiple clock input sources Output polarity control Interrupt capability Figure 20-1 is a simplified block diagram of the NCOx module. 2011-2015 Microchip Technology Inc. DS40001585C-page 119 NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM NCOxINCH NCOxINCL Rev. 10-000028A 7/30/2013 16 (1) INCBUFH INCBUFL 16 NCO_overflow HFINTOSC 00 FOSC 01 LCx_out 10 20 Adder 20 NCOx_clk NCOxACCU NCOxACCH NCOxACCL 20 11 NCO1CLK NxCKS<1:0> NCO_interrupt set bit NCOxIF 2 Fixed Duty Cycle Mode Circuitry D Q D Q 0 _ 1 Q NxPFM NxOE TRIS bit NCOx NxPOL NCOx_out 2011-2015 Microchip Technology Inc. EN S Q Ripple Counter R Q R 3 NxPWS<2:0> Note 1: D _ Pulse Frequency Mode Circuitry Q To Peripherals NxOUT Q1 The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference. PIC10(L)F320/322 DS40001585C-page 120 FIGURE 20-1: PIC10(L)F320/322 20.1 20.1.3 NCOx OPERATION ADDER The NCOx operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCOx output. This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 20-1. The NCOx Adder is a full adder, which operates asynchronously to the clock source selected. The addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock. The NCOx output can be further modified by stretching the pulse or toggling a flip-flop. The modified NCOx output is then distributed internally to other peripherals and optionally output to a pin. The accumulator overflow also generates an interrupt. The Increment value is stored in two 8-bit registers making up a 16-bit increment. In order of LSB to MSB they are: The NCOx output creates an instantaneous frequency, which may cause uncertainty. This output depends on the ability of the receiving circuit (i.e., CWG or external resonant converter circuitry) to average the instantaneous frequency to reduce uncertainty. Both of the registers are readable and writable. The Increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx module. 20.1.1 NCOx CLOCK SOURCES Clock sources available to the NCOx include: • • • • HFINTOSC FOSC LC1OUT NCO1CLK pin 20.1.4 INCREMENT REGISTERS • NCOxINCL • NCOxINCH The buffer loads are immediate when the module is disabled. Writing to the MS register first is necessary because then the buffer is loaded synchronously with the NCOx operation after the write is executed on the lower increment register. Note: The increment buffer registers are not useraccessible. The NCOx clock source is selected by configuring the NxCKS<1:0> bits in the NCOxCLK register. 20.1.2 ACCUMULATOR The Accumulator is a 20-bit register. Read and write access to the Accumulator is available through three registers: • NCOxACCL • NCOxACCH • NCOxACCU EQUATION 20-1: NCO Clock Frequency Increment Value F OVERFLOW = --------------------------------------------------------------------------------------------------------------n 2 n = Accumulator width in bits 2011-2015 Microchip Technology Inc. DS40001585C-page 121 PIC10(L)F320/322 20.2 FIXED DUTY CYCLE (FDC) MODE In Fixed Duty Cycle (FDC) mode, every time the Accumulator overflows, the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 20-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 20.3 PULSE FREQUENCY (PF) MODE In Pulse Frequency (PF) mode, every time the Accumulator overflows, the output becomes active for one or more clock periods. See Section 20.3.1 “OUTPUT PULSE WIDTH CONTROL” for more information. Once the clock period expires, the output returns to an inactive state. This provides a pulsed output. The output becomes active on the rising clock edge immediately following the overflow event. For more information, see Figure 20-2. The value of the active and inactive states depends on the Polarity bit, NxPOL in the NCOxCON register. The PF mode is selected by setting the NxPFM bit in the NCOxCON register. 20.3.1 OUTPUT PULSE WIDTH CONTROL When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various pulse widths are selected with the NxPWS<2:0> bits in the NCOxCLK register. When the selected pulse width is greater than the Accumulator overflow time frame, then NCOx operation is undefined. 20.4 OUTPUT POLARITY CONTROL The last stage in the NCOx module is the output polarity. The NxPOL bit in the NCOxCON register selects the output polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. The NCOx output can be used internally by source code or other peripherals. This is done by reading the NxOUT (read-only) bit of the NCOxCON register. DS40001585C-page 122 2011-2015 Microchip Technology Inc. 2011-2015 Microchip Technology Inc. FIGURE 20-2: NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM Rev. 10-000029A 11/7/2013 NCOx Clock Source NCOx Increment Value NCOx Accumulator Value 4000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h NCO_overflow NCO_interrupt DS40001585C-page 123 NCOx Output PF Mode NCOxPWS = 000 NCOx Output PF Mode NCOxPWS = 001 PIC10(L)F320/322 NCOx Output FDC Mode PIC10(L)F320/322 20.5 Interrupts When the Accumulator overflows, the NCOx Interrupt Flag bit, NCOxIF, of the PIR1 register is set. To enable this interrupt event, the following bits must be set: • • • • NxEN bit of the NCOxCON register NCOxIE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 20.6 Effects of a Reset All of the NCOx registers are cleared to zero as the result of a Reset. 20.7 Operation In Sleep The NCO module operates independently from the system clock and will continue to run during Sleep, provided that the clock source selected remains active. The HFINTOSC remains active during Sleep when the NCO module is enabled and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO clock source, when the NCO is enabled, the CPU will go idle during Sleep, but the NCO will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. DS40001585C-page 124 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 20.8 NCOx Control Registers REGISTER 20-1: NCOxCON: NCOx CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 NxEN NxOE NxOUT NxPOL — — — NxPFM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 NxEN: NCOx Enable bit 1 = NCOx module is enabled 0 = NCOx module is disabled bit 6 NxOE: NCOx Output Enable bit 1 = NCOx output pin is enabled 0 = NCOx output pin is disabled bit 5 NxOUT: NCOx Output bit 1 = NCOx output is high 0 = NCOx output is low bit 4 NxPOL: NCOx Polarity bit 1 = NCOx output signal is active-low (inverted) 0 = NCOx output signal is active-high (non-inverted) bit 3-1 Unimplemented: Read as ‘0’. bit 0 NxPFM: NCOx Pulse Frequency mode bit 1 = NCOx operates in Pulse Frequency mode 0 = NCOx operates in Fixed Duty Cycle mode REGISTER 20-2: R/W-0/0 NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 NxPWS<2:0>(1,2) U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 NxCKS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2) 111 = 128 NCOx clock periods 110 = 64 NCOx clock periods 101 = 32 NCOx clock periods 100 = 16 NCOx clock periods 011 = 8 NCOx clock periods 010 = 4 NCOx clock periods 001 = 2 NCOx clock periods 000 = 1 NCOx clock periods bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 NxCKS<1:0>: NCOx Clock Source Select bits 11 = LC1OUT 10 = HFINTOSC (16 MHz) 01 = FOSC 00 = NCO1CLK pin Note 1: NxPWS applies only when operating in Pulse Frequency mode. 2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined. 2011-2015 Microchip Technology Inc. DS40001585C-page 125 PIC10(L)F320/322 REGISTER 20-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, low byte Note 1: NxPWS applies only when operating in Pulse Frequency mode. 2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined. REGISTER 20-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<15:8>: NCOx Accumulator, high byte REGISTER 20-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<19:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 NCOxACC<19:16>: NCOx Accumulator, upper byte DS40001585C-page 126 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 20-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, low byte REGISTER 20-7: R/W-0/0 NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxINC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<15:8>: NCOx Increment, high byte 2011-2015 Microchip Technology Inc. DS40001585C-page 127 PIC10(L)F320/322 TABLE 20-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH NCOx Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLC1SEL0 — LC1D2S2 LC1D2S1 LC1D2S0 — LC1D1S2 LC1D1S1 LC1D1S0 112 CLC1SEL1 — LC1D4S2 LC1D4S1 LC1D4S0 — LC1D3S2 LC1D3S1 LC1D3S0 113 CWG1CON1 G1ASDLB<1:0> INTCON GIE G1ASDLA<1:0> TMR0IE PEIE INTE — — IOCIE TMR0IF G1IS<1:0> INTF IOCIF 140 40 NCO1ACCH NCO1ACCH<15:8> 126 NCO1ACCL NCO1ACCL<7:0> 126 — NCO1ACCU NCO1CLK NCO1CON NCO1ACCU<19:16 N1PWS<2:0> N1EN N1OE N1OUT NCO1INCH — — — N1POL — — — N1PFM NCO1INCH<15:8> NCO1INCL — ADIE — NCO1IE CLC1IE PIR1 — ADIF — NCO1IF TRISA — — — — 125 125 127 NCO1INCL<7:0> PIE1 Legend: 126 N1CKS<1:0> 127 — TMR2IE — 41 CLC1IF — TMR2IF — 42 — TRISA2 TRISA1 TRISA0 69 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for NCO module. DS40001585C-page 128 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 21.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. The CWG module has the following features: • • • • • Selectable dead-band clock source control Selectable input sources Output enable control Output polarity control Dead-band control with Independent 6-bit rising and falling edge dead-band counters • Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 2011-2015 Microchip Technology Inc. DS40001585C-page 129 CWG BLOCK DIAGRAM GxASDLA GxCS 00 2 FOSC 2 ‘0’ 10 ‘1’ 11 1 cwg_clock GxASDLA = 01 GxOEA CWGxDBR HFINTOSC 6 1 GxIS 2 PWM1OUT PWM2OUT N1OUT LC1OUT EN S Q R Q R = 0 TRISx GxPOLA Input Source CWGxDBF 6 EN GxOEB R TRISx = 0 GxPOLB 1 GxASDLB = 01 00 2011-2015 Microchip Technology Inc. CWG1FLT (INT pin) GxASDFLT GxASE Auto-Shutdown Source LC1OUT S Q R Q GxASDCLC1 GxASE Data Bit WRITE x = CWG module number GxARSEN set dominate D S CWGxA Q shutdown ‘0’ 10 ‘1’ 11 GxASDLB 2 CWGxB PIC10(L)F320/322 DS40001585C-page 130 FIGURE 21-1: PIC10(L)F320/322 FIGURE 21-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB 2011-2015 Microchip Technology Inc. DS40001585C-page 131 PIC10(L)F320/322 21.1 Fundamental Operation The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 21.5 “Dead-Band Control”. A typical operating waveform, with dead band, generated from a single input signal is shown in Figure 21-2. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 21.9 “Auto-shutdown Control”. 21.4.2 POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the GxPOLA and GxPOLB bits of the CWGxCON0 register. 21.5 Dead-Band Control Dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. The CWG contains two 6-bit dead-band counters. One dead-band counter is used for the rising edge of the input source control. The other is used for the falling edge of the input source control. The CWG module allows the following clock sources to be selected: Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWGxDBR and CWGxDBF registers (Register 21-4 and Register 21-5, respectively). • Fosc (system clock) • HFINTOSC (16 MHz only) 21.6 21.2 Clock Source The clock sources are selected using the G1CS0 bit of the CWGxCON0 register (Register 21-1). 21.3 Selectable Input Sources The CWG can generate the complementary waveform for the following input sources: • • • • PWM1 PWM2 N1OUT LC1OUT The input sources are selected using the GxIS<1:0> bits in the CWGxCON1 register (Register 21-2). 21.4 Output Control Immediately after the CWG module is enabled, the complementary drive is configured with both CWGxA and CWGxB drives cleared. 21.4.1 Rising Edge Dead Band The rising edge dead band delays the turn-on of the CWGxA output from when the CWGxB output is turned off. The rising edge dead-band time starts when the rising edge of the input source signal goes true. When this happens, the CWGxB output is immediately turned off and the rising edge dead-band delay time starts. When the rising edge dead-band delay time is reached, the CWGxA output is turned on. The CWGxDBR register sets the duration of the deadband interval on the rising edge of the input source signal. This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. OUTPUT ENABLES Each CWG output pin has individual output enable control. Output enables are selected with the GxOEA and GxOEB bits of the CWGxCON0 register. When an output enable control is cleared, the module asserts no control over the pin. When an output enable is set, the override value or active PWM waveform is applied to the pin per the port priority selection. The output pin enables are dependent on the module enable bit, GxEN. When GxEN is cleared, CWG output enables and CWG drive levels have no effect. DS40001585C-page 132 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 21.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on. The CWGxDBF register sets the duration of the deadband interval on the falling edge of the input source signal. This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. Refer to Figure 21-3 and Figure 21-4 for examples. 21.8 Dead-Band Uncertainty When the rising and falling edges of the input source triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 21-1 for more detail. 2011-2015 Microchip Technology Inc. DS40001585C-page 133 DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H cwg_clock Input Source CWGxA CWGxB FIGURE 21-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA source shorter than dead band CWGxB PIC10(L)F320/322 DS40001585C-page 134 FIGURE 21-3: 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 EQUATION 21-1: DEAD-BAND DELAY TIME UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock EXAMPLE 21-1: DEAD-BAND DELAY TIME UNCERTAINTY Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 625ns 2011-2015 Microchip Technology Inc. DS40001585C-page 135 PIC10(L)F320/322 21.9 Auto-shutdown Control Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 21.9.1 SHUTDOWN The Shutdown state can be entered by either of the following two methods: • Software generated • External Input 21.9.1.1 Software Generated Shutdown Setting the GxASE bit of the CWGxCON2 register will force the CWG into the shutdown state. When auto-restart is disabled, the shutdown state will persist as long as the GxASE bit is set. 21.10 Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the CWG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, the CPU will go idle during Sleep, but the CWG will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. When auto-restart is enabled, the GxASE bit will clear automatically and resume operation on the next rising edge event. See Figure 21-6. 21.9.1.2 External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes high, the CWG outputs will immediately go to the selected override levels without software delay. Any combination of two input sources can be selected to cause a shutdown condition. The two sources are: • LC1OUT • CWG1FLT Shutdown inputs are selected using the GxASDS0 and GxASDS1 bits of the CWGxCON2 register. (Register 21-3). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. DS40001585C-page 136 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 21.11 Configuring the CWG 21.11.2.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: When the GxARSEN bit of the CWGxCON2 register is cleared, the CWG must be restarted after an auto-shutdown event by software. 1. 2. 3. 4. 5. 6. 7. 8. 9. Ensure that the TRIS control bits corresponding to CWGxA and CWGxB are set so that both are configured as inputs. Clear the GxEN bit, if not already cleared. Set desired dead-band times with the CWGxDBR and CWGxDBF registers. Setup the following controls in CWGxCON2 auto-shutdown register: • Select desired shutdown source. • Select both output overrides to the desired levels (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). • Set the GxASE bit and clear the GxARSEN bit. Select the desired input source using the CWGxCON1 register. Configure the following controls in CWGxCON0 register: • Select desired clock source. • Select the desired output polarities. • Set the output enables for the outputs to be used. Set the GxEN bit. Clear TRIS control bits corresponding to CWGxA and CWGxB to be used to configure those pins as outputs. If auto-restart is to be used, set the GxARSEN bit and the GxASE bit will be cleared automatically. Otherwise, clear the GxASE bit to start the CWG. 21.11.1 Software controlled restart The CWG will resume operation on the first rising edge event after the GxASE bit is cleared. Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the GxASE bit will remain set. 21.11.2.2 Auto-Restart When the GxARSEN bit of the CWGxCON2 register is set, the CWG will restart from the auto-shutdown state automatically. After the shutdown event clears, the GxASE bit will clear automatically and the CWG will resume operation on the first rising edge event. PIN OVERRIDE LEVELS The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON1 register (Register 21-2). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state. The polarity control does not apply to the override level. 21.11.2 AUTO-SHUTDOWN RESTART After an auto-shutdown event has occurred, there are two ways to have resume operation: • Software controlled • Auto-restart The restart method is selected with the GxARSEN bit of the CWGxCON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 21-5 and Figure 21-6. 2011-2015 Microchip Technology Inc. DS40001585C-page 137 SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0) Shutdown Event Ceases PIC10(L)F320/322 DS40001585C-page 138 FIGURE 21-5: GxASE Cleared by Software CWG Input Source Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Output Resumes Shutdown FIGURE 21-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1) Shutdown Event Ceases GxASE auto-cleared by hardware CWG Input Source 2011-2015 Microchip Technology Inc. Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Shutdown Output Resumes PIC10(L)F320/322 21.12 CWG Control Registers REGISTER 21-1: CWGxCON0: CWG CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 GxEN GxOEB GxOEA GxPOLB GxPOLA — — GxCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxEN: CWGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 GxOEB: CWGxB Output Enable bit 1 = CWGxB is available on appropriate I/O pin 0 = CWGxB is not available on appropriate I/O pin bit 5 GxOEA: CWGxA Output Enable bit 1 = CWGxA is available on appropriate I/O pin 0 = CWGxA is not available on appropriate I/O pin bit 4 GxPOLB: CWGxB Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 3 GxPOLA: CWGxA Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 2-1 Unimplemented: Read as ‘0’ bit 0 GxCS0: CWGx Clock Source Select bit 1 = HFINTOSC 0 = FOSC 2011-2015 Microchip Technology Inc. DS40001585C-page 139 PIC10(L)F320/322 REGISTER 21-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u GxASDLA<1:0> U-0 — U-0 R/W-0/0 R/W-0/0 GxIS<1:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown event is present (GxASE = 1): 11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit. 10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit. 01 = CWGxB pin is tri-stated 00 = CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will control the polarity of the output. bit 5-4 GxASDLA<1:0>: CWGx Shutdown State for CWGxA When an auto shutdown event is present (GxASE = 1): 00 = CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will control the polarity of the output. 01 = CWGxA pin is tri-stated 10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit. 11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit. bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 GxIS<1:0>: CWGx Dead-band Source Select bits 11 = LC1OUT 10 = N1OUT 01 = PWM2OUT 00 = PWM1OUT DS40001585C-page 140 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 REGISTER 21-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W/HC/HS-0/0 R/W-0/0 GxASE GxARSEN U-0 U-0 — — U-0 — U-0 R/W-0/0 R/W-0/0 — GxASDCLC1 GxASDFLT bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An Auto-Shutdown event has occurred. GxOEB/GxOEA Output Controls overridden, Outputs disabled. 0 = No Auto-Shutdown event has occurred, or an Auto-restart has occurred. GxOEB/GxOEA Output Controls enabled. bit 6 GxARSEN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-2 Unimplemented: Read as ‘0’ bit 1 GxASDCLC1: CWG Auto-shutdown Source Enable bit 1 1 = Shutdown when LC1OUT is high 0 = LC1OUT has no effect on shutdown bit 0 GxASDFLT: CWG Auto-shutdown Source Enable bit 0 1 = Shutdown when CWG1FLT input is low 0 = CWG1FLT input has no effect on shutdown 2011-2015 Microchip Technology Inc. DS40001585C-page 141 PIC10(L)F320/322 REGISTER 21-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band REGISTER 21-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band. Dead-band generation is bypassed. DS40001585C-page 142 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 21-1: Name ANSELA CWG1CON0 CWG1CON1 CWG1CON2 CWG1DBF SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — — ANSA2 ANSA1 ANSA0 70 G1EN G1OEB G1OEA G1POLB — G1CS0 G1ASDLB<1:0> G1POLA — G1ASDLA<1:0> — — — — — G1IS<1:0> 139 140 G1ASE G1ARSEN — — CWG1DBF<5:0> 142 CWG1DBR<5:0> 142 — G1ASDCLC1 G1ASDFLT 141 CWG1DBR — — LATA — — — — — LATA2 LATA1 LATA0 70 TRISA — — — — — TRISA2 TRISA1 TRISA0 69 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG. 2011-2015 Microchip Technology Inc. DS40001585C-page 143 PIC10(L)F320/322 22.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC10(L)F320/322 Flash Memory Programming Specification" (DS41572). 22.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 22.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. 22.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6 connector) configuration. See Figure 22-1. FIGURE 22-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 22-2. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 5.4 “Low-Power Brown-out Reset (LPBOR)” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. DS40001585C-page 144 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 22-2: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 2 3 4 5 6 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. 2011-2015 Microchip Technology Inc. DS40001585C-page 145 PIC10(L)F320/322 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 22-3 for more information. FIGURE 22-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS40001585C-page 146 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 23.0 INSTRUCTION SET SUMMARY The PIC10(L)F320/322 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 23-1, while the various opcode fields are summarized in Table 23-1. Table 23-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 23.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the IOCIF flag. 2011-2015 Microchip Technology Inc. TABLE 23-1: OPCODE FIELD DESCRIPTIONS Field Description Register file address (0x00 to 0x7F) f W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. PC Program Counter TO Time-out bit Carry bit C DC Digit carry bit Zero bit Z PD Power-down bit FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 OPCODE 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value DS40001585C-page 147 PIC10(L)F320/322 TABLE 23-2: INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 C, DC, Z Z Z Z Z Z Z Z Z C C C, DC, Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 1 (2) 1 (2) 01 01 01 01 1, 2 1, 2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 2: 3: k k k – k k k – k – – k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS40001585C-page 148 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 23.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operands: 0 f 127 0b7 Operation: (W) + (f) (destination) Operation: 1 (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: Bit ‘b’ in register ‘f’ is set. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW Syntax: [ label ] BTFSC f,b Operands: 0 k 255 Operands: Operation: (W) .AND. (k) (W) 0 f 127 0b7 Status Affected: Z Operation: skip if (f<b>) = 0 Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. Status Affected: None Description: ANDWF AND W with f If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. f,d k Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 Operation: (W) .AND. (f) (destination) f,d Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2011-2015 Microchip Technology Inc. f,b DS40001585C-page 149 PIC10(L)F320/322 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF Operands: 0 k 2047 Operands: Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> 0 f 127 d [0,1] f,d Operation: (f) (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW f Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001585C-page 150 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. The contents of the W register are OR’ed with the 8-bit literal ‘k’. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. GOTO k INCF f,d 2011-2015 Microchip Technology Inc. INCFSZ f,d Inclusive OR literal with W IORLW k IORWF f,d DS40001585C-page 151 PIC10(L)F320/322 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 Operation: (W) (f) Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself. d = 1 is useful to test a file register since Status flag Z is affected. Move data from W register to register ‘f’. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVF f,d MOVF Example: MOVW F MOVWF OPTION_REG Before Instruction OPTION_REG = W = After Instruction OPTION_REG = W = FSR, 0 f 0xFF 0x4F 0x4F 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: None Operation: k (W) Operation: No operation Status Affected: None Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Description: No operation. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVLW k Example: MOVLW NOP 0x5A After Instruction W = DS40001585C-page 152 NOP 0x5A 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 TABLE RETLW k CALL TABLE;W contains ;table offset ;value GOTO DONE • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ;End of table DONE Before Instruction W = 0x07 After Instruction W = value of k8 2011-2015 Microchip Technology Inc. RETURN Return from Subroutine Syntax: [ label ] Operands: None Operation: TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruction. RETURN DS40001585C-page 153 PIC10(L)F320/322 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 00h WDT, 0 WDT prescaler, 1 TO, 0 PD RLF f,d C Words: 1 Cycles: 1 Example: Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Register f RLF REG1,0 Before Instruction REG1 C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C RRF Rotate Right f through Carry SUBLW Syntax: [ label ] Syntax: [ label ] SUBLW k Operands: 0 k 255 k - (W) W) RRF f,d Subtract W from literal Operands: 0 f 127 d [0,1] Operation: Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. C DS40001585C-page 154 Register f The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’. The result is placed in the W register. Result Condition C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW f,d Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register. 2011-2015 Microchip Technology Inc. DS40001585C-page 155 PIC10(L)F320/322 24.0 ELECTRICAL SPECIFICATIONS 24.1 Absolute Maximum Ratings(†) Ambient temperature under bias ...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC10F320/322 ......................................................................................................... -0.3V to +6.5V PIC10LF320/322 ....................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40°C TA +85°C .............................................................................................................. 250 mA +85°C TA +125°C ............................................................................................................. 85 mA on VDD pin(1) -40°C TA +85°C .............................................................................................................. 250 mA +85°C TA +125°C ............................................................................................................. 85 mA Sunk by any I/O pin .............................................................................................................................. 50 mA Sourced by any I/O pin ......................................................................................................................... 50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2) ...............................................................................................................................800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Section 24.4 “Thermal Considerations” to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001585C-page 156 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 24.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC10LF320/322 VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc 20 MHz) ......................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC10F320/322 VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V VDDMIN (16 MHz < Fosc 20 MHz) ......................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C Note 1: See Parameter D001, DC Characteristics: Supply Voltage. 2011-2015 Microchip Technology Inc. DS40001585C-page 157 PIC10(L)F320/322 PIC10F320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 24-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 24-6 for each Oscillator mode’s supported frequencies. PIC10LF320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 24-2: 3.6 2.5 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 24-6 for each Oscillator mode’s supported frequencies. DS40001585C-page 158 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 24.3 DC Characteristics TABLE 24-1: SUPPLY VOLTAGE PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) PIC10F320/322 Param. No. D001 Sym. VDD Characteristic VDR VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage VFVR SVDD Units Conditions 1.8 2.5 — — 3.6 3.6 V V FOSC 16 MHz: FOSC 20 MHz 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz: FOSC 20 MHz 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 0.8 — V Device in Sleep mode — 1.7 — V Device in Sleep mode -19 — +19 % VDD 2.5V, -40°C TA +85°C VDD 2.5V, -40°C TA +85°C VDD 4.75V, -40°C TA +85°C 0.05 — — V/ms Fixed Voltage Reference Voltage 1x gain (1.024V nominal) 2x gain (2.048V nominal) 4x gain (4.096V nominal) D004* Max. RAM Data Retention Voltage(1) D002* D003 Typ† Supply Voltage D001 D002* Min. VDD Rise Rate to ensure internal Power-on Reset signal See Section 5.1 “Power-On Reset (POR)” for details. * † Note These parameters are characterized but not tested. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2011-2015 Microchip Technology Inc. DS40001585C-page 159 PIC10(L)F320/322 FIGURE 24-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: DS40001585C-page 160 TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 24-2: SUPPLY VOLTAGE (IDD)(1,2) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) PIC10F320/322 Param No. D013 D013 D014 D014 D015 D015 D016 D016 D016A D016A Note 1: 2: Device Characteristics Conditions Min. Typ† Max. Units Note VDD — 34 45 A 1.8 — 60 105 A 3.0 — 76 101 A 2.3 — 110 148 A 3.0 — 153 211 A 5.0 — 190 290 A 1.8 — 350 500 A 3.0 — 290 430 A 2.3 — 395 600 A 3.0 — 480 775 A 5.0 — 0.8 1.3 mA 3.0 — 1.1 1.8 mA 3.6 — 0.8 1.4 mA 3.0 — 1.1 1.8 mA 5.0 — 2.2 4.1 A 1.8 — 3.9 6.5 A 3.0 — 31 44 A 2.3 — 40 57 A 3.0 — 71 117 A 5.0 — 3.2 4.5 A 1.8 — 4.8 7.0 A 3.0 — 31 44 A 2.3 — 40 57 A 3.0 — 71 117 A 5.0 FOSC = 500 kHz EC mode FOSC = 500 kHz EC mode FOSC = 8 MHz EC mode FOSC = 8 MHz EC mode FOSC = 20 MHz EC mode FOSC = 20 MHz EC mode FOSC = 32 kHz LFINTOSC mode, 85°C FOSC = 32 kHz LFINTOSC mode, 85°C FOSC = 32 kHz LFINTOSC mode, 125°C FOSC = 32 kHz LFINTOSC mode,125°C The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 2011-2015 Microchip Technology Inc. DS40001585C-page 161 PIC10(L)F320/322 TABLE 24-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) PIC10F320/322 Param No. Device Characteristics D017 D017 D018 D018 D019 D019 Note 1: 2: Conditions Min. Typ† Max. Units VDD — 213 290 A 1.8 — 264 360 A 3.0 — 272 368 A 2.3 — 310 422 A 3.0 — 372 515 A 5.0 — 0.33 0.50 mA 1.8 — 0.43 0.70 mA 3.0 — 0.45 1.0 mA 2.3 — 0.56 1.1 mA 3.0 — 0.64 1.2 mA 5.0 — 0.46 1.1 mA 1.8 — 0.73 1.2 mA 3.0 — 0.60 1.1 mA 2.3 — 0.76 1.2 mA 3.0 — 0.85 1.3 mA 5.0 Note FOSC = 500 kHz HFINTOSC mode FOSC = 500 kHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. DS40001585C-page 162 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 24-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) PIC10F320/322 Param No. Device Characteristics D023 D023 D024 D024 Min. Typ† Conditions Max. +85°C Max. +125°C Units Note VDD — 0.06 1.1 2 A 1.8 — 0.08 1.3 2 A 3.0 — 0.20 1.1 2 A 2.3 — 0.30 1.4 2 A 3.0 — 0.40 2.4 2.4 A 5.0 — 0.5 9 11 A 1.8 — 0.8 11 13 A 3.0 — 4.0 10 12 A 2.3 — 4.2 12 14 A 3.0 WDT, BOR, and FVR disabled, all Peripherals Inactive WDT, BOR, and FVR disabled, all Peripherals Inactive WDT Current (Note 1) WDT Current (Note 1) — 4.3 14 16 A 5.0 — 30 96 120 A 1.8 — 39 106 123 A 3.0 — 32 96 120 A 2.3 — 39 106 133 A 3.0 — 70 136 170 A 5.0 D026 — 7.5 16 18 A 3.0 BOR Current (Note 1) D026 — 8 18 20 A 3.0 BOR Current (Note 1) — 9 20 20.2 A 5.0 D026A — 2.7 10 15 A 3.0 LPBOR Current D026A — 3.0 10 15 A 3.0 LPBOR Current — 3.2 15 20 A 5.0 — 0.1 4 5 A 1.8 — 0.1 5 6 A 3.0 — 3.4 6 7 A 2.3 — 3.6 7 8 A 3.0 D025 D025 D028 D028 D029 D029 * † Note 1: 2: 3: — 3.8 8 9 A 5.0 — 250 — — A 1.8 — 250 — — A 3.0 — 280 — — A 2.3 — 280 — — A 3.0 — 280 — — A 5.0 FVR current FVR current A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. 2011-2015 Microchip Technology Inc. DS40001585C-page 163 PIC10(L)F320/322 TABLE 24-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D032 with TTL buffer D032A D033 with Schmitt Trigger buffer D034 MCLR VIH — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.2 VDD V Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer D042 MCLR IIL 2.0 — — V 4.5V VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V VDD 4.5V 2.0V VDD 5.5V 0.8 VDD — — V 0.8 VDD — — V nA Input Leakage Current(2) D060 I/O ports — ±5 ± 125 ±5 ± 1000 nA VSS VPIN VDD, Pin at high-impedance @ 85°C 125°C D061 MCLR — ± 50 ± 200 nA VSS VPIN VDD @ 85°C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS — — 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage I/O ports VOH D090 Output High Voltage I/O ports * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. DS40001585C-page 164 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 TABLE 24-5: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDD max. V VDD for Write or Row Erase VDD min. — VDD max. V — 1.0 mA 5.0 mA D112 D113 VPEW D114 IPPPGM Current on MCLR/VPP during Erase/Write — D115 IDDPGM Current on VDD during Erase/Write — (Note 2) Program Flash Memory D121 EP Cell Endurance 10K — — E/W D122 VPR VDD for Read VDD min. — VDD max. V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention 40 — — Year † Note 1: 2: -40C to +85C (Note 1) Provided no other specifications are violated Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Self-write and Block Erase. Required only if single-supply programming is disabled. 2011-2015 Microchip Technology Inc. DS40001585C-page 165 PIC10(L)F320/322 24.4 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60 C/W 6-pin SOT-23 package 80 C/W 8-pin PDIP package 8-pin DFN package 90 C/W 31.4 C/W 6-pin SOT-23 package 24 C/W 8-pin PDIP package 8-pin DFN package 24 C/W 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS40001585C-page 166 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 24.5 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKR cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 24-4: T Time osc rd rw sc ss t0 t1 wr CLKIN RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins 2011-2015 Microchip Technology Inc. DS40001585C-page 167 PIC10(L)F320/322 FIGURE 24-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS03 CLKR (CLKROE = 1) TABLE 24-6: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions OS01 FOSC External CLKIN Frequency(1) DC — 20 MHz OS02 TOSC External CLKIN Period(1) 31.25 — ns EC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC EC mode * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. TABLE 24-7: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) ±3% -8 to +4% — — 16.0 16.0 — — MHz MHz OS09 LFOSC Internal LFINTOSC Frequency ±25% — 31 — kHz OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time — — 5 8 s Conditions 0°C TA +85°C, VDD 2.3V -40°C TA 125°C * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. DS40001585C-page 168 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 24-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE Rev. 10-000135D 2/11/2014 125 -15% to +12% Temperature (°C) 85 60 ±6.5% 25 0 -15% to +12% -40 1.8 2.3 5.5 VDD (V) 2011-2015 Microchip Technology Inc. DS40001585C-page 169 PIC10(L)F320/322 FIGURE 24-7: CLKR AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKR OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 24-8: CLKR AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.0V OS12 TosH2ckH FOSC to CLKOUT(1) — — 72 ns 3.3V VDD 5.0V OS13 TckL2ioV CLKOUT to Port out valid OS14 TioV2ckH Port input valid before CLKOUT(1) OS15 TosH2ioV OS16 (1) — — 20 ns TOSC + 200 ns — — ns Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V VDD 5.0V TosH2ioI Fosc (Q2 cycle) to Port input invalid (I/O in setup time) 50 — — ns 3.3V VDD 5.0V OS17 TioV2osH Port input valid to Fosc(Q2 cycle) (I/O in setup time) 20 — — ns OS18* TioR Port output rise time — — 40 15 72 32 ns VDD = 1.8V 3.3V VDD 5.0V OS19* TioF Port output fall time — — 28 15 55 30 ns VDD = 1.8V 3.3V VDD 5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level time 25 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC. DS40001585C-page 170 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 24-8: RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 24-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 2011-2015 Microchip Technology Inc. 33 DS40001585C-page 171 PIC10(L)F320/322 TABLE 24-9: RESET, WATCHDOG TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDTLP Low-Power Watchdog Timer Time-out Period 10 16 27 ms VDD = 3.3V-5V 1:16 Prescaler used 33* TPWRT Power-up Timer Period, PWRTE = 0 40 64 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage(1) 2.55 2.70 2.85 V BORV = 0 2.30 1.80 2.40 1.90 2.55 2.05 V V BORV = 1 (PIC10F320/322) BORV = 1 (PIC10LF320/322) 0 25 50 mV 36* VHYST 37* TBORDC Brown-out Reset DC Response Time 1 3 5 s VDD VBOR 38 VLPBOR Low-Power Brown-Out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1 Brown-out Reset Hysteresis -40°C to +85°C * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. FIGURE 24-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 TMR0 TABLE 24-10: TIMER0 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P * † T0CKI Period Typ† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns Conditions N = prescale value (2, 4, ..., 256) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001585C-page 172 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 24-11: CLC PROPAGATION TIMING Rev. 10-000031A 7/30/2013 CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 CLC02 CLC03 Note 1: See FIGURE 19-1: CLCx Simplified Block Diagram, to identify specific CLC signals. TABLE 24-11: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions CLC01* TCLCIN CLC input time — 7 — ns CLC02* TCLC CLC module input to output propagation time — — 24 12 — — ns ns VDD = 1.8V VDD > 3.6V — OS18 — — (Note 1) — OS19 — — (Note 1) — 45 — MHz CLC03* TCLCOUT CLC output time Rise Time Fall Time CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1:See Table 24-8 for OS18 and OS19 rise and fall times. 2011-2015 Microchip Technology Inc. DS40001585C-page 173 PIC10(L)F320/322 TABLE 24-12: A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 8 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN — — ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(3) 1.8 — VDD AD07 VAIN Full-Scale Range VSS — VREF AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 * † Note 1: 2: 3: 4: 5: Gain Error bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V V VREF = (VREF+ minus VREF-) (Note 5) V k Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. FVR voltage selected must be 2.048V or 4.096V. TABLE 24-13: A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 6.0 s TOSC-based A/D Internal FRC Oscillator Period 1.0 1.6 6.0 s ADCS<1:0> = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) — 9.5 — TAD Set GO/DONE bit to conversion complete AD132* TACQ Acquisition Time — 5.0 — s AD133* THCD Holding Capacitor Disconnect Time — — 1/2 TAD 1/2 TAD + 1TCY — — AD130* TAD AD131 TCNV FOSC-based ADCS<2:0> = x11 (ADC FRC mode) * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001585C-page 174 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 24-12: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON, GO AD134 1 Tcy (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 Tcy ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 24-13: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON, GO AD134 (TOSC/2 + TCY(1)) 1 Tcy AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 OLD_DATA ADRES 2 1 0 NEW_DATA 1 Tcy ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2011-2015 Microchip Technology Inc. DS40001585C-page 175 PIC10(L)F320/322 25.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. DS40001585C-page 176 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 26.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 26.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker 2011-2015 Microchip Technology Inc. DS40001585C-page 177 PIC10(L)F320/322 26.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 26.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001585C-page 178 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 26.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 26.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011-2015 Microchip Technology Inc. 26.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 26.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 26.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001585C-page 179 PIC10(L)F320/322 26.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 26.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001585C-page 180 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 6-Lead SOT-23 Example LA11 XXNN 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN Example 10F320 I/P e3 07Q 1110 YYWW 8-Lead DFN (2x3x0.9 mm) Example BAA 110 20 Legend: XX...X Y YY WW NNN e3 * Note: Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011-2015 Microchip Technology Inc. DS40001585C-page 181 PIC10(L)F320/322 TABLE 27-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number PIC10F322(T)-I/MC Marking TABLE 27-2: 6-LEAD SOT-23 (OT) PACKAGE TOP MARKING Part Number Marking BAA PIC10F322(T)-I/OT LA/LJ PIC10F322(T)-E/MC BAB PIC10F322(T)-E/OT LB/LK PIC10F320(T)-I/MC BAC PIC10F320(T)-I/OT LC PIC10F320(T)-E/MC BAD PIC10F320(T)-E/OT LD PIC10LF322(T)-I/MC BAF PIC10LF322(T)-I/OT LE PIC10LF322(T)-E/MC BAG PIC10LF322(T)-E/OT LF PIC10LF320(T)-I/MC BAH PIC10LF320(T)-I/OT LG PIC10LF320(T)-E/MC BAJ PIC10LF320(T)-E/OT LH DS40001585C-page 182 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 27.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU27>627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H %6& 2XWVLGH/HDG3LWFK H %6& 2YHUDOO+HLJKW $ ± 0ROGHG3DFNDJH7KLFNQHVV $ ± 6WDQGRII $ ± 2YHUDOO:LGWK ( ± 0ROGHG3DFNDJH:LGWK ( ± 2YHUDOO/HQJWK ' ± )RRW/HQJWK / ± )RRWSULQW / ± )RRW$QJOH ± /HDG7KLFNQHVV F ± /HDG:LGWK E ± 1RWHV 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2011-2015 Microchip Technology Inc. DS40001585C-page 183 PIC10(L)F320/322 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001585C-page 184 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 2011-2015 Microchip Technology Inc. DS40001585C-page 185 PIC10(L)F320/322 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS40001585C-page 186 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0&±[[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 2 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 5() 2YHUDOO/HQJWK ' %6& 2YHUDOO:LGWK ( ([SRVHG3DG/HQJWK ' ± ([SRVHG3DG:LGWK ( ± E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . ± ± &RQWDFW:LGWK %6& %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ && 2011-2015 Microchip Technology Inc. DS40001585C-page 187 PIC10(L)F320/322 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001585C-page 188 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (07/2011) Original release. Revision B (02/2014) Electrical Specifications update and new formats; Minor edits. Revision C (05/2015) Updated Figures 7-1 and 11-1. Update Sections 5.4.1, 24.1, and 24.3. Updated Tables 24-2 and 24-9. 2011-2015 Microchip Technology Inc. DS40001585C-page 189 PIC10(L)F320/322 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS40001585C-page 190 2011-2015 Microchip Technology Inc. PIC10(L)F320/322 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC10F320, PIC10LF320, PIC10F322, PIC10LF322 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package: OT P MC = SOT-23 = PDIP = DFN Pattern: (Industrial) (Extended) QTP, SQTP, Code or Special Requirements (blank otherwise) 2011-2015 Microchip Technology Inc. c) PIC10LF320T - I/OT Tape and Reel, Industrial temperature, SOT-23 package PIC10F322 - I/P Industrial temperature PDIP package PIC10F322 - E/MC Extended temperature, DFN package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS40001585C-page 191 PIC10(L)F320/322 NOTES: DS40001585C-page 192 2011-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-367-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2011-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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