PIC10(L)F320/322 PIC10(L)F320/322 Flash Memory Programming Specification This document includes the programming specifications for the following devices: • PIC10F320 • PIC10LF320 • PIC10F322 • PIC10LF322 1.0 1.1 Hardware Requirements 1.1.1 HIGH-VOLTAGE ICSP PROGRAMMING In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/VPP pin. OVERVIEW 1.1.2 The PIC10(L)F320/322 devices are programmed using In-Circuit Serial Programming™ (ICSP™). This programming specification applies to the PIC10(L)F320/322 devices in all packages. With the exception of memory size and the voltage regulator, all other aspects of the PIC10(L)F320/322 devices are identical. LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSP mode, the PIC10(L)F320/322 devices can be programmed using a single VDD source in the operating range. The MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. 1.1.2.1 Single-Supply ICSP Programming The LVP bit in the Configuration Word enables singlesupply (low-voltage) ICSP programming. The LVP bit defaults to a ‘1’ (enabled) from the factory. The LVP bit may only be programmed to ‘0’ by entering the HighVoltage ICSP mode, where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/ VPP pin. 2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port pin can no longer be used as a general purpose input. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 1 PIC10(L)F320/322 1.2 Pin Utilization Five pins are needed for ICSP™ programming. The pins are listed in Table 1-1. TABLE 1-1: Pin Name PIN DESCRIPTIONS DURING PROGRAMMING During Programming Function Pin Type RA1 ICSPCLK I/O Clock Input – Schmitt Trigger Input RA0 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input RA3/MCLR/VPP Program/Verify mode Pin Description (1) Program Mode Select/Programming Power Supply P VDD VDD P Power Supply VSS VSS P Ground Legend: I = Input, O = Output, P = Power Note 1: To activate the Program/Verify mode, high voltage needs to be applied to MCLR/VPP input. Since the MCLR /VPP is used for a level source, MCLR/VPP does not draw any significant current. DS41572D-page 2 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 2.0 DEVICE PINOUTS The pin diagrams for the PIC10(L)F320/322 family are shown in Figure 2-1 and Figure 2-2. The pins that are required for programming are listed in Table 1-1 and shown in bold lettering in the pin diagrams. FIGURE 2-1: 6-PIN DIAGRAM FOR PIC10(L)F320/322 FIGURE 2-2: ICSPDAT/RA0 1 VSS 2 ICSPCLK/RA1 3 PIC10(L)F320 PIC10(L)F322 SOT-23 6 RA3/MCLR/VPP 5 VDD 4 RA2 8-PIN DIAGRAM FOR PIC10(L)F320/322 N/C 1 VDD 2 RA2 3 ICSPCLK/RA1 4 2011-2012 Microchip Technology Inc. PIC10(L)F320 PIC10(L)F322 PDIP, DFN 8 RA3/MCLR/VPP 7 VSS 6 N/C 5 RA0/ICSPDAT Advance Information DS41572D-page 3 PIC10(L)F320/322 3.0 MEMORY MAP The memory for the PIC10(L)F320/322 devices is broken into two sections: program memory and configuration memory. The size of the program memory and the configuration memory is different between devices. FIGURE 3-1: PIC10F320 AND PIC10LF320 PROGRAM MEMORY MAPPING 256 W 0000h 00FFh Program Memory 2000h User ID Location 2001h User ID Location 2002h User ID Location 2003h User ID Location 2004h Reserved 2005h Reserved 2006h Device ID 2007h Configuration Word 1 2008h Calibration Word 1 2009h Calibration Word 2 Maps to 0000h-00FFh 1FFFh 2000h Implemented 2080h Maps to 2000h-2080h Configuration Memory 3FFFh 200Ah-207Fh DS41572D-page 4 Reserved Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 3-2: PIC10F322 AND PIC10LF322 PROGRAM MEMORY MAPPING 512 W 0000h 01FFh Program Memory 2000h User ID Location 2001h User ID Location 2002h User ID Location 2003h User ID Location 2004h Reserved 2005h Reserved 2006h Device ID 2007h Configuration Word 1 2008h Calibration Word 1 2009h Calibration Word 2 Maps to 0000h-01FFh 1FFFh 2000h Implemented 2080h Maps to 2000h-2080h Configuration Memory 3FFFh 200Ah-207Fh 2011-2012 Microchip Technology Inc. Reserved Advance Information DS41572D-page 5 PIC10(L)F320/322 3.1 User ID Location A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to 2000h-2003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location may be read with code protection enabled or disabled. MPLAB® IDE only displays the 7 Least Significant bits (LSb) of each user ID location, the upper bits are not read. It is recommended that only the 7 LSbs be used if MPLAB IDE is the primary tool used to read these addresses. Note: 3.2 Device ID The device ID word for the PIC10(L)F320 and the PIC10(L)F322 is located at 2006h. This location cannot be erased or modified. DEVICEID: DEVICE ID REGISTER(1) REGISTER 3-1: R R R R R R DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 13 bit 8 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit ‘1’ = Bit is set ‘0’ = Bit is cleared -n = Value at POR W = Writable bit U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 13-5 DEV<8:0>: Device ID bits These bits are used to identify the part number. bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. TABLE 3-1: DEVICE DEVICE ID VALUES DEVICE ID VALUES DEV<8:0> REV<4:0> PIC10F320 10 1001 101 x xxxx PIC10F322 10 1001 100 x xxxx PIC10LF320 10 1001 111 x xxxx PIC10LF322 10 1001 110 x xxxx DS41572D-page 6 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 3.3 Configuration Word The PIC10(L)F320 and PIC10(L)F322 have one Configuration Word, Configuration Word 1 (2007h). The individual bits within this Configuration Word are used to enable or disable device functions such as the Brown-out Reset, code protection and Power-up Timer. 3.4 Calibration Words For the PIC10(L)F320 and PIC10(L)F322 devices, the 16 MHz internal oscillator (INTOSC) and the Brown-out Reset (BOR) are factory calibrated and stored in Calibration Words 1 and 2 (2008h and 2009h). The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration Words. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 7 PIC10(L)F320/322 REGISTER 3-2: CONFIGURATION WORD 1 U-1 R/P-1 R/P-1 R/P-1 R/P-0 — WRT1 WRT0 BORV LPBOREN R/P-1 LVP bit 8 bit 13 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE WDTE1 WDTE0 BOREN1 BOREN0 bit 7 Legend: R = Readable bit 0 = Bit is cleared P = Programmable bit ‘1’ = Bit is set R/P-1 FOSC bit 0 U = Unimplemented bit, read as ‘1’ -n = Value when blank or after Bulk Erase bit 13 Unimplemented: Reads as ‘1’ bit 12-11 WRT<1:0>: Flash Memory Self-Write Protection bits 256 W Flash memory: PIC10F320: 11 = Write protection off 10 = 000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control 01 = 000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control 00 = 000h to 0FFh write-protected, no addresses may be modified by PMCON control 512 W Flash memory: PIC10F322: 11 = Write protection off 10 = 000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control 01 = 000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control 00 = 000h to 1FFh write-protected, no addresses may be modified by PMCON control bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset Voltage (VBOR) set to 1.9V (LF parts) or 2.4V (F parts) 0 = Brown-out Reset Voltage (VBOR) set to 2.7V bit 9 LPBOREN: Low-Power Brown-out Reset Enable bit 1 = Low-power Brown-out Reset is enabled 0 = Low-power Brown-out Reset is disabled bit 8 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled. RA3/MCLR/VPP pin function is MCLR. 0 = High Voltage on MCLR/VPP must be used for programming bit 7 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = Code protection on bit 6 MCLRE: RA3/MCLR/VPP Pin Function Select bit When LVP = 1, this bit is overridden to ‘1’: pin function is MCLR, weak pull-up enabled 1 = RA3/MCLR/VPP pin function is MCLR; Weak pull-up enabled 0 = RA3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under software control bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled, SWDTEN is ignored 10 = WDT enabled while running and disabled in Sleep. SWDTEN is ignored 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled. SWDTEN is ignored DS41572D-page 8 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset enabled; SBOREN bit is ignored 10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = Brown-out Reset controlled by the SBOREN bit in the BORCON register 00 = Brown-out Reset disabled; SBOREN bit is ignored bit 0 FOSC: Oscillator Selection bit 1 = EC oscillator from CLKIN 0 = INTOSC oscillator; CLKIN not enabled 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 9 PIC10(L)F320/322 4.0 PROGRAM/VERIFY MODE In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and latched on the falling edge. In Program/Verify mode, both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/Os are automatically configured as high-impedance inputs and the address is cleared. 4.1 Program/Verify Mode Entry and Exit There are two different methods of entering Program/ Verify mode: • VPP – First entry mode • VDD – First entry mode 4.1.1 VPP – FIRST ENTRY MODE To enter Program/Verify mode via the VPP-first method the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered. Raise the voltage on MCLR from 0V to VIHH. Raise the voltage on VDD from 0V to the desired operating voltage. The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, the device will execute code when the Configuration Word has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal oscillator is selected (FOSC = 10x), and RA0 and RA1 are driven by the user application. Since this may prevent entry, VPP-First Entry mode is strongly recommended. See the timing diagram in Figure 8-2. 4.1.2 4.1.3 PROGRAM/VERIFY MODE EXIT To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figures 8-3 and 8-4. 4.2 Low-Voltage Programming (LVP) Mode The Low-Voltage Programming mode allows the PIC10(L)F320/322 devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 1 register is set to ‘1’, the lowvoltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry mode. Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least Significant bit of the Least Significant nibble must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For low-voltage programming timing, see Figure 8-7 and Figure 8-8. Exiting Program/Verify mode is done by no longer driving MCLR to VIL. See Figure 8-7 and Figure 8-8. Note: To enter LVP mode, the LSb of the Least Significant nibble must be shifted in first. This differs from entering the key sequence on other parts. VDD – FIRST ENTRY MODE To enter Program/Verify mode via the VDD-first method, the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. Raise the voltage on VDD from 0V to the desired operating voltage. Raise the voltage on MCLR from VDD or below to VIHH. The VDD-first method is useful when programming the device, when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-1. DS41572D-page 10 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 4.3 Program/Verify Commands The PIC10(L)F320 and PIC10(L)F322 devices implement 10 programming commands, each six bits in length. The commands are summarized in Table 4-1. Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay, 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. TABLE 4-1: COMMAND MAPPING FOR PIC10(L)F320 AND PIC10(L)F322 Mapping Command Data/Note Binary (MSb … LSb) Hex Load Configuration x 0 0 0 0 0 00h 0, data (14), 0 Load Data For Program Memory x 0 0 0 1 0 02h 0, data (14), 0 Read Data From Program Memory x 0 0 1 0 0 04h 0, data (14), 0 Increment Address x 0 0 1 1 0 06h Reset Address x 1 0 1 1 0 16h Begin Internally Timed Programming x 0 1 0 0 0 08h Begin Externally Timed Programming x 1 1 0 0 0 18h End Externally Timed Programming x 0 1 0 1 0 0Ah Bulk Erase Program Memory x 0 1 0 0 1 09h Internally Timed Row Erase Program Memory x 1 0 0 0 1 11h Internally Timed 4.3.1 LOAD CONFIGURATION The Load Configuration command is used to access the configuration memory (user ID locations, Configuration Word and Calibration Words). The Load Configuration command sets the address to 2000h and loads the data latches with one word of data (see Figure 4-1). Note: The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address command after the configuration memory has been accessed by the Load Configuration command. After issuing the Load Configuration command, use the Increment Address command until the proper address to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or Begin Externally Timed Programming command. FIGURE 4-1: Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write to the Configuration or Calibration Word will have no effect on the targeted word. LOAD CONFIGURATION 1 2 3 4 5 2 1 6 15 16 TDLY ICSPCLK ICSPDAT 0 0 2011-2012 Microchip Technology Inc. 0 0 0 X 0 Advance Information LSb MSb 0 DS41572D-page 11 PIC10(L)F320/322 4.3.2 LOAD DATA FOR PROGRAM MEMORY The Load Data for Program Memory command is used to load one 14-bit word into the data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is issued (see Figure 4-2). FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY 1 2 5 4 3 2 1 6 16 15 TDLY ICSPCLK 0 ICSPDAT 4.3.3 1 0 0 0 X 0 LSb MSb 0 READ DATA FROM PROGRAM MEMORY The Read Data from Program Memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program memory is code-protected (CP), the data will be read as zeros (see Figure 4-3). FIGURE 4-3: READ DATA FROM PROGRAM MEMORY 1 2 3 4 5 6 1 2 15 16 TDLY ICSPCLK ICSPDAT (from Programmer) 0 0 1 0 0 ICSPDAT (from Device) X x Input DS41572D-page 12 Advance Information LSb MSb Output Input 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 4.3.4 INCREMENT ADDRESS The address is incremented when this command is received. It is not possible to decrement the address. To reset this counter, the user must use the Reset Address command or exit Program/Verify mode and reenter it. If the address is incremented from address 1FFFh, it will wrap-around to location 0000h. If the address is incremented from 3FFFh, it will wrap-around to location 2000h. FIGURE 4-4: INCREMENT ADDRESS Next Command 1 2 4 3 2 1 6 5 3 TDLY ICSPCLK 0 ICSPDAT 1 1 0 0 X X Address 4.3.5 X X Address + 1 RESET ADDRESS The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in program memory or the configuration memory. FIGURE 4-5: RESET ADDRESS Next Command 1 2 4 3 5 6 2 1 3 TDLY ICSPCLK ICSPDAT 0 Address 2011-2012 Microchip Technology Inc. 1 1 0 1 X N Advance Information X X X 0000h DS41572D-page 13 PIC10(L)F320/322 4.3.6 BEGIN INTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. An internal timing mechanism executes the write. The user must allow for the program cycle time, TPINT, for the programming to complete. The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used to start the programming. The program memory address that is being programmed is not erased prior to being programmed. FIGURE 4-6: BEGIN INTERNALLY TIMED PROGRAMMING 1 2 5 4 3 Next Command 1 2 3 6 TPINT ICSPCLK ICSPDAT 4.3.7 0 0 0 0 1 X X X X BEGIN EXTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. To complete the programming, the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT. The program memory address that is being programmed is not erased prior to being programmed. The Begin Externally Timed Programming command cannot be used for programming the Configuration Word (see Figure 4-7). FIGURE 4-7: BEGIN EXTERNALLY TIMED PROGRAMMING End Externally Timed Programming Command 1 2 4 3 5 6 2 1 3 TPEXT ICSPCLK ICSPDAT DS41572D-page 14 0 0 0 1 1 X Advance Information 0 1 0 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 4.3.8 END EXTERNALLY TIMED PROGRAMMING This command is required after a Begin Externally Timed Programming command is given. This command must be sent within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent. After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 4-8). FIGURE 4-8: END EXTERNALLY TIMED PROGRAMMING 1 2 5 4 3 Next Command 2 1 3 6 TDIS ICSPCLK 4.3.9 1 0 ICSPDAT 0 0 1 BULK ERASE PROGRAM MEMORY X X X X After receiving the Bulk Erase Program Memory command, the erase will not complete until the time interval, TERAB, has expired. The Bulk Erase Program Memory command performs two different functions dependent on the current state of the address. Note: Address 0000h-1FFFh: Program Memory is erased The code protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command. Configuration Word is erased Address 2000h-2008h: Program Memory is erased Configuration Word is erased User ID Locations are erased A Bulk Erase Program Memory command should not be issued when the address is greater than 2008h. FIGURE 4-9: BULK ERASE PROGRAM MEMORY 1 2 4 3 5 Next Command 2 1 3 6 TERAB ICSPCLK ICSPDAT 1 2011-2012 Microchip Technology Inc. 0 0 1 0 X Advance Information X X X DS41572D-page 15 PIC10(L)F320/322 4.3.10 ROW ERASE PROGRAM MEMORY This command erases the 16-word row of program memory pointed to by PC<13:5>. If the program memory array is protected (CP = 0) or the PC points to the configuration memory (> 0x2000), the command is ignored. When the address is 2000h-2008h, the Row Erase Program Memory command will only erase the user ID locations, regardless of the Configuration bit CP setting. After receiving the Row Erase Program Memory command, the erase will not be complete until the time interval, TERAR, has expired. FIGURE 4-10: ROW ERASE PROGRAM MEMORY 1 2 4 3 5 Next Command 2 1 3 6 TERAR ICSPCLK ICSPDAT DS41572D-page 16 1 0 0 0 1 X Advance Information X X X 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 5.0 PROGRAMMING ALGORITHMS The PIC10(L)F320 and PIC10(L)F322 devices have the capability of storing 16 14-bit words in its data latches. The data latches are internal to the PIC10(L)F320 and PIC10(L)F322 devices and are only used for programming. The data latches allow the user to program up to 16 program words with a single Begin Externally Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally Timed Programming or Begin Internally Timed Programming command is given. The data latches are aligned with the 5 LSb of the address. The address at the time the Begin Externally Timed Programming or Begin Internally Timed Programming command is given will determine which location(s) in memory are written. Writes cannot cross a physical 16-word boundary. For example, attempting to write from address 0002h-0021h will result in data being written to 0020h-003Fh. If more than 16 data latches are written without a Begin Externally Timed Programming or Begin Internally Timed Programming command, the data in the data latches will be overwritten. The following figures show the recommended flowcharts for programming. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 17 PIC10(L)F320/322 FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART Start Enter Programming Mode Bulk Erase Device(3) Write Program Memory(1) Write User IDs Verify Program Memory Verify User IDs Write Configuration Word(2) Verify Configuration Word Exit Programming Mode Done Note 1: DS41572D-page 18 See Figure 5-2. 2: See Figure 5-5. 3: See Figure 5-6. Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 5-2: PROGRAM MEMORY FLOWCHART Start Bulk Erase Program Memory(1, 2) Program Cycle(3) Read Data from Program Memory Data Correct? No Report Programming Failure Yes Increment Address Command No All Locations Done? Yes Done Note 1: This step is optional if the device has already been erased or has not been previously programmed. 2: If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6. 3: See Figure 5-3 or Figure 5-4. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 19 PIC10(L)F320/322 FIGURE 5-3: ONE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS DS41572D-page 20 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Latch 1 Increment Address Command Load Data for Program Memory Latch 2 Increment Address Command Load Data for Program Memory Latch 32 Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 21 PIC10(L)F320/322 FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART Start Load Configuration Bulk Erase Program Memory(1) One-word Program Cycle(2) (User ID) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 2004h? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle(2) (Config. Word) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command One-word Program Cycle(2) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Note 1: This step is optional if the device is erased or not previously programmed. 2: See Figure 5-3. DS41572D-page 22 Advance Information Done 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 5-6: ERASE FLOWCHART Start Load Configuration Bulk Erase Program Memory Done Note: This sequence does not erase the Calibration Words. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 23 PIC10(L)F320/322 6.0 CODE PROTECTION Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations, 0000h-00FFh for the PIC10(L)F320 and 0000h-01FFh for the PIC10(L)F322, will read as ‘0’ and further programming of the program memory is disabled. Program memory can still be read by user code during program execution. The user ID locations and Configuration Word can be programmed and read out regardless of the code protection settings. 6.1 Enabling Code Protection Code protection is enabled by programming the CP bit in Configuration Word 1 to ‘0’. 6.2 Disabling Code Protection The only way to disable code protection is to use the Bulk Erase Program Memory command. DS41572D-page 24 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 7.0 HEX FILE USAGE 7.3 In the hex file there are two bytes per program word stored in the Intel® INH8M hex format. Data is stored LSB first, MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. (Example: The Configuration Word 1 is stored at 2007h on the PIC10(L)F320 and PIC10(L)F322. In the hex file this will be at location 400Eh-400Fh). 7.1 Configuration Word To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Word and user ID locations from the hex file. If the Configuration Word information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and user ID information should be included. 7.2 Device ID and Revision If a device ID is present in the hex file at 400Ch-400Dh (2006h on the part), the programmer should verify the device ID (excluding the revision) against the value read from the part. On a mismatch condition, the programmer should generate a warning message. Checksum Computation The checksum is calculated by two different methods, dependent on the setting of the CP Configuration bit. TABLE 7-1: CONFIGURATION WORD MASK VALUES Device Config. Word 1 Mask PIC10F320 1FFFh PIC10LF320 1FFFh PIC10F322 1FFFh PIC10LF322 1FFFh 7.3.1 CODE PROTECTION DISABLED With the code protection disabled, the checksum is computed by reading the contents of the PIC10(L)F320 and PIC10(L)F322 program memory locations and adding up the program memory data, starting at address 0000h, up to the maximum user addressable location, 00FFh for the PIC10(L)F320 and 01FFh for the PIC10(L)F322. Any Carry bit exceeding 16 bits are neglected. Additionally, the relevant bits of the Configuration Word are added to the checksum. All unused Configuration bits are masked to ‘0’. See Table 7-1 for Configuration Word mask values. Example 7-1 through Example 7-4 shown below are for a blank device and for a device with 00AAh at the first and last program memory locations. EXAMPLE 7-1: PIC10F320 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC10F320), BLANK DEVICE Sum of Memory addresses 0000h-00FFh(1) Configuration Word 1(2) 3FFFh Configuration Word 1 mask(3) Checksum FF00h 1FFFh = FF00h + (3FFFh and 1FFFh) = FF00h + 1FFFh = 1EFFh(4) Note 1: Sum of Memory addresses = (Total number of program memory address locations) x (3FFFh) = FF00h, truncated to 16 bits. 2: Configuration Word 1 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’. 4: Truncate to 16 bits. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 25 PIC10(L)F320/322 EXAMPLE 7-2: PIC10LF320 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC10LF320), 00AAh AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-00FFh(1) 8056h 1(2) 3FFFh Configuration Word Configuration Word 1 mask(3) Checksum 1FFFh = 8056h + (3FFFh and 1FFFh) = 8056h + 1FFFh = A055h(4) Note 1: Total number of program memory address locations: 00FFh + 1 = 0100h. Then, 0100h - 2 = 00FEh. Thus, [(00FEh x 3FFFh) + (2 x 00AAh)] = 8056h, truncated to 16 bits. 2: Configuration Word 1 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits that are ‘0’. 4: Truncate to 16 bits. EXAMPLE 7-3: PIC10F322 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC10F322), BLANK DEVICE Sum of Memory addresses 0000h-01FFh(1) FE00h Configuration Word 1(2) 3FFFh Configuration Word 1 mask(3) 1FFFh Checksum = FE00h + (3FFFh and 1FFFh) = FE00h + 1FFFh = 1DFFh Note 1: Sum of Memory addresses = (Total number of program memory address locations) x (3FFFh) = FE00h, truncated to 16 bits. 2: Configuration Word 1 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’. EXAMPLE 7-4: PIC10LF322 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC10LF322), 00AAh AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-01FFh(1) Configuration Word 1(2) 3FFFh Configuration Word 1 mask(3) Checksum 7F56h 1FFFh = 7F56h + (3FFFh and 1FFFh) = 7F56h + 1FFFh = 9F55h Note 1: Total number of program memory address locations: 01FFh + 1 = 0200h. Then, 0200h - 2 = 01FEh. Thus, [(01FEh x 3FFFh) + (2 x 00AAh)] = 7F56h, truncated to 16 bits. 2: Configuration Word 1 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits that are ‘0’. DS41572D-page 26 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 7.3.2 CODE PROTECTION ENABLED With the program code protection enabled, the checksum is computed in the following manner: the Least Significant nibble of each user ID is used to create a 16-bit value. The masked value of user ID location 2000h is the Most Significant nibble. This Sum of user IDs is summed with the Configuration Word (all unimplemented Configuration bits are masked to ‘0’). Example 7-5 through Example 7-8 shown below are for a blank device and for a device with 00AAh at the first and last program memory locations. Also, see Table 7-1 for Configuration Word mask values with code protection enabled. EXAMPLE 7-5: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC10F320), BLANK DEVICE PIC10F320 Configuration Word 1(2) 3F7Fh Configuration Word 1 mask(3) 1FFFh (2000h)(1) 0001h User ID (2001h)(1) 0007h (1) 000Ah User ID (2003h)(1) 000Fh User ID User ID (2002h) Sum of User IDs(4) = (0001h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (000Ah and 000Fh) << 4 + (000Fh and 000Fh) = 1000h + 0700h + 00A0h + 000Fh = 17AFh Checksum = (3F7Fh and 1FFFh) + Sum of User IDs = 1F7Fh + 17AFh = 372Eh Note 1: User ID values in this example are random values. 2: Configuration Word 1 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 27 PIC10(L)F320/322 EXAMPLE 7-6: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC10F322), BLANK DEVICE PIC10F322 Configuration Word 1 (2) 3F7Fh Configuration Word 1 mask(3) 1FFFh (1) 0001h User ID (2001h)(1) 0007h (1) 000Ah User ID (2003h)(1) 000Fh User ID (2000h) User ID (2002h) Sum of User IDs(4) = (0001h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (000Ah and 000Fh) << 4 + (000Fh and 000Fh) = 1000h + 0700h + 00A0h + 000Fh = 17AFh Checksum = (3F7Fh and 1FFFh) + Sum of User IDs = 1F7Fh + 17AFh = 372Eh Note 1: User ID values in this example are random values. 2: Configuration Word 1 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. EXAMPLE 7-7: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC10LF320), 00AAh AT FIRST AND LAST ADDRESS PIC10LF320 Configuration Word 1(2) 3F7Fh Configuration Word 1 mask (3) 1FFFh User ID (2000h)(1) 0009h User ID (2001h)(1) 0008h User ID (2002h)(1) 000Dh User ID (2003h)(1) Sum of User IDs (4) 0005h = (0009h and 000Fh) << 12 + (0008h and 000Fh) << 8 + (000Dh and 000Fh) << 4 + (0005h and 000Fh) = 9000h + 0800h + 00D0h + 0005h = 98D5h Checksum = (3F7Fh and 1FFFh) + Sum of User IDs = 1F7Fh + 98D5h = B854h Note 1: User ID values in this example are random values. 2: Configuration Word 1 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. DS41572D-page 28 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 EXAMPLE 7-8: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC10LF322), 00AAh AT FIRST AND LAST ADDRESS PIC10LF322 Configuration Word 1(2) 3F7Fh Configuration Word 1 mask(3) 1FFFh (1) 0009h User ID (2001h)(1) 0008h (1) 000Dh User ID (2003h)(1) 0005h User ID (2000h) User ID (2002h) Sum of User IDs(4) = (0009h and 000Fh) << 12 + (0008h and 000Fh) << 8 + (000Dh and 000Fh) << 4 + (0005h and 000Fh) = 9000h + 0800h + 00D0h + 0005h = 98D5h Checksum = (3F7Fh and 1FFFh) + Sum of User IDs = 1F7Fh + 98D5h = B854h Note 1: User ID values in this example are random values. 2: Configuration Word 1 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 29 PIC10(L)F320/322 8.0 ELECTRICAL SPECIFICATIONS Refer to device specific data sheet for absolute maximum ratings. TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature +10°C TA +40°C AC/DC CHARACTERISTICS Sym. VDD Characteristics Supply Voltage (VDDMIN, VDDMAX) Min. Supply Voltages and currents PIC10F320 2.3 — PIC10F322 PIC10LF320 PIC10LF322 VPEW VPBE Type. Read/Write and Row Erase operations VPBE Bulk Erase operations PIC10F320 PIC10F322 Bulk Erase operations PIC10LF320 PIC10LF322 Max. Units 5.5 V 1.8 — 3.6 V VDDMIN 2.7 — — VDDMAX VDDMAX V V 2.3 — 5.5 V 2.3 — 3.6 V IDDI Current on VDD, Idle — — 1.0 mA IDDA Current on VDD, program cycle or Bulk Erase in progress — — 5.0 mA High voltage on MCLR/VPP for Program/Verify mode entry 8.0 — 9.0 V TVHHR MCLR rise time (VDD to VIHH) for Program/Verify mode entry — — 1.0 s IPP Current on MCLR/VPP 600 A VIH VIL I/O pins (ICSPCLK, ICSPDAT) input high level (ICSPCLK, ICSPDAT) input low level ICSPDAT output high level Conditions/ Comments VPP VIHH VOH 0.8 VDD — VDD-0.7 VDD-0.7 VDD-0.7 — — — 0.2 VDD V V — VDD V VSS — VSS+0.6 VSS+0.6 VSS+0.6 V — ns — s — — — — ns ns ns ns 80 ns 80 ns 80 ns ICSPDAT output low level VOL TENTS TENTH TCKL TCKH TDS TDH TCO TLZD THZD Programming mode entry and exit Programing mode entry setup time: ICSPCLK, 100 — ICSPDAT setup time before VDD or MCLR Programing mode entry hold time: ICSPCLK, 250 — ICSPDAT hold time after VDD or MCLR Serial Program/Verify Clock Low Pulse Width 100 — Clock High Pulse Width 100 — Data in setup time before clock 100 — Data in hold time after clock 100 — Clock to data out valid (during a Read Data 0 — command) Clock to data low-impedance (during a Read 0 — Data command) Clock to data high-impedance (during a Read 0 — Data command) DS41572D-page 30 Advance Information IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 2 mA, VDD = 1.8V IOH = 8 mA, VDD = 5V IOH = 6 mA, VDD = 3.3V IOH = 3 mA, VDD = 1.8V 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE (CONTINUED) Standard Operating Conditions (unless otherwise stated) Operating Temperature +10°C TA +40°C AC/DC CHARACTERISTICS Sym. TDLY TERAB TERAR TPINT TPEXT TDIS TEXIT Characteristics Data input not driven to next clock input (delay required between command/data or command/ command) Bulk Erase cycle time Row Erase cycle time Internally timed programming operation time Externally timed programming pulse Time delay from program to compare (HV discharge time) Time delay when exiting Program/Verify mode 2011-2012 Microchip Technology Inc. Min. Type. Max. Units 1.0 — — s — — — — — — — — 5 2.5 2.5 5 ms ms ms ms 1.0 — 2.1 ms 100 — — s 1 — — s Advance Information Conditions/ Comments Program memory Configuration fuses 10°C TA +40°C Program memory DS41572D-page 31 PIC10(L)F320/322 8.1 AC Timing Diagrams FIGURE 8-1: FIGURE 8-4: PROGRAMMING MODE ENTRY – VDD FIRST TENTS PROGRAMMING MODE EXIT – VDD LAST TEXIT VIHH TENTH MCLR/VPP is at VDD VIL VIHH MCLR/VPP is at VDD VIL VDD ICSPDAT VDD ICSPCLK ICSPDAT ICSPCLK FIGURE 8-5: CLOCK AND DATA TIMING TCKH FIGURE 8-2: PROGRAMMING MODE ENTRY – MCLR/VPP FIRST TENTS TCKL ICSPCLK TENTH TDS TDH VIHH ICSPDAT as Input MCLR/VPP VIL TCO VDD ICSPDAT as Output ICSPDAT TLZD ICSPCLK FIGURE 8-3: PROGRAMMING MODE EXIT – MCLR/VPP LAST TEXIT ICSPDAT from Input to Output THZD ICSPDAT from Output to Input VIHH MCLR/VPP VIL VDD ICSPDAT ICSPCLK DS41572D-page 32 Advance Information 2011-2012 Microchip Technology Inc. PIC10(L)F320/322 FIGURE 8-6: COMMAND-PAYLOAD TIMING TDLY 1 2 3 4 5 X X X X X 1 6 2 15 16 ICSPCLK ICSPDAT 0 LSb X Payload Command FIGURE 8-7: MSb 0 Next Command LVP ENTRY (POWERING UP) VDD MCLR TENTS TENTH 33 clocks TCKH TCKL ICSPCLK TDH ICSPDAT FIGURE 8-8: LSb of Pattern 0 TDS 1 2 ... MSb of Pattern 31 LVP ENTRY (POWERED) VDD MCLR TENTH 33 Clocks TCKH TCKL ICSPCLK TDH ICSPDAT LSb of Pattern 0 TDS 1 2 ... MSb of Pattern 31 Note 1: Sequence matching can start with no edge on MCLR first. 2011-2012 Microchip Technology Inc. Advance Information DS41572D-page 33 PIC10(L)F320/322 APPENDIX A: REVISION HISTORY Revision A (03/2011) Initial release of this document. Revision B (05/2011) Added sections 1.1.1, 1.1.2 and 1.1.2.1; Updated Figures 2-1 and 2-2; Updated Table 3-1; Updated Registers 3-1 and 3-2; Other minor corrections. Revision C (10/2011) Updated Examples 7-1 to 7-8; Updated Electrical Specifications; Other minor corrections. Revision D (03/2012) Added new section 4.2, Low-Voltage Programming (LVP) mode; Added Note to section 4.3.1; Added Figures 8-7 and 8-8. DS41572D-page 34 Advance Information 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620761571 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2011-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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