MICROCHIP PIC16F1507T

PIC16(L)F1507
Data Sheet
20-Pin Flash, 8-Bit Microcontrollers
 2011 Microchip Technology Inc.
Preliminary
DS41586A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-342-5
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41586A-page 2
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
20-Pin Flash, 8-Bit Microcontrollers
High-Performance RISC CPU:
Analog Features:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Up to 3.5 Kbytes Linear Program Memory
Addressing
• Up to 128 bytes Linear Data Memory Addressing
• Operating Speed:
- DC – 20 MHz clock input
- DC – 125 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Up to 12 channels
- Auto acquisition capability
- Conversion available during Sleep
- FVR available as channel
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Factory calibrated to  1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
Special Microcontroller Features:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1507)
- 2.3V to 5.5V (PIC16F1507)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-Out Reset
(LPBOR)
• Extended Watch-Dog Timer (WDT):
- Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via two
pins
• Enhanced Low-Voltage Programming (LVP)
• Power-Saving Sleep mode
Low-Power Features (PIC16LF1507):
• Standby Current:
- 20 nA @ 1.8V, typical
• Operating Current:
- 30 A per MHz @ 1.8V, typical
• Low-Power Watchdog Timer Current:
- 300 nA @ 1.8V, typical
 2011 Microchip Technology Inc.
Peripheral Features:
• 17 I/O Pins and 1 Input-only Pin:
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable
interrupt-on-change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• Two Configurable Logic Cell (CLC) modules:
- 22 individual input sources
- Four inputs and 16 selectable input sources
per module
- Software selectable logic functions including:
AND/OR/XOR/D Flop/D Latch/SR/JK
- External and internal inputs/outputs
- Operation while in Sleep
• Numerically Controlled Oscillator (NCO):
- 20-bit Accumulator
- 16-bit Increment
- Linear frequency control
- High-speed clock input
- Selectable Output modes
- Fixed Duty Cycle (FDC) mode
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- 6 selectable signal sources
- Selectable falling and rising edge dead-band
control
- Polarity control
- 2 auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO
Preliminary
DS41586A-page 3
PIC16(L)F1507
PIC16(L)F1507 Family Types
Device
Program
Memory Flash
(words)
PIC16F1507
2048
PIC16LF1507
Note 1: One pin is input-only.
FIGURE 1:
SRAM
(bytes)
I/O(1)
10-bit A/D
(ch)
Timers
8/16-bit
PWM
CWG
CLC
NCO
128
18
12
2/1
4
1
2
1
20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1507
PDIP, SOIC, SSOP
20
RA5
2
19
VSS
RA0/ICSPDAT
RA4
18
RA1/ICSPCLK
MCLR/VPP/RA3
3
4
17
RA2
RC5
5
RC4
6
RC3
7
RC6
RC7
RB7
PIC16LF1507
1
PIC16F1507
VDD
16
RC0
15
RC1
14
RC2
8
13
RB4
9
12
RB5
10
11
RB6
Note: See Table 1 for location of all peripheral functions.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 4
PIC16(L)F1507
20-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1507
VSS
RA5
VDD
RA4
QFN 4x4
RA0/ICSPDAT
FIGURE 2:
20 19 18 17 16
3
RC3
4
RC6
5
6
7
8
15
RA1/ICSPCLK
14
RA2
13
RC0
12
RC1
11
RC2
9 10
RB4
RC4
PIC16F1507
PIC16LF1507
RB5
2
RB6
RC5
RB7
1
RC7
MCLR/VPP/RA3
Note: See Table 1 for location of all peripheral functions.
DS41586A-page 5
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
RA1
18
15
AN1
RA2
17
14
AN2
RA3
4
1
RA4
3
RA5
2
RB4
—
—
VREF+
—
—
—
—
—
CWG1FLT
—
CLC1(1)
T0CKI
—
—
—
—
CLC1IN0
—
20
AN3
—
—
—
—
19
—
—
—
NCO1CLK
—
13
10
AN10
—
—
—
—
RB5
12
9
AN11
—
—
—
RB6
11
8
—
—
—
—
Basic
—
Pull-up
—
Interrupt
—
PWM
Timers
AN0
CLC
16
NCO
A/D
19
CWG
20-Pin QFN
RA0
Reference
20-Pin PDIP/SOIC/SSOP
20-PIN ALLOCATION TABLE (PIC16(L)F1507)
I/O
TABLE 1:
—
IOC
Y
ICSPDAT
—
IOC
Y
ICSPCLK
PWM3
INT/
IOC
Y
—
—
IOC
Y
MCLR
VPP
T1G
—
IOC
Y
CLKOUT
T1CKI
—
IOC
Y
CLKIN
—
—
IOC
Y
—
—
—
—
IOC
Y
—
—
—
—
IOC
Y
—
RB7
10
7
—
—
—
—
—
—
—
IOC
Y
—
RC0
16
13
AN4
—
—
—
CLC2
—
—
—
—
—
RC1
15
12
AN5
—
—
NCO1(1)
—
—
PWM4
—
—
—
RC2
14
11
AN6
—
—
—
—
—
—
—
—
—
RC3
7
4
AN7
—
—
—
CLC2IN0
—
PWM2
—
—
—
RC4
6
3
—
—
CWG1B
—
CLC2IN1
—
—
—
—
—
RC5
5
2
—
—
CWG1A
—
CLC1(2)
—
PWM1
—
—
—
—
RC6
8
5
AN8
—
—
NCO1(2)
—
—
—
—
—
RC7
9
6
AN9
—
—
—
CLC1IN1
—
—
—
—
—
VDD
1
18
—
—
—
—
—
—
—
—
—
VDD
VSS
20
17
—
—
—
—
—
—
—
—
—
VSS
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 6
PIC16(L)F1507
Table of Contents
1.0 Device Overview ............................................................................................................................................................................. 9
2.0.Enhanced Mid-Range CPU........................................................................................................................................................... 13
3.0 Memory Organization.................................................................................................................................................................... 15
4.0 Device Configuration..................................................................................................................................................................... 39
5.0 Oscillator Module (With Fail-Safe Clock Monitor) ......................................................................................................................... 45
6.0 Resets ........................................................................................................................................................................................... 53
7.0 Interrupts ....................................................................................................................................................................................... 61
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................... 75
9.0 Watchdog Timer............................................................................................................................................................................ 79
10.0 Flash Program Memory Control .................................................................................................................................................. 83
11.0 I/O Ports ...................................................................................................................................................................................... 99
12.0 Interrupt-On-Change ................................................................................................................................................................. 111
13.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 117
14.0 Temperature Indicator Module .................................................................................................................................................. 119
15.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 121
16.0 Timer0 Module .......................................................................................................................................................................... 135
17.0 Timer1 Module with Gate Control ............................................................................................................................................. 139
18.0 Timer2 Modules ........................................................................................................................................................................ 151
19.0 PWM Modules ........................................................................................................................................................................... 155
20.0 Configurable Logic Cell (CLC) ................................................................................................................................................... 161
21.0 Numerically Controlled Oscillator (NCO) Module ...................................................................................................................... 177
22.0 Complementary Waveform Generator (CWG) Module ............................................................................................................. 187
23.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 203
24.0 Instruction Set Summary ........................................................................................................................................................... 207
25.0 Electrical Specifications ............................................................................................................................................................ 221
26.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 239
27.0 Development Support ............................................................................................................................................................... 241
28.0 Packaging Information .............................................................................................................................................................. 245
Appendix A: Data Sheet Revision History ......................................................................................................................................... 255
Index ................................................................................................................................................................................................. 257
The Microchip Web Site .................................................................................................................................................................... 263
Customer Change Notification Service ............................................................................................................................................. 263
Customer Support ............................................................................................................................................................................. 263
Reader Response ............................................................................................................................................................................. 264
Product Identification System ............................................................................................................................................................ 265
Worldwide Sales and Service ........................................................................................................................................................... 266
DS41586A-page 7
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 8
PIC16(L)F1507
1.0
DEVICE OVERVIEW
The PIC16(L)F1507 are described within this data sheet.
They are available in 20 pin packages. Figure 1-1 shows
a block diagram of the PIC16(L)F1507 devices.
Tables 1-2 shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
Peripheral
PIC16LF1507
DEVICE PERIPHERAL
SUMMARY
PIC16F1507
TABLE 1-1:
Analog-to-Digital Converter (ADC)
●
●
Complementary Wave Generator (CWG)
●
●
Fixed Voltage Reference (FVR)
●
●
Numerically Controlled Oscillator (NCO)
●
●
Temperature Indicator
●
●
CLC1
●
●
CLC2
●
●
PWM1
●
●
PWM2
●
●
PWM3
●
●
PWM4
●
●
Timer0
●
●
Timer1
●
●
Timer2
●
●
Configurable Logic Cell (CLC)
PWM Modules
Timers
DS41586A-page 9
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 1-1:
PIC16(L)F1507 BLOCK DIAGRAM
Program
Flash Memory
RAM
CLKOUT
Timing
Generation
CLKIN
INTRC
Oscillator
PORTA
CPU
PORTB
(Figure 2-1)
MCLR
PORTC
CLC1
Temp.
Indicator
Note
1:
2:
ADC
10-Bit
CLC2
Timer0
FVR
Timer1
PWM1
Timer2
PWM2
NCO1
CWG1
PWM3
PWM4
See applicable chapters for more information on peripherals.
See Table 1-1 for peripherals available on specific devices.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 10
PIC16(L)F1507
TABLE 1-2:
PIC16(L)F1507 PINOUT DESCRIPTION
Name
RA0/AN0/ICSPDAT
RA1/AN1/VREF+/ICSPCLK
RA2/AN2/T0CKI/INT/PWM3/
CLC1(1)/CWG1FLT
RA3/CLC1IN0/VPP/MCLR
RA4/AN3/CLKOUT/T1G
RA5/CLKIN/T1CKI/NCO1CLK
RB4/AN10
Function
Input
Type
RA0
TTL
AN0
AN
Output
Type
Description
CMOS General purpose I/O.
—
A/D Channel input.
ICSPDAT
ST
CMOS ICSP™ Data I/O.
RA1
TTL
CMOS General purpose I/O.
AN1
AN
—
A/D Channel input.
VREF+
AN
—
A/D Positive Voltage Reference input.
ICSPCLK
ST
—
Serial Programming Clock.
RA2
ST
CMOS General purpose I/O.
AN2
AN
—
A/D Channel input.
T0CKI
ST
—
Timer0 clock input.
INT
ST
—
External interrupt.
PWM3
—
CMOS Pulse Width Module source output.
CMOS Configurable Logic Cell source output.
CLC1
—
CWG1FLT
ST
—
Complementary Waveform Generator Fault input.
RA3
TTL
—
General purpose input.
CLC1IN0
ST
—
Configurable Logic Cell source input.
VPP
HV
—
Programming voltage.
MCLR
ST
—
Master Clear with internal pull-up.
RA4
TTL
AN3
AN
CLKOUT
—
T1G
ST
CMOS General purpose I/O.
—
A/D Channel input.
CMOS FOSC/4 output.
—
Timer1 Gate input.
RA5
TTL
CLKIN
CMOS
CMOS General purpose I/O.
—
T1CKI
ST
—
Timer1 clock input.
NCO1CLK
ST
—
Numerically Controlled Oscillator Clock source input.
External clock input (EC mode).
RB4
TTL
AN10
AN
RB5
TTL
AN11
AN
RB6
RB6
TTL
RB7
RB7
TTL
CMOS General purpose I/O.
RC0/AN4/CLC2
RC0
TTL
CMOS General purpose I/O.
AN4
AN
RB5/AN11
RC1/AN5/PWM4/NCO1(1)
RC2/AN6
CLC2
—
RC1
TTL
AN5
AN
PWM4
—
NCO1
—
RC2
TTL
AN6
AN
CMOS General purpose I/O.
—
A/D Channel input.
CMOS General purpose I/O.
—
A/D Channel input.
CMOS General purpose I/O.
—
A/D Channel input.
CMOS Configurable Logic Cell source output.
CMOS General purpose I/O.
—
A/D Channel input.
CMOS Pulse Width Module source output.
CMOS Numerically Controlled Oscillator is source output.
CMOS General purpose I/O.
—
A/D Channel input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
DS41586A-page 11
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 1-2:
PIC16(L)F1507 PINOUT DESCRIPTION (CONTINUED)
Name
RC3/AN7/PWM2/CLC2IN0
RC4/CLC2IN1/CWG1B
RC5/PWM1/CLC1(2)/
CWG1A
RC6/AN8/NCO1(2)
RC7/AN9/CLC1IN1
Function
Input
Type
RC3
TTL
AN7
AN
PWM2
—
CLC2IN0
ST
RC4
TTL
CLC2IN1
ST
CWG1B
—
RC5
TTL
PWM1
—
Output
Type
Description
CMOS General purpose I/O.
—
A/D Channel input.
CMOS Pulse Width Module source output.
—
Configurable Logic Cell source input.
CMOS General purpose I/O.
—
Configurable Logic Cell source input.
CMOS CWG complementary output.
CMOS General purpose I/O.
CMOS PWM output.
CLC1
—
CMOS Configurable Logic Cell source output.
CWG1A
—
CMOS CWG primary output.
RC6
TTL
CMOS General purpose I/O.
AN8
AN
NCO1
—
RC7
TTL
—
A/D Channel input.
CMOS Numerically Controlled Oscillator source output.
CMOS General purpose I/O.
AN8
AN
—
A/D Channel input.
CLC1IN1
ST
—
Configurable Logic Cell source input.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 12
PIC16(L)F1507
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
•
•
•
•
Automatic Interrupt Context Saving
16-level Stack with Overflow and Underflow
File Select Registers
Instruction Set
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 “Stack” for more
details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 24.0 “Instruction Set Summary” for more
details.
DS41586A-page 13
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
8
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
CLKIN
CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Internal
Oscillator
Block
 2011 Microchip Technology Inc.
MUX
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
ALU
8
W Reg
VSS
Preliminary
DS41586A-page 14
PIC16(L)F1507
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
TABLE 3-1:
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
3.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See
Figure 3-1).
DEVICE SIZES AND ADDRESSES
Device
PIC16F1507
PIC16LF1507
DS41586A-page 15
Program Memory Space (Words)
Last Program Memory Address
2,048
07FFh
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1507
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
3.1.1
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1
RETLW Instruction
Stack Level 0
Stack Level 1
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
Stack Level 15
EXAMPLE 3-1:
Reset Vector
0000h
Interrupt Vector
0004h
0005h
constants
BRW
RETLW
RETLW
RETLW
RETLW
Page 0
Rollover to Page 0
Wraps to Page 0
07FFh
0800h
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
Wraps to Page 0
 2011 Microchip Technology Inc.
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
call constants
;… THE CONSTANT IS IN W
Wraps to Page 0
Rollover to Page 0
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
7FFFh
Preliminary
DS41586A-page 16
PIC16(L)F1507
3.1.1.2
Indirect Read with FSR
3.2.1
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For for detailed
information, see Table 3-4.
TABLE 3-2:
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2
CORE REGISTERS
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
•
•
•
•
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
DS41586A-page 17
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 3-1:
U-0
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 24.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
STATUS: STATUS REGISTER
U-0
—
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
—
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
—
TO
PD
Z
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 18
PIC16(L)F1507
3.2.2
SPECIAL FUNCTION REGISTER
FIGURE 3-2:
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.
3.2.3
7-bit Bank Offset
0Bh
0Ch
GENERAL PURPOSE RAM
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
1Fh
20h
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4
Memory Region
00h
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1
BANKED MEMORY
PARTITIONING
General Purpose RAM
(80 bytes maximum)
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5
DEVICE MEMORY MAPS
The memory maps for PIC16(L)F1507 are as shown in
Table 3-3.
DS41586A-page 19
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507 MEMORY MAP
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTA
PORTB
PORTC
—
—
PIR1
PIR2
PIR3
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
—
—
Core Registers
(Table 3-2)
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
General
Purpose
Register
80 Bytes
0BFh
0C0h
Common RAM
 2011 Microchip Technology Inc.
07Fh
Legend:
TRISA
TRISB
TRISC
—
—
PIE1
PIE2
PIE3
—
OPTION_REG
PCON
WDTCON
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
ADCON2
General
Purpose
Register
32 Bytes
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
LATA
LATB
LATC
—
—
—
—
—
—
—
BORCON
FVRCON
—
—
—
—
—
APFCON
—
—
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
ANSELA
ANSELB
ANSELC
—
—
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
BANK 5
280h
WPUA
WPUB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
Unimplemented
Read as ‘0’
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
Unimplemented
Read as ‘0’
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
Unimplemented
Read as ‘0’
—
—
—
—
—
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
0EFh
0F0h
06Fh
070h
BANK 2
100h
0FFh
Common RAM
(Accesses
70h – 7Fh)
16Fh
170h
17Fh
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h – 7Fh)
26Fh
270h
27Fh
Common RAM
(Accesses
70h – 7Fh)
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h – 7Fh)
36Fh
370h
37Fh
Common RAM
(Accesses
70h – 7Fh)
3EFh
3F0h
3FFh
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1507
DS41586A-page 20
TABLE 3-3:
 2011 Microchip Technology Inc.
TABLE 3-3:
PIC16(L)F1507 MEMORY MAP (CONTINUED)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Preliminary
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
46Fh
470h
47Fh
4EFh
4F0h
4FFh
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
DS41586A-page 21
87Fh
Legend:
Common RAM
(Accesses
70h – 7Fh)
56Fh
570h
57Fh
8FFh
5EFh
5F0h
5FFh
= Unimplemented data memory locations, read as ‘0’
64Fh
650h
67Fh
6EFh
6F0h
6FFh
76Fh
770h
77Fh
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 23
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B7Fh
Common RAM
(Accesses
70h – 7Fh)
B80h
Core Registers
(Table 3-2)
B6Fh
B70h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
BANK 22
Unimplemented
Read as ‘0’
AFFh
Common RAM
(Accesses
70h – 7Fh)
B0Bh
B0Ch
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
AEFh
AF0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B00h
A8Bh
A8Ch
Common RAM
(Accesses
70h – 7Fh)
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
BANK 21
Unimplemented
Read as ‘0’
A7Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
A6Fh
A70h
—
—
—
—
—
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1CON2
—
—
—
—
—
—
—
—
—
—
A80h
A0Bh
A0Ch
Common RAM
(Accesses
70h – 7Fh)
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
BANK 20
Unimplemented
Read as ‘0’
9FFh
Common RAM
(Accesses
70h – 7Fh)
BANK 14
700h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
9EFh
9F0h
—
—
—
—
—
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
—
—
—
A00h
98Bh
98Ch
Common RAM
(Accesses
70h – 7Fh)
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
BANK 19
Unimplemented
Read as ‘0’
97Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 13
680h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
96Fh
970h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
980h
90Bh
90Ch
Common RAM
(Accesses
70h – 7Fh)
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
BANK 18
Unimplemented
Read as ‘0’
8EFh
8F0h
Common RAM
(Accesses
70h – 7Fh)
BANK 12
600h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
900h
88Bh
88Ch
86Fh
870h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
BANK 17
880h
80Bh
80Ch
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 16
800h
—
—
—
—
—
—
—
—
—
—
—
—
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
—
NCO1CON
NCO1CLK
BANK 11
580h
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1507
Common RAM
(Accesses
70h – 7Fh)
BANK 10
500h
PIC16(L)F1507 MEMORY MAP (CONTINUED)
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
Preliminary
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as ‘0’
C6Fh
C70h
 2011 Microchip Technology Inc.
CFFh
Legend:
Common RAM
(Accesses
70h – 7Fh)
BANK 26
D00h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as ‘0’
CEFh
CF0h
CFFh
Common RAM
(Accesses
70h – 7Fh)
BANK 27
D80h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Unimplemented
Read as ‘0’
D6Fh
D70h
D7Fh
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’.
BANK 28
E00h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
Unimplemented
Read as ‘0’
DEFh
DF0h
DFFh
Common RAM
(Accesses
70h – 7Fh)
BANK 29
E80h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Core Registers
(Table 3-2)
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
Unimplemented
Read as ‘0’
E6Fh
E70h
E7Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 30
F00h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BANK 31
F80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
See Table 3-3 for
F18h register mapping
F19h
details
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-3 for
F98h register mapping
F99h
details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
F6Fh
F70h
FEFh
FF0h
Unimplemented
Read as ‘0’
EEFh
EF0h
EFFh
Common RAM
(Accesses
70h – 7Fh)
F7Fh
Common RAM
(Accesses
70h – 7Fh)
FFFh
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1507
DS41586A-page 22
TABLE 3-3:
PIC16(L)F1507
TABLE 3-3:
PIC16(L)F1507 MEMORY MAP (CONTINUED)
Bank 31
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F6Fh
Legend:
DS41586A-page 23
F8Ch
—
—
—
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
Unimplemented
Read as ‘0’
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Unimplemented
Read as ‘0’
= Unimplemented data memory locations, read as ‘0’.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
3.2.6
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-4 can be
addressed from any Bank.
TABLE 3-4:
Addr
Name
CORE FUNCTION REGISTERS SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other resets
Bank 0-31
x00h or
INDF0
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
Program Counter (PC) Least Significant Byte
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
—
—
—
TO
PD
Z
DC
C
x04h or
FSR0L
x84h
Indirect Data Memory Address 0 Low Pointer
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
Indirect Data Memory Address 0 High Pointer
0000 0000
0000 0000
x06h or
FSR1L
x86h
Indirect Data Memory Address 1 Low Pointer
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
Indirect Data Memory Address 1 High Pointer
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
—
x09h or
WREG
x89h
—
BSR<4:0>
Working Register
x0Ah or
PCLATH
x8Ah
—
x0Bh or
INTCON
x8Bh
GIE
Legend:
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 24
PIC16(L)F1507
TABLE 3-5:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx --xx xxxx
00Dh
PORTB
RB7
RB6
RB5
RB4
—
—
—
—
xxxx ---- xxxx ----
00Eh
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx xxxx xxxx
00Fh
—
Unimplemented
—
—
010h
—
Unimplemented
—
—
011h
PIR1
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
00-- --00 00-- --00
012h
PIR2
—
—
—
—
—
NCO1IF
—
—
---- -0-- ---- -0--
013h
PIR3
—
—
—
—
—
—
CLC2IF
CLC1IF
---- --00 ---- --00
014h
—
Unimplemented
015h
TMR0
Holding Register for the 8-bit Timer0 Count
xxxx xxxx uuuu uuuu
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
xxxx xxxx uuuu uuuu
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
018h
T1CON
019h
T1GCON
01Ah
TMR2
Timer2 Module Register
01Bh
PR2
Timer2 Period Register
01Ch
T2CON
01Dh
—
Unimplemented
—
—
01Eh
—
Unimplemented
—
—
01Fh
—
Unimplemented
—
—
—
TMR1CS<1:0>
TMR1GE
T1GPOL
—
T1CKPS<1:0>
T1GTM
T1GSPM
—
xxxx xxxx uuuu uuuu
—
T1SYNC
—
TMR1ON
0000 -0-0 uuuu -u-u
T1GGO/
DONE
T1GVAL
—
T1GSS
0000 0x-0 uuuu ux-u
0000 0000 0000 0000
1111 1111 1111 1111
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
Bank 1
08Ch
TRISA
—
—
TRISA5
TRISA4
—(2)
TRISA2
TRISA1
TRISA0
--11 1111 --11 1111
08Dh
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ---- 1111 ----
08Eh
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111 1111 1111
08Fh
—
Unimplemented
—
—
090h
—
Unimplemented
—
—
091h
PIE1
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
00-- --00 00-- --00
092h
PIE2
—
—
—
—
—
NCO1IE
—
—
---- -0-- ---- -0--
093h
PIE3
—
—
—
—
—
—
CLC2IE
CLC1IE
---- --00 ---- --00
094h
—
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
STKOVF
STKUNF
—
RWDT
—
—
096h
PCON
097h
WDTCON
098h
—
099h
OSCCON
Unimplemented
—
RMCLR
PS<2:0>
RI
POR
WDTPS<4:0>
BOR
00-1 11qq qq-q qquu
SWDTEN
--01 0110 --01 0110
Unimplemented
—
—
IRCF<3:0>
09Ah
OSCSTAT
09Bh
ADRESL
A/D Result Register Low
09Ch
ADRESH
A/D Result Register High
09Dh
ADCON0
—
09Eh
ADCON1
ADFM
09Fh
ADCON2
—
—
—
HFIOFR
—
—
—
SCS<1:0>
LFIOFR
HFIOFS
1-q0 --00 q-qq --qq
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
GO/DONE
—
—
—
—
ADON
ADPREF<1:0>
—
—
-000 0000 -000 0000
0000 --00 0000 --00
0000 ---- 0000 ----
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
DS41586A-page 25
—
-011 1-00 -011 1-00
Legend:
Note
—
1111 1111 1111 1111
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 3-5:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
10Ch
LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
--xx -xxx --uu -uuu
10Dh
LATB
LATB7
LATB6
LATB5
LATB4
—
—
—
—
xxxx ---- uuuu ----
10Eh
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx uuuu uuuu
10Fh
to
115h
—
Unimplemented
—
116h
BORCON
SBOREN
BORFS
—
—
—
—
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
118h
to
11Ch
—
—
BORRDY
ADFVR<1:0>
—
10-- ---q uu-- ---u
0q00 --00 0q00 --00
Unimplemented
—
—
11Dh
APFCON
11Eh
—
Unimplemented
—
—
11Fh
—
Unimplemented
—
—
—
—
—
—
—
—
CLC1SEL
NCO1SEL
---- --00 ---- --00
Bank 3
18Ch
ANSELA
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
---1 -111 ---1 -111
18Dh
ANSELB
—
—
ANSB5
ANSB4
—
—
—
—
--11 ---- --11 ----
18Eh
ANSELC
ANSC7
ANSC6
—
—
ANSC3
ANSC2
ANSC1
ANSC0
11-- 1111 11-- 1111
18Fh
—
Unimplemented
—
—
190h
—
Unimplemented
—
—
191h
PMADRL
Flash Program Memory Address Register Low Byte
192h
PMADRH
193h
PMDATL
194h
PMDATH
195h
PMCON1
196h
PMCON2
197h
VREGCON(1)
198h
to
19Fh
—
—
0000 0000 0000 0000
Flash Program Memory Address Register High Byte
-000 0000 -000 0000
Flash Program Memory Read Data Register Low Byte
—
—
—(2)
CFGS
xxxx xxxx uuuu uuuu
Flash Program Memory Read Data Register High Byte
LWLO
FREE
--xx xxxx --uu uuuu
WRERR
WREN
WR
RD
0000 x000 0000 q000
—
—
VREGPM
Reserved
---- --01 ---- --01
Flash Program Memory Control Register 2
—
—
—
0000 0000 0000 0000
—
Unimplemented
—
—
Bank 4
20Ch
WPUA
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111 --11 1111
20Dh
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
—
—
—
—
1111 ---- 1111 ----
20Eh
to
21Fh
—
Unimplemented
—
—
—
Unimplemented
—
—
—
Unimplemented
—
—
Bank 5
28Ch
to
29Fh
Bank 6
30Ch
to
31Fh
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
Legend:
Note
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 26
PIC16(L)F1507
TABLE 3-5:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
—
—
Bank 7
38Ch
to
390h
—
Unimplemented
391h
IOCAP
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
--00 0000 --00 0000
392h
IOCAN
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
--00 0000 --00 0000
393h
IOCAF
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
--00 0000 --00 0000
394h
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
—
—
—
—
0000 ---- 0000 ----
395h
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
—
—
—
—
0000 ---- 0000 ----
396h
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
—
—
—
—
0000 ---- 0000 ----
397h
to
39Fh
—
Unimplemented
—
—
—
Unimplemented
—
—
—
Unimplemented
—
—
Bank 8
40Ch
to
41Fh
Bank 9
48Ch
to
497h
498h
NCO1ACCL
NCO1ACC<7:0>
0000 0000 0000 0000
499h
NCO1ACCH
NCO1ACC<15:8>
0000 0000 0000 0000
49Ah
NCO1ACCU
NCO1ACC<23:16>
0000 0000 0000 0000
49Bh
NCO1INCL
NCO1INC<7:0>
0000 0000 0000 0000
49Ch
NCO1INCH
NCO1INC<15:8>
0000 0000 0000 0000
49Dh
—
49Eh
NCO1CON
49Fh
NCO1CLK
Unimplemented
N1EN
N1OE
N1PWS<2:0>
—
N1OUT
N1POL
—
—
—
—
—
—
N1PFM
N1CKS<1:0>
—
0000 ---0 0000 ---0
0000 --00 0000 --00
Bank 10
50Ch
to
51Fh
—
Unimplemented
—
—
Unimplemented
—
—
Bank 11
58Ch
to
59Fh
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
Legend:
Note
DS41586A-page 27
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 3-5:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
—
—
Bank 12
60Ch
to
610h
—
611h
PWM1DCL
612h
PWM1DCH
613h
PWM1CON0
614h
PWM2DCL
615h
PWM2DCH
616h
PWM2CON0
617h
PWM3DCL
618h
PWM3DCH
619h
PWM3CON0
61Ah
PWM4DCL
61Bh
PWM4DCH
61Ch
PWM4CON0
61Dh
to
61Fh
—
Unimplemented
PWM1DCL<7:6>
—
—
—
—
—
—
—
—
—
—
0000 ---- 0000 ----
—
—
—
—
00-- ---- 00-- ----
—
—
—
—
0000 ---- 0000 ----
—
—
—
—
00-- ---- 00-- ----
—
—
—
—
0000 ---- 0000 ----
—
—
—
—
00-- ---- 00-- ----
—
—
—
00-- ---- 00-- ----
PWM1DCH<7:0>
PWM1EN
PWM1OE PWM1OUT PWM1POL
PWM2DCL<7:6>
—
—
xxxx xxxx uuuu uuuu
PWM2DCH<7:0>
PWM2EN
PWM2OE PWM2OUT PWM2POL
PWM3DCL<7:6>
—
—
xxxx xxxx uuuu uuuu
PWM3DCH<7:0>
PWM3EN
PWM3OE PWM3OUT PWM3POL
PWM4DCL<7:6>
—
—
xxxx xxxx uuuu uuuu
PWM4DCH<7:0>
PWM4EN
PWM4OE PWM4OUT PWM4POL
—
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
Unimplemented
—
—
Unimplemented
—
—
Bank 13
68Ch
to
690h
—
691h
CWG1DBR
—
—
CWG1DBR<5:0>
692h
CWG1DBF
—
—
CWG1DBF<5:0>
693h
CWG1CON0
G1EN
G1OEB
694h
CWG1CON1
695h
CWG1ASD
696h
to
69Fh
—
G1ASDLB<1:0>
G1ASE
G1ARSEN
G1OEA
G1POLB
G1POLA
G1ASDLA<1:0>
—
—
—
—
—
--00 0000 --00 0000
--xx xxxx --xx xxxx
—
G1IS<2:0>
—
G1CS0
0000 0--0 0000 0--0
0000 -000 0000 -000
G1ASDSFLT G1ASDSCLC2 00-- --00 00-- --00
Unimplemented
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
Legend:
Note
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 28
—
PIC16(L)F1507
TABLE 3-5:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
POR, BOR
Value on all
other
Resets
Unimplemented
—
—
Unimplemented
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 14-29
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—
Bank 30
F0Ch
to
F0Eh
—
F0Fh
CLCDATA
—
—
—
—
—
F10h
CLC1CON
LC1EN
LC1OE
LC1OUT
LC1INTP
LC1INTN
F11h
CLC1POL
LC1POL
—
—
—
—
PWM1POL
PWM1POL
LC1MODE<2:0>
LC1G4POL LC1G3POL LC1G2POL
LC1G1POL
---- --00 ---- --00
0000 0000 0000 0000
0--- xxxx 0--- uuuu
F12h
CLC1SEL0
—
LC1D2S<2:0>
—
LC1D1S<2:0>
F13h
CLC1SEL1
—
LC1D4S<2:0>
—
LC1D3S<2:0>
F14h
CLC1GLS0
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T
LC1G1D1N
xxxx xxxx uuuu uuuu
F15h
CLC1GLS1
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T
LC1G2D1N
xxxx xxxx uuuu uuuu
F16h
CLC1GLS2
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T
LC1G3D1N
xxxx xxxx uuuu uuuu
F17h
CLC1GLS3
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T
LC1G4D1N
xxxx xxxx uuuu uuuu
F18h
CLC2CON
LC2EN
LC2OE
LC2OUT
LC2INTP
F19h
CLC2POL
LC2POL
—
—
—
F1Ah
CLC2SEL0
—
LC2D2S<2:0>
—
LC2D1S<2:0>
F1Bh
CLC2SEL1
—
LC2D4S<2:0>
—
LC2D3S<2:0>
F1Ch
CLC2GLS0
LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T
LC2G1D1N
xxxx xxxx uuuu uuuu
F1Dh
CLC2GLS1
LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T
LC2G2D1N
xxxx xxxx uuuu uuuu
F1Eh
CLC2GLS2
LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T
LC2G3D1N
xxxx xxxx uuuu uuuu
F1Fh
CLC2GLS3
LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T
LC2G4D1N
xxxx xxxx uuuu uuuu
—
Unimplemented
F20h
to
F6Fh
LC2INTN
-xxx -xxx -uuu -uuu
-xxx -xxx -uuu -uuu
LC2MODE<2:0>
LC2G4POL LC2G3POL LC2G2POL
LC2G1POL
0000 0000 0000 0000
0--- xxxx 0--- uuuu
-xxx -xxx -uuu -uuu
-xxx -xxx -uuu -uuu
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
Legend:
Note
DS41586A-page 29
Preliminary
 2011 Microchip Technology Inc.
—
PIC16(L)F1507
TABLE 3-5:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
—
—
Bank 31
F8Ch
—
FE3h
—
FE4h
STATUS_
Unimplemented
—
—
—
—
—
Z_SHAD
DC_SHAD
C_SHAD
---- -xxx ---- -uuu
SHAD
FE5h
WREG_
Working Register Shadow
xxxx xxxx uuuu uuuu
SHAD
FE6h
BSR_
—
—
—
Bank Select Register Shadow
---x xxxx ---u uuuu
SHAD
FE7h
PCLATH_
—
Program Counter Latch High Register Shadow
-xxx xxxx uuuu uuuu
SHAD
FE8h
FSR0L_
Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Unimplemented
—
—
—
—
Current Stack pointer
Top-of-Stack Low byte
—
xxxx xxxx uuuu uuuu
Top-of-Stack High byte
-xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
1:
PIC16F1507 only.
2:
Unimplemented, read as ‘1’.
Legend:
Note
 2011 Microchip Technology Inc.
—
---1 1111 ---1 1111
Preliminary
DS41586A-page 30
PIC16(L)F1507
3.3
PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-3 shows the five
situations for the loading of the PC.
FIGURE 3-3:
14
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
0
PC
6
7
8
0
PCLATH
Instruction with
PCL as
Destination
14
PCH
PCL
0
GOTO, CALL
6 4
0
PCLATH
11
OPCODE <10:0>
14
PCH
PCL
0
6
7
0
W
14
PCH
PCL
0
BRW
PC + W
PCH
PCL
PC
BRANCHING
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
15
14
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
CALLW
8
PC
COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
3.3.4
PC
PCLATH
3.3.3
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
ALU Result
PC
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
0
BRA
15
PC + OPCODE <8:0>
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values contained in the PCLATH register and those being written
to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
DS41586A-page 31
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
3.4
3.4.1
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-4 through 3-7). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘(Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
FIGURE 3-4:
ACCESSING THE STACK
Reference Figure 3-4 through Figure 3-7 for examples
of accessing the stack.
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F
STKPTR = 0x1F
Stack Reset Disabled
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
 2011 Microchip Technology Inc.
0x1F
0x0000
Preliminary
STKPTR = 0x1F
Stack Reset Enabled
(STVREN = 1)
DS41586A-page 32
PIC16(L)F1507
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS41586A-page 33
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
Preliminary
STKPTR = 0x06
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 4
TOSH:TOSL
3.4.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 34
PIC16(L)F1507
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
Reserved
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS41586A-page 35
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
3.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-9:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
4
BSR
0
6
Indirect Addressing
From Opcode
0
7
0
Bank Select
Location Select
FSRxH
0
0
0
7
FSRxL
0
0
Bank Select
00000 00001 00010
11111
Bank 0 Bank 1 Bank 2
Bank 31
Location Select
0x00
0x7F
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 36
PIC16(L)F1507
3.5.2
3.5.3
LINEAR DATA MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-10:
7
FSRnH
0 0 1
LINEAR DATA MEMORY
MAP
0
7
FSRnL
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-11:
7
1
0
PROGRAM FLASH MEMORY
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
7
FSRnL
0x8000
0
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS41586A-page 37
0xF6F
Preliminary
0xFFFF
0x7FFF
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 38
PIC16(L)F1507
4.0
DEVICE CONFIGURATION
Device Configuration consists of Configuration Words,
Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
DS41586A-page 39
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
U-1
U-1
R/P-1
—
—
CLKOUTEN
R/P-1
R/P-1
U-1
BOREN<1:0>
—
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
bit 8
R/P-1
R/P-1
U-1
WDTE<1:0>
R/P-1
—
R/P-1
FOSC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13-12
Unimplemented: Read as ‘1’
bit 11
CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-Up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bits
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2
Unimplemented: Read as ‘1’
bit 1-0
FOSC<1:0>: Oscillator Selection bits
11 = ECH: External Clock, High-Power mode: on CLKIN pin
10 = ECM: External Clock, Medium-Power mode: on CLKIN pin
01 = ECL: External Clock, Low-Power mode: on CLKIN pin
00 = INTOSC oscillator: I/O function on CLKIN pin
Note 1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Once enabled, code-protect can only be disabled by bulk erasing the device.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 40
PIC16(L)F1507
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2
R/P-1
U-1
R/P-1
R/P-1
R/P-1
U-1
LVP
—
LPBOR
BORV
STVREN
—
bit 13
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12
Unimplemented: Read as ‘1’
bit 11
LPBOR: Low-Power BOR Enable bit
1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10
BORV: Brown-Out Reset Voltage Selection bit
1 = Brown-out Reset voltage set to:
1.9V (PIC16LF1507)
2.4V (PIC16F1507), typical
0 = Brown-out Reset voltage set to 2.7V (typical)
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-2
Unimplemented: Read as ‘1’
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory:
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified
00 = 000h to 7FFh write-protected, no addresses may be modified
Note 1:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
DS41586A-page 41
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
4.2
Code Protection
Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.3
“Write
Protection” for more information.
4.3
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573).
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 42
PIC16(L)F1507
4.5
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3:
DEVICEID: DEVICE ID REGISTER
R
R
R
R
R
R
DEV<8:3>
bit 13
R
R
bit 8
R
R
R
DEV<2:0>
R
R
R
REV<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
P = Programmable bit
bit 13-5
DEV<8:0>: Device ID bits
DEVICEID<13:0> Values
Device
bit 4-0
DEV<8:0>
REV<4:0>
PIC16F1507
10 1101 000
x xxxx
PIC16LF1507
10 1101 110
x xxxx
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
DS41586A-page 43
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 44
PIC16(L)F1507
5.0
OSCILLATOR MODULE
The oscillator module can be configured in one of the
following clock modes.
5.1
Overview
1.
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
2.
3.
4.
ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)
ECH – External Clock High-Power mode
(4 MHz to 20 MHz)
INTOSC – Internal oscillator (31 kHz to 16 MHz).
Clock Source modes are selected by the FOSC<1:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC clock mode relies on an external logic level
signal as the device clock source.
The INTOSC internal oscillator block produces low and
high frequency clock sources, designated LFINTOSC
and HFINTOSC. (see Internal Oscillator Block,
Figure 5-1). A wide selection of device clock
frequencies may be derived from these clock sources.
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
CLKIN EC
EC
Sleep
MUX
CLKIN
16 MHz
Source
16 MHz
(HFINTOSC)
Postscaler
Internal
Oscillator
Block
31 kHz
Source
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
MUX
IRCF<3:0>
CPU and
Peripherals
Internal Oscillator
Clock
Control
FOSC<1:0> SCS<1:0>
31 kHz
31 kHz (LFINTOSC)
DS41586A-page 45
WDT, PWRT and other modules
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
5.2
5.2.1.1
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator modules (EC mode).
Internal clock sources are contained within the
oscillator module. The oscillator block has two internal
oscillators that are used to generate two system clock
sources: the 16 MHz High-Frequency Internal
Oscillator (HFINTOSC) and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
5.2.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the FOSC<1:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Clear the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- An external clock source determined by the
value of the FOSC bits.
See Section 5.3 “Clock Switching”for more information.
 2011 Microchip Technology Inc.
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 5-2 shows the pin connections for EC mode.
EC mode has 3 power modes to select from through
Configuration Words:
• High power, 4-20 MHz (FOSC = 11)
• Medium power, 0.5-4 MHz (FOSC = 10)
• Low power, 0-0.5 MHz (FOSC = 01)
When EC mode is selected, there is no delay in operation after a Power-on Reset (POR) or wake-up from
Sleep. Because the PIC® MCU design is fully static,
stopping the external clock input will have the effect of
halting the device while leaving all data intact. Upon
restarting the external clock, the device will resume
operation as if no time had elapsed.
FIGURE 5-2:
Clock from
Ext. System
FOSC/4 or I/O(1)
Note 1:
Preliminary
EXTERNAL CLOCK (EC)
MODE OPERATION
CLKIN
PIC® MCU
CLKOUT
Output depends upon CLKOUTEN bit of the
Configuration Words.
DS41586A-page 46
PIC16(L)F1507
5.2.2
INTERNAL CLOCK SOURCES
5.2.2.2
The device may be configured to use the internal oscillator block as the system clock by performing one of the
following actions:
• Program the FOSC<1:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
“Clock Switching”for more information.
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT is available for general purpose
I/O or CLKOUT.
The function of the CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent
oscillators clock sources.
1.
2.
The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz.
The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
5.2.2.1
HFINTOSC
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT) and
Watchdog Timer (WDT).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000x) as
the system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<1:0> = 00, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
The outputs of the HFINTOSC connects to a prescaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.4 “Internal
Oscillator Clock Switch Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<1:0> = 00, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to power
up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
DS41586A-page 47
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
5.2.2.3
Internal Oscillator Frequency
Selection
5.2.2.4
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The outputs of the 16 MHz HFINTOSC postscaler and
the LFINTOSC connect to a multiplexer (see
Figure 5-1). The Internal Oscillator Frequency Select
bits IRCF<3:0> of the OSCCON register select the
frequency output of the internal oscillators. One of the
following frequencies can be selected via software:
Note:
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-3). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1.
• HFINTOSC
- 16 MHz
- 8 MHz
- 4 MHz
- 2 MHz
- 1 MHz
- 500 kHz (Default after Reset)
- 250 kHz
- 125 kHz
- 62.5 kHz
- 31.25 kHz
• LFINTOSC
- 31 kHz
Internal Oscillator Clock Switch
Timing
2.
3.
4.
IRCF<3:0> bits of the OSCCON register are
modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
Clock switch is complete.
See Figure 5-3 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected.
Start-up delay specifications are located in the
oscillator tables of Section 25.0 “Electrical
Specifications”
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes
that use the same oscillator source.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 48
PIC16(L)F1507
FIGURE 5-3:
HFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (WDT disabled)
HFINTOSC
Start-up Time
2-cycle Sync
Running
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
HFINTOSC
LFINTOSC (WDT enabled)
HFINTOSC
LFINTOSC
0
IRCF <3:0>
0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT is enabled
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC
IRCF <3:0>
=0
0
System Clock
DS41586A-page 49
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
5.3
5.3.1
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
• Default system oscillator determined by FOSC
bits in Configuration Words
• Internal Oscillator Block (INTOSC)
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<1:0> bits in the Configuration Words.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-2.
TABLE 5-1:
OSCILLATOR SWITCHING DELAYS
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC
HFINTOSC
31 kHz
31.25 kHz-16 MHz
Oscillator Warm-up Delay (TWARM)
Sleep/POR
EC
DC – 20 MHz
2 cycles
LFINTOSC
EC
DC – 20 MHz
1 cycle of each
Any clock source
HFINTOSC
31.25 kHz-16 MHz
2 s (typical)
Any clock source
LFINTOSC
31 kHz
1 cycle of each
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 50
PIC16(L)F1507
5.4
Oscillator Control Registers
REGISTER 5-1:
U-0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
IRCF<3:0>
—
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz
1110 = 8 MHz
1101 = 4 MHz
1100 = 2 MHz
1011 = 1 MHz
1010 = 500 kHz(1)
1001 = 250 kHz(1)
1000 = 125 kHz(1)
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz
000x = 31 kHz (LFINTOSC)
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Reserved
00 = Clock determined by FOSC<1:0> in Configuration Words.
Note 1:
Duplicate frequency derived from HFINTOSC.
DS41586A-page 51
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
U-0
U-0
U-0
R-0/q
U-0
U-0
R-0/q
R-0/q
—
—
—
HFIOFR
—
—
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Conditional
bit 7-5
Unimplemented: Read as ‘0’
bit 4
HFIOFR: High Frequency Internal Oscillator Ready bit
1 = 16 MHz Internal Oscillator (HFINTOSC) is ready
0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready
bit 3-2
Unimplemented: Read as ‘0’
bit 1
LFIOFR: Low Frequency Internal Oscillator Ready bit
1 = 31 kHz Internal Oscillator (LFINTOSC) is ready
0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready
bit 0
HFIOFS: High Frequency Internal Oscillator Stable bit
1 = 16 MHz Internal Oscillator (HFINTOSC) is stable
0 = 16 MHz Internal Oscillator (HFINTOSC) is not yet stable.
TABLE 5-2:
Name
Bit 7
OSCCON
CONFIG1
Legend:
Bit 5
Bit 4
Bit 3
IRCF<3:0>
—
—
—
Bit 2
Bit 1
—
HFIOFR
—
Bit 0
SCS<1:0>
—
LFIOFR
Register
on Page
51
HFIOFS
52
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3:
Name
Bit 6
—
OSCSTAT
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
—
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
Register
on Page
40
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 52
PIC16(L)F1507
6.0
RESETS
There are multiple ways to reset this device:
•
•
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Low-Power Brown-out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP™ Programming Mode Exit
RESET Instruction
Stack
Pointer
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
R
PWRT
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1:
See Table 6-1 for BOR active conditions.
DS41586A-page 53
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
6.1
Power-on Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
6.1.1
•
•
•
•
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
BOR OPERATING MODES
Instruction Exection upon:
Release of POR or Wake-up from Sleep
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
X
X
Active
Waits for BOR ready(1)
(BORRDY = 1)
Awake
Active
10
X
Sleep
Disabled
Waits for BOR ready
(BORRDY = 1)
Active
Waits for BOR ready(1)
(BORRDY = 1)
X
Disabled
X
Disabled
Begins immediately
(BORRDY = x)
1
X
0
X
01
00
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
6.2.1
BOR IS ALWAYS ON
When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold.
 2011 Microchip Technology Inc.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up
is not delayed by the BOR ready condition or the VDD
level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
Preliminary
DS41586A-page 54
PIC16(L)F1507
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
TPWRT(1)
TPWRT delay only if PWRTE bit is programmed to ‘0’.
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1:
BOREN<1:0> bits are located in Configuration Words.
DS41586A-page 55
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
6.3
Low-Power Brown-out Reset
(LPBOR)
6.5
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.3.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.3.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR module to provide the generic BOR signal which goes to
the PCON register and to the power control block.
6.4
MCLR
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer” for more information.
6.6
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.7
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.4.2 “Overflow/Underflow
Reset” for more information.
6.8
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.9
TABLE 6-2:
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
MCLR CONFIGURATION
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
x
1
Enabled
6.4.1
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.2 “PORTA Registers” for more information.
 2011 Microchip Technology Inc.
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.4.2
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
6.10
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
Note:
Power-Up Timer
1.
2.
Power-up Timer runs to completion (if enabled).
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module” for more information.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Preliminary
DS41586A-page 56
PIC16(L)F1507
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
DS41586A-page 57
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
6.11
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT
RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
1
1
1
0
x
1
1
Power-on Reset
0
0
1
1
1
0
x
0
x
Illegal, TO is set on POR
0
0
1
1
1
0
x
x
0
Illegal, PD is set on POR
0
0
u
1
1
u
0
1
1
Brown-out Reset
u
u
0
u
u
u
u
0
u
WDT Reset
u
u
u
u
u
u
u
0
0
WDT Wake-up from Sleep
u
u
u
u
u
u
u
1
0
Interrupt Wake-up from Sleep
u
u
u
0
u
u
u
u
u
MCLR Reset during normal operation
u
u
u
0
u
u
u
1
0
MCLR Reset during Sleep
u
u
u
u
0
u
u
u
u
RESET Instruction Executed
1
u
u
u
u
u
u
u
u
Stack Overflow Reset (STVREN = 1)
u
1
u
u
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
MCLR Reset during normal operation
0000h
---u uuuu
uu-- 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
Interrupt Wake-up from Sleep
RESET Instruction Executed
PC + 1
(1)
0000h
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-- uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 58
PIC16(L)F1507
6.12
Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
—
R/W/HC-1/q R/W/HC-1/q
RWDT
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RI
POR
BOR
RMCLR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5
Unimplemented: Read as ‘0’
bit 4
RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
DS41586A-page 59
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 6-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
—
—
—
—
—
BORRDY
55
PCON
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
BOR
59
STATUS
—
—
—
TO
PD
Z
DC
C
18
WDTCON
—
—
SWDTEN
81
WDTPS<4:0>
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TABLE 6-6:
Name
CONFIG1
CONFIG2
Legend:
Bits
SUMMARY OF CONFIGURATION WORD WITH RESETS
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
—
CLKOUTEN
Bit 10/2
13:8
—
—
—
7:0
CP
MCLRE
PWRTE
13:8
—
—
LVP
—
LPBOR
BORV
7:0
—
—
—
—
—
—
WDTE<1:0>
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
STVREN
—
WRT<1:0>
Register
on Page
40
41
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 60
PIC16(L)F1507
7.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
•
•
•
•
•
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
Many peripherals produce Interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IF) PIR1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
DS41586A-page 61
GIE
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
7.1
Operation
7.2
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-2
and Figure 7.3 for more details.
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 62
PIC16(L)F1507
FIGURE 7-2:
INTERRUPT LATENCY
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
DS41586A-page 63
Preliminary
PC+2
NOP
NOP
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FOSC
CLKOUT
(3)
INT pin
(1)
(1)
INTF
Interrupt Latency (2)
(4)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC – 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
—
Forced NOP
0004h
0005h
Inst (0004h)
Inst (0005h)
Forced NOP
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications””.
4:
INTF is enabled to be set any time during the Q4-Q1 cycles.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 64
PIC16(L)F1507
7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0 “PowerDown Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
•
•
•
•
•
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s application, other registers may also need to be saved.
DS41586A-page 65
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
7.6
Interrupt Control Registers
Note:
7.6.1
INTCON REGISTER
The INTCON register is a readable and writable
register, that contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1:
The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register
have been cleared by software.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 66
PIC16(L)F1507
7.6.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
REGISTER 7-2:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5-2
Unimplemented: Read as ‘0’
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
DS41586A-page 67
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
7.6.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
REGISTER 7-3:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
—
—
—
—
—
NCO1IE
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit
1 = Enables the NCO interrupt
0 = Disables the NCO interrupt
bit 1-0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 68
PIC16(L)F1507
7.6.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.
REGISTER 7-4:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
CLC2IE
CLC1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
CLC2IE: Configurable Logic Block 2 Interrupt Enable bit
1 = Enables the CLC 2 interrupt
0 = Disables the CLC 2 interrupt
bit 0
CLC1IE: Configurable Logic Block 1 Interrupt Enable bit
1 = Enables the CLC 1 interrupt
0 = Disables the CLC 1 interrupt
DS41586A-page 69
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
7.6.5
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-5.
REGISTER 7-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5-2
Unimplemented: Read as ‘0’
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 70
PIC16(L)F1507
7.6.6
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-6.
REGISTER 7-6:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
—
—
—
—
—
NCO1IF
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
NCO1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1-0
Unimplemented: Read as ‘0’
DS41586A-page 71
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
7.6.7
PIR3 REGISTER
The PIR3 register contains the interrupt flag bits, as
shown in Register 7-7.
REGISTER 7-7:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
CLC2IF
CLC1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 72
PIC16(L)F1507
TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
OPTION_REG WPUEN
INTEDG TMR0CS TMR0SE
PSA
PS<2:0>
PIE1
TMR1GIE
ADIE
—
—
—
—
TMR2IE
137
TMR1IE
67
PIE2
—
—
—
—
—
NCO1IE
—
—
68
PIE3
—
—
—
—
—
—
CLC2IE
CLC1IE
69
PIR1
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
70
PIR2
—
—
—
—
—
NCO1IF
—
—
71
PIR3
—
—
—
—
—
—
CLC2IF
CLC1IF
72
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
DS41586A-page 73
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 74
PIC16(L)F1507
8.0
POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions exist:
1.
2.
3.
4.
5.
6.
7.
8.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
ADC is unaffected, if the dedicated FRC clock is
selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
•
•
•
•
•
•
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
CWG, NCO and CLC modules using HFINTOSC
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 13.0
“Fixed Voltage Reference (FVR)” for more
information on this module.
DS41586A-page 75
8.1
Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of program execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.11
“Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction
- SLEEP instruction will be completely executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
T1OSC(3)
CLKOUT(2)
Interrupt flag
Interrupt Latency (4)
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
T1OSC; See Section 25.0 “Electrical Specifications”.
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 76
PIC16(L)F1507
8.2
8.2.2
Low-Power Sleep Mode
The PIC16(L)F1507 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16(L)F1507 allows the user to optimize the operating current in Sleep, depending on the application
requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal configuration and stabilize.
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
DS41586A-page 77
PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal Power
mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these
peripherals:
•
•
•
•
Brown-Out Reset (BOR)
Watchdog Timer (WDT)
External interrupt pin/Interrupt-on-change pins
Timer1 (with external clock source)
The Complementary Waveform Generator (CWG), the
Numerically Controlled Oscillator (NCO) and the Configurable Logic Cell (CLC) modules can utilize the
HFINTOSC oscillator as either a clock source or as an
input source. Under certain conditions, when the HFINTOSC is selected for use with the CWG, NCO or CLC
modules, the HFINTOSC will remain active during
Sleep. This will have a direct effect on the Sleep mode
current.
Please refer to sections 20.5 “Operation During
Sleep”, 21.7 “Operation In Sleep” and 22.10 “Operation During Sleep” for more information.
Note:
Preliminary
The PIC16LF1507 does not have a configurable Low-Power Sleep mode.
PIC16LF1507 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16(L)F1507. See Section 25.0 “Electrical Specifications” for more information.
 2011 Microchip Technology Inc.
PIC16(L)F1507
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
—
—
—
—
—
—
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1:
PIC16F1507 only.
TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
113
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
113
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
113
IOCAF
IOCAN
—
—
IOCAN5
IOCAP
—
—
IOCAP5
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
—
—
—
—
114
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
—
—
—
—
114
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
—
—
—
—
114
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
67
PIE1
PIE2
—
—
—
—
—
NCO1IE
—
—
68
PIR1
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
70
PIR2
—
—
—
—
—
NCO1IF
—
—
71
STATUS
—
—
—
TO
PD
Z
DC
C
18
WDTCON
—
—
SWDTEN
81
WDTPS<4:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 78
PIC16(L)F1507
9.0
WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 9-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
DS41586A-page 79
WDTPS<4:0>
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
9.1
Independent Clock Source
9.3
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 25.0 “Electrical Specifications” for the
LFINTOSC tolerances.
9.2
Time-Out Period
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
9.4
Clearing the WDT
The WDT is cleared when any of the following conditions occur:
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 9-1.
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.
•
•
•
•
•
•
WDT protection is active during Sleep.
See Table 9-2 for more information.
9.2.2
9.5
9.2.1
WDT IS ALWAYS ON
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
9.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1:
WDT OPERATING MODES
WDTE<1:0>
SWDTEN
Device
Mode
WDT
Mode
11
X
X
Active
Awake
Active
10
X
Sleep
Disabled
1
X
01
0
00
TABLE 9-2:
X
X
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module” for more information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” for
more information.
Active
Disabled
Disabled
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = INTOSC, EXTCLK
Change INTOSC divider (IRCF bits)
 2011 Microchip Technology Inc.
Unaffected
Preliminary
DS41586A-page 80
PIC16(L)F1507
9.6
Watchdog Control Register
REGISTER 9-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (217) (Interval 4s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10010 = 1:8388608 (223) (Interval 256s nominal)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
Note 1:
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
DS41586A-page 81
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 9-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7
OSCCON
Bit 6
—
PCON
Bit 5
Bit 4
Bit 3
IRCF<3:0>
STKUNF
—
RWDT
STATUS
—
—
—
TO
WDTCON
—
—
CONFIG1
Legend:
Bit 0
SCS<1:0>
RMCLR
RI
POR
PD
Z
DC
WDTPS<4:0>
Register
on Page
51
BOR
59
C
18
SWDTEN
81
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 9-4:
Name
Bit 1
—
STKOVF
Legend:
Bit 2
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
—
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
Register
on Page
40
— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 82
PIC16(L)F1507
10.0
FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the VDD range specified
in the Electrical Specification. See Section 25.0
“Electrical Specifications”. Program memory is
indirectly addressed using Special Function Registers
(SFRs). The SFRs used to access program memory
are:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge
pump.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration
Words).
Code protection (CP = 0), disables access, reading and
writing, to the entire Flash program memory via
external device programmers. Code protection does
not affect the self-write and erase functionality. Code
protection can only be reset by a device programmer
performing a Bulk Erase to the device, clearing all
Flash program memory, Configuration bits and User
IDs.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
10.2
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
10.1
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 16K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
10.1.1
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. However, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
TABLE 10-1:
PMCON1 AND PMCON2
REGISTERS
Device
PMCON1 is the control register for Flash program
memory accesses.
DS41586A-page 83
Flash Program Memory Overview
PIC16F1507
PIC16LF1507
Preliminary
FLASH MEMORY
ORGANIZATION BY DEVICE
Row Erase
(words)
Write
Latches
(words)
16
16
 2011 Microchip Technology Inc.
PIC16(L)F1507
10.2.1
READING THE FLASH PROGRAM
MEMORY
FIGURE 10-1:
To read a program memory location, the user must:
1.
2.
3.
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation
(RD = 1)
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
Data read now in
PMDATH:PMDATL
End
Read Operation
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 84
PIC16(L)F1507
FIGURE 10-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PC
+3
PC+3
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
PC + 5
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; Select Bank for PMCON registers
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
Do not select Configuration Space
Initiate read
Ignored (Figure 10-2)
Ignored (Figure 10-2)
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
DS41586A-page 85
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
10.2.2
FLASH MEMORY UNLOCK
SEQUENCE
FIGURE 10-3:
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write programming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to program memory
• Write of program memory write latches to User
IDs
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
Write 055h to
PMCON2
The unlock sequence consists of the following steps:
Write 0AAh to
PMCON2
1. Write 55h to PMCON2
Initiate
Write or Erase operation
(WR = 1)
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
End
Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 86
PIC16(L)F1507
10.2.3
ERASING FLASH PROGRAM
MEMORY
FIGURE 10-4:
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 10-3
(FIGURE
x-x)
CPU stalls while
Erase operation completes
(2ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
DS41586A-page 87
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
EXAMPLE 10-2:
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
PMCON1,WREN
INTCON,GIE
 2011 Microchip Technology Inc.
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase
Write 55h
Write AAh
Set WR bit to begin erase
NOP instructions are forced as processor starts
row erase of program memory.
The processor stalls until the erase process is complete
after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
DS41586A-page 88
PIC16(L)F1507
10.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the
row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
Note:
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Program memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-5 (row writes to program memory with 16
write latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper 11-bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:4>)
with the lower 4-bits of PMADRL, (PMADRL<3:0>)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1.
2.
3.
Set the WREN bit of the PMCON1 register.
Clear the CFGS bit of the PMCON1 register.
Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
DS41586A-page 89
Preliminary
 2011 Microchip Technology Inc.
7
6
-
r10
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
0 7
5 4
PMADRH
r9
r8
r7
r6
0
7
PMADRL
r5
r4
r3
r2
r1
r0
c3
c2
c1
c0
5
-
0
7
PMDATH
6
0
PMDATL
8
14
11
Program Memory Write Latches
4
14
Write Latch #0
00h
PMADRL<4:0>
Preliminary
14
CFGS = 0
 2011 Microchip Technology Inc.
PMADRH<6:0>
:PMADRL<7:4>
Row
Address
Decode
14
14
Write Latch #1
01h
14
Write Latch #14
0Eh
14
Write Latch #15
0Fh
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
000Eh
001Fh
001h
0010h
0011h
001Eh
001Fh
002h
0020h
0021h
002Eh
002Fh
7FEh
7FE0h
7FE1h
7FEEh
7FEFh
7FFh
7FF0h
7FF1h
7FFEh
7FFFh
Flash Program Memory
800h
8000h - 8003h
USER ID 0 - 3
CFGS = 1
8004h - 8005h
8006h
8007h – 8008h
8009h - 801Fh
reserved
DEVICEID
REVID
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1507
DS41586A-page 90
FIGURE 10-5:
PIC16(L)F1507
FIGURE 10-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt)
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
Update the word counter
(word_cnt--)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure10-3
x-x)
Figure
Select Write Operation
(FREE = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Increment Address
(PMADRH:PMADRL++)
Write Latches to Flash
(LWLO = 0)
Unlock Sequence
(Figure10-3
x-x)
Figure
CPU stalls while Write
operation completes
(2ms typical)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
DS41586A-page 91
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
EXAMPLE 10-3:
;
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:
1. 32 bytes of data are loaded, starting at the address in DATA_ADDR
2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
stored in little endian format
3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable ints so required sequences will execute properly
Bank 3
Load initial address
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x0F
0x0F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 16 addresses
;
; Exit if last of 16 words,
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Load initial data address
Load initial data address
Not configuration space
Enable writes
Only Load Write Latches
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
PMCON1,WREN
INTCON,GIE
 2011 Microchip Technology Inc.
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor
loads program memory write latches
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor writes
all the program memory write latches simultaneously
to program memory.
After NOPs, the processor
stalls until the self-write process in complete
after write processor continues with 3rd instruction
Disable writes
Enable interrupts
Preliminary
DS41586A-page 92
PIC16(L)F1507
10.3
Modifying Flash Program Memory
FIGURE 10-7:
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be
modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
(Figure10-2
x.x)
Figure
An image of the entire row read
must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure10-4
x.x)
Figure
Write Operation
use RAM image
(Figure10-5
x.x)
Figure
End
Modify Operation
DS41586A-page 93
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
10.4
User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 10-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 10-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 10-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space
Disable interrupts
Initiate read
Executed (See Figure 10-2)
Ignored (See Figure 10-2)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 94
PIC16(L)F1507
10.5
Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
(Figure
x.x)
Figure
10-2
PMDAT =
RAM image
?
Yes
No
No
Fail
Verify Operation
Last
Word ?
Yes
End
Verify Operation
DS41586A-page 95
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
10.6
Flash Program Memory Control Registers
REGISTER 10-1:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4:
U-1
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘1’
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for program memory address
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 96
PIC16(L)F1507
REGISTER 10-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W/HC-x/q
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit(2)
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read
Note 1:
2:
3:
Unimplemented bit, read as ‘1’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
DS41586A-page 97
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 10-6:
W-0/0
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Flash memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 10-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
97
PMCON1
PMCON2
Program Memory Control Register 2
98
PMADRL
PMADRL<7:0>
96
—
PMADRH
PMADRH<6:0>
PMDATL
PMDATH
—
—
INTCON
GIE
PEIE
Legend:
CONFIG1
CONFIG2
Legend:
96
PMDATH<5:0>
TMR0IE
INTE
IOCIE
96
TMR0IF
INTF
IOCIF
66
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
TABLE 10-4:
Name
96
PMDATL<7:0>
Bits
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
—
CLKOUTEN
Bit 10/2
13:8
—
—
—
7:0
CP
MCLRE
PWRTE
13:8
—
—
LVP
—
LPBOR
BORV
7:0
—
—
—
—
—
—
WDTE<1:0>
Bit 9/1
Bit 8/0
BOREN<1:0>
—
—
FOSC<1:0>
STVREN
—
WRT<1:0>
Register
on Page
40
41
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 98
PIC16(L)F1507
11.0
I/O PORTS
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
Read LATx
D
Some ports may have one or more of the following
additional registers. These registers are:
Write LATx
Write PORTx
• ANSELx (analog select)
• WPUx (weak pull-up)
Q
CK
VDD
Data Register
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
Data Bus
I/O pin
Read PORTx
To peripherals
ANSELx
Device
PORTB
PORTC
PORT AVAILABILITY PER
DEVICE
PORTA
TABLE 11-1:
TRISx
PIC16(L)F1507
●
●
●
VSS
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
DS41586A-page 99
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
11.1
Alternate Pin Function
The Alternate Pin Function Control register is used to
steer specific peripheral input and output functions
between different pins. The APFCON register is shown
in Register 11-1. For this device family, the following
functions can be moved between different pins.
• CLC1
• NCO1
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
REGISTER 11-1:
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
CLC1SEL
NCO1SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
CLC1SEL: Pin Selection bit
1 = CLC1 function is on RC5
0 = CLC1 function is on RA2
bit 0
NCO1SEL: Pin Selection bit
1 = NCO1 function is on RC6
0 = NCO1 function is on RC1
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 100
PIC16(L)F1507
11.2
11.2.2
PORTA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 11-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input only and its TRIS bit will always read as ‘1’.
Example 11-1 shows how to initialize an I/O port.
Reading the PORTA register (Register 11-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC and comparator
inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown below in Table 11-2.
TABLE 11-2:
Pin Name
The TRISA register (Register 11-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
11.2.1
ANSELA REGISTER
The ANSELA register (Register 11-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Note 1:
2:
PORTA OUTPUT PRIORITY
Function Priority(1)
RA0
ICSPDAT
RA0
RA1
RA1
RA2
CLC1(2)
PWM3
RA2
RA3
None
RA4
CLKOUT
RA4
RA5
RA5
Priority listed from highest to lowest.
Default pin (see APFCON register).
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
EXAMPLE 11-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTA
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
DS41586A-page 101
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 11-2:
PORTA: PORTA REGISTER
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
—
—
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-3:
TRISA: PORTA TRI-STATE REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
U-1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3
Unimplemented: Read as ‘1’
bit 2-0
TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1:
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 102
PIC16(L)F1507
REGISTER 11-4:
LATA: PORTA DATA LATCH REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LATA<2:0>: RA<2:0> Output Latch Value bits(1)
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-5:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4
ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS41586A-page 103
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 11-6:
WPUA: WEAK PULL-UP PORTA REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
WPUA<5:0>: Weak Pull-up Register bits(3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1:
2:
3:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
TABLE 11-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ANSELA
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
103
APFCON
—
—
—
—
—
—
CLC1SEL
NCO1SEL
100
LATA2
LATA1
LATA0
LATA
Bit 1
Bit 0
Register
on Page
Bit 7
—
—
LATA5
LATA4
—
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
102
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
102
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
104
OPTION_REG
WPUA
Legend:
Note 1:
CONFIG1
Legend:
137
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Unimplemented, read as ‘1’.
TABLE 11-4:
Name
103
PS<2:0>
Bits
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
—
CLKOUTEN
13:8
—
—
—
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
Register
on Page
40
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 104
PIC16(L)F1507
11.3
11.3.2
PORTB Registers
PORTB is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 11-8). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 11-1 shows how to initialize an I/O port.
Reading the PORTB register (Register 11-7) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
The TRISB register (Register 11-8) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
11.3.1
ANSELB REGISTER
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-5.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the output priority list. These input functions
can remain active when the pin is configured as an
output. Certain digital input functions override other
port functions and are included in the output priority list.
TABLE 11-5:
PORTB OUTPUT PRIORITY
Pin Name
Function Priority(1)
RB4
RB4
RB5
RB5
RB6
RB6
RB7
RB7
Note 1:
2:
Priority listed from highest to lowest.
Default pin (see APFCON register).
The ANSELB register (Register 11-10) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected
port.
Note:
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
DS41586A-page 105
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 11-7:
PORTB: PORTB REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
RB<7:4>: PORTB General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 11-8:
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
TRISB<7:4>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 11-9:
LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATB7
LATB6
LATB5
LATB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
LATB<7:4>: PORTB Output Latch Value bits(1)
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 106
PIC16(L)F1507
REGISTER 11-10: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
—
—
ANSB5
ANSB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
WPUB7
WPUB6
WPUB5
WPUB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
WPUB<7:4>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 11-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
ANSB5
ANSB4
—
—
—
—
107
LATB7
LATB6
LATB5
LATB4
—
—
—
—
106
RB7
RB6
RB5
RB4
—
—
—
—
106
—
—
—
106
—
—
—
107
ANSELB
LATB
PORTB
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
—
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.
DS41586A-page 107
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
11.4
11.4.2
PORTC Registers
PORTC is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 11-8). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance
mode). Clearing a TRISC bit (= 0) will make the
corresponding PORTC pin an output (i.e., enable the
output driver and put the contents of the output latch
on the selected pin). Example 11-1 shows how to
initialize an I/O port.
Reading the PORTC register (Register 11-7) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-7.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the output priority list. These input functions
can remain active when the pin is configured as an
output. Certain digital input functions override other
port functions and are included in the output priority list.
TABLE 11-7:
Pin Name
The TRISC register (Register 11-8) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
11.4.1
ANSELC REGISTER
The ANSELC register (Register 11-10) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected
port.
Note:
The ANSELC bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
 2011 Microchip Technology Inc.
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Function Priority(1)
RC0
CLC2
RC0
RC1
NCO1(2)
PWM4
RC1
RC2
RC2
RC3
PWM2
RC3
RC4
CWG1B
RC4
RC5
CWG1A
CLC1(3)
PWM1
RC5
RC6
NCO1(3)
RC6
RC7
RC7
Note 1:
2:
3:
Preliminary
PORTC OUTPUT PRIORITY
Priority listed from highest to lowest.
Default pin (see APFCON register).
Alternate pin (see APFCON register).
DS41586A-page 108
PIC16(L)F1507
REGISTER 11-12: PORTC: PORTC REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
RC<7:0>: PORTC General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 11-13: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 11-14: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATC<7:0>: PORTC Output Latch Value bits(1)
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
DS41586A-page 109
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 11-15: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC7
ANSC6
—
—
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 11-16: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC7
WPUC6
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
WPUC<7:0>: Weak Pull-Up Register bits(1, 2)
1 = Pull-up enabled
0 = Pull-up disabled
bit 7-0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 11-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
ANSC3
ANSC2
ANSC1
ANSC0
107
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
106
RC4
RC3
RC2
RC1
RC0
106
Bit 7
Bit 6
ANSELC
ANSC7
ANSC6
LATC
LATC7
LATC6
RC7
RC6
RC5
PORTC
Bit 5
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
106
WPUC
WPUC7
WPUC6
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
107
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 110
PIC16(L)F1507
12.0
INTERRUPT-ON-CHANGE
12.3
The PORTA and PORTB pins can be configured to
operate as Interrupt-On-Change (IOC) pins. An interrupt
can be generated by detecting a signal that has either a
rising edge or a falling edge. Any individual port pin, or
combination of port pins, can be configured to generate
an interrupt. The interrupt-on-change module has the
following features:
•
•
•
•
Interrupt-on-Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
The IOCAFx and IOCBFx bits located in the IOCAF and
IOCBF registers, respectively, are status flags that
correspond to the interrupt-on-change pins of the
associated port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
12.4
Clearing Interrupt Flags
The individual status flags, (IOCAFx and IOCBFx bits),
can be cleared by resetting them to zero. If another edge
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 12-1 is a block diagram of the IOC module.
12.1
Interrupt Flags
Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
12.2
Individual Pin Configuration
EXAMPLE 12-1:
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
MOVLW
XORWF
ANDWF
A pin can be configured to detect rising and falling
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
12.5
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
DS41586A-page 111
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 12-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTB EXAMPLE)
IOCBNx
D
Q4Q1
Q
CK
Edge
Detect
R
RBx
IOCBPx
D
Data Bus =
0 or 1
Q
Write IOCBFx
CK
D
S
Q
To Data Bus
IOCBFx
CK
IOCIE
R
Q2
From all other
IOCBFx individual
Pin Detectors
Q1
Q2
Q3
Q4
Q4Q1
Q1
Q1
Q2
Q2
Q3
Q4
Q4Q1
 2011 Microchip Technology Inc.
IOC interrupt
to CPU core
Q3
Q4
Q4
Q4Q1
Preliminary
Q4Q1
DS41586A-page 112
PIC16(L)F1507
12.6
Interrupt-On-Change Registers
REGISTER 12-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 12-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 12-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.
DS41586A-page 113
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 12-4:
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be
set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 12-5:
IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be
set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 5-0
Unimplemented: Read as ‘0’
REGISTER 12-6:
IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBF7
IOCBF6
IOCBF5
IOCBF4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-4
IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge
was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
bit 5-0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 114
PIC16(L)F1507
TABLE 12-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
103
107
ANSELA
ANSELB
—
—
ANSB5
ANSB4
—
—
—
—
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
IOCAF
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
113
IOCAN
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
113
IOCAP
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
113
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
—
—
—
—
114
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
—
—
—
—
114
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
—
—
—
—
114
TRISA2
TRISA1
TRISA0
102
—
—
—
106
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
Legend:
Note 1:
— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Unimplemented, read as ‘1’.
DS41586A-page 115
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 116
PIC16(L)F1507
13.0
FIXED VOLTAGE REFERENCE
(FVR)
13.1
Independent Gain Amplifier
The output of the FVR supplied to the ADC is routed
through a programmable gain amplifier. The amplifier
can be programmed for a gain of 1x, 2x or 4x, to
produce the three possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
13.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 25.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 13-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
x2
x4
FVR BUFFER1
(To ADC Module)
1.024V Fixed
Reference
+
FVREN
FVRRDY
-
Any peripheral requiring
the Fixed Reference
(See Table 13-1)
TABLE 13-1:
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
HFINTOSC
BOR
LDO
Conditions
Description
FOSC<1:0> = 00 and
IRCF<3:0> = 000x
INTOSC is active and device is not in Sleep.
BOREN<1:0> = 11
BOR always enabled.
BOREN<1:0> = 10 and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1
BOR under software control, BOR Fast Start enabled.
All PIC16F1507 devices, when
VREGPM = 1 and not in Sleep
The device runs off of the Low-Power Regulator when in
Sleep mode.
DS41586A-page 117
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
13.3
FVR Control Registers
REGISTER 13-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
U-0
U-0
FVREN
FVRRDY(1)
TSEN
TSRNG
—
—
R/W-0/0
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5
TSEN: Temperature Indicator Enable bit
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4
TSRNG: Temperature Indicator Range Selection bit
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = ADC Fixed Voltage Reference Peripheral output is off
Note 1:
2:
FVRRDY is always ‘1’ for the PIC16F1507 devices.
Fixed Voltage Reference output cannot exceed VDD.
TABLE 13-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
118
Shaded cells are unused by the Fixed Voltage Reference module.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 118
PIC16(L)F1507
14.0
TEMPERATURE INDICATOR
MODULE
FIGURE 14-1:
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
TEMPERATURE CIRCUIT
DIAGRAM
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
14.1
Circuit Operation
14.2
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 14-1 describes the output characteristics of
the temperature indicator.
EQUATION 14-1:
VOUT
VOUT RANGES
To ADC
Minimum Operating VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is correctly biased.
Table 14-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
TABLE 14-1:
Low Range: VOUT = VDD - 2VT
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 13.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
DS41586A-page 119
RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
14.3
Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
14.4
ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 14-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
118
Shaded cells are unused by the temperature indicator module.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 120
PIC16(L)F1507
15.0
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 15-1:
ADC BLOCK DIAGRAM
VDD
ADPREF = 00
VREF+
AN0
00000
VREF+/AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
AN8
01000
AN9
01001
AN10
01010
AN11
01011
ADPREF = 10
VREF- = VSS
VREF+
ADC
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
ADON
Temp Indicator
Reserved
11110
FVR Buffer1
11111
11101
16
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
When ADON = 0, all multiplexer inputs are disconnected.
DS41586A-page 121
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
15.1
15.1.4
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
15.1.1
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 11.0 “I/O Ports” for more information.
Note:
15.1.2
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
•
•
•
•
•
•
•
PORT CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input buffer to conduct excess current.
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 25.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of appropriate ADC clock selections.
Note:
CHANNEL SELECTION
CONVERSION CLOCK
There are 14 channel selections available:
• AN<11:0> pins
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
Refer to Section 13.0 “Fixed Voltage Reference (FVR)”
and Section 14.0 “Temperature Indicator Module” for
more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
•
•
•
•
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 122
PIC16(L)F1507
TABLE 15-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
(2)
200 ns
(2)
250 ns
(2)
Fosc/8
001
400 ns(2)
0.5 s(2)
Fosc/16
101
800 ns
010
Fosc/64
FRC
Fosc/32
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
1.0 s
2.0 s
4.0 s
16.0 s(3)
1.6 s
2.0 s
4.0 s
110
3.2 s
4.0 s
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
500 ns
8.0 s
(3)
1.0-6.0 s(1,4)
8.0 s
(3)
16.0 s
(3)
1.0-6.0 s(1,4)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS41586A-page 123
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
15.1.5
INTERRUPTS
15.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
(ADFM = 1)
bit 0
MSB
bit 7
LSB
bit 0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
bit 7
bit 0
10-bit A/D Result
Preliminary
DS41586A-page 124
PIC16(L)F1507
15.2
15.2.1
15.2.4
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
15.2.2
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.6 “A/D Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
DS41586A-page 125
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
15.2.5
AUTO-CONVERSION TRIGGER
The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
The auto-conversion trigger source is selected with the
TRIGSEL<3:0> bits of the ADCON2 register.
Using the auto-conversion trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
Auto-Conversion sources are:
•
•
•
•
•
TMR0
TMR1
TMR2
CLC1
CLC2
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
15.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 15-1:
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B’11110000’ ;Right justify, Frc
;clock
MOVWF
ADCON1
;Vdd and Vss Vref+
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B’00000001’ ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.3 “A/D Acquisition
Requirements”.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 126
PIC16(L)F1507
15.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 15-1:
U-0
ADCON0: A/D CONTROL REGISTER 0
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000 = AN0
00001 = AN1
00010 = AN2
00011 = AN3
00100 = AN4
00101 = AN5
00110 = AN6
00111 = AN7
01000 = AN8
01001 = AN9
01010 = AN10
01011 = AN11
01100 = Reserved. No channel connected.
•
•
•
11101 = Temperature Indicator(2)
11110 = Reserved. No channel connected
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
2:
See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.
See Section 14.0 “Temperature Indicator Module” for more information.
DS41586A-page 127
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 15-2:
R/W-0/0
ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
—
—
R/W-0/0
bit 7
R/W-0/0
ADPREF<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00 = VREF+ is connected to VDD
01 = Reserved
10 = VREF+ is connected to external VREF+ pin(1)
11 = Reserved
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 25.0 “Electrical Specifications” for details.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 128
PIC16(L)F1507
REGISTER 15-3:
R/W-0/0
ADCON2: A/D CONTROL REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<3:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
TRIGSEL<3:0>: Auto-conversion Trigger Selection bits(1)
0000 = No auto-conversion trigger selected
0001 = Reserved
0010 = Reserved
0011 = TMR0 Overflow(2)
0100 = TMR1 Overflow(2)
0101 = TMR2 Match to PR2(2)
0110 = Reserved
0111 = Reserved
1000 = CLC1
1001 = CLC2
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
This is a rising edge sensitive input for all sources.
Signal also sets its corresponding interrupt flag.
DS41586A-page 129
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 15-4:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 15-5:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0
Reserved: Do not use.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 130
PIC16(L)F1507
REGISTER 15-6:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Reserved: Do not use.
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 15-7:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41586A-page 131
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
15.3
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
 = V CHOLD
V AP P LI ED  1 – -------------------------n+1


2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------

RC
V AP P LI ED  1 – e  = V CHOLD


;[2] VCHOLD charge response to VAPPLIED
– Tc
---------

1
RC
 ;combining [1] and [2]
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------n+1



2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 12.5pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.12 µs
Therefore:
T A CQ = 5µs + 1.12 µs +   50°C- 25°C   0.05 µs/°C  
= 7.37µs
Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 132
PIC16(L)F1507
FIGURE 15-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Rs
VT  0.6V
CPIN
5 pF
VA
RIC  1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT  0.6V
CHOLD = 10 pF
VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
RSS
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
RSS
= Resistance of Sampling Switch
SS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
FIGURE 15-5:
5 6 7 8 9 10 11
Sampling Switch
(k)
Refer to Section 25.0 “Electrical Specifications”.
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
VREF-
DS41586A-page 133
1.5 LSB
Zero-Scale
Transition
Full-Scale
Transition
Preliminary
VREF+
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 15-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
ADCON0
—
ADCON1
ADFM
ADCON2
Bit 6
Bit 5
Bit 4
Bit 2
—
—
ADPREF<1:0>
128
—
—
—
129
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
Bit 1
Bit 0
GO/DONE
ADON
Register
on Page
Bit 3
—
127
ADRESH
A/D Result Register High
130, 131
ADRESL
A/D Result Register Low
130, 131
ANSELA
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
103
ANSELB
—
—
ANSB5
ANSB4
—
—
—
—
107
ANSELC
ANSC7
ANSC6
—
—
ANSC3
ANSC2
ANSC1
ANSC0
110
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
PIE1
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
67
PIR1
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
70
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
102
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
106
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
109
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
Legend:
Note 1:
ADFVR<1:0>
118
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 134
PIC16(L)F1507
16.0
16.1.2
TIMER0 MODULE
8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the
following features:
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
•
•
•
•
•
•
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
8-bit timer/counter register (TMR0)
8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
TMR0 can be used to gate Timer1
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
Figure 16-1 is a block diagram of the Timer0 module.
16.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
16.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 16-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
8
T0CKI
1
Sync
2 TCY
1
TMR0
0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
Set Flag bit TMR0IF
on Overflow
Overflow to Timer1
8
PS<2:0>
DS41586A-page 135
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
16.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
16.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
16.1.5
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
16.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 136
PIC16(L)F1507
16.2
Option and Timer0 Control Register
REGISTER 16-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN: Weak Pull-Up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
TABLE 16-1:
Bit 7
ADCON2
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
TRIGSEL<3:0>
OPTION_REG
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
—
129
TMR0IF
INTF
IOCIF
GIE
PEIE
TMR0IE
INTE
IOCIE
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
INTCON
PS<2:0>
—
—
TRISA5
TRISA4
66
137
Holding Register for the 8-bit Timer0 Count
TRISA
Legend:
*
Note 1:
Timer0 Rate
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
Bit Value
135*
—(1)
TRISA2
TRISA1
TRISA0
102
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
Unimplemented, read as ‘1’.
DS41586A-page 137
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 138
PIC16(L)F1507
17.0
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
Figure 17-1 is a block diagram of the Timer1 module.
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
2-bit prescaler
Optionally synchronized comparator out
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Special Event Trigger
• Selectable Gate Source Polarity
• Gate Toggle mode
FIGURE 17-1:
TIMER1 BLOCK DIAGRAM
T1GSS
T1G
T1GSPM
0
From Timer0
Overflow
0
t1g_in
1
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
D
Q
CK
R
Q
1
Acq. Control
1
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
det
Set
TMR1GIF
T1GTM
TMR1GE
Set flag bit
TMR1IF on
Overflow
To ADC Auto-Conversion
TMR1ON
TMR1(2)
TMR1H
TMR1L
EN
Q
D
T1CLK
Synchronized
Clock Input
0
1
TMR1CS<1:0>
LFINTOSC
T1SYNC
11
(1)
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
T1CKI
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
DS41586A-page 139
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
17.1
Timer1 Operation
17.2
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> bits of the T1CON register are used
to select the clock source for Timer1. Table 17-2
displays the clock source selections.
17.2.1
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and increments on every selected edge of the external source.
INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 17-1 displays the Timer1 enable
selections.
TABLE 17-1:
Clock Source Selection
TIMER1 ENABLE
SELECTIONS
The following asynchronous sources may be used:
• Asynchronous event on the T1G pin to Timer1
gate
Timer1
Operation
TMR1ON
TMR1GE
0
0
Off
17.2.2
0
1
Off
1
0
Always On
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
1
1
Count Enabled
EXTERNAL CLOCK SOURCE
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. The
external clock source can be synchronized to the
microcontroller system clock or it can run
asynchronously.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•
•
•
•
TABLE 17-2:
Timer1 enabled after POR
Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
T1OSCEN
Clock Source
1
1
x
LFINTOSC
1
0
0
External Clocking on T1CKI Pin
0
1
x
System Clock (FOSC)
0
0
x
Instruction Clock (FOSC/4)
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 140
PIC16(L)F1507
17.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
17.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 17.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
17.4.1
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 17-3 for timing details.
TABLE 17-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G

0
0
Counts

0
1
Holds Count

1
0
Holds Count

1
1
Counts
17.5.2
Timer1 Operation
TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 17-4.
Source selection is controlled by the T1GSS bit of the
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
TABLE 17-4:
T1GSS
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
TIMER1 GATE SOURCES
Timer1 Gate Source
0
Timer1 Gate Pin
1
Overflow of Timer0
(TMR0 increments from FFh to 00h)
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
17.5
Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
17.5.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
DS41586A-page 141
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
17.5.2.1
T1G Pin Gate Operation
17.5.5
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
gate circuitry.
17.5.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
17.5.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the signal. See Figure 17-4 for timing details.
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
17.5.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
17.5.4
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 17-5 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 17-6 for timing
details.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 142
PIC16(L)F1507
17.6
Timer1 Interrupt
17.7
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
•
•
•
•
TMR1ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 17-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
DS41586A-page 143
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 17-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
N
FIGURE 17-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N
 2011 Microchip Technology Inc.
N+1 N+2 N+3
N+4
Preliminary
N+5 N+6 N+7
N+8
DS41586A-page 144
PIC16(L)F1507
FIGURE 17-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS41586A-page 145
N
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by software
Preliminary
Cleared by
software
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 17-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
N
Cleared by software
 2011 Microchip Technology Inc.
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
Preliminary
N+4
Cleared by
software
DS41586A-page 146
PIC16(L)F1507
17.8
Timer1 Control Registers
REGISTER 17-1:
R/W-0/u
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
TMR1CS<1:0>
R/W-0/u
R/W-0/u
T1CKPS<1:0>
U-0
R/W-0/u
U-0
R/W-0/u
—
T1SYNC
—
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Timer1 clock source is LFINTOSC
10 = Timer1 clock source is T1CKI pin (on rising edge)
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
Unimplemented: Read as ‘0’
bit 2
T1SYNC: Timer1 Synchronization Control bit
1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
DS41586A-page 147
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 17-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
U-0
R/W-0/u
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
—
T1GSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1
Unimplemented: Read as ‘0’
bit 0
T1GSS: Timer1 Gate Source Select bit
0 = Timer1 gate pin
1 = Timer0 overflow output
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 148
PIC16(L)F1507
TABLE 17-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
103
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
PIE1
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
67
PIR1
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
70
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
143*
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
143*
TRISA
—
T1CON
TMR1CS<1:0>
T1GCON
Legend:
*
Note 1:
TMR1GE
—
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
—(1)
TRISA2
TRISA1
TRISA0
102
—
T1SYNC
—
TMR1ON
147
T1GGO/
DONE
T1GVAL
—
T1GSS
148
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
Unimplemented, read as ‘1’.
DS41586A-page 149
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 150
PIC16(L)F1507
18.0
TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
• Optional use as the shift clock for the MSSP
modules
See Figure 18-1 for a block diagram of Timer2.
FIGURE 18-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
Postscaler
1:1 to 1:16
EQ
T2CKPS<1:0>
4
PR2
T2OUTPS<3:0>
DS41586A-page 151
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
18.1
Timer2 Operation
18.3
The clock input to the Timer2 module is the system
instruction clock (FOSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
counter/postscaler
(see
Section 18.2
“Timer2
Interrupt”).
Timer2 Output
The unscaled output of TMR2 is available primarily to
the PWMx module, where it is used as a time base for
operation.
18.4
Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
•
•
•
•
•
•
•
•
•
a write to the TMR2 register
a write to the T2CON register
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note:
18.2
TMR2 is not cleared when T2CON is
written.
Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 152
PIC16(L)F1507
REGISTER 18-1:
U-0
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
R/W-0/0
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16
11 = Prescaler is 64
DS41586A-page 153
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 18-1:
Name
INTCON
PIE1
PIR1
PR2
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
TMR1GIE
ADIE
—
—
—
—
TMR2IE
TMR1IE
67
TMR1GIF
ADIF
—
—
—
—
TMR2IF
TMR1IF
Timer2 Module Period Register
70
151*
PWM1CON
PWM1EN
PWM1OE
PWM1OUT PWM1POL
—
—
—
—
159
PWM2CON
PWM2EN
PWM2OE
PWM2OUT PWM2POL
—
—
—
—
159
PWM3CON
PWM3EN
PWM3OE
PWM3OUT PWM3POL
—
—
—
—
159
PWM4CON
PWM4EN
PWM4OE
PWM4OUT PWM4POL
—
—
—
—
159
T2CON
TMR2
Legend:
*
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Holding Register for the 8-bit TMR2 Count
153
151*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2/4/6 module.
Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 154
PIC16(L)F1507
19.0
For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section 19.1.9
“Setup for PWM Operation using PWMx Pins”.
PULSE WIDTH MODULATION
(PWM) MODULE
The PWM module generates a Pulse-Width Modulated
signal determined by the duty cycle, period, and resolution that are configured by the following registers:
•
•
•
•
•
FIGURE 19-1:
PWM OUTPUT
Period
PR2
T2CON
PWMxDCH
PWMxDCL
PWMxCON
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
Figure 19-2 shows a simplified block diagram of PWM
operation.
Figure 19-1 shows a typical waveform of the PWM
signal.
FIGURE 19-2:
SIMPLIFIED PWM BLOCK DIAGRAM
Duty Cycle registers
PWMxDCL<7:6>
PWMxDCH
PWMxOUT
to other peripherals: CLC and CWG
Latched
(Not visible to user)
Output Enable (PWMxOE)
TRIS Control
Comparator
R
Q
0
PWMx
S
Q
1
TMR2 Module
TMR2
Output Polarity (PWMxPOL)
(1)
Comparator
PR2
Note 1:
DS41586A-page 155
Clear Timer,
PWMx pin and
latch Duty Cycle
8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by
the Timer2 prescaler to create a 10-bit time base.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
19.1
PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
Note:
19.1.1
Clearing the PWMxOE bit will relinquish
control of the PWMx pin.
FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note:
The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle).
Note:
19.1.2
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
Note:
19.1.4
Equation 19-2 is used to calculate the PWM pulse
width.
Equation 19-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 19-2:
T OS C  (TMR2 Prescale Value)
Note: TOSC = 1/FOSC
EQUATION 19-3:
EQUATION 19-1:
PWM PERIOD
DUTY CYCLE RATIO
 PWMxDCH:PWMxDCL<7:6> 
Duty Cycle Ratio = ----------------------------------------------------------------------------------4  PR2 + 1 
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 19-1.
PULSE WIDTH
Pulse Width =  PWMxDCH:PWMxDCL<7:6>  
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
19.1.3
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDCH and PWMxDCL register pair.
The PWMxDCH register contains the eight MSbs and
the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
and PWMxDCL registers can be written to at any time.
The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are
updated when Timer2 matches PR2. Care
should be taken to update both registers
before the timer match occurs.
PWM OUTPUT POLARITY
The Timer2 postscaler has no effect on
the PWM operation.
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 156
PIC16(L)F1507
19.1.5
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an
8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 19-4.
EQUATION 19-4:
PWM RESOLUTION
log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 19-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)
PR2 Value
78.12 kHz
156.3 kHz
208.3 kHz
64
4
1
1
1
1
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)
PR2 Value
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
Maximum Resolution (bits)
19.1.6
19.53 kHz
0xFF
Maximum Resolution (bits)
TABLE 19-2:
4.88 kHz
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
19.1.7
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module” for additional details.
19.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
DS41586A-page 157
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
19.1.9
SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx pins:
1.
Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the PR2 register with the PWM period
value.
4. Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the T2CKPS bits of the T2CON register
with the Timer2 prescale value.
• Enable Timer2 by setting the TMR2ON bit of the
T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See note below.
7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 158
PIC16(L)F1507
19.2
PWM Register Definitions
REGISTER 19-1:
PWMxCON: PWM CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
PWMxOE
PWMxOUT
PWMxPOL
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PWMxEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 6
PWMxOE: PWM Module Output Enable bit
1 = Output to PWMx pin is enabled
0 = Output to PWMx pin is disabled
bit 5
PWMxOUT: PWM Module Output Value bit
bit 4
PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active low
0 = PWM output is active high
bit 3-0
Unimplemented: Read as ‘0’
DS41586A-page 159
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 19-2:
R/W-x/u
PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDCH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 19-3:
R/W-x/u
PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
PWMxDCL<7:6>
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
bit 5-0
Unimplemented: Read as ‘0’
TABLE 19-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 7
Bit 6
Bit 5
PWM1EN
PWM1OE
PWM1OUT
PR2
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Timer2 module Period Register
PWM1CON
PWM1DCH
PWM1DCL
PWM2CON
PWM3CON
PWM1DCL<7:6>
PWM4CON
151*
PWM2EN
PWM2OE
160
—
—
—
—
—
160
PWM2OUT
PWM2POL
—
—
—
—
160
PWM2DCH<7:0>
PWM2DCL<7:6>
PWM3EN
PWM3OE
160
—
—
—
—
—
—
160
PWM3OUT
PWM3POL
—
—
—
—
159
PWM3DCH<7:0>
PWM3DCL<7:6>
PWM4EN
PWM4OE
160
—
—
—
—
—
—
160
PWM4OUT
PWM4POL
—
—
—
—
159
—
—
—
PWM4DCH
PWM4DCH<7:0>
PWM4DCL
PWM4DCL<7:6>
T2CON
—
159
—
PWM3DCH
PWM3DCL
—
PWM1DCH<7:0>
PWM2DCH
PWM2DCL
PWM1POL
Register
on Page
—
—
—
T2OUTPS<3:0>
TMR2
160
TMR2ON
T2CKPS<1:0>
Timer2 module Register
160
153
151*
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
102
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
109
Legend:
Note
*
1:
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
Page provides register information.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 160
PIC16(L)F1507
20.0
CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals and through the use of configurable gates
reduces the 16 inputs to four logic lines that drive one
of eight selectable single-output logic functions.
Input sources are a combination of the following:
•
•
•
•
I/O pins
Internal clocks
Peripherals
Register bits
The output can be directed internally to peripherals and
to an output pin.
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
Possible configurations include:
• Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
CLCx SIMPLIFIED BLOCK DIAGRAM
D
Q1
See Figure 20-3
Input Data Selection Gates
FIGURE 20-1:
Refer to Figure 20-1 for a simplified diagram showing
signal flow through the CLCx.
MLCxOUT
TRIS Control
lcxg2
Logic
lcxg3
Function
lcxq
lcx_out
CLCx
lcxg4
LCxPOL
LCxMODE<2:0>
Interrupt
det
LCxINTP
LCxINTN
sets
CLCxIF
flag
Interrupt
See Figure 20-2
DS41586A-page 161
LE
LCxOUT
LCxOE
LCxEN
lcxg1
Q
det
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
20.1
20.1.1
CLCx Setup
Programming the CLCx module is performed by configuring the 4 stages in the logic signal flow. The 4 stages
are:
•
•
•
•
Data selection
Data gating
Logic function selection
Output polarity
Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
DATA SELECTION
There are 16 signals available as inputs to the configurable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrangement makes possible selection of up to two from a
group without precluding a selection from another
group.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 20-3 and Register 20-4,
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 20-3 and Register 20-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 20-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 20-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note:
TABLE 20-1:
Data selections are undefined at power-up.
CLCx DATA INPUT SELECTION
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
CLCxIN[0]
000
—
—
100
CLC1IN0
CLC2IN0
CLCxIN[1]
001
—
—
101
CLC1IN1
CLC2IN1
CLCxIN[2]
010
—
—
110
Reserved
Reserved
CLCxIN[3]
011
—
—
111
Reserved
Reserved
Data Input
CLC 1
CLC 2
CLCxIN[4]
100
000
—
—
FOSC
FOSC
CLCxIN[5]
101
001
—
—
TMR0IF
TMR0IF
CLCxIN[6]
110
010
—
—
TMR1IF
TMR1IF
CLCxIN[7]
111
011
—
—
TMR2 = PR2
TMR2 = PR2
CLCxIN[8]
—
100
000
—
lcx1_out
lcx1_out
CLCxIN[9]
—
101
001
—
lcx2_out
lcx2_out
CLCxIN[10]
—
110
010
—
lcx3_out
lcx3_out
CLCxIN[11]
—
111
011
—
lcx4_out
lcx4_out
CLCxIN[12]
—
—
100
000
NCO1OUT
LFINTOSC
CLCxIN[13]
—
—
101
001
HFINTOSC
ADCFRC
CLCxIN[14]
—
—
110
010
PWM3OUT
PWM1OUT
CLCxIN[15]
—
—
111
011
PWM4OUT
PWM2OUT
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 162
PIC16(L)F1507
20.1.2
DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
Note:
20.1.3
Data gating is undefined at power-up.
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. Directed signals are
ANDed together in each gate. The output of each gate
can be inverted before going on to the logic function
stage.
The gating is in essence a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND or all enabled inputs.
Table 20-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
TABLE 20-2:
LCxG1POL
Gate Logic
0x55
1
AND
0x55
0
NAND
0xAA
1
NOR
0xAA
0
OR
0x00
0
Logic 0
0x00
1
Logic 1
LOGIC FUNCTION
There are 8 available logic functions including:
•
•
•
•
•
•
•
•
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
Logic functions are shown in Figure 20-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
20.1.4
OUTPUT POLARITY
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
DATA GATING LOGIC
CLCxGLS0
Data gating is indicated in the right side of Figure 20-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select registers as follows:
•
•
•
•
Gate 1: CLCxGLS0 (Register 20-5)
Gate 2: CLCxGLS1 (Register 20-6)
Gate 3: CLCxGLS2 (Register 20-7)
Gate 4: CLCxGLS3 (Register 20-8)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
DS41586A-page 163
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
20.1.5
CLCx SETUP STEPS
• PEIE and GIE bits of the INTCON register
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 and
CLCxSEL1 registers (See Table 20-1).
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the LCxPOLy bits of the CLCxPOL register.
• Select the desired logic function with the
LCxMODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate output polarity step).
• If driving the CLCx pin, set the LCxOE bit of the
CLCxCON register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
- Set the LCxINTN bit in the CLCxCON
register or falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
20.2
The LCxIF bit of the associated PIR registers, must be
cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
20.3
Output Mirror Copies
Mirror copies of all LCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
20.4
Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
20.5
Operation During Sleep
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The LCxIF bit of the associated PIR registers will be set
when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising
edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON register.
To fully enable the interrupt, set the following bits:
• LCxON bit of the CLCxCON register
• LCxIE bit of the associated PIE registers
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a falling edge detection)
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 164
PIC16(L)F1507
FIGURE 20-2:
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
INPUT DATA SELECTION AND GATING
Data Selection
000
Data GATE 1
lcxd1T
LCxD1G1T
lcxd1N
LCxD1G1N
111
LCxD2G1T
LCxD1S<2:0>
LCxD2G1N
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
LCxD3G1T
lcxd2T
LCxD3G1N
LCxD4G1T
111
LCxD4G1N
000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
111
lcxg3
LCxD3S<2:0>
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
LCxG1POL
lcxd2N
LCxD2S<2:0>
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
lcxg1
000
(Same as Data GATE 1)
Data GATE 4
000
lcxg4
(Same as Data GATE 1)
lcxd4T
lcxd4N
111
LCxD4S<2:0>
Note:
DS41586A-page 165
All controls are undefined at power-up.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 20-3:
PROGRAMMABLE LOGIC FUNCTIONS
AND - OR
OR - XOR
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
lcxq
lcxg3
lcxg4
lcxg4
LCxMODE<2:0>= 000
LCxMODE<2:0>= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
S
lcxg3
lcxg4
R
lcxg4
LCxMODE<2:0>= 010
lcxq
Q
LCxMODE<2:0>= 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg2
D
S
lcxg4
Q
lcxq
D
lcxg2
lcxg1
lcxg1
Q
lcxq
R
R
lcxg3
lcxg3
LCxMODE<2:0>= 100
LCxMODE<2:0>= 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
lcxg2
J
Q
lcxq
lcxg1
lcxg4
K
R
lcxg2
D
lcxg1
LE
lcxg3
S
lcxq
Q
R
lcxg3
LCxMODE<2:0>= 110
 2011 Microchip Technology Inc.
LCxMODE<2:0>= 111
Preliminary
DS41586A-page 166
PIC16(L)F1507
20.6
CLCx Control Registers
REGISTER 20-1:
CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
LCxEN
LCxOE
LCxOUT
LCxINTP
LCxINTN
R/W-0/0
R/W-0/0
R/W-0/0
LCxMODE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxEN: Configurable Logic Cell Enable bit
1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6
LCxOE: Configurable Logic Cell Output Enable bit
1 = Configurable logic cell port pin output enabled
0 = Configurable logic cell port pin output disabled
bit 5
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
bit 4
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = LCxIF will be set when a rising edge occurs on lcx_out
0 = LCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = LCxIF will be set when a falling edge occurs on lcx_out
0 = LCxIF will not be set
bit 2-0
LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K Flip-Flop with R
101 = Cell is 2-input D Flip-Flop with R
100 = Cell is 1-input D Flip-Flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR
DS41586A-page 167
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 20-2:
CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxPOL
—
—
—
LCxG4POL
LCxG3POL
LCxG2POL
LCxG1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxPOL: LCOUT Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4
Unimplemented: Read as ‘0’
bit 3
LCxG4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted
bit 2
LCxG3POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 1
LCxG2POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 0
LCxG1POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 168
PIC16(L)F1507
REGISTER 20-3:
U-0
CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER
R/W-x/u
—
R/W-x/u
R/W-x/u
LCxD2S<2:0>
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
LCxD1S<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD2S<2:0>: Input Data 2 Selection Control bits(1)
111 = CLCxIN[11] is selected for lcxd2
110 = CLCxIN[10] is selected for lcxd2
101 = CLCxIN[9] is selected for lcxd2
100 = CLCxIN[8] is selected for lcxd2
011 = CLCxIN[7] is selected for lcxd2
010 = CLCxIN[6] is selected for lcxd2
001 = CLCxIN[5] is selected for lcxd2
000 = CLCxIN[4] is selected for lcxd2
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD1S<2:0>: Input Data 1 Selection Control bits(1)
111 = CLCxIN[7] is selected for lcxd1
110 = CLCxIN[6] is selected for lcxd1
101 = CLCxIN[5] is selected for lcxd1
100 = CLCxIN[4] is selected for lcxd1
011 = CLCxIN[3] is selected for lcxd1
010 = CLCxIN[2] is selected for lcxd1
001 = CLCxIN[1] is selected for lcxd1
000 = CLCxIN[0] is selected for lcxd1
Note 1:
See Table 20-1 for signal names associated with inputs.
DS41586A-page 169
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 20-4:
U-0
CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER
R/W-x/u
—
R/W-x/u
R/W-x/u
LCxD4S<2:0>
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
LCxD3S<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD4S<2:0>: Input Data 4 Selection Control bits(1)
111 = CLCxIN[3] is selected for lcxd4
110 = CLCxIN[2] is selected for lcxd4
101 = CLCxIN[1] is selected for lcxd4
100 = CLCxIN[0] is selected for lcxd4
011 = CLCxIN[15] is selected for lcxd4
010 = CLCxIN[14] is selected for lcxd4
001 = CLCxIN[13] is selected for lcxd4
000 = CLCxIN[12] is selected for lcxd4
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD3S<2:0>: Input Data 3 Selection Control bits(1)
111 = CLCxIN[15] is selected for lcxd3
110 = CLCxIN[14] is selected for lcxd3
101 = CLCxIN[13] is selected for lcxd3
100 = CLCxIN[12] is selected for lcxd3
011 = CLCxIN[11] is selected for lcxd3
010 = CLCxIN[10] is selected for lcxd3
001 = CLCxIN[9] is selected for lcxd3
000 = CLCxIN[8] is selected for lcxd3
Note 1:
See Table 20-1 for signal names associated with inputs.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 170
PIC16(L)F1507
REGISTER 20-5:
CLCxGLS0: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N
LCxG1D3T
LCxG1D3N
LCxG1D2T
LCxG1D2N
LCxG1D1T
LCxG1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit
1 = lcxd4T is gated into lcxg1
0 = lcxd4T is not gated into lcxg1
bit 6
LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg1
0 = lcxd4N is not gated into lcxg1
bit 5
LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg1
0 = lcxd3T is not gated into lcxg1
bit 4
LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg1
0 = lcxd3N is not gated into lcxg1
bit 3
LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg1
0 = lcxd2T is not gated into lcxg1
bit 2
LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg1
0 = lcxd2N is not gated into lcxg1
bit 1
LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg1
0 = lcxd1T is not gated into lcxg1
bit 0
LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg1
0 = lcxd1N is not gated into lcxg1
DS41586A-page 171
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 20-6:
CLCxGLS1: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N
LCxG2D3T
LCxG2D3N
LCxG2D2T
LCxG2D2N
LCxG2D1T
LCxG2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit
1 = lcxd4T is gated into lcxg2
0 = lcxd4T is not gated into lcxg2
bit 6
LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg2
0 = lcxd4N is not gated into lcxg2
bit 5
LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg2
0 = lcxd3T is not gated into lcxg2
bit 4
LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg2
0 = lcxd3N is not gated into lcxg2
bit 3
LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg2
0 = lcxd2T is not gated into lcxg2
bit 2
LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg2
0 = lcxd2N is not gated into lcxg2
bit 1
LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg2
0 = lcxd1T is not gated into lcxg2
bit 0
LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg2
0 = lcxd1N is not gated into lcxg2
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 172
PIC16(L)F1507
REGISTER 20-7:
CLCxGLS2: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N
LCxG3D3T
LCxG3D3N
LCxG3D2T
LCxG3D2N
LCxG3D1T
LCxG3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit
1 = lcxd4T is gated into lcxg3
0 = lcxd4T is not gated into lcxg3
bit 6
LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg3
0 = lcxd4N is not gated into lcxg3
bit 5
LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg3
0 = lcxd3T is not gated into lcxg3
bit 4
LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg3
0 = lcxd3N is not gated into lcxg3
bit 3
LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg3
0 = lcxd2T is not gated into lcxg3
bit 2
LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg3
0 = lcxd2N is not gated into lcxg3
bit 1
LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg3
0 = lcxd1T is not gated into lcxg3
bit 0
LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg3
0 = lcxd1N is not gated into lcxg3
DS41586A-page 173
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 20-8:
CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N
LCxG4D3T
LCxG4D3N
LCxG4D2T
LCxG4D2N
LCxG4D1T
LCxG4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit
1 = lcxd4T is gated into lcxg4
0 = lcxd4T is not gated into lcxg4
bit 6
LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg4
0 = lcxd4N is not gated into lcxg4
bit 5
LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg4
0 = lcxd3T is not gated into lcxg4
bit 4
LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg4
0 = lcxd3N is not gated into lcxg4
bit 3
LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg4
0 = lcxd2T is not gated into lcxg4
bit 2
LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg4
0 = lcxd2N is not gated into lcxg4
bit 1
LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg4
0 = lcxd1T is not gated into lcxg4
bit 0
LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg4
0 = lcxd1N is not gated into lcxg4
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 174
PIC16(L)F1507
REGISTER 20-9:
CLCDATA: CLC DATA OUTPUT
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
MLC2OUT: Mirror copy of LC2OUT bit
bit 0
MLC1OUT: Mirror copy of LC1OUT bit
DS41586A-page 175
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 20-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
Register
on Page
ANSELB
—
—
ANSB5
ANSB4
—
—
—
—
107
ANSELC
ANSC7
ANSC6
—
—
ANSC3
ANSC2
ANSC1
ANSC0
110
CLC1CON
LC1EN
LC1OE
LC1OUT
LC1INTP
LC1INTN
LC1MODE<2:0>
167
CLC2CON
LC2EN
LC2OE
LC2OUT
LC2INTP
LC2INTN
LC2MODE<2:0>
167
CLCDATA
—
—
—
—
—
—
MLC2OUT
MLC1OUT
171
CLC1GLS0
LC1G1D4T
LC1G1D4N
LC1G1D3T
LC1G1D3N
LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N
171
CLC1GLS1
LC1G2D4T
LC1G2D4N
LC1G2D3T
LC1G2D3N
LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N
172
CLC1GLS2
LC1G3D4T
LC1G3D4N
LC1G3D3T
LC1G3D3N
LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N
173
CLC1GLS3
LC1G4D4T
LC1G4D4N
LC1G4D3T
LC1G4D3N
LC1G4D2T
LC1G4D2N
LC1G4D1T
LC1G4D1N
174
CLC1POL
LC1POL
—
—
—
LC1G4POL
LC1G3POL
LC1G2POL
LC1G1POL
168
CLC1SEL0
—
LC1D2S<2:0>
—
LC1D1S<2:0>
169
CLC1SEL1
—
LC1D4S<2:0>
—
LC1D3S<2:0>
170
CLC2GLS0
LC2G1D4T
LC2G1D4N
LC2G1D3T
LC2G1D3N
LC2G1D2T
LC2G1D2N
LC2G1D1T
LC2G1D1N
171
CLC2GLS1
LC2G2D4T
LC2G2D4N
LC2G2D3T
LC2G2D3N
LC2G2D2T
LC2G2D2N
LC2G2D1T
LC2G2D1N
172
CLC2GLS2
LC2G3D4T
LC2G3D4N
LC2G3D3T
LC2G3D3N
LC2G3D2T
LC2G3D2N
LC2G3D1T
LC2G3D1N
173
CLC2GLS3
LC2G4D4T
LC2G4D4N
LC2G4D3T
LC2G4D3N
LC2G4D2T
LC2G4D2N
LC2G4D1T
LC2G4D1N
174
CLC2POL
LC2POL
—
—
—
LC2G4POL
LC2G3POL
LC2G2POL
LC2G1POL
CLC2SEL0
—
CLC2SEL1
LC2D2S<2:0>
—
—
LC2D4S<2:0>
LC2D1S<2:0>
—
168
169
LC2D3S<2:0>
170
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
PIE3
—
—
—
—
—
—
CLC2IE
CLC1IE
69
PIR3
—
—
—
—
—
—
CLC2IF
CLC1IF
72
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
102
INTCON
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
106
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
109
Legend:
Note 1:
— = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 176
PIC16(L)F1507
21.0
NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCOx) module
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the resolution of division does not
vary with the divider value. The NCOx is most useful for
applications that require frequency accuracy and fine
resolution at a fixed duty cycle.
Features of the NCOx include:
•
•
•
•
•
•
•
16-bit increment function
Fixed Duty Cycle (FDC) mode
Pulse Frequency (PF) mode
Output pulse width control
Multiple clock input sources
Output polarity control
Interrupt capability
Figure 21-1 is a simplified block diagram of the NCOx
module.
DS41586A-page 177
Preliminary
 2011 Microchip Technology Inc.
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM
Increment
16
(1)
Buffer
16
Interrupt event
Set NCOxIF flag
To CLC and
CWG modules

NCO1CLK
20
11
LC1OUT
FOSC
Preliminary
HFINTOSC
10
Accumulator
01
20
D
To NxOUT bit
Q
NxOE
Overflow
Q
NCOx Clock
NxEN
00
TRIS Control
0
NCOx
1
2
NxCKS<1:0>
Overflow
S
 2011 Microchip Technology Inc.
NCOx Clock
Ripple Counter
Note 1:
NxPFM
NxPOL
R
3
Q
Q
NxPWS<2:0>
Reset
The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx
module. They are shown here for reference. The buffers are not user-accessible.
PIC16(L)F1507
DS41586A-page 178
FIGURE 21-1:
PIC16(L)F1507
21.1
21.1.3
NCOx OPERATION
ADDER
The NCOx operates by repeatedly adding a fixed value
to an accumulator. Additions occur at the input clock
rate. The accumulator will overflow with a carry
periodically, which is the raw NCOx output. This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 21-1.
The NCOx Adder is a full adder, which operates
independently from the system clock. The addition of
the previous result and the increment value replaces
the accumulator value on the rising edge of each input
clock.
The NCOx output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCOx
output is then distributed internally to other peripherals
and optionally output to a pin. The accumulator overflow
also generates an interrupt.
The Increment value is stored in two 8-bit registers
making up a 16-bit increment. In order of LSB to MSB
they are:
The NCOx period changes in discrete steps to create an
average frequency. This output depends on the ability of
the receiving circuit (i.e., CWG or external resonant
converter circuitry) to average the NCOx output to
reduce uncertainty.
Both of the registers are readable and writeable. The
Increment registers are double-buffered to allow for
value changes to be made without first disabling the
NCOx module.
21.1.1
NCOx CLOCK SOURCES
Clock sources available to the NCOx include:
•
•
•
•
HFINTOSC
FOSC
LCxOUT
CLKIN pin
21.1.4
INCREMENT REGISTERS
• NCOxINCL
• NCOxINCH
The buffer loads are immediate when the module is disabled. Writing to the NCOxINCH register first is necessary because then the buffer is loaded synchronously
with the NCOx operation after the write is executed on
the NCOxINCL register.
Note: The increment buffer registers are not
user-accessible.
The NCOx clock source is selected by configuring the
NxCKS<2:0> bits in the NCOxCLK register.
21.1.2
ACCUMULATOR
The accumulator is a 20-bit register. Read and write
access to the Accumulator is available through three
registers:
• NCOxACCL
• NCOxACCH
• NCOxACCU
EQUATION 21-1:
NCO Clock Frequency  Increment Value
F OVERFLOW = --------------------------------------------------------------------------------------------------------------n
2
n = Accumulator width in bits
DS41586A-page 179
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
21.2
FIXED DUTY CYCLE (FDC) MODE
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows, the output is toggled. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure 21-2.
The FDC mode is selected by clearing the NxPFM bit
in the NCOxCON register.
21.3
PULSE FREQUENCY (PF) MODE
In Pulse Frequency (PF) mode, every time the accumulator overflows, the output becomes active for one or
more clock periods. Once the clock period expires, the
output returns to an inactive state. This provides a
pulsed output.
The output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see Figure 21-2.
The value of the active and inactive states depends on
the polarity bit, NxPOL in the NCOxCON register.
The PF mode is selected by setting the NxPFM bit in
the NCOxCON register.
21.3.1
OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various
pulse widths are selected with the NxPWS<2:0> bits in
the NCOxCLK register.
When the selected pulse width is greater than the
accumulator overflow time frame, the output of the
NCOx operation is indeterminate.
21.4
OUTPUT POLARITY CONTROL
The last stage in the NCOx module is the output polarity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition.
The NCOx output can be used internally by source
code or other peripherals. Accomplish this by reading
the NxOUT (read-only) bit of the NCOxCON register.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 180
FDC OUTPUT MODE OPERATION DIAGRAM
Clock Source
NCOx
Increment
Value
NCOx
Accumulator
Input
2000h
02000h
04000h
06000h
08000h
0A000h
0C000h
0E000h
10000h
02000h
04000h
06000h
08000h
0A000h
0C000h
0E000h
10000h
02000h
2000h
4000h
6000h
8000h
A000h
C000h
E000h
0000h
04000h
Tadder
Overflow is the
MSB of the accumulator
Accumulator Input Overflow
Preliminary
Tadder_
NCOx
Accumulator
Value
0000h
2000h
4000h
6000h
8000h
A000h
C000h
E000h
0000h
Tadder
Overflow
PWS = 000
Interrupt
Event
 2011 Microchip Technology Inc.
NCOx Output
FDC mode
NCOx Output PF mode
NCOX PWS = 000
NCOx Output PF mode
NCOx PWS = 010
Tadder
2000h
PIC16(L)F1507
DS41586A-page 181
FIGURE 21-2:
PIC16(L)F1507
21.5
Interrupts
When the accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIRx register is set. To enable
the interrupt event, the following bits must be set:
•
•
•
•
NxEN bit of the NCOxCON register
NCOxIE bit of the PIEx register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
21.6
Effects of a Reset
All of the NCOx registers are cleared to zero as the
result of a Reset.
21.7
Operation In Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains
active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
21.8
Alternate Pin Locations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 182
PIC16(L)F1507
21.9
NCOx Control Registers
REGISTER 21-1:
NCOxCON: NCOx CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
NxEN
NxOE
NxOUT
NxPOL
—
—
—
NxPFM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
NxEN: NCOx Enable bit
1 = NCOx module is enabled
0 = NCOx module is disabled
bit 6
NxOE: NCOx Output Enable bit
1 = NCOx output pin is enabled
0 = NCOx output pin is disabled
bit 5
NxOUT: NCOx Output bit
1 = NCOx output is high
0 = NCOx output is low
bit 4
NxPOL: NCOx Polarity bit
1 = NCOx output signal is active high
0 = NCOx output signal is active low
bit 3-1
Unimplemented: Read as ‘0’.
bit 0
NxPFM: NCOx Pulse Frequency Mode bit
1 = NCOx operates in Pulse Frequency mode
0 = NCOx operates in Fixed Duty Cycle mode
REGISTER 21-2:
R/W-0/0
NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
NxPWS<2:0>
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
NxCKS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2)
111 = 128 NCOx clock periods
110 = 64 NCOx clock periods
101 = 32 NCOx clock periods
100 = 16 NCOx clock periods
011 = 8 NCOx clock periods
010 = 4 NCOx clock periods
001 = 2 NCOx clock periods
000 = 1 NCOx clock periods
bit 4-2
Unimplemented: Read as ‘0’
bit 1-0
NxCKS<1:0>: NCOx Clock Source Select bits
11 = NCO1CLK
10 = LC1OUT
01 = FOSC
00 = HFINTOSC (16 MHz)
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undeterminate.
DS41586A-page 183
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 21-3:
R/W-0/0
NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxACC<7:0>: NCOx Accumulator, low byte
REGISTER 21-4:
R/W-0/0
NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxACC<15:8>: NCOx Accumulator, high byte
REGISTER 21-5:
NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC<19:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NCOxACC<19:16>: NCOx Accumulator, upper byte
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 184
PIC16(L)F1507
REGISTER 21-6:
R/W-0/0
NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCOxINC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxINC<7:0>: NCOx Increment, low byte
REGISTER 21-7:
R/W-0/0
NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxINC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxINC<15:8>: NCOx Increment, high byte
DS41586A-page 185
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 21-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH NCOx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON
—
—
—
—
—
—
CLC1SEL
NCO1SEL
100
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
NCO1ACCH
NCO1ACC<15:8>
184
NCO1ACCL
NCO1ACC<7:0>
184
—
NCO1ACCU
NCO1CLK
NCO1CON
NCO1ACC<19:16>
N1PWS<2:0>
N1EN
N1OE
N1OUT
NCO1INCH
—
—
—
N1POL
—
—
184
N1CKS<1:0>
—
N1PFM
NCO1INC<15:8>
NCO1INCL
183
183
185
NCO1INC<7:0>
185
PIE2
—
—
—
—
—
NCO1IE
—
—
PIR2
—
—
—
—
—
NCO1IF
—
—
71
TRISA
—
—
TRISA5
TRISA4
—(1)
TRISA2
TRISA1
TRISA0
102
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
109
TRISC
Legend:
Note 1:
68
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 186
PIC16(L)F1507
22.0
COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band
delay from a selection of input sources.
The CWG module has the following features:
•
•
•
•
•
Selectable dead-band clock source control
Selectable input sources
Output enable control
Output polarity control
Dead-band control with independent 6-bit rising
and falling edge dead-band counters
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
DS41586A-page 187
Preliminary
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
FIGURE 22-1:
CWG BLOCK DIAGRAM
GxASDLA
GxCS
00
1
FOSC
2
‘0’
10
‘1’
11
1
cwg_clock
GxASDLA = 01
GxOEA
CWGxDBR
HFINTOSC
6
1
GxIS
3
Preliminary
PWM1OUT
PWM2OUT
PWM3OUT
PWM4OUT
NCO1OUT
LC1OUT
EN
S
Q
R
Q
R
=
0
TRISx
GxPOLA
Input Source
CWGxA
CWGxDBF
6
EN
GxOEB
R
TRISx
=
0
GxPOLB
1
CWGxB
GxASDLB = 01
00
GxASDS1
GxASE
Auto-Shutdown
Source
LC2OUT
S
Q
R
Q
GxASDS0
DS41586A-page 188
GxASE Data Bit
WRITE
x = CWG module number
GxARSEN
set dominate
D
S
Q
shutdown
10
11
GxASDLB
2
PIC16(L)F1507
CWG1FLT (INT pin)
‘0’
‘1’
PIC16(L)F1507
FIGURE 22-2:
TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)
cwg_clock
PWM1
CWGxA
Rising Edge
Dead Band
Falling Edge Dead Band
Rising Edge Dead Band
Rising Edge D
Falling Edge Dead Band
CWGxB
DS41586A-page 189
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
22.1
22.4.2
Fundamental Operation
The CWG generates a two output complementary
waveform from one of four selectable input sources.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 22.5 “Dead-Band Control”. A typical
operating waveform, with dead band, generated from a
single input signal is shown in Figure 22-2.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in
Section 22.9 “Auto-shutdown Control”.
POLARITY CONTROL
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active high. Clearing the output
polarity bit configures the corresponding output as
active low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.
22.5
Dead-Band Control
Dead-band control provides for non-overlapping output
signals to prevent shoot through current in power
switches. The CWG contains two 6-bit dead-band
counters. One dead-band counter is used for the rising
edge of the input source control. The other is used for
the falling edge of the input source control.
The CWG module allows for up to 2 different clock
sources to be selected:
Dead band is timed by counting CWG clock periods
from zero up to the value in the rising or falling deadband counter registers. See CWGxDBR and
CWGxDBF registers (Register 22-4 and Register 22-5,
respectively).
• Fosc (system clock)
• HFINTOSC (16 MHz only)
22.6
22.2
Clock Source
The clock sources are selected using the G1CS0 bit of
the CWGxCON0 register (Register 22-1).
22.3
Selectable Input Sources
The CWG uses four different input sources to generate the complementary waveform:
•
•
•
•
•
•
PWM1
PWM2
PWM3
PWM4
N1OUT
LC1OUT
Output Control
Immediately after the CWG module is enabled, the
complementary drive is configured with both CWGxA
and CWGxB drives cleared.
22.4.1
The rising edge dead-band delays the turn-on of the
CWGxA output from when the CWGxB output is turned
off. The rising edge dead-band time starts when the
rising edge of the input source signal goes true. When
this happens, the CWGxB output is immediately turned
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
The CWGxDBR register sets the duration of the deadband interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
The input sources are selected using the GxIS<2:0>
bits in the CWGxCON1 register (Register 22-2).
22.4
Rising Edge Dead Band
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
OUTPUT ENABLES
Each CWG output pin has individual output enable
control. Output enables are selected with the GxOEA
and GxOEB bits of the CWGxCON0 register. When an
output enable control is cleared, the module asserts no
control over the pin. When an output enable is set, the
override value or active PWM waveform is applied to
the pin per the port priority selection. The output pin
enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
and CWG drive levels have no effect.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 190
PIC16(L)F1507
22.7
Falling Edge Dead Band
The falling edge dead band delays the turn-on of the
CWGxB output from when the CWGxA output is turned
off. The falling edge dead-band time starts when the
falling edge of the input source goes true. When this
happens, the CWGxA output is immediately turned off
and the falling edge dead-band delay time starts. When
the falling edge dead-band delay time is reached, the
CWGxB output is turned on.
The CWGxDBF register sets the duration of the deadband interval on the falling edge of the input source signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
Refer to Figure 22-3 and Figure 22-4 for examples.
22.8
Dead-Band Uncertainty
When the rising and falling edges of the input source
triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the deadband time delay. The maximum uncertainty is equal to
one CWG clock period. Refer to Equation 22-1 for more
detail.
DS41586A-page 191
Preliminary
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
FIGURE 22-3:
DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 22-4:
DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND
Preliminary
cwg_clock
Input Source
CWGxA
source shorter than dead band
CWGxB
PIC16(L)F1507
DS41586A-page 192
PIC16(L)F1507
EQUATION 22-1:
DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
Example:
Fcwg_clock = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
1
= ------------------16 MHz
= 625ns
DS41586A-page 193
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
22.9
Auto-shutdown Control
22.10 Operation During Sleep
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can be
either cleared automatically or held until cleared by
software.
22.9.1
SHUTDOWN
The shutdown state can be entered by either of the following two methods:
• Software generated
• External Input
22.9.1.1
Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will
force the CWG into the shutdown state.
When auto-restart is disabled, the shutdown state will
persist as long as the GxASE bit is set.
The CWG module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep, provided
that the CWG module is enabled, the input source is
active, and the HFINTOSC is selected as the clock
source, regardless of the system clock source
selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input
source is active, the CPU will go idle during Sleep, but
the CWG will continue to operate and the HFINTOSC
will remain active.
This will have a direct effect on the Sleep mode current.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
edge event. See Figure 22-6.
22.9.1.2
External Input Source
External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to
the selected override levels without software delay. Any
combination of two input sources can be selected to
cause a shutdown condition. The two sources are:
• LC2OUT
• CWG1FLT
Shutdown inputs are selected using the GxASDS0 and
GxASDS1 bits of the CWGxCON2 register.
(Register 22-3).
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input
level persists.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 194
PIC16(L)F1507
22.11 Configuring the CWG
22.11.1
The following steps illustrate how to properly configure
the CWG to ensure a synchronous start:
The levels driven to the output pins, while the shutdown
input is true, are controlled by the GxASDLA and
GxASDLB bits of the CWGxCON2 register
(Register 22-3). GxASDLA controls the CWG1A
override level and GxASDLB controls the CWG1B
override level. The control bit logic level corresponds to
the output logic drive level while in the shutdown state.
The polarity control does not apply to the override level.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Ensure that the TRIS control bits corresponding
to CWGxA and CWGxB are set so that both are
configured as inputs.
Clear the GxEN bit, if not already cleared.
Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
Setup the following controls in CWGxCON2
auto-shutdown register:
• Select desired shutdown source.
• Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
• Set the GxASE bit and clear the GxARSEN
bit.
Select the desired input source using the
CWGxCON1 register.
Configure the following controls in CWGxCON0
register:
• Select desired clock source.
• Select the desired output polarities.
• Set the output enables for the outputs to be
used.
Set the GxEN bit.
Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automatically. Otherwise, clear the GxASE bit to start the
CWG.
DS41586A-page 195
22.11.2
PIN OVERRIDE LEVELS
AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to have resume operation:
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 22-5 and Figure 22-6.
22.11.2.1
Software controlled restart
When the GxARSEN bit of the CWGxCON2 register is
cleared, the CWG must be restarted after an auto-shutdown event by software.
Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the GxASE bit will
remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
The CWG will then resume operation.
22.11.2.2
Auto-Restart
When the GxARSEN bit of the CWGxCON2 register is
set, the CWG will restart from the auto-shutdown state
automatically.
The GxASE bit will clear automatically when all shutdown sources go low. The overrides will remain in
effect until the first rising edge event after the GxASE
bit is cleared. The CWG will then resume operation.
Preliminary
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
FIGURE 22-5:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)
Shutdown Event Ceases
GxASE Cleared by Software
CWG Input
Source
Shutdown Source
GxASE
CWG1A
Tri-State (No Pulse)
CWG1B
Tri-State (No Pulse)
No Shutdown
Preliminary
Output Resumes
Shutdown
FIGURE 22-6:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)
Shutdown Event Ceases
GxASE auto-cleared by hardware
CWG Input
Source
GxASE
DS41586A-page 196
CWG1A
Tri-State (No Pulse)
CWG1B
Tri-State (No Pulse)
No Shutdown
Shutdown
Output Resumes
PIC16(L)F1507
Shutdown Source
PIC16(L)F1507
22.12
CWG Control Registers
REGISTER 22-1:
CWGxCON0: CWG CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
GxEN
GxOEB
GxOEA
GxPOLB
GxPOLA
—
—
GxCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
GxEN: CWGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
GxOEB: CWGxB Output Enable bit
1 = CWGxB is available on appropriate I/O pin
0 = CWGxB is not available on appropriate I/O pin
bit 5
GxOEA: CWGxA Output Enable bit
1 = CWGxA is available on appropriate I/O pin
0 = CWGxA is not available on appropriate I/O pin
bit 4
GxPOLB: CWGxB Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3
GxPOLA: CWGxA Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2-1
Unimplemented: Read as ‘0’
bit 0
GxCS0: CWGx Clock Source bit
1 = HFINTOSC
0 = FOSC
DS41586A-page 197
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 22-2:
R/W-x/u
CWGxCON1: CWG CONTROL REGISTER 1
R/W-x/u
GxASDLB<1:0>
R/W-x/u
R/W-x/u
GxASDLA<1:0>
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
GxIS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
GxASDLB<1:0>: CWGx Shutdown State for CWGxB
When an auto shutdown event is present (GxASE = 1):
11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.
10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.
01 = CWGxB pin is tri-stated
00 = CWGxB pin is driven to it’s inactive state after the selected dead-band interval. GxPOLB still will
control the polarity of the output.
bit 5-4
GxASDLA<1:0>: CWGx Shutdown State for CWGxA
When an auto shutdown event is present (GxASE = 1):
11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.
10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.
01 = CWGxA pin is tri-stated
00 = CWGxA pin is driven to it’s inactive state after the selected dead-band interval. GxPOLA still will
control the polarity of the output.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
GxIS<2:0>: CWGx Dead-Band Source Select bits
111 = LC1OUT
110 = N1OUT
101 = PWM4OUT
100 = PWM3OUT
011 = PWM2OUT
010 = PWM1OUT
001 = Reserved
000 = Reserved
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 198
PIC16(L)F1507
REGISTER 22-3:
CWGxCON2: CWG CONTROL REGISTER 2
R/W-0/0
R/W-0/0
GxASE
GxARSEN
U-0
—
U-0
—
U-0
—
U-0
R/W-0/0
R/W-0/0
—
GxASDFLT
GxASDCLC2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
GxASE: Auto-Shutdown Event Status bit
1 = An auto-shutdown event has occurred
0 = No auto-shutdown event has occurred
bit 6
GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-2
Unimplemented: Read as ‘0’
bit 1
GxASDFLT: CWG Auto-shutdown on FLT Enable bit
1 = Shutdown when CWG1FLT in put is low
0 = CWG1FLT input has no effect on shutdown
bit 0
GxASDCLC2: CWG Auto-shutdown on CLC2 Enable bit
1 = Shutdown when LC2OUT is high
0 = LC2OUT has no effect on shutdown
DS41586A-page 199
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
REGISTER 22-4:
U-0
CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING
DEAD-BAND COUNT REGISTER
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBR<5:0>
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising counts
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band



00 0010 = 2-3 counts of dead band
00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band
REGISTER 22-5:
CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING
DEAD-BAND COUNT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling counts
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band



00 0010 = 2-3 counts of dead band
00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band. Dead-band generation is bypassed.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 200
PIC16(L)F1507
TABLE 22-1:
Name
ANSELA
CWG1CON0
CWG1CON1
CWG1CON2
CWG1DBF
SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
ANSA4
—
ANSA2
ANSA1
ANSA0
103
G1EN
G1OEB
G1OEA
G1POLB
—
G1CS0
G1ASDLB<1:0>
G1POLA
—
G1ASDLA<1:0>
—
—
—
—
—
197
198
G1ASE
G1ARSEN
—
—
CWG1DBF<5:0>
200
CWG1DBR<5:0>
200
—
CWG1DBR
—
—
TRISA
—
—
TRISA5
TRISA4
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
Legend:
Note 1:
G1IS<1:0>
—
(1)
TRISC3
G1ASDS1
G1ASDS0
199
TRISA2
TRISA1
TRISA0
102
TRISC2
TRISC1
TRISC0
109
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
Unimplemented, read as ‘1’.
DS41586A-page 201
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 202
PIC16(L)F1507
23.0
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the Program Memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573).
23.1
High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
Some programmers produce VPP greater than VIHH
(9.0V), an external circuit is required to limit the VPP
voltage. See Figure 23-1 for example circuit.
FIGURE 23-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN
6
5
4
3
2
1
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
5
ICSP_CLOCK
6
NC
RJ11-6PIN
®
To MPLAB ICD 2
R1
To Target Board
270 Ohm
LM431BCMX
1
2 A
K
3 A U1
6 A
NC 4
7 A
NC 5
R2
VREF
8
10k 1%
Note:
R3
24k 1%
The MPLAB® ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16(L)F1507.
DS41586A-page 203
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
23.2
FIGURE 23-2:
Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC16(L)F1507 devices to be programmed using VDD
only, without high voltage. When the LVP bit of
Configuration Words is set to ‘1’, the low-voltage ICSP
programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
VDD
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1.
2.
ICD RJ-11 STYLE
CONNECTOR INTERFACE
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
VPP/MCLR
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
VSS
Pin Description*
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
1 = VPP/MCLR
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.4 “MCLR” for more
information.
4 = ICSPDAT
2 = VDD Target
3 = VSS (ground)
5 = ICSPCLK
6 = No Connect
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
23.3
Target
PC Board
Bottom Side
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 23-3.
Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6 pin, 6
connector) configuration. See Figure 23-2.
FIGURE 23-3:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1
2
3
4
5
6
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 204
PIC16(L)F1507
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 23-4 for more
information.
FIGURE 23-4:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
DS41586A-page 205
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 206
PIC16(L)F1507
24.0
INSTRUCTION SET SUMMARY
24.1
Read-Modify-Write Operations
• Byte Oriented
• Bit Oriented
• Literal and Control
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
The literal and control category contains the most varied instruction word format.
TABLE 24-1:
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The op codes are broken into three broad categories.
Table 24-3 lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
TABLE 24-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-out bit
C
DC
Z
PD
DS41586A-page 207
Description
PC
Preliminary
Carry bit
Digit carry bit
Zero bit
Power-down bit
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 24-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
OPCODE
8
7
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLP instruction only
13
OPCODE
7
6
0
k (literal)
k = 7-bit immediate value
MOVLB instruction only
13
OPCODE
5 4
0
k (literal)
k = 5-bit immediate value
BRA instruction only
13
OPCODE
9
8
0
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
OPCODE
7
6
n
5
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
3
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 208
PIC16(L)F1507
TABLE 24-3:
PIC16(L)F1507 ENHANCED INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff
1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
1, 2
1, 2
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
DS41586A-page 209
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 24-3:
PIC16(L)F1507 ENHANCED INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
2
2
2
2
2
2
2
2
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
1
1
11
00
1
1
11
00
0001 0nkk kkkk
0000 0001 0nmm Z
kkkk
1111 0nkk 1nmm Z
0000 0001 kkkk
1
11
1111 1nkk
2, 3
2
2, 3
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 210
PIC16(L)F1507
24.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32  k  31
n  [ 0, 1]
Operands:
0  k  255
Operation:
FSR(n) + k  FSR(n)
Status Affected:
None
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
k
Operation:
(W) .AND. (k)  (W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ADDLW
Add literal and W
ANDWF
AND W with f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0  f  127
d 0,1
Operation:
(W) .AND. (f)  (destination)
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
k
Operands:
0  k  255
Operation:
(W) + k  (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ADDWF
Add W and f
f,d
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0  f  127
d 0,1
Operands:
0  f  127
d [0,1]
Operation:
(W) + (f)  (destination)
Operation:
(f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
f,d
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0  f  127
d [0,1]
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
register f
C
f {,d}
Operation:
(W) + (f) + (C)  dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
DS41586A-page 211
f {,d}
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
BCF
Bit Clear f
Syntax:
[ label ] BCF
f,b
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0  f  127
0b7
Operands:
0  f  127
0b7
Operands:
Operation:
0  (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
Operands:
-256  label - PC + 1  255
-256  k  255
0  f  127
0b<7
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruction. This branch has a limited range.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W)  PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to
the PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0  f  127
0b7
Operation:
1  (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
 2011 Microchip Technology Inc.
f,b
Preliminary
DS41586A-page 212
PIC16(L)F1507
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0  k  2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k  PC<10:0>,
(PCLATH<4:3>)  PC<12:11>
Operation:
Status Affected:
None
00h  WDT
0  WDT prescaler,
1  TO
1  PD
Description:
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
Subroutine Call With W
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1  TOS,
(W)  PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0  f  127
d  [0,1]
Operation:
(f)  (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Status Affected:
None
Description:
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
f
f,d
Operands:
0  f  127
Operands:
Operation:
00h  (f)
1Z
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are cleared
and the Z bit is set.
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h  (W)
1Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
DS41586A-page 213
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination);
skip if result = 0
Operation:
(f) + 1  (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0  k  2047
Operands:
0  k  255
Operation:
k  PC<10:0>
PCLATH<4:3>  PC<12:11>
Operation:
(W) .OR. k  (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) + 1  (destination)
Operation:
(W) .OR. (f)  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Description:
Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
INCF f,d
 2011 Microchip Technology Inc.
Preliminary
IORWF
f,d
DS41586A-page 214
PIC16(L)F1507
LSLF
Logical Left Shift
f {,d}
MOVF
Move f
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0  f  127
d [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f<7>)  C
(f<6:0>)  dest<7:1>
0  dest<0>
Operation:
(f)  (dest)
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
C
register f
0
Status Affected:
Z
Description:
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Words:
1
Cycles:
1
Example:
Logical Right Shift
Syntax:
[ label ] LSLF
Operands:
0  f  127
d [0,1]
Operation:
0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
DS41586A-page 215
f {,d}
register f
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
0
MOVF f,d
C
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
MOVIW
Move INDFn to W
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn]
Operands:
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Operation:
INDFn  W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
Status Affected:
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVLP k
Operands:
0  k  127
Operation:
k  PCLATH
Status Affected:
None
Description:
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
MOVLW
Move literal to W
Syntax:
[ label ]
Operands:
0  k  255
Operation:
k  (W)
Status Affected:
None
Description:
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assemble as ‘0’s.
Words:
1
1
Z
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Syntax:
[ label ] MOVLB k
Operands:
0  k  15
Operation:
k  BSR
Status Affected:
None
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
 2011 Microchip Technology Inc.
0x5A
MOVWF
Move W to f
Syntax:
[ label ]
0x5A
MOVWF
Operands:
0  f  127
Operation:
(W)  (f)
f
Status Affected:
None
Description:
Move data from W register to register
‘f’.
Words:
1
Cycles:
1
Example:
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
Move literal to BSR
MOVLW
After Instruction
W =
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
MOVLB
MOVLW k
Preliminary
MOVWF
OPTION_REG
Before Instruction
OPTION_REG =
W
=
After Instruction
OPTION_REG =
W
=
0xFF
0x4F
0x4F
0x4F
DS41586A-page 216
PIC16(L)F1507
MOVWI
Move W to INDFn
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
W  INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
None
Mode
Syntax
mm
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
Words:
1
Cycles:
1
Example:
NOP
NOP
OPTION
Load OPTION_REG Register
with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)  OPTION_REG
Status Affected:
None
Description:
Move data from W register to
OPTION_REG register.
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to
execute a hardware Reset by software.
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
DS41586A-page 217
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
RETFIE
Return from Interrupt
Syntax:
[ label ]
RETURN
RETFIE
Return from Subroutine
Syntax:
[ label ]
None
RETURN
Operands:
None
Operands:
Operation:
TOS  PC,
1  GIE
Operation:
TOS  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Words:
1
Cycles:
2
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
Return with literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  k  255
Operands:
Operation:
k  (W);
TOS  PC
0  f  127
d  [ 0, 1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
Cycles:
2
RETLW
Example:
TABLE
RETLW k
RLF
f,d
C
CALL TABLE;W contains table
;offset value
•
;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W =
After Instruction
W =
 2011 Microchip Technology Inc.
Words:
1
Cycles:
1
Example:
RLF
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
Preliminary
DS41586A-page 218
PIC16(L)F1507
SUBLW
Subtract W from literal
Syntax:
[ label ]
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
See description below
Status Affected:
C, DC, Z
Status Affected:
C
Description:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
The W register is subtracted (2’s complement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
RRF f,d
C
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0>  k<3:0>
DC = 1
W<3:0>  k<3:0>
SLEEP
Enter Sleep mode
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d  [0,1]
Operation:
(f) - (W) destination)
Status Affected:
C, DC, Z
Description:
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
SLEEP
Operands:
None
Operation:
00h  WDT,
0  WDT prescaler,
1  TO,
0  PD
Status Affected:
TO, PD
Description:
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
DS41586A-page 219
SUBWF f,d
C=0
Wf
C=1
Wf
DC = 0
W<3:0>  f<3:0>
DC = 1
W<3:0>  f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
0  f  127
d  [0,1]
Operation:
(f) – (W) – (B) dest
f {,d}
Status Affected:
C, DC, Z
Description:
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
SWAPF f,d
(f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
XORLW k
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Z
Description:
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
None
Description:
The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS
Load TRIS Register with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
5f7
Operands:
Operation:
(W)  TRIS register ‘f’
0  f  127
d  [0,1]
Status Affected:
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Z
Description:
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
Description:
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
 2011 Microchip Technology Inc.
Preliminary
XORWF
f,d
DS41586A-page 220
PIC16(L)F1507
25.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias ....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F1507 ............................................................................. -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC16LF1507 ........................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ............................................................................ -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 396 mA
Maximum current out of VSS pin, -40°C  TA  +125°C for extended ............................................................ 114 mA
Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 292 mA
Maximum current into VDD pin, -40°C  TA  +125°C for extended ............................................................... 107 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin............................................................................................... 25 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS41586A-page 221
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
PIC16F1507 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
FIGURE 25-1:
VDD (V)
5.5
2.5
2.3
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
PIC16LF1507 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
VDD (V)
FIGURE 25-2:
3.6
2.5
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 222
PIC16(L)F1507
25.1
DC Characteristics: PIC16(L)F1507-I/E (Industrial, Extended)
PIC16LF1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param.
No.
D001
Sym.
VDD
D001
D002*
VDR
D002*
Characteristic
Min.
Typ†
Max.
Units
Conditions
PIC16LF1507
1.8
2.5
—
—
3.6
3.6
V
V
FOSC  16 MHz:
FOSC  20 MHz
PIC16F1507
2.3
2.5
—
—
5.5
5.5
V
V
FOSC  16 MHz:
FOSC  20 MHz
Supply Voltage
RAM Data Retention Voltage(1)
PIC16LF1507
1.5
—
—
V
Device in Sleep mode
PIC16F1507
1.7
—
—
V
Device in Sleep mode
—
1.6
—
V
VPOR*
Power-on Reset Release Voltage
VPORR*
Power-on Reset Rearm Voltage
PIC16LF1507
—
0.8
—
V
Device in Sleep mode
PIC16F1507
—
1.7
—
V
Device in Sleep mode
Fixed Voltage Reference Voltage for
ADC, Initial Accuracy
—
—
—
—
—
—
1
1
1
1
1
1
—
—
—
—
—
—
%
1.024V, VDD  2.5V, 85°C (NOTE 2)
1.024V, VDD  2.5V, 125°C (NOTE 2)
2.048V, VDD  2.5V, 85°C
2.048V, VDD  2.5V, 125°C
4.096V, VDD  4.75V, 85°C
4.096V, VDD  4.75V, 125°C
D003C* TCVFVR
Temperature Coefficient, Fixed
Voltage Reference
—
-130
—
ppm/°C
D003D* VFVR/
VIN
Line Regulation, Fixed Voltage
Reference
—
0.270
—
%/V
D004*
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms
D003
VADFVR
SVDD
See Section 6.1 “Power-on Reset
(POR)” for details.
*
†
Note
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting
the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or
greater.
DS41586A-page 223
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 25-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 224
PIC16(L)F1507
25.2
DC Characteristics: PIC16(L)F1507-I/E (Industrial, Extended)
PIC16LF1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
Note
VDD
Supply Current (IDD)(1, 2)
D013
D013
D014
D014
D015
D015
D017*
D017*
D018
D018
—
40
—
A
1.8
—
70
—
A
3.0
—
60
—
A
2.3
—
80
—
A
3.0
—
93
—
A
5.0
—
260
—
A
2.3
—
550
—
A
3.0
—
375
—
A
2.3
—
600
—
A
3.0
—
650
—
A
5.0
—
3.6
—
A
1.8
—
7.0
—
A
3.0
—
21
—
A
2.3
—
27
—
A
3.0
—
28
—
A
5.0
—
0.8
—
mA
1.8
—
1.3
—
mA
3.0
—
1.0
—
mA
2.3
—
1.5
—
mA
3.0
—
1.7
—
mA
5.0
—
1.2
—
mA
1.8
—
2.5
—
mA
3.0
—
1.7
—
mA
2.3
—
2.7
—
mA
3.0
FOSC = 1 MHz
EC Oscillator mode, Medium-power mode
FOSC = 1 MHz
EC Oscillator mode
Medium-power mode
FOSC = 4 MHz
EC Oscillator mode,
Medium-power mode
FOSC = 4 MHz
EC Oscillator mode
Medium-power mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
—
3.0
—
mA
5.0
D019A
—
1.15
—
mA
3.0
FOSC = 20 MHz
ECH mode
D019A
—
1.15
—
mA
3.0
—
1.3
—
mA
5.0
FOSC = 20 MHz
ECH mode
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
DS41586A-page 225
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
25.2
DC Characteristics: PIC16(L)F1507-I/E (Industrial, Extended) (Continued)
PIC16LF1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
VDD
—
8
—
A
1.8
—
10
—
A
3.0
D019B
—
10
—
A
3.0
—
11
—
A
5.0
D019C
—
25
—
A
1.8
—
35
—
A
3.0
—
35
—
A
3.0
—
40
—
A
5.0
D019B
D019C
Note
FOSC = 32 kHz
ECL mode
FOSC = 32 kHz
ECL mode
FOSC = 500 kHz
ECM mode
FOSC = 500 kHz
ECM mode
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 226
PIC16(L)F1507
25.3
DC Characteristics: PIC16(L)F1507-I/E (Power-Down)
PIC16LF1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1507
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device Characteristics
Power-down Base Current
Min.
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
VDD
Note
(IPD)(2)
—
0.02
—
—
A
—
0.03
—
—
A
3.0
—
300
—
—
nA
3.0
—
470
—
—
nA
5.0
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
—
0.5
—
—
A
1.8
LPWDT Current (Note 1)
—
0.8
—
—
A
3.0
—
500
—
—
nA
2.3
—
770
—
—
nA
3.0
—
850
—
—
nA
5.0
—
8.5
—
—
A
1.8
—
8.5
—
—
A
3.0
—
18
—
—
A
2.3
—
18.5
—
—
A
3.0
—
19
—
—
mA
5.0
D024
—
8.1
—
—
A
3.0
BOR Current (Note 1)
D024
—
7
—
—
A
3.0
BOR Current (Note 1)
—
9
—
—
A
5.0
D24A
—
300
—
—
nA
3.0
LPBOR Current
D026
—
0.1
—
—
A
1.8
—
0.1
—
—
A
3.0
A/D Current (Note 1, Note 3), no
conversion in progress
—
160
—
—
nA
2.3
—
400
—
—
nA
3.0
—
500
—
—
nA
5.0
—
250
—
—
A
1.8
—
250
—
—
A
3.0
—
280
—
—
A
2.3
—
280
—
—
A
3.0
—
280
—
—
A
5.0
D022
D022
D023
D023
D023A
D023A
D026
D026A*
D026A*
*
†
Note 1:
2:
3:
1.8
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
LPWDT Current (Note 1)
FVR current (Note 1)
FVR current (Note 1)
A/D Current (Note 1, Note 3), no
conversion in progress
A/D Current (Note 1, Note 3),
conversion in progress
A/D Current (Note 1, Note 3),
conversion in progress
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
A/D oscillator source is FRC.
DS41586A-page 227
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
25.4
DC Characteristics: PIC16(L)F1507-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Min.
Typ†
Max.
Units
—
—
Conditions
—
0.8
V
4.5V  VDD  5.5V
—
0.15 VDD
V
1.8V  VDD  4.5V
—
—
0.2 VDD
V
2.0V  VDD  5.5V
—
—
0.2 VDD
V
—
—
Input Low Voltage
I/O PORT:
D030
with TTL buffer
D030A
D031
with Schmitt Trigger buffer
D032
MCLR
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
D042
MCLR
IIL
2.0
—
—
V
4.5V  VDD 5.5V
0.25 VDD +
0.8
—
—
V
1.8V  VDD  4.5V
2.0V  VDD  5.5V
0.8 VDD
—
—
V
0.8 VDD
—
—
V
nA
Input Leakage Current(1)
D060
I/O ports
—
±5
± 125
±5
± 1000
nA
VSS  VPIN  VDD, Pin at highimpedance at 85°C
125°C
D061
MCLR(2)
—
± 50
± 200
nA
VSS  VPIN  VDD at 85°C
25
25
100
140
200
300
A
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
—
—
0.6
V
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VDD - 0.7
—
—
V
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
—
50
pF
IPUR
Weak Pull-up Current
D070*
VOL
D080
Output Low Voltage(3)
I/O ports
VOH
D090
Output High Voltage(3)
I/O ports
Capacitive Loading Specs on Output Pins
D101A* CIO
All I/O pins
—
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Including OSC2 in CLKOUT mode.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 228
PIC16(L)F1507
25.5
Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
Voltage on MCLR/VPP pin
8.0
—
9.0
V
D111
IDDP
Supply Current during
Programming
—
—
10
mA
D112
VDD for Bulk Erase
(Note 2, Note 3)
2.7
—
VDD max.
V
D113
VPEW
VDD for Write or Row Erase
VDD min.
—
VDD max.
V
D114
IPPPGM Current on MCLR/VPP during Erase/
Write
—
—
1.0
mA
D115
IDDPGM Current on VDD during Erase/Write
—
5.0
mA
D121
EP
Cell Endurance
E/W
Program Flash Memory
D122
VPR
VDD for Read
D123
TIW
Self-timed Write Cycle Time
D124
TRETD Characteristic Retention
10K
—
—
VDD min.
—
VDD max.
V
—
2
2.5
ms
40
—
—
Year
-40C to +85C (Note 1)
Provided no other
specifications are violated
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
3: The MPLAB® ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage
must be placed between the MPLAB ICD 2 and target system when programming or debugging with the
MPLAB ICD 2.
DS41586A-page 229
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
25.6
Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
TH01
TH02
Sym.
Characteristic
Typ.
Units
JA
Thermal Resistance Junction to Ambient
TBD
C/W
20-pin PDIP package
TBD
C/W
20-pin SOIC package
89.3
C/W
20-pin SSOP package
TBD
C/W
20-pin QFN 4X4mm package
TBD
C/W
20-pin PDIP package
TBD
C/W
20-pin SOIC package
JC
TH03
TJMAX
TH04
PD
TH05
Thermal Resistance Junction to Case
Maximum Junction Temperature
Power Dissipation
PINTERNAL Internal Power Dissipation
Conditions
31.1
C/W
20-pin SSOP package
TBD
C/W
20-pin QFN 4X4mm package
150
C
—
W
PD = PINTERNAL + PI/O
—
W
PINTERNAL = IDD x VDD(1)
TH06
PI/O
I/O Power Dissipation
—
W
PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07
PDER
Derated Power
—
W
PDER = PDMAX (TJ - TA)/JA(2)
Legend:
TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 230
PIC16(L)F1507
25.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDIx
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 25-4:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
CLKIN
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins
DS41586A-page 231
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
25.8
AC Characteristics: PIC16(L)F1507-I/E
FIGURE 25-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note
1:
See Table 25-3.
TABLE 25-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
OS01
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Min.
Typ†
Max.
Units
Conditions
DC
—
0.5
MHz
EC Oscillator mode (low)
DC
—
4
MHz
EC Oscillator mode (medium)
EC Oscillator mode (high)
DC
—
20
MHz
OS02
TOSC
External CLKIN Period(1)
31.25
—

ns
EC mode
OS03
TCY
Instruction Cycle Time(1)
125
—
DC
ns
TCY = FOSC/4
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 25-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
No.
Sym.
Characteristic
Freq.
Tolerance
Min.
Typ†
Max.
Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency(1)
10%
—
16.0
—
MHz
0°C  TA  +85°C
OS09
LFOSC
Internal LFINTOSC Frequency
—
—
31
—
kHz
-40°C  TA  +125°C
OS10*
TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
—
—
5
8
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 232
PIC16(L)F1507
FIGURE 25-6:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 25-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
FOSC to CLKOUT (1)
OS11
TosH2ckL
OS12
TosH2ckH FOSC to CLKOUT
(1)
(1)
OS13
TckL2ioV
CLKOUT to Port out valid
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18* TioR
Port input valid before CLKOUT(1)
Fosc (Q1 cycle) to Port out valid
Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
Port output rise time(2)
OS19* TioF
Port output fall time(2)
Min.
Typ†
Max.
Units
Conditions
—
—
70
ns
VDD = 3.3-5.0V
—
—
72
ns
VDD = 3.3-5.0V
—
—
20
ns
TOSC + 200 ns
—
50
—
50
—
—
70*
—
ns
ns
ns
20
—
—
ns
—
—
—
—
25
25
15
40
28
15
—
—
32
72
55
30
—
—
ns
OS20* Tinp
OS21* Tioc
INT pin input high or low time
Interrupt-on-change new input level
time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.
DS41586A-page 233
Preliminary
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 2.0V
VDD = 5.0V
VDD = 2.0V
VDD = 5.0V
ns
ns
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 25-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 25-8:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 234
PIC16(L)F1507
TABLE 25-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
2
5
—
—
—
—
s
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
10
16
27
ms
VDD = 3.3V-5V,
1:16 Prescaler used
30
TMCL
MCLR Pulse Width (low)
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.0
s
35
VBOR
Brown-out Reset Voltage
2.50
2.30
1.8
2.70
2.40
1.90
2.80
2.50
2.00
V
V
V
36*
VHYST
Brown-out Reset Hysteresis
0
25
50
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
1
3
5
s
VDD  VBOR
BORV = 2.7V
BORV = 2.4V (PIC16F1507)
BORV = 1.9V (PIC16LF1507)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 25-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
DS41586A-page 235
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
TABLE 25-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
40*
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
T0CKI Low Pulse Width
No Prescaler
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous,
with Prescaler
—
—
ns
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
46*
TT1L
T1CKI Low
Time
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ†
30
—
—
ns
Synchronous, No Prescaler
0.5 TCY + 20
—
—
ns
Synchronous, with Prescaler
15
—
—
ns
Asynchronous
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
47*
TT1P
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
T1CKI Input Synchronous
Period
Asynchronous
60
—
—
ns
2 TOSC
—
7 TOSC
—
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting
the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V
or greater.
TABLE 25-6:
PIC16(L)F1507 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
AD01
NR
Resolution
—
—
10
AD02
EIL
Integral Error
—
—
±1.7
AD03
EDL
Differential Error
—
—
±1
AD04
EOFF Offset Error
—
—
±2.5
LSb VREF = 5.0V
AD05
EGN
—
—
±2.0
LSb VREF = 5.0V
AD06
VREF Reference Voltage(3)
1.8
—
VDD
V
AD07
VAIN
Full-Scale Range
VSS
—
VREF
V
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
—
—
10
k
*
†
Note 1:
2:
3:
4:
5:
Gain Error
bit
LSb VREF = 5.0V
LSb No missing codes
VREF = 5.0V
VREF = (VREF+ minus VREF-) (NOTE 5)
Can go higher if external 0.01F capacitor is
present on input pin.
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Total Absolute Error includes integral, differential, offset and gain errors.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input.
When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
FVR voltage selected must be 2.048V or 4.096V.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 236
PIC16(L)F1507
TABLE 25-7:
PIC16(L)F1507 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym.
Characteristic
AD130* TAD
AD131
TCNV
AD132* TACQ
Min.
Typ†
Max.
Units
Conditions
A/D Clock Period
1.0
—
9.0
s
TOSC-based
A/D Internal FRC Oscillator
Period
1.0
1.6
6.0
s
ADCS<1:0> = 11 (ADFRC mode)
Conversion Time (not including
Acquisition Time)(1)
—
11
—
TAD
Set GO/DONE bit to conversion
complete
Acquisition Time
—
5.0
—
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
FIGURE 25-10:
PIC16(L)F1507 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
9
A/D Data
8
7
6
3
OLD_DATA
ADRES
1
0
NEW_DATA
1 TCY
ADIF
GO
Sample
2
DONE
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS41586A-page 237
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
FIGURE 25-11:
PIC16(L)F1507 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
9
A/D Data
8
7
6
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 238
PIC16(L)F1507
26.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
DS41586A-page 239
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 240
PIC16(L)F1507
27.0
DEVELOPMENT SUPPORT
27.1
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
DS41586A-page 241
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
27.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3
HI-TECH C for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
27.4
27.5
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 242
PIC16(L)F1507
27.7
MPLAB SIM Software Simulator
27.9
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
27.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
DS41586A-page 243
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
27.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
27.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
 2011 Microchip Technology Inc.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Preliminary
DS41586A-page 244
PIC16(L)F1507
28.0
PACKAGING INFORMATION
28.1
Package Marking Information
20-Lead PDIP (300 mil)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F1507
-I/P e3
1120123
20-Lead SOIC (7.50 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F1507
-I/SO e3
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
1120123
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS41586A-page 245
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
28.2
Package Marking Information
20-Lead SSOP (5.30 mm)
Example
PIC16F1507
-I/SS e3
1120123
20-Lead QFN (4x4x0.9 mm)
Example
PIN 1
PIN 1
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
PIC16
F1507
I/ML e3
120123
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 246
PIC16(L)F1507
28.3
Package Details
The following sections give the technical details of the packages.
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DS41586A-page 247
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 248
PIC16(L)F1507
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41586A-page 249
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 250
PIC16(L)F1507
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DS41586A-page 251
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 252
PIC16(L)F1507
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DS41586A-page 253
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
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 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 254
PIC16(L)F1507
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
Original release (06/2011).
DS41586A-page 255
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 256
PIC16(L)F1507
INDEX
A
A/D
Specifications .................................................... 236, 237
Absolute Maximum Ratings .............................................. 221
AC Characteristics
Industrial and Extended ............................................ 232
Load Conditions ........................................................ 231
ADC................................................................................... 121
Acquisition Requirements ......................................... 132
Associated registers.................................................. 134
Block Diagram........................................................... 121
Calculating Acquisition Time ..................................... 132
Channel Selection ..................................................... 122
Configuration............................................................. 122
Configuring Interrupt ................................................. 126
Conversion Clock ...................................................... 122
Conversion Procedure .............................................. 126
Internal Sampling Switch (RSS) Impedance .............. 132
Interrupts ................................................................... 124
Operation .................................................................. 125
Operation During Sleep ............................................ 125
Port Configuration ..................................................... 122
Reference Voltage (VREF)......................................... 122
Source Impedance .................................................... 132
Starting an A/D Conversion ...................................... 124
ADCON0 Register....................................................... 25, 127
ADCON1 Register....................................................... 25, 128
ADCON2 Register............................................................. 129
ADDFSR ........................................................................... 211
ADDWFC .......................................................................... 211
ADRESH Register............................................................... 25
ADRESH Register (ADFM = 0) ......................................... 130
ADRESH Register (ADFM = 1) ......................................... 131
ADRESL Register (ADFM = 0).......................................... 130
ADRESL Register (ADFM = 1).......................................... 131
Alternate Pin Function....................................................... 100
Analog-to-Digital Converter. See ADC
ANSELA Register.............................................................. 103
ANSELB Register.............................................................. 107
ANSELC Register ............................................................. 110
APFCON Register............................................................. 100
Assembler
MPASM Assembler ................................................... 242
Automatic Context Saving................................................... 65
B
Bank 10 ............................................................................... 27
Bank 11 ............................................................................... 27
Bank 12 ............................................................................... 28
Bank 13 ............................................................................... 28
Bank 2 ................................................................................. 26
Bank 3 ................................................................................. 26
Bank 30 ............................................................................... 29
Bank 4 ................................................................................. 26
Bank 5 ................................................................................. 26
Bank 6 ................................................................................. 26
Bank 7 ................................................................................. 27
Bank 8 ................................................................................. 27
Bank 9 ................................................................................. 27
Block Diagrams
ADC .......................................................................... 121
ADC Transfer Function ............................................. 133
Analog Input Model ................................................... 133
DS41586A-page 257
Clock Source .............................................................. 45
Generic I/O Port.......................................................... 99
Interrupt Logic............................................................. 61
NCO.......................................................................... 178
On-Chip Reset Circuit................................................. 53
PIC16(L)F1507 ....................................................... 4, 10
PWM ......................................................................... 155
Timer0 ...................................................................... 135
Timer1 ...................................................................... 139
Timer1 Gate.............................................. 144, 145, 146
Timer2 ...................................................................... 151
Voltage Reference .................................................... 117
BORCON Register.............................................................. 55
BRA .................................................................................. 212
Brown-out Reset (BOR)...................................................... 55
Specifications ........................................................... 235
Timing and Characteristics ....................................... 234
C
C Compilers
MPLAB C18 .............................................................. 242
CALL................................................................................. 213
CALLW ............................................................................. 213
CLCDATA Register........................................................... 175
CLCxCON Register .......................................................... 167
CLCxGLS0 Register ......................................................... 171
CLCxGLS1 Register ......................................................... 172
CLCxGLS2 Register ......................................................... 173
CLCxGLS3 Register ......................................................... 174
CLCxPOL Register ........................................................... 168
CLCxSEL0 Register.......................................................... 169
Clock Sources
External Modes........................................................... 46
EC....................................................................... 46
Internal Modes ............................................................ 47
HFINTOSC ......................................................... 47
Internal Oscillator Clock Switch Timing .............. 48
LFINTOSC.......................................................... 47
Clock Switching .................................................................. 50
Code Examples
A/D Conversion......................................................... 126
Initializing PORTA..................................................... 101
Writing to Flash Program Memory .............................. 92
Comparators
C2OUT as T1 Gate................................................... 141
Complementary Waveform Generator (CWG).................. 187
CONFIG1 Register ............................................................. 40
CONFIG2 Register ............................................................. 41
Core Function Register....................................................... 24
Customer Change Notification Service............................. 262
Customer Notification Service .......................................... 262
Customer Support............................................................. 262
CWG
Auto-shutdown Control ............................................. 194
Clock Source ............................................................ 190
Output Control .......................................................... 190
Selectable Input Sources.......................................... 190
CWGxCON0 Register....................................................... 197
CWGxCON1 Register....................................................... 198
CWGxCON2 Register....................................................... 199
CWGxDBF Register.......................................................... 200
CWGxDBR Register ......................................................... 200
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
D
Data Memory ...................................................................... 17
DC and AC Characteristics ............................................... 239
DC Characteristics
Extended and Industrial ............................................ 228
Industrial and Extended ............................................ 223
Development Support ....................................................... 241
Device Configuration........................................................... 39
Code Protection .......................................................... 42
Configuration Word ..................................................... 39
User ID.................................................................. 42, 43
Device ID Register .............................................................. 43
Device Overview ............................................................. 9, 79
E
Effects of Reset
PWM mode ............................................................... 157
Electrical Specifications .................................................... 221
Enhanced Mid-Range CPU................................................. 13
Extended Instruction Set
ADDFSR ................................................................... 211
F
Firmware Instructions........................................................ 207
Fixed Voltage Reference (FVR) ........................................ 117
Associated Registers ................................................ 118
Flash Program Memory ...................................................... 83
Associated Registers .................................................. 98
Configuration Word w/ Flash Program Memory.......... 98
Erasing........................................................................ 87
Modifying..................................................................... 93
Write Verify ................................................................. 95
Writing......................................................................... 89
FSR Register ...................................................................... 24
FVRCON (Fixed Voltage Reference Control) Register ..... 118
I
INDF Register ..................................................................... 24
Indirect Addressing ............................................................. 34
Instruction Format ............................................................. 208
Instruction Set ................................................................... 207
ADDLW ..................................................................... 211
ADDWF..................................................................... 211
ADDWFC .................................................................. 211
ANDLW ..................................................................... 211
ANDWF..................................................................... 211
BRA........................................................................... 212
CALL ......................................................................... 213
CALLW...................................................................... 213
LSLF ......................................................................... 215
LSRF......................................................................... 215
MOVF........................................................................ 215
MOVIW ..................................................................... 216
MOVLB ..................................................................... 216
MOVWI ..................................................................... 217
OPTION .................................................................... 217
RESET ...................................................................... 217
SUBWFB................................................................... 219
TRIS.......................................................................... 220
BCF........................................................................... 212
BSF ........................................................................... 212
BTFSC ...................................................................... 212
BTFSS ...................................................................... 212
CALL ......................................................................... 213
CLRF......................................................................... 213
 2011 Microchip Technology Inc.
CLRW ....................................................................... 213
CLRWDT .................................................................. 213
COMF ....................................................................... 213
DECF........................................................................ 213
DECFSZ ................................................................... 214
GOTO ....................................................................... 214
INCF ......................................................................... 214
INCFSZ..................................................................... 214
IORLW...................................................................... 214
IORWF...................................................................... 214
MOVLW .................................................................... 216
MOVWF.................................................................... 216
NOP.......................................................................... 217
RETFIE..................................................................... 218
RETLW ..................................................................... 218
RETURN................................................................... 218
RLF........................................................................... 218
RRF .......................................................................... 219
SLEEP ...................................................................... 219
SUBLW..................................................................... 219
SUBWF..................................................................... 219
SWAPF..................................................................... 220
XORLW .................................................................... 220
XORWF .................................................................... 220
INTCON Register................................................................ 66
Internal Oscillator Block
INTOSC
Specifications ................................................... 232
Internal Sampling Switch (RSS) Impedance ..................... 132
Internet Address ............................................................... 262
Interrupt-On-Change......................................................... 111
Associated Registers................................................ 115
Interrupts ............................................................................ 61
ADC .......................................................................... 126
Associated registers w/ Interrupts .............................. 73
Configuration Word w/ Clock Sources........................ 52
TMR1........................................................................ 143
INTOSC Specifications ..................................................... 232
IOCAF Register ................................................................ 113
IOCAN Register ................................................................ 113
IOCAP Register ................................................................ 113
IOCBF Register ................................................................ 114
IOCBN Register ................................................................ 114
IOCBP Register ................................................................ 114
L
LATA Register .......................................................... 103, 109
LATB Register .................................................................. 106
Load Conditions................................................................ 231
LSLF ................................................................................. 215
LSRF ................................................................................ 215
M
MCLR ................................................................................. 56
Internal........................................................................ 56
Memory Organization ......................................................... 15
Data ............................................................................ 17
Program...................................................................... 15
Microchip Internet Web Site.............................................. 262
MOVIW ............................................................................. 216
MOVLB ............................................................................. 216
MOVWI ............................................................................. 217
MPLAB ASM30 Assembler, Linker, Librarian ................... 242
MPLAB Integrated Development Environment Software.. 241
MPLAB PM3 Device Programmer .................................... 244
MPLAB REAL ICE In-Circuit Emulator System ................ 243
Preliminary
DS41586A-page 258
PIC16(L)F1507
MPLINK Object Linker/MPLIB Object Librarian ................ 242
N
NCO
Associated registers.................................................. 186
NCOxACCH Register........................................................ 184
NCOxACCL Register ........................................................ 184
NCOxACCU Register........................................................ 184
NCOxCLK Register ........................................................... 183
NCOxCON Register .......................................................... 183
NCOxINCH Register ......................................................... 185
NCOxINCL Register.......................................................... 185
Numerically Controlled Oscillator (NCO)........................... 177
O
OPCODE Field Descriptions ............................................. 207
OPTION ............................................................................ 217
OPTION Register .............................................................. 137
OSCCON Register .............................................................. 51
Oscillator
Associated Registers .................................................. 52
Associated registers.................................................. 201
Oscillator Module ................................................................ 45
ECH ............................................................................ 45
ECL ............................................................................. 45
ECM ............................................................................ 45
INTOSC ...................................................................... 45
Oscillator Parameters........................................................ 232
Oscillator Specifications .................................................... 232
Oscillator Start-up Timer (OST)
Specifications ............................................................ 235
OSCSTAT Register............................................................. 52
P
Packaging ......................................................................... 245
Marking ............................................................. 245, 246
PDIP Details.............................................................. 247
PCL and PCLATH ............................................................... 14
PCL Register....................................................................... 24
PCLATH Register................................................................ 24
PCON Register ............................................................. 25, 59
PIE1 Register ................................................................ 25, 67
PIE2 Register ................................................................ 25, 68
PIE3 Register ................................................................ 25, 69
Pinout Descriptions
PIC16(L)F1507 ........................................................... 11
PIR1 Register................................................................ 25, 70
PIR2 Register................................................................ 25, 71
PIR3 Register................................................................ 25, 72
PMADR Registers ............................................................... 83
PMADRH Registers ............................................................ 83
PMADRL Register............................................................... 96
PMADRL Registers ............................................................. 83
PMCON1 Register ........................................................ 83, 97
PMCON2 Register ........................................................ 83, 98
PMDATH Register............................................................... 96
PMDATL Register ............................................................... 96
PMDRH Register................................................................. 96
PORTA.............................................................................. 101
ANSELA Register ..................................................... 101
Associated Registers ................................................ 104
Configuration Word w/ PORTA ................................. 104
LATA Register............................................................. 26
PORTA Register ......................................................... 25
Specifications ............................................................ 233
PORTA Register ............................................................... 102
DS41586A-page 259
PORTB
ANSELB Register ..................................................... 105
Associated Registers ................................................ 107
LATB Register ............................................................ 26
Pin Descriptions and Diagrams ................................ 105
PORTB Register ......................................................... 25
PORTB Register ............................................................... 106
PORTC
ANSELC Register ..................................................... 108
Associated Registers ................................................ 110
LATC Register ............................................................ 26
Pin Descriptions and Diagrams ................................ 108
PORTC Register......................................................... 25
PORTC Register............................................................... 109
Power-Down Mode (Sleep)................................................. 75
Associated Registers .................................................. 78
Power-on Reset .................................................................. 54
Power-up Time-out Sequence ............................................ 56
Power-up Timer (PWRT) .................................................... 54
Specifications ........................................................... 235
PR2 Register ...................................................................... 25
Program Memory ................................................................ 15
Map and Stack (PIC16(L)F1507 ................................. 16
Programming, Device Instructions .................................... 207
Pulse Width Modulation (PWM)........................................ 155
Associated registers w/ PWM ................................... 160
PWM Mode
Duty Cycle ........................................................ 156
Effects of Reset ................................................ 157
Example PWM Frequencies and
Resolutions, 20 MHZ ................................ 157
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 157
Operation in Sleep Mode.................................. 157
Setup for Operation using PWMx pins ............. 158
System Clock Frequency Changes .................. 157
PWM Period.............................................................. 156
Setup for PWM Operation using PWMx Pins ........... 158
PWMxCON Register ......................................................... 159
PWMxDCH Register ......................................................... 160
PWMxDCL Register.......................................................... 160
R
Reader Response............................................................. 263
Read-Modify-Write Operations ......................................... 207
Registers
ADCON0 (ADC Control 0) ........................................ 127
ADCON1 (ADC Control 1) ........................................ 128
ADCON2 (ADC Control 2) ........................................ 129
ADRESH (ADC Result High) with ADFM = 0) .......... 130
ADRESH (ADC Result High) with ADFM = 1) .......... 131
ADRESL (ADC Result Low) with ADFM = 0)............ 130
ADRESL (ADC Result Low) with ADFM = 1)............ 131
ANSELA (PORTA Analog Select)............................. 103
ANSELB (PORTB Analog Select)............................. 107
ANSELC (PORTC Analog Select) ............................ 110
APFCON (Alternate Pin Function Control) ............... 100
BORCON Brown-out Reset Control) .......................... 55
CLCDATA (Data Output) .......................................... 175
CLCxCON (CLCx Control)........................................ 167
CLCxGLS0 (Gate 1 Logic Select)............................. 171
CLCxGLS1 (Gate 2 Logic Select)............................. 172
CLCxGLS2 (Gate 3 Logic Select)............................. 173
CLCxGLS3 (Gate 4 Logic Select)............................. 174
CLCxPOL (Signal Polarity Control)........................... 168
CLCxSEL0 (Multiplexer Data 1 and 2 Select)........... 169
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
Configuration Word 1 .................................................. 40
Configuration Word 2 .................................................. 41
Core Function, Summary ............................................ 24
CWGxCON0 (CWG Control 0).................................. 197
CWGxCON1 (CWG Control 1).................................. 198
CWGxCON2 (CWG Control 1).................................. 199
CWGxDBF (CWGx Dead Band Falling Count) ......... 200
CWGxDBR (CWGx Dead Band Rising Count) ......... 200
Device ID .................................................................... 43
FVRCON................................................................... 118
INTCON (Interrupt Control)......................................... 66
IOCAF (Interrupt-on-Change PORTA Flag).............. 113
IOCAN (Interrupt-on-Change PORTA
Negative Edge) ................................................. 113
IOCAP (Interrupt-on-Change PORTA
Positive Edge)................................................... 113
IOCBF (Interrupt-on-Change PORTB Flag).............. 114
IOCBN (Interrupt-on-Change PORTB
Negative Edge) ................................................. 114
IOCBP (Interrupt-on-Change PORTB
Positive Edge)................................................... 114
LATA (Data Latch PORTA)....................................... 103
LATB (Data Latch PORTB)....................................... 106
LATC (Data Latch PORTC) ...................................... 109
NCOxACCH (NCOx Accumulator High Byte) ........... 184
NCOxACCL (NCOx Accumulator Low Byte)............. 184
NCOxACCU (NCOx Accumulator Upper Byte)......... 184
NCOxCLK (NCOx Clock Control) ............................. 183
NCOxCON (NCOx Control) ...................................... 183
NCOxINCH (NCOx Increment High Byte)................. 185
NCOxINCL (NCOx Increment Low Byte) .................. 185
OPTION_REG (OPTION) ......................................... 137
OSCCON (Oscillator Control) ..................................... 51
OSCSTAT (Oscillator Status) ..................................... 52
PCON (Power Control Register) ................................. 59
PCON (Power Control) ............................................... 59
PIE1 (Peripheral Interrupt Enable 1)........................... 67
PIE2 (Peripheral Interrupt Enable 2)........................... 68
PIE3 (Peripheral Interrupt Enable 3)........................... 69
PIR1 (Peripheral Interrupt Register 1) ........................ 70
PIR2 (Peripheral Interrupt Request 2) ........................ 71
PIR3 (Peripheral Interrupt Request 3) ........................ 72
PMADRL (Program Memory Address)........................ 96
PMCON1 (Program Memory Control 1)...................... 97
PMCON2 (Program Memory Control 2)...................... 98
PMDATH (Program Memory Data) ............................. 96
PMDATL (Program Memory Data).............................. 96
PMDRH (Program Memory Address) ......................... 96
PORTA...................................................................... 102
PORTB...................................................................... 106
PORTC ..................................................................... 109
PWMxCON (PWM Control)....................................... 159
PWMxDCH (PWM Control)....................................... 160
PWMxDCL (PWM Control) ....................................... 160
Special Function, Summary ........................................ 25
STATUS...................................................................... 18
T1CON (Timer1 Control)........................................... 147
T1GCON (Timer1 Gate Control) ............................... 148
T2CON...................................................................... 153
TRISA (Tri-State PORTA)......................................... 102
TRISB (Tri-State PORTB)......................................... 106
TRISC (Tri-State PORTC) ........................................ 109
VREGCON (Voltage Regulator Control) ..................... 78
WDTCON (Watchdog Timer Control) ......................... 81
WPUA (Weak Pull-up PORTA) ................................. 104
 2011 Microchip Technology Inc.
WPUB (Weak Pull-up PORTB)................................. 107
WPUC (Weak Pull-up PORTC) ................................ 110
RESET.............................................................................. 217
Reset .................................................................................. 53
Reset Instruction................................................................. 56
Resets ................................................................................ 53
Associated Registers.................................................. 60
Configuration Word w/ Resets.................................... 60
Revision History................................................................ 255
S
Software Simulator (MPLAB SIM) .................................... 243
Special Function Registers (SFRs)..................................... 25
Stack................................................................................... 32
Accessing ................................................................... 32
Reset .......................................................................... 34
Stack Overflow/Underflow .................................................. 56
STATUS Register ............................................................... 18
SUBWFB .......................................................................... 219
T
T1CON Register ......................................................... 25, 147
T1GCON Register ............................................................ 148
T2CON (Timer2) Register................................................. 153
T2CON Register ................................................................. 25
Temperature Indicator
Associated Registers................................................ 120
Temperature Indicator Module.......................................... 119
Thermal Considerations.................................................... 230
Timer0 .............................................................................. 135
Associated Registers................................................ 137
Operation.................................................................. 135
Specifications ........................................................... 236
Timer1 .............................................................................. 139
Associated registers ................................................. 149
Asynchronous Counter Mode ................................... 141
Reading and Writing ......................................... 141
Clock Source Selection ............................................ 140
Interrupt .................................................................... 143
Operation.................................................................. 140
Operation During Sleep ............................................ 143
Prescaler .................................................................. 141
Specifications ........................................................... 236
Timer1 Gate
Selecting Source .............................................. 141
TMR1H Register....................................................... 139
TMR1L Register ....................................................... 139
Timer2 .............................................................................. 151
Associated registers ................................................. 154
Timers
Timer1
T1CON ............................................................. 147
T1GCON........................................................... 148
Timer2
T2CON ............................................................. 153
Timing Diagrams
A/D Conversion ........................................................ 237
A/D Conversion (Sleep Mode).................................. 238
Brown-out Reset (BOR)............................................ 234
Brown-out Reset Situations ........................................ 55
CLKOUT and I/O ...................................................... 233
Clock Timing............................................................. 232
INT Pin Interrupt ......................................................... 64
Internal Oscillator Switch Timing ................................ 49
Reset Start-up Sequence ........................................... 57
Reset, WDT, OST and Power-up Timer ................... 234
Preliminary
DS41586A-page 260
PIC16(L)F1507
Timer0 and Timer1 External Clock ........................... 235
Timer1 Incrementing Edge........................................ 143
Wake-up from Interrupt ............................................... 76
Timing Parameter Symbology........................................... 231
TMR0 Register .................................................................... 25
TMR1H Register ................................................................. 25
TMR1L Register .................................................................. 25
TMR2 Register .................................................................... 25
TRIS .................................................................................. 220
TRISA Register ........................................................... 25, 102
TRISB................................................................................ 105
TRISB Register ........................................................... 25, 106
TRISC ............................................................................... 108
TRISC Register ........................................................... 25, 109
V
VREF. SEE ADC Reference Voltage
VREGCON Register............................................................ 78
W
Wake-up Using Interrupts ................................................... 75
Watchdog Timer (WDT) ...................................................... 56
Associated Registers .................................................. 82
Configuration Word w/ Watchdog Timer ..................... 82
Modes ......................................................................... 80
Specifications ............................................................ 235
WDTCON Register.............................................................. 81
WPUA Register ................................................................. 104
WPUB Register ................................................................. 107
WPUC Register................................................................. 110
Write Protection................................................................... 42
WWW Address.................................................................. 262
DS41586A-page 261
Preliminary
 2011 Microchip Technology Inc.
PIC16(L)F1507
NOTES:
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 262
PIC16(L)F1507
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS41586A-page 263
 2011 Microchip Technology Inc.
PIC16(L)F1507
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
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RE:
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Total Pages Sent ________
From: Name
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City / State / ZIP / Country
Telephone: (_______) _________ - _________
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Application (optional):
Would you like a reply?
Y
N
Device: PIC16(L)F1507
Literature Number: DS41586A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
 2011 Microchip Technology Inc.
Preliminary
DS41586A-page 264
PIC16(L)F1507
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC16F1507, PIC16LF1507
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:
ML
P
SO
SS
Pattern:
DS41586A-page 265
=
=
=
=
c)
PIC16LF1507T - I/SO
Tape and Reel,
Industrial temperature,
SOIC package
PIC16F1507 - I/P
Industrial temperature
PDIP package
PIC16F1507 - E/ML 298
Extended temperature,
QFN package
QTP pattern #298
(Industrial)
(Extended)
Micro Lead Frame (QFN) 4x4
Plastic DIP
SOIC
SSOP
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Preliminary
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
 2011 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS41586A-page 266
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
05/02/11
Preliminary
 2011 Microchip Technology Inc.