CA3318 CMOS Video Speed, 8-Bit, Flash A/D Converter August 1997 Features Description • CMOS Low Power with SOS Speed (Typ). . . . . . . . 150mW The CA3318 is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization. • Parallel Conversion Technique • 15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns • 8-Bit Latched Three-State Output with Overflow Bit • Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB • Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V • 2 Units in Series Allow 9-Bit Output • 2 Units in Parallel Allow 30MHz Sampling Rate Applications • • • • • • • • • • TV Video Digitizing (Industrial/Security/Broadcast) High Speed A/D Conversion Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research General-Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis µP Data Acquisition Systems The CA3318 operates over a wide full scale input voltage range of 4V up to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the CA3318 is 150mW. The intrinsic high conversion rate makes the CA3318 ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz). 256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3318. 255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overflow bit. Ordering Information PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE (oC) SAMPLING RATE PACKAGE PKG. NO. CA3318CE ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld PDIP E24.6 CA3318CM ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SOIC M24.3 CA3318CD ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SBDIP D24.6 Pinout CA3318 (PDIP, SBDIP, SOIC) TOP VIEW (LSB) B1 1 24 VAA + (ANA. SUP.) B2 2 23 3/4R B3 3 22 VREF + B4 4 21 VIN B5 5 20 p B6 6 19 PHASE B7 7 18 CLK 17 VAA - (ANA. GND) (MSB) B8 8 16 VIN OVERFLOW 9 1/ R 10 4 15 VREF - (DIG. GND) VSS 11 14 CE1 (DIG. SUP.) VDD 12 13 CE2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-9 File Number 3103.1 CA3318 Functional Block Diagram VAA+ ANALOG SUPPLY 24 φ2 φ1 φ1 φ1 φ1 φ2 21 D Q D Q COUNT 256 D Q CAB # 256 LATCH 256 D Q D Q D Q COUNT 193 ENCODER LOGIC ARRAY BIT 7 LATCH LATCH BIT 6 D Q R D Q D Q COUNT 129 6 CLK BIT 5 CAB # 129 20 7 CLK R 1/ REF 2 8 CLK D Q CAB # 193 = 7Ω 9 BIT 8 (MSB) LATCH 256 R 23 12 CLK R = 2Ω 3/ REF 4 DIGITAL SUPPLY THREESTATE OUTPUT REGISTER DRIVERS OVERFLOW VIN VREF + 1 /2 R 22 VDD φ1 D Q = 30Ω LATCH R 5 CLK LATCH BIT 4 R 1/ REF 4 D D Q D Q = 4Ω 4 CLK CAB # 65 10 BIT 3 LATCH R VIN Q COUNT 65 D Q LATCH 3 CLK 16 ≅ 2K R VREF 15 D CAB (NOTE 1) COMPARATOR #1 1/ R 2 Q D COUNT 1 BIT 2 D Q 2 CLK LATCH 1 BIT 1 (LSB) LATCH 11 D Q ≅ 50K φ1 (AUTO BALANCE) CLOCK Q 1 CLK 18 PHASE VAA17 CE1 φ2 (SAMPLE UNKNOWN) 19 14 ANALOG GND CE2 13 NOTE: 1. Cascaded Auto Balance (CAB). VSS DIGITAL GND 4-10 11 CA3318 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V (Referenced to VSS or VAA- Terminal, Whichever is More Negative) Input Voltage Range CE2 and CE1 . . . . . . . . . . . . . . . . . . . . VAA- -0.5V to VDD + 0.5V Clock, Phase, VREF -, 1/2 Ref . . . . . . . VAA- -0.5V to VAA+ + 0.5V Clock, Phase, VREF -, 1/4 Ref . . . . . . . . VSS- -0.5V to VDD + 0.5V VIN , 3/4 REF, VREF + . . . . . . . . . . . . . . VAA- -0.5V to VAA- + 7.5V Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V Bits 1-8, Overflow (Outputs Off) DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Clock, Phase, CE1, CE2, VIN , Bits 1-8, Overflow Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . . . 60 22 PDIP Package . . . . . . . . . . . . . . . . . . . . . 60 N/A SOIC Package . . . . . . . . . . . . . . . . . . . . . 75 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 265oC (SOIC - Lead Tips Only) Operating Conditions Operating Voltage Range (VDD or VAA+) . . . 4V (Min) to 7.5V (Max) Recommended VAA + Operating Range . . . . . . . . . . . . . . . VDD ±1V Recommended VAA - Operating Range . . . . . . . . . . . . . . . VSS ±1V Operating Temperature Range (TA) . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications At 25oC, VAA+ = VDD = 5V, VREF + = 6.4V, VREF - = VAA- = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Resolution 8 - - Bits Integral Linearity Error - - ± 1.5 LSB SYSTEM PERFORMANCE Differential Linearity Error - - +1, -0.8 LSB VIN = VREF- + 1/2 LSB VIN = VREF+ - 1/2 LSB -0.5 4.5 6.4 LSB -1.5 0 1.5 LSB Maximum Input Bandwidth (Note 1) CA3318 2.5 5.0 - MHz Maximum Conversion Speed CLK = Square Wave 15 17 - MSPS Signal to Noise Ratio (SNR) fS = 15MHz, fIN = 100kHz - 47 - dB fS = 15MHz, fIN = 4MHz - 43 - dB Offset Error, Unadjusted Gain Error Unadjusted DYNAMIC CHARACTERISTICS RMSSignal = -------------------------------RMSNoise Signal to Noise Ratio (SINAD) RMSSignal = -----------------------------------------------------------RMSNoise+Distortion Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - 45 - dB fS = 15MHz, fIN = 4MHz - 35 - dB fS = 15MHz, fIN = 100kHz - -46 - dBc fS = 15MHz, fIN = 4MHz - -36 - dBc fS = 15MHz, fIN = 100kHz - 7.2 - Bits fS = 15MHz, fIN = 4MHz - 5.5 - Bits Differential Gain Error Unadjusted - 2 - % Differential Phase Error Unadjusted - 1 - % Notes 2, 4 4 - 7 V - 30 - pF VIN = 5V, VREF+ = 5V - - 3.5 mA 270 500 800 Ω Effective Number of Bits (ENOB) ANALOG INPUTS Full Scale Range, VIN and (VREF+) - (VREF -) Input Capacitance, VIN Input Current, VIN , (See Text) REFERENCE INPUTS Ladder Impedance 4-11 CA3318 Electrical Specifications At 25oC, VAA+ = VDD = 5V, VREF + = 6.4V, VREF - = VAA- = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Low Level Input Voltage, VOL CE1, CE2 Phase, CLK High Level Input Voltage, VIN CE1, CE2 Phase, CLK Input Leakage Current, II (Except CLK Input) Note 4 - - 0.2VDD V Note 4 - - 0.2VAA V V Note 4 0.7VDD - - Note 4 0.7VAA - - V Note 3 - ±0.2 ±5 µA - 3 - pF Input Capacitance, CI DIGITAL OUTPUTS Output Low (Sink) Current VO = 0.4V 4 10 - mA Output High (Source) Current VO = 4.5V -4 -6 - mA Three-State Output Off-State Leakage Current, IOZ - ±0.2 ±5 µA Output Capacitance, CO - 4 - pF 33 - ∞ ns 25 - 500 ns - 15 - ns TIMING CHARACTERISTICS Auto Balance Time (φ1) Sample Time (φ2) Note 4 Aperture Delay Aperture Jitter - 100 - ps Data Valid Time, tD Note 4 - 50 65 ns Data Hold Time, tH Note 4 25 40 - ns Output Enable Time, tEN - 18 - ns Output Disable Time, tDIS - 18 - ns POWER SUPPLY CHARACTERISTICS Device Current (IDD + IA) (Excludes IREF) Continuous Conversion (Note 4) - 30 60 mA Auto Balance (φ1) - 30 60 mA NOTES: 1. A full scale sine wave input of greater than fCLOCK/2 or the specified input bandwidth (whichever is less) may cause an erroneous code. The -3dB bandwidth for frequency response purposes is greater than 30MHz. 2. VIN (Full Scale) or VREF+ should not exceed VAA+ + 1.5V for accuracy. 3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1VP-P minimum source. 4. Parameter not tested, but guaranteed by design or characterization. Timing Waveforms DECODED DATA IS SHIFTED TO OUTPUT REGISTERS COMPARATOR DATA IS LATCHED CLOCK (PIN 18) IF PHASE (PIN 19) IS LOW CLOCK IF PHASE IS HIGH φ1 φ2 SAMPLE N AUTO BALANCE φ2 SAMPLE N+1 φ1 φ2 AUTO BALANCE SAMPLE N+2 tD tH DATA N-2 DATA N-1 FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM 4-12 DATA N CA3318 Timing Waveforms (Continued) CE1 CE2 tDIS tEN tDIS BITS 1 - 8 DATA tEN DATA DATA HIGH IMPEDANCE OF HIGH IMPEDANCE DATA HIGH IMPEDANCE FIGURE 2. OUTPUT ENABLE TIMING DIAGRAM AUTO BALANCE AUTO BALANCE SAMPLE N CLOCK NO MAX LIMIT 25ns MIN SAMPLE N+1 33ns MIN 25ns MIN 50ns MIN DATA FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW) CLOCK SAMPLE N 500ns MAX AUTO BALANCE 33ns MIN SAMPLE N+1 25ns MIN AUTO BALANCE SAMPLE N+2 50ns TYP DATA N-1 DATA FIGURE 3B. STANDBY IN SAMPLE (SHOWN WITH PHASE = LOW) FIGURE 3. PULSE MODE OPERATION 4-13 DATA N CA3318 Typical Performance Curves 40 28 35 27 IDD (mA) IDD (mA) 30 25 26 25 20 24 15 10 10 0 20 23 -50 30 -25 25 0 50 TEMPERATURE (oC) fS (MHz) FIGURE 4. DEVICE CURRENT vs SAMPLE FREQUENCY 1.00 fS = 15MHz, fI = 1MHz 7.8 fS = 15MHz 0.90 7.6 NON-LINEARITY (LSB) 0.80 7.4 ENOB (LSB) 100 FIGURE 5. DEVICE CURRENT vs TEMPERATURE 8.0 7.2 7.0 6.8 6.6 0.70 0.50 0.40 0.30 0.20 6.2 0.10 0 10 20 30 40 50 70 60 80 INL 0.60 6.4 6.0 -40 -30 -20 -10 DNL 0 -40 -30 -20 -10 90 0 TEMPERATURE (oC) 1.08 1.80 0.96 1.60 NON-LINEARITY (LSB) 1.00 0.84 INL 0.60 0.48 0.36 DNL 0.24 20 30 40 50 60 70 80 90 FIGURE 7. NON-LINEARITY vs TEMPERATURE 1.20 0.72 10 TEMPERATURE (oC) FIGURE 6. ENOB vs TEMPERATURE NON-LINEARITY (LSB) 75 fS = 15MHz 1.40 1.20 1.00 INL 0.80 0.60 DNL 0.40 0.20 0.12 0 0 0 5 10 15 20 0 25 fS (MHz) FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY 1 2 3 4 VREF (V) 5 6 FIGURE 9. NON-LINEARITY vs REFERENCE VOLTAGE 4-14 7 CA3318 Typical Performance Curves (Continued) 8.0 7.6 fS = 15MHz 7.2 ENOB (LSB) 6.8 6.4 6.0 5.6 5.2 4.8 4.4 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 fI (MHz) FIGURE 10. ENOB vs INPUT FREQUENCY Pin Descriptions CHIP ENABLE TRUTH TABLE PIN NAME 1 B1 Bit 1 (LSB) DESCRIPTION 2 B2 Bit 2 3 B3 Bit 3 4 B4 Bit 4 5 B5 Bit 5 6 B6 Bit 6 7 B7 Bit 7 8 B8 Bit 8 (MSB) Output Data Bits (High = True) Overflow CE1 CE2 B1 - B8 OF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don’t Care Theory of Operation A sequential parallel technique is used by the CA3318 converter to obtain its high speed operation. The sequence consists of the “Auto-Balance” phase, φ1, and the “Sample Unknown” phase, φ2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control (pin 19) high, the “Auto-Balance” (φ1) occurs during the high period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the low period of the clock cycle. 9 OF 10 1/ R 4 Reference Ladder 1/4 Point 11 VSS Digital Ground 12 VDD Digital Power Supply, +5V 13 CE2 Three-State Output Enable Input, Active Low, See Truth Table. NOTE: The device requires only a single phase clock The terminology of φ1 and φ2 refers to the high and low periods of the same clock. 14 CE1 Three-State Output Enable Input Active High. See Truth Table. 15 VREF - Reference Voltage Negative Input During the “Auto-Balance” phase, a transmission switch is used to connect each of the first set of 256 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: 16 VIN Analog Signal Input 17 VAA- Analog Ground 18 CLK Clock Input 19 PHASE 20 1/ R 2 21 VIN Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs when the clock is low and “Auto Balance” occurs when the clock is high (see text). VTAP (N) = [(N/256) VREF] - (1/512) VREF] = [(2N - 1)/512] VREF , Where: VTAP (n) = reference ladder tap voltage at point n, VREF = voltage across VREF - to VREF +, N = tap number (1 through 256). Reference Ladder Midpoint Analog Signal Input 22 VREF+ 23 3/ R 4 Reference Ladder 3/4 Point 24 VAA+ Analog Power Supply, +5V Reference Voltage Positive Input The other side of these capacitors are connected to singlestage amplifiers whose outputs are shorted to their inputs by switches. This balances the amplifiers at their intrinsic trip points, which is approximately (VAA+ - VAA-)/2. The first set of capacitors now charges to their associated tap voltages. 4-15 CA3318 At the same time a second set of commutating capacitors and amplifiers is also auto-balanced. The balancing of the second-stage amplifier at its intrinsic trip point removes any tracking differences between the first and second amplifier stages. The cascaded auto-balance (CAB) technique, used here, increases comparator sensitivity and temperature tracking. In the “Sample Unknown” phase, all ladder tap switches and comparator shorting switches are opened. At the same time VlN is switched to the first set of commutating capacitors. Since the other end of the capacitors are now looking into an effectively open circuit, any input voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators that had tap voltages greater than VlN will go to a “high” state at their outputs. All comparators that had tap voltages lower than VlN will go to a “low” state. The status of all these comparator amplifiers is AC coupled through the second-stage comparator and stored at the end of this phase (φ2) by a latching amplifier stage. The latch feeds a second latching stage, triggered at the end of φ1. This delay allows comparators extra settling time. The status of the comparators is decoded by a 256 to 9-bit decoder array, and the results are clocked into a storage register at the end of the next φ2. A 3-stage buffer is used at the output of the 9 storage registers which are controlled by two chip-enable signals. CE1 will independently disable B1 through B6 when it is in a high state. CE2 will independently disable B1 through B8 and the OF buffers when it is in the low state. To facilitate usage of this device, a phase control input is provided which can effectively complement the clock as it enters the chip. Continuous-Clock Operation One complete conversion cycle can be traced through the CA3318 via the following steps. (Refer to timing diagram.) With the phase control in a “low” state, the rising edge of the clock input will start a “sample” phase. During this entire “high” state of the clock, the comparators will track the input voltage and the first-stage latches will track the comparator outputs. At the falling edge of the clock, all 256 comparator outputs are captured by the 256 latches. This ends the “sample” phase and starts the “auto-balance” phase for the comparators. During this “low” state of the clock, the output of the latches settles and is captured by a second row of latches when the clock returns high. The second-stage latch output propagates through the decode array, and a 9-bit code appears at the D inputs of the output registers. On the next falling edge of the clock, this 9-bit code is shifted into the output registers and appears with time delay tD as valid data at the output of the three-state drivers. This also marks the end of the next “sample” phase, thereby repeating the conversion process for this next cycle. Pulse-Mode Operation The CA3318 needs two of the same polarity clock edges to complete a conversion cycle: If, for instance, a negative going clock edge ends sample “N”, then data “N” will appear after the next negative going edge. Because of this requirement, and because there is a maximum sample time of 500ns (due to capacitor droop), most pulse or intermittent sample applications will require double clock pulsing. If an indefinite standby state is desired, standby should be in auto-balance, and the operation would be as in Figure 3A. If the standby state is known to last less than 500ns and lowest average power is desired, then operation could be as in Figure 3B. Increased Accuracy In most cases the accuracy of the CA3318 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, five adjustments can be made to obtain better accuracy, i.e., offset trim; gain trim; and 1/4 , 1/2 and 3/4 point trim. Offset Trim In general, offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the op amp. When this is not possible the VREF - input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equation is as follows: VlN (0 to 1 transition) = 1/2 LSB = 1/2 (VREF/256) = VREF /512. If VlN for the first transition is less than the theoretical, then a single-turn 50Ω pot connected between VREF - and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0-to-1 transition occurs. If VlN for the first transition is greater than the theoretical, then the 50Ω pot should be connected between VREF - and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general, the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 255 to overflow transition. That voltage is 1/3 LSB less than VREF + and is calculated as follows: VlN (255 to 256 transition) = VREF - VREF /512 = VREF(511/512). To perform the gain trim, first do the offset trim and then apply the required VlN for the 255 to overflow transition. Now adjust VREF + until that transition occurs on the outputs. 4-16 CA3318 +10V TO 30V INPUT The first step for connecting a 9-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. + 3 18Ω 2 1 (NOTE) 5K IOT 6 4 VREF+ 8 CA3085E 7 (PIN 22) CW 10µF, TAN (NOTE) 1.5K + 4.7µF, TAN/IOV NOTE: Bypass VREF+ to analog GND near A/D with 0.1µF ceramic cap. Parts noted should have low temperature drift. FIGURE 11. TYPICAL VOLTAGE REFERENCE SOURCE FOR DRIVING VREF+ INPUT Grounding/Bypassing 1/ Point Trims 4 The 1/4 , 1/2 and 3/4 points on the reference ladder are brought out for linearity adjusting or if the user wishes to create a nonlinear transfer function. The 1/4 points can be driven by the reference drivers shown (Figure 12) or by 2-K pots connected between VREF + and VREF -. The 1/2 (mid-) point should be set first by applying an input of 257/512 x (VREF) and adjusting for an output changing from 128 to 129. Similarly the 1/4 and 3/4 points can be set with inputs of 129/512 and 385/512 x (VREF) and adjusting for counts of 192 to 193 and 64 to 65. (Note that the points are actually 1/ , 1/ and 3 / of full scale +1 LSB.) 4 2 4 VREF+ (PIN 22) +10V TO +30V 510Ω 4 3 1K IOT CW 1K IOT CW 1K IOT 2 11 + 5 + 6 3/ REF 4 (PIN 23) 7 10Ω 1/ REF 2 (PIN 20) 8 10Ω 1/ REF 4 The analog and digital supply grounds of a system should be kept separate and only connected at the A/D. This keeps digital ground noise out of the analog data to be converted. Reference drivers, input amps, reference taps, and the VAA supply should be bypassed at the A/D to the analog side of the ground. See Figure 15 for a block diagram of this concept. All capacitors shown should be low impedance 0.1µF ceramics and should be mounted as close to the A/D as possible. If VAA+ is derived from VDD , a small (10Ω resistor or inductor and additional filtering (4.7µF tantalum) may be used to keep digital noise out of the analog system. Input Loading The CA3318 outputs a current pulse to the VlN terminal at the start of every sample period. This is due to capacitor charging and switch feedthrough and varies with input voltage and sampling rate. The signal source must be capable of recovering from the pulse before the end of the sample period to guarantee a valid signal for the A/D to convert. Suitable high speed amplifiers include the HA-5033, HA-2542; and CA3450. Figure 16 is an example of an amplifier which recovers fast enough for sampling at 15MHz. Output Loading + 9 10Ω - 10 CW 1 - The overflow output of the lower device now becomes the ninth bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overtlow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The threestate outputs of the two devices (bits 1 through 8) are now connected in parallel to complete the circuitry. The complete circuit for a 9-bit A/D converter is shown in Figure 13. - The CMOS digital output stage, although capable of driving large loads, will reflect these loads into the local ground. It is recommended that a local QMOS buffer such as CD74HC541 E be used to isolate capacitive loads. (PIN 10) 510Ω NOTES: Definitions 1. All Op Amps = 3/4 CA324E. 2. Bypass all reference points to analog ground near A/D with 0.1µF ceramic caps. 3. Adjust VREF+ first, then 1/3 , 3/4 and 1/4 points. FIGURE 12. TYPICAL 1/4 POINT DRIVERS FOR ADJUSTING LINEARITY (USE FOR MAXIMUM LINEARITY) 9-Bit Resolution To obtain 9-bit resolution, two CA3318s can be wired together. Necessary ingredients include an open-ended ladder network, an overflow indicator, three-state outputs, and chipenable controls - all of which are available on the CA3318. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. 4-17 CA3318 Signal-to-Noise + Distortion Ratio (SINAD) Total Harmonic Distortion (THD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR)/6.02, where: VCORR = 0.5dB. +6.4V REF +5V VREF+ OF NC VAA+ VDD +5V VAA- BIT 8 VIN BIT 1 VIN CL A VIN1 0V TO 6.4V PH CE2 CE1 MID-POINT DRIVER 6.4V REF VREF- VSS D A VREF+ +5V VDD CE2 +5V A VIN CE1 VIN OF BIT 9 BIT 8 BIT 8 BIT 1 BIT 1 CLOCK VAA+ CL VAAVREF - PH VSS PHASE D A FIGURE 13. USING TWO CA3318s FOR 9-BIT RESOLUTION 4-18 CA3318 4.7µF/10V TANTALUM + +5V (ANALOG SUPPLY) A +4V TO +6.5V REFERENCE OPTIONAL CAP (SEE TEXT) 0.01µF CLOCK SOURCE VAA+ BIT 1 3/ REF 4 BIT 2 VREF+ BIT 3 VIN BIT 4 1/ REF 2 BIT 5 PHASE BIT 6 CLK BIT 7 VAA- BIT 8 OVF VIN INPUT SIGNAL 1/ REF 4 VREF- AMPLIFIER/BUFFER (SEE TEXT) A D DIGITAL OUTPUT CE1 VSS CE2 VDD A D + CA3318 4.7µF TANTALUM/10V +5V (DIGITAL SUPPLY) FIGURE 14. TYPICAL CIRCUIT CONFIGURATION FOR THE CA3318 WITH NO LINEARITY ADJUST VIN AMP SIGNAL SOURCE REF TO DIGITAL SYSTEM OUTPUT DRIVERS VIN VREF+ SIGNAL GROUND REFERENCE TAPS VDD VAA+ VREF VAA- - VSS SYSTEM DIGITAL GROUND ANALOG + SUPPLIES VAA SUPPLY VDD SUPPLY FIGURE 15. TYPICAL SYSTEM GROUNDING/BYPASSING +8V 75Ω 1VP-P VIDEO INPUT 10Ω 14 75Ω 0.001µF 7 11 5pF 8 13 3 16 A/D FLASH INPUT 21 12 4 390 5 0.001µF 10Ω NOTE: Ground-planing and tight layout are extremely important. 10Ω 6 CA3450 9 750 0.1 -4V 110 0V TO -10V OFFSET SOURCE RS < 10Ω FIGURE 16. TYPICAL HIGH BANDWIDTH AMPLIFIER FOR DRIVING THE CA3318 4-19 CA3318 TABLE 1. OUTPUT CODE TABLE (NOTE 1) INPUT VOLTAGE BINARY OUTPUT CODE CODE DESCRIPTION VREF 6.40V (V) VREF 5.12V (V) OF MSB B8 B7 B6 B5 B4 B3 B2 LSB B1 DECIMAL COUNT Zero 0.00 0.00 0 0 0 0 0 0 0 0 0 0 1 LSB 0.025 0.02 0 0 0 0 0 0 0 0 1 1 2 LSB 0.05 0.04 0 0 0 0 0 0 0 1 0 2 • • • • • • • • • 1/ Full Scale 4 1.60 1.28 • • • • • • • • • 1/ Full Scale - 1 LSB 2 3.175 2.54 0 0 1 1 1 1 1 1 1 127 1/ Full Scale 2 3.20 2.56 0 1 0 0 0 0 0 0 0 128 1/ Full Scale + 1 LSB 2 3.225 2.58 0 1 0 0 0 0 0 0 1 129 • • • • • • • • • 3/ Full Scale 4 4.80 3.84 • • • • • • • • • Full Scale - 1 LSB 6.35 5.08 0 1 1 1 1 1 1 1 0 254 Full Scale 6.375 5.10 0 1 1 1 1 1 1 1 1 255 Over Flow 6.40 5.12 1 1 1 1 1 1 1 1 1 511 • • • 0 0 1 0 0 • • • 0 0 0 0 • • • • • • • • • 0 1 1 0 0 64 • • • 0 0 0 0 • • • 192 • • • NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. Reducing Power Clock Input Most power is consumed while in the auto-balance state. When operating at lower than 15MHz clock speed, power can be reduced by stretching the sample (φ2) time. The constraints are a minimum balance time (φ1) of 33ns, and a maximum sample time of 500ns. Longer sample times cause droop in the auto-balance capacitors. Power can also be reduced in the reference string by switching the reference on only during auto-balance. The Clock and Phase inputs feed buffers referenced to VAA+ and VAA-. Phase should be tied to one of these two potentials, while the clock (if DC coupled) should be driven at least from 0.2 to 0.7 x (VAA+ - VAA-). The clock may also be AC coupled with at least a 1VP-P swing. This allows TTL drive levels or 5V QMOS levels when VAA+ is greater than 5V. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. 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