INTERSIL HI9P5701K-5

HI-5701
Data Sheet
June 1999
File Number
6-Bit, 30MSPS, Flash A/D Converter
Features
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-toDigital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7 LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
• 30MSPS with No Missing Codes
The HI-5701 is available in Commercial and Industrial
temperature ranges and is supplied in 18 lead Plastic DIP
and SOIC packages
2937.8
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW
• CMOS/TTL Compatible
• Overflow Bit
• /883 Version Available
Applications
• Video Digitizing
• Radar Systems
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
• Communication Systems
PACKAGE
PKG.
NO.
HI3-5701K-5
0 to 70
18 Ld PDIP
E18.3
HI9P5701K-5
0 to 70
18 Ld SOIC
M18.3
HI3-5701B-9
-40 to 85
18 Ld PDIP
E18.3
HI9P5701B-9
-40 to 85
18 Ld SOIC
M18.3
HI5701-EV
25
Evaluation Board
1
• High Speed Data Acquisition Systems
Pinout
HI-5701
(PDIP, SOIC)
TOP VIEW
D5 (MSB)
1
18
D4
OVF
2
17
D3
VSS
3
16
1/ R
2
NC
4
15
D2
CE2
5
14
D1
CE1
6
13
D0 (LSB)
CLK
7
12
VDD
PHASE
8
11
VIN
VREF +
9
10
VREF -
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HI-5701
Functional Block Diagram
φ1
φ2
φ1
φ1
φ2
VIN
D
Q
CL
OVERFLOW
(OVF)
R
D
Q
CL
D5 (MSB)
R
D
Q
CL
D4
D
Q
CL
D3
D
Q
CL
D2
D
Q
CL
D1
D
Q
CL
D0 (LSB)
R/2
VREF +
COMP 64
COMP 63
R
1/ R
2
R
COMP 32
COMPARATOR
LATCHES
AND
63 TO 6
ENCODER
LOGIC
R
COMP 2
R
VREF R/2
COMP 1
CE1
CE2
CLOCK
φ2 (SAMPLE)
PHASE
φ1 (AUTO BALANCE)
2
VDD
VSS
HI-5701
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD to VSS . . . . . . . . . . . (VSS - 0.5) < VDD < +7V
Analog and Reference Input Pins (VSS - 0.5) < VINA < (VDD +0.5V)
Digital I/O Pins . . . . . . . . . . . . . . . .(VSS - 0.5) < VI/O < (VDD +0.5V)
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
Maximum Power Dissipation at 70oC (Note 2) . . . . . . . . . . .635mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HI3-5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
HI9P5701-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Electrical Specifications
VDD = +5.0V; VREF + = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle;
CL = 30pF; Unless Otherwise Specified
(NOTE 3)
0oC TO 70oC
-40oC TO 85oC
25oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
6
-
-
6
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Best Fit Line)
fS = 20MHz
-
±0.5
±1.25
-
±2.0
LSB
fS = 30MHz
-
±1.5
-
-
-
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fS = 20MHz
-
±0.3
±0.6
-
±0.75
LSB
fS = 30MHz
-
±0.7
-
-
Offset Error, VOS
(Adjustable to Zero)
fS = 20MHz (Note 3)
-
±0.5
±2.0
-
±2.5
LSB
fS = 30MHz
-
±0.5
-
-
-
LSB
Full Scale Error, FSE
(Adjustable to Zero)
fS = 20MHz (Note 3)
-
±0.25
±2.0
-
±2.5
LSB
fS = 30MHz
-
±0.25
-
-
-
LSB
30
40
-
30
-
MSPS
LSB
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate
No Missing Codes
Minimum Conversion Rate
No Missing Codes (Note 3)
-
-
0.125
-
0.125
MSPS
Full Power Input Bandwidth
fS = 30MHz
-
20
-
-
-
MHz
Signal to Noise Ratio, SNR
fS = 1MHz, fIN = 100kHz
-
36
-
-
-
dB
RMS Signal
= --------------------------------RMS Noise
fS = 30MHz, fIN = 4MHz
-
31
-
-
-
dB
Signal to Noise Ratio, SINAD
fS = 1MHz, fIN = 100kHz
-
35
-
-
-
dB
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
fS = 30MHz, fIN = 4MHz
-
30
-
-
-
dB
Total Harmonic Distortion
fS = 1MHz, fIN = 100kHz
-
-44
-
-
-
dBc
fS = 30MHz, fIN = 4MHz
-
-38
-
-
-
dBc
Differential Gain
fS = 14.32MHz, fIN = 3.58MHz
-
2
-
-
-
%
Differential Phase
fS = 14.32MHz, fIN = 3.58MHz
-
2
-
-
-
Degree
3
HI-5701
Electrical Specifications
VDD = +5.0V; VREF + = +4.0V; VREF- = VSS = GND; fS = Specified Clock Frequency at 50% Duty Cycle;
CL = 30pF; Unless Otherwise Specified (Continued)
(NOTE 3)
0oC TO 70oC
-40oC TO 85oC
25oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ANALOG INPUTS
Analog Input Resistance, RIN
VIN = 4V
-
30
-
-
-
MΩ
Analog Input Capacitance, CIN
VIN = 0V
-
20
-
-
-
pF
Analog Input Bias Current, IB
VIN = 0V, 4V
-
0.01
±1.0
-
±1.0
µA
250
370
-
235
-
Ω
-
+0.266
-
-
-
Ω/oC
Input Logic High Voltage, VIH
2.0
-
-
2.0
-
V
Input Logic Low Voltage, VIL
-
-
0.8
-
0.8
V
REFERENCE INPUTS
Total Reference Resistance, RL
Reference Resistance Tempco, TC
DIGITAL INPUTS
Input Logic High Current, IIH
VIN = 5V
-
-
1.0
-
1.0
µA
Input Logic Low Current, IIL
VIN = 0V
-
-
1.0
-
1.0
µA
-
7
-
-
-
pF
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic Sink Current, IOL
VO = 0.4V
3.2
-
-
3.2
-
mA
Output Logic Source Current, IOH
VO = 4.5V
-3.2
-
-
-3.2
-
mA
Output Leakage, IOFF
CE2 = 0V
-
-
±1.0
-
±1.0
µA
Output Capacitance, COUT
CE2 = 0V
-
5.0
-
-
-
pF
Aperture Delay, tAP
-
6
-
-
-
ns
Aperture Jitter, tAJ
-
30
-
-
-
ps
TIMING CHARACTERISTICS
Data Output Enable Time, tEN
(Note 3)
-
12
20
-
20
ns
Data Output Disable Time, tDIS
(Note 3)
-
11
20
-
20
ns
Data Output Delay, tOD
(Note 3)
-
14
20
-
20
ns
Data Output Hold, tH
(Note 3)
5
10
-
5
-
ns
Offset Error PSRR, ∆VOS
VDD = 5V ±10%
-
±0.1
±1.0
-
±1.5
LSB
Gain Error PSRR, ∆FSE
VDD = 5V ±10%
-
±0.1
±1.0
-
±1.5
LSB
fS = 20MHz
-
50
60
-
75
mA
POWER SUPPLY REJECTION
POWER SUPPLY CURRENT
Supply Current, IDD
NOTE:
3. Parameter guaranteed by design or characterization and not production tested.
4
HI-5701
Timing Waveforms
COMPARATOR DATA
IS LATCHED
CLOCK
INPUT
PHASE - HIGH
CLOCK
INPUT
PHASE - LOW
φ1
φ2
SAMPLE
N-2
φ1
φ2
AUTO
BALANCE
tAB
SAMPLE
N-1
tS
φ1
φ2
AUTO
BALANCE
ANALOG
INPUT
SAMPLE
N
φ1
φ2
AUTO
BALANCE
SAMPLE
N+1
ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
AUTO
BALANCE
φ2
SAMPLE
N+2
tAP
tH
tAJ
tOD
DATA
OUTPUT
DATA N - 4
DATA N - 3
DATA N - 2
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
tDIS
D0 - D5
tEN
HIGH
DATA
IMPEDANCE
OVF
DATA
tEN
tDIS
DATA
HIGH
DATA
IMPEDANCE
HIGH
DATA
IMPEDANCE
FIGURE 2. OUTPUT ENABLE TIMING
5
DATA N - 1
DATA N
HI-5701
Typical Performance Curves
6
6
fS = 1MHz, fIN = 100kHz
EFFECTIVE BITS
EFFECTIVE BITS
fS = 20MHz
5
fS = 30MHz
fS = 40MHz
4
5
fS = 30MHz, fIN = 4MHz
4
VDD = 5V, VREF + = 4V
TA = 25oC
VDD = 5V, VREF + = 4V
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
3
5
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (oC)
INPUT FREQUENCY (fIN) - MHz
FIGURE 3. EFFECTIVE NUMBER OF BITS vs fIN
FIGURE 4. ENOB vs TEMPERATURE
38
-34
VDD = 5V, VREF + = 4V
fS = 1MHz, fIN = 100kHz
36
fS = 30MHz, fIN = 4MHz
-36
34
fS = 30MHz, fIN = 4MHz
-38
VDD = 5V, VREF + = 4V
dB
dBc
32
30
-40
-42
28
fS = 1MHz, fIN = 100kHz
-44
26
24
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
-46
-40 -30 -20 -10
90
0
TEMPERATURE (oC)
FIGURE 5. SNR vs TEMPERATURE
20
30
40
50
60
70
80
90
FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE
2
1
fIN = 100kHz
VDD = 5V, VREF + = 4V
fIN = 100kHz
VDD = 5V, VREF + = 4V
1.5
0.75
fS = 30MHz
LSBs
LSBs
10
TEMPERATURE (oC)
1
0.5
fS = 30MHz
0.5
0.25
fS = 1MHz
fS = 1MHz
0
-40 -30 -20 -10
0
10
20
30
40
50
60
TEMPERATURE (oC)
FIGURE 7. INL vs TEMPERATURE
6
70
80
90
0
-40 -30 -20 -10
0
10
20
30
40
50
60
TEMPERATURE (oC)
FIGURE 8. DNL vs TEMPERATURE
70
80
90
HI-5701
Typical Performance Curves
(Continued)
1
60
VDD = 5V ±10%, VREF + = 4V
55
VDD = 5V, VREF + = 4V
50
0.5
45
IDD (mA)
LSBs
PSRR VOS
0
PSRR FSE
fS = 20MHz
40
35
30
25
-0.5
fS = 1MHz
20
15
-1
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
10
-40
90
-20
TEMPERATURE (oC)
100
fI = 1MHz
5.0
EFFECTIVE BITS
IDD (mA)
80
5.5
D = 50%
45
D = 25%
t AB
D = -----------------------t AB + t S
30
D = 10%
25
4.5
4.0
3.5
3.0
2.5
20
2.0
15
10
0.1
60
6.0
VDD = 5V, VREF + = 4V
TA = 25oC
50
35
40
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
60
40
20
TEMPERATURE (oC)
FIGURE 9. POWER SUPPLY REJECTION vs TEMPERATURE
55
0
1.5
1
10
100
CLOCK FREQUENCY (MHz)
FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE
7
30
40
50
CLOCK FREQUENCY (MHz)
FIGURE 12. EFFECTIVE NUMBER OF BITS vs CLOCK
FREQUENCY
60
HI-5701
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.
TABLE 1. PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
1
D5
Bit 6, Output (MSB).
2
OVF
Overflow, Output.
3
VSS
Digital Ground.
4
NC
No Connection.
5
CE2
Three-State Output Enable Input, Active
High (See Table 2).
6
CE1
Three-State Output Enable Input, Active
Low (See Table 2).
7
CLK
Clock Input.
8
PHASE
Sample Clock Phase Control Input. When
Phase is Low, Sample Unknown (φ1) Occurs When the Clock is Low and Auto Balance (φ2) Occurs When the Clock is High
(See Text).
9
VREF +
Reference Voltage Positive Input.
10
VREF -
Reference Voltage Negative Input.
11
VIN
Analog Signal Input.
12
VDD
Power Supply, +5V.
13
D0
Bit 1, Output (LSB).
14
D1
Bit 2, Output.
15
D2
Bit 3, Output.
16
1/ R2
2
Reference Ladder Midpoint.
17
D3
Bit 4, Output.
18
D4
Bit 5, Output.
TABLE 2. CHIP ENABLE TRUTH TABLE
D0 - D5
CE1
CE2
OVF
0
1
Valid
Valid
1
1
Three-State
Valid
X
0
Three-State
Three-State
X = Don’t Care
Theory of Operation
The HI-5701 is a 6-bit analog-to-digital converter based on a
parallel CMOS “flash” architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.
The CMOS HI-5701 works by alternately switching between
a “Sample” mode and an “Auto Balance” mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
8
The input clock which controls the operation of the HI-5701
is first split into a non-inverting φ1 clock and an inverting φ2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.
In the “Auto Balance” mode (φ1), all φ1 switches close and
φ2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between VSS and VDD and presenting a low
impedance to a small input capacitor. Each capacitor, in
turn, is connected to a reference voltage tap from the
resistor ladder. The Auto Balance mode quickly precharges
all 64 input capacitors between the self-bias voltage and
each respective tap voltage.
In the “Sample” mode (φ2), all φ1 switches open and φ2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The φ2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during φ1 will push comparator inputs higher than the
self bias voltage at φ2; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a “low”
voltage at comparator inputs; those precharged below the
input voltage force “high” inputs at the comparators.
During the next φ1 state, comparator output data is latched
into the encoder logic block and the first stage of encoding
takes place. The following φ2 state completes the encoding
process. The 6 data bits (plus overflow bit) are latched into
the output flip-flops at the next falling clock edge. The
Overflow bit is set if the input voltage exceeds VREF + - 1/2
LSB. The output bus may be either enabled or disabled
according to the state of CE1 and CE2 (See Table 2). When
disabled, output bits assume a high impedance state.
As shown in the timing diagram, the digital output word
becomes valid after the second φ1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. “Data Output Delay” time indicates the slight
time delay for data to become valid at the end of the φ1 state.
Refer to the Glossary of Terms for other definitions.
HI-5701
D5
OVF
VSS
D4
DATA
OUPUT
D3
1/2R
NC
D2
+5V
CE2
CE1
D1
D0
VDD
+5V
10µF
0.01µF
CLOCK
INPUT
CLK
+9V to +12V
50Ω
0.01µF
PHASE
VIN
100Ω
VREF+
+4V
10µF
10µF
50Ω
HA-5033
ANALOG
SIGNAL
INPUT
VREF-
0.01µF
0.01µF
10µF
-9V to -12V
FIGURE 13. TEST CIRCUIT
Application Information
Voltage Reference
The reference voltage is applied across the resistor ladder at
the input of the converter, between VREF + and VREF -. In
most applications, VREF - is simply tied to analog ground
such that the reference source drives VREF +. The reference
must be capable of supplying enough current to drive the
minimum ladder resistance of 235Ω over temperature.
The HI-5701 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the VDD supply. In the
case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
(VREF + -VREF )/64, or 62.5mV. Reducing the reference
voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2V. Because the reference voltage terminals
are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01µF and 10µF) capacitors near
the package pin are recommended. It is not necessary to
decouple the 1/2R tap point pin for most applications.
It is possible to elevate VREF - from ground if necessary. In
this case, the VREF - pin must be driven from a low
impedance reference capable of sinking the current through
the resistor ladder. Careful decoupling is again
recommended.
clock and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits D0 through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, and output bits D0
through D5 are independently controlled by CE1.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance φ1 half cycle of the clock may be reduced to 16ns;
the Sample φ2 half cycle may be varied from a minimum of
16ns to a maximum of 8µs.
TABLE 3. PHASE CONTROL
CLOCK
PHASE
INTERNAL GENERATION
0
0
Sample Unknown (φ2)
0
1
Auto Balance (φ1)
1
0
Auto Balance (φ1)
1
1
Sample Unknown (φ2)
Digital Control and Interface
Gain and Offset Adjustment
The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs
are provided to control the function of the converter. The
In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
9
HI-5701
Signal Source
midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.
A current pulse is present at the analog input (VIN) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.
Offset Adjustment
The preferred offset correction method is to introduce a DC
component to VIN of the converter. An alternate method is to
adjust the VREF - input to produce the desired offset
adjustment. The theoretical input voltage to produce the first
transition is 1/2 LSB.
The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a
valid signal for conversion. Suitable broad band amplifiers or
buffers which exhibit low output impedance and high output
drive include the HFA-0005, HA-5004, HA-5002, and HA5033.
VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128.
Gain Adjustment
In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the VREF + input voltage. This
adjustment is performed by setting VIN to the 63 to overflow
transition. The theoretical input voltage to produce the
transition is 1/2 LSB less than VREF + and is calculated as
follows:
The signal source may drive above or below the power
supply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +1/2 LSB are
converted to all zeros; input voltages of VREF + - 1/2 LSB to
VDD + 0.5 are converted to all ones with the Overflow bit set.
Power Supply
VIN (63 to 64 transition) = VREF - (VREF /128)
= VREF (127/128).
The HI-5701 operates nominally from a 5V supply, but will
function from 3V to 6V. The supply should be well regulated
and “clean” of significant noise, especially high frequency
noise. It is recommended that power supply decoupling
capacitors be placed as close to the supply pin as possible.
A combination of 0.01µF ceramic and 10µF tantalum
capacitors is recommended for this purpose as shown in the
test circuit Figure 13.
To perform the gain trim, first do the offset trim and then
apply the required VIN for the 63 to overflow transition. Now
adjust VREF + until that transition occurs on the outputs.
Midpoint Trim
The reference center (1/2R) is available to the user as the
midpoint of the resistor ladder. The 1/2 R point can be used
to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31.5 LSBs. That voltage is calculated as follows:
Reducing Power Consumption
Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle. For a fixed 50% clock duty cycle, power
may be reduced by lowering the clock frequency. For a given
conversion frequency, power may be reduced by shortening
the Auto Balance φ1 portion of the clock duty cycle.
VIN (31 to 32 transition) = 31.5(VREF/64) = VREF(63/128).
An adjustable voltage follower can be used to drive the 1/2 R
pin. Set VIN to the 31 to 32 transition voltage, then adjust the
voltage follower until the transition occurs on the output bits.
TABLE 4. OUTPUT CODE TABLE
BINARY OUTPUT CODE
CODE
DESCRIPTION
INPUT VOLTAGE†
VREF + = 4V
VREF - = 0V
(V)
DECIMAL
COUNT
OVF
D5
D4
D3
D2
D1
D0
Overflow (OVF)
4.000
127
1
1
1
1
1
1
1
Full Scale (FS)
3.9063
63
0
1
1
1
1
1
1
FS - 1 LSB
3.8438
•
•
62
0
1
1
1
•
•
•
1
1
0
3/ FS
4
2.9688
•
•
•
48
0
1
1
0
•
•
•
0
0
0
10
MSB
LSB
HI-5701
TABLE 4. OUTPUT CODE TABLE (Continued)
CODE
DESCRIPTION
INPUT VOLTAGE†
VREF + = 4V
VREF - = 0V
(V)
BINARY OUTPUT CODE
MSB
LSB
DECIMAL
COUNT
OVF
D5
D4
D3
D2
D1
D0
1/ FS
2
1.9688
•
•
•
32
0
1
0
0
•
•
•
0
0
0
1/ FS
4
0.9688
•
•
•
16
0
0
1
0
•
•
•
0
0
0
1 LSB
0.0313
1
0
0
0
0
0
0
1
Zero
0
0
0
0
0
0
0
0
0
† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
Glossary of Terms
Aperture Delay - is The time delay between the external
sample command (the rising edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter, tAJ - This is the RMS variation in the
aperture delay due to variation of internal φ1 and φ2 clock
path delays and variation between the individual comparator
switching times.
Differential Linearity Error, DNL - The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1 LSB. The range of values possible is from
-1 LSB (which implies a missing code) to greater than
+1 LSB.
Full Power Input Bandwidth - Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude
of an input sine wave. The input sine wave has a peak-topeak amplitude equal to the reference voltage. The
bandwidth given is measured at the specified sampling
frequency.
Full Scale Error, FSE - is The difference between the actual
input voltage of the 63 to 64 code transition and the ideal
value of VREF + - 1.5 LSB. This error is expressed in LSBs.
Integral Linearity Error, INL - The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter’s
transfer function.
LSB - Least Significant Bit = (VREF + - VREF -)/64. All
HI-5701 specifications are given for a 62.5mV LSB size
VREF + = 4V, VREF - = 0V.
11
Offset Error, VOS - Offset error is the difference between
the actual input voltage of the 0 to 1 code transition and the
ideal value of VREF - + 0.5 LSB. VOS error is expressed in
LSBs.
Power Supply Rejection Ratio, PSRR - Is expressed in
LSBs and is the maximum shift in code transition points due
to a power supply voltage shift. This is measured at the 0 to
1 code transition point and the 62 to 63 code transition point
with a power supply voltage shift from the nominal value of
5.0V.
Signal to Noise Ratio, SNR - SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.
Signal to Noise and Distortion Ratio, SINAD - Is the ratio
in dB of the RMS signal to the RMS sum of the noise and
harmonic distortion at specified input and sampling
frequencies.
Total Harmonic Distortion, THD - Is the ratio in dBc of the
RMS sum of the first five harmonic components to the RMS
signal for a specified input and sampling frequency
HI-5701
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
<2.0 x 105 A/cm2
86.6 mils x 130.7 mils x 19 mils ±1 mil
TRANSISTOR COUNT:
METALLIZATION:
4000
Type: SiAl
Thickness: 11kÅ ±1kÅ
SUBSTRATE POTENTIAL (POWERED UP):
PASSIVATION:
V+
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
(17) D3
(18) D4
(1) D5
(3) VSS
(2) OVF
HI-5701
VSS (3)
(16) 1/2 R
(15) D2
CE2 (5)
(14) D1
(13) D0
(12) VDD
12
VDD (12)
VIN (11)
VREF- (10)
VREF+ (9)
PHASE (8)
CLK (7)
CE1 (6)
HI-5701
Dual-In-Line Plastic Packages (PDIP)
N
E18.3 (JEDEC MS-001-BC ISSUE D)
E1
INDEX
AREA
1 2 3
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be
perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
13
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.845
0.880
21.47
D1
0.005
-
0.13
22.35
-
5
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
18
18
9
Rev. 0 12/93
HI-5701
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
H
0.25(0.010) M
M18.3 (JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4469
0.4625
11.35
11.75
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
MAX
A1
e
A1
MIN
α
18
0o
18
7
8o
Rev. 0 12/93
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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14
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