PCF8553
40 × 4 LCD segment driver
Rev. 3 — 27 March 2015
Product data sheet
1. General description
PCF8553 is an ultra low-power LCD segment driver with 4 backplane- and 40
segment-driver outputs, with either an I2C- or an SPI-bus interface. It comprises an
internal oscillator, bias generation, instruction decoding, and display controller.
For a selection of NXP LCD segment drivers, see Table 24 on page 45.
2. Features and benefits
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with buffers
40 segment drives:
Up to 20 7-segment numeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 segments/elements
Auto-incrementing display data and instruction loading
Versatile blinking modes
Independent supplies of VLCD and VDD
Power supply ranges:
1.8 V to 5.5 V for VLCD
1.8 V to 5.5 V for VDD
Ultra low-power consumption
400 kHz I2C-bus interface
5 MHz SPI-bus interface
Internally generated or externally supplied clock signal
3. Applications
Metering equipment
Small appliances
Consumer healthcare devices
Battery operated devices
Measuring equipment
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCF8553DTT
Name
Description
Version
TSSOP56
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
SOT364-1
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF8553DTT/A
PCF8553DTT/AJ
tape and reel, 13 inch
1
935304762118
5. Marking
Table 3.
PCF8553
Product data sheet
Marking codes
Type number
Marking code
PCF8553DTT/A
PCF8553D
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
6. Block diagram
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PCF8553
Product data sheet
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Block diagram of PCF8553
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
7. Pinning information
7.1 Pinning
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Fig 2.
PCF8553
Product data sheet
Pin configuration of PCF8553DTT (TSSOP56)
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
7.2 Pin description
Table 4.
Pin description of PCF8553DTT (TSSOP56)
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
Backplane and segment outputs
SEG34 to SEG39 1 to 6
output
LCD segments
7 to 10
output
LCD backplanes
VLCD
11
supply
LCD supply voltage
VDD
12
supply
supply voltage
VSS
14
supply
ground supply
SEG0 to SEG33
23 to 56
COM0 to COM3
Supply pins
Clock and control pins
RST
15
input
reset input, active LOW
PORE[1]
21
input
Power-On Reset (POR) enable
•
•
CLK
18
connect to VSS (or leave open) for disabling POR
input/output internal oscillator output, external oscillator input
•
must be left open if unused
I2C-bus
Bus-related pins
IFS[1]
connect to VDD for enabling POR
13
input
SPI-bus
interface selector input
•
connect to VSS (or leave open)
•
connect to VDD
SDIO
16
input/output unused
serial data input/output
A0[1]
17
input
unused
A1[1]
22
input
hardware device address selection;
•
connect to VSS (or leave open) for
logic 0
•
connect to VDD for logic 1
SCL
19
input
SDA/CE
20
input/output serial data output
[1]
serial clock input
serial clock input
chip enable input, active LOW
A series resistance between VDD and the pin must not exceed 1 k to ensure proper functionality, see Section 16.3.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
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5 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
8. Functional description
8.1 Registers of the PCF8553
The registers of the PCF8553 are arranged in bytes with 8 bit, addressed by an address
pointer. Table 5 depicts the layout.
Table 5.
Registers of the PCF8553
Bits labeled as 0 must always be written with logic 0.
Register name
Address Bits
AP[4:0]
7
Reference
6
5
4
3
2
1
0
Command registers
Software_reset
00h
SR[7:0]
Device_ctrl
01h
0
0
0
0
FF[1:0]
OSC
COE
Table 6
Display_ctrl_1
02h
0
0
0
BOOST
MUX[1:0]
B
DE
Table 7
Display_ctrl_2
03h
0
0
0
0
0
BL[1:0]
INV
Table 8
04h
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Table 10
05h
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
06h
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
07h
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
08h
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
09h
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
:
:
:
:
:
:
:
:
:
Display data
registers[1]
COM0
COM1
COM2
COM3
[1]
Table 9
0Dh
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
0Eh
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
:
:
:
:
:
:
:
:
:
12h
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
13h
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
:
:
:
:
:
:
:
:
:
17h
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
See Table 10.
For writing to the registers, send the address byte first, then write the data to the register
(see Section 11.1.4 and Section 11.2.1). The address byte works as an address pointer.
For the succeeding registers, the address pointer is automatically incremented by 1 (see
Figure 3) and all following data are written into these register addresses. After register
17h, the auto-incrementing will stop and data are ignored.
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
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Address counter incrementing
8.2 Command registers of the PCF8553
8.2.1 Command: Device_ctrl
The Device_ctrl command sets the device into a defined state. It should be executed
before enabling the display (see bit DE in Table 7).
Table 6.
Device_ctrl - device control command register (address 01h) bit description
Bit
Symbol
Value
Description
7 to 4
-
0000
default value
3 to 2
FF[1:0]
frame frequency selection
00
1
0
ffr = 32 Hz
01[1]
ffr = 64 Hz
10
ffr = 96 Hz
11
ffr = 128 Hz
OSC
internal oscillator control
0[1]
enabled
1
disabled
COE
clock output enable
0[1]
clock signal not available on pin CLK;
pin CLK is in 3-state
1
[1]
8.2.1.1
clock signal available on pin CLK
Default value.
Internal oscillator and clock output
Bit OSC enables or disables the internal oscillator. When the internal oscillator is used, bit
COE allows making the clock signal available on pin CLK. If this is not intended, pin CLK
should be left open. The design ensures that the duty cycle of the clock output is 50 : 50
(% HIGH-level time : % LOW-level time).
In applications where an external clock has to be applied to the PCF8553, bit OSC must
be set logic 1 and COE logic 0. In this case pin CLK becomes an input.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
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7 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
In power-down mode (see Section 8.3.1)
• if pin CLK is configured as an output, there is no signal on CLK
• if pin CLK is configured as an input, the signal on CLK can be removed.
Remark: A clock signal must always be supplied to the device if the display is enabled
(see bit DE in Table 7 on page 8). Removing the clock may freeze the LCD in a DC state,
which is not suitable for the liquid crystal.
8.2.2 Command: Display_ctrl_1
The Display_ctrl_1 command allows configuring the basic display set-up.
Table 7.
Display_ctrl_1 - display control command 1 register (address 02h) bit description
Bit
Symbol
Value
Description
7 to 5
-
000
default value
4
BOOST
3 to 2
1
0
8.2.2.1
large display mode support
0[1]
standard power drive scheme
1
enhanced power drive scheme for higher display
loads
MUX[1:0]
multiplex drive mode selection
00[1]
1:4 multiplex drive mode; COM0 to COM3
(nMUX = 4)
01
1:3 multiplex drive mode; COM0 to COM2
(nMUX = 3)
10
1:2 multiplex drive mode; COM0 and COM1
(nMUX = 2)
11
static drive mode; COM0 (nMUX = 1)
B[2]
bias mode selection
0[1]
1⁄
3
bias (abias = 2)
1
1⁄
2
bias (abias = 1)
display enable[3]
DE
0[1]
display disabled; device is in power-down mode
1
display enabled; device is in power-on mode
[1]
Default value.
[2]
Not applicable for static drive mode.
[3]
See Section 8.3.1.
Enhanced power drive mode
By setting the BOOST bit to logic 1, the driving capability of the display signals is
increased to cope with large displays with a higher effective capacitance. Setting this bit
increases the current consumption on VLCD.
8.2.2.2
Multiplex drive mode
MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals,
which are active. For further details, see Section 9.2 on page 16.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
8.2.3 Command: Display_ctrl_2
Table 8.
Display_ctrl_2 - display control command 2 register (address 03h) bit description
Bit
Symbol
Value
Description
7 to 3
-
00000
default value
2 to 1
BL[1:0]
blink control
00[1]
blinking off
01
blinking on, fblink = 0.5 Hz
10
blinking on, fblink = 1 Hz
11
0
[1]
8.2.3.1
INV
blinking on, fblink = 2 Hz
inversion mode selection
0[1]
line inversion (driving scheme A)
1
frame inversion (driving scheme B)
Default value.
Blinking
The whole display blinks at frequencies selected by the blink control bits BL[1:0], see
Table 8. The blink frequencies are derived from the clock frequency. During the blank-out
phase of the blinking period, the display is turned off.
If an external clock with frequency fclk(ext) is used, the blinking frequency is determined by
Equation 1. For notation, see Section 9.2.
2 n MUX f fr f blink
f blink eff = ----------------------------------------------------f clk ext
8.2.3.2
(1)
Line inversion (driving scheme A) and frame inversion (driving scheme B)
The waveforms used to drive LCD inherently produce a DC voltage across the display
cell. The PCF8553 compensates for the DC voltage by inverting the waveforms on
alternate frames or alternate lines. The choice of compensation method is determined
with the INV bit.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
8.3 Starting and resetting the PCF8553
If the internal Power-On Reset (POR) is enabled by connecting pin PORE to VDD, the chip
resets automatically when VDD rises above the minimum supply voltage. No further action
is required.
If the internal POR is disabled by connecting pin PORE to VSS, the chip must be reset by
driving the RST pin to logic 0 for at least 10 s, see Figure 4.
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Reset pulse timing
Alternatively a software reset can be applied (see Section 8.3.4).
Following a reset, the register 00h has to be rewritten with 0h by the next command byte
or the address pointer AP[4:0] has to be set to the required address after a new START
procedure.
8.3.1 Power-down mode
After a reset, the PCF8553 remains in power-down mode. In power-down mode the
oscillator is switched off and there is no output on pin CLK. The register settings remain
unchanged and the bus remains active. To enable the PCF8553, bit DE (command
Display_ctrl_1, see Table 7 on page 8) must be set to logic 1.
8.3.2 Power-On Reset (POR)
If pin PORE is connected to VDD, the PCF8553 comprises an internal POR, which puts the
device into the following starting conditions:
•
•
•
•
•
•
All backplane and segment outputs are set to VSS
The selected drive mode is: 1:4 multiplex with 1⁄3 bias
Blinking is switched off
The address pointer is cleared (set to logic 0)
The display and the internal oscillator are disabled
The display registers are set to logic 0
Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this case,
the internal registers are not defined and require a hardware reset according to
Section 8.3.3 or a software reset, see Section 8.3.4.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
8.3.3 Hardware reset: RST pin
At power-on the PCF8553 can be reset to the following starting conditions by pulling pin
RST low:
•
•
•
•
•
•
•
All backplane and segment outputs are set to VSS
The selected drive mode is: 1:4 multiplex with 1⁄3 bias
Blinking is switched off
The bus interface is initialized
The address pointer is cleared (set to logic 0)
The display and the internal oscillator are disabled
The display registers are set to logic 0
Remark: The hardware reset overrides the POR see Section 8.3.2.
8.3.4 Command: Software_reset
The internal registers including the display registers and the address pointer (set to
logic 0) of the device are reset by the Software_reset command.
Table 9.
Software_reset - software reset command register (address 00h) bit description
Bit
Symbol
7 to 0
SR[7:0]
[1]
Value
Description
software reset
00000000[1]
no reset
00101100
software reset
Default value.
8.4 Display data register mapping
The example in Table 10 and Figure 5 illustrates the segment and backplane mapping of
the display in relation to the display RAM.
For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to
COM3 and the segments are driven by signals SEG0 to SEG39. Contents of addresses
04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost
element and moving forward to the right with increasing bit position. If a bit is logic 0, the
element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB
left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve
COM2 signals, and addresses 13h to 17h serve COM3 signals.
For displays with fewer segments/elements the unused bits are ignored.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
Table 10.
Register to segment and backplane mapping
Backplanes[1] Segments
SEG0 to SEG7
SEG8 to SEG15
SEG16 to SEG23
SEG24 to SEG31
SEG32 to SEG39
LSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
MSB
1:4 multiplex drive mode
COM0
content of 04h
content of 05h
content of 06h
content of 07h
content of 08h
COM1
content of 09h
content of 0Ah
content of 0Bh
content of 0Ch
content of 0Dh
COM2
content of 0Eh
content of 0Fh
content of 10h
content of 11h
content of 12h
COM3
content of 13h
content of 14h
content of 15h
content of 16h
content of 17h
content of 07h
content of 08h
1:3 multiplex drive mode
COM0
content of 04h
content of 05h
content of 06h
COM1
content of 09h
content of 0Ah
content of 0Bh
content of 0Ch
content of 0Dh
COM2
content of 0Eh
content of 0Fh
content of 10h
content of 11h
content of 12h
1:2 multiplex drive mode
COM0
content of 04h
content of 05h
content of 06h
content of 07h
content of 08h
COM1
content of 09h
content of 0Ah
content of 0Bh
content of 0Ch
content of 0Dh
content of 05h
content of 06h
content of 07h
content of 08h
static drive mode
COM0
[1]
content of 04h
See also Section 9.3.1 on page 24.
PCF8553
Product data sheet
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Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 55
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Rev. 3 — 27 March 2015
All information provided in this document is subject to legal disclaimers.
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Display RAM organization bitmap for MUX 1:4
40 × 4 LCD segment driver
13 of 55
© NXP Semiconductors N.V. 2015. All rights reserved.
Fig 5.
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
9. Possible display configurations
The possible display configurations of the PCF8553 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 11. All
of these configurations can be implemented in the typical systems shown in Figure 7 or
Figure 8.
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Example of displays suitable for PCF8553
Table 11.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
PCF8553
Product data sheet
14-segment[2]
Dot matrix:
segments/
elements
4
160
20
10
160 dots (4 40)
3
120
15
7
120 (3 40)
2
80
10
5
80 dots (2 40)
1
40
5
2
40 dots (1 40)
[1]
7 segment display has 8 segments/elements including the decimal point.
[2]
14 segment display has 16 segments/elements including decimal point and accent dot.
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Rev. 3 — 27 March 2015
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14 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
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The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least
100 nF is recommended for the supplies.
Fig 7.
Typical system configuration using I2C-bus, internal power-on reset enabled
The host microcontroller manages the 2-line I2C-bus communication channel with the
PCF8553. The internal oscillator is used and the internal POR is enabled in the example.
The appropriate biasing voltages for the multiplexed LCD waveforms are generated
internally. The only other connections required to complete the system are the reset, the
power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application.
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The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least
100 nF is recommended for the supplies.
Fig 8.
Typical system configuration using SPI-bus, internal power-on reset disabled
The host microcontroller manages the 3-line SPI-bus communication channel with the
PCF8553. The internal oscillator is enabled. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally. The only other connections required
to complete the system are reset, the power supplies (VDD, VSS, and VLCD) and the LCD
panel chosen for the application.
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
9.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between VLCD and VSS. These intermediate levels are tapped off
at positions of 1⁄3 and 2⁄3, or 1⁄2, depending on the bias mode chosen. To keep current
consumption to a minimum, on-chip low-power buffers provide these levels to the display.
9.2 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
Display_ctrl_1 command (see Table 7). The biasing configurations that apply to the
preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 12.
Table 12.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off RMS
------------------------V LCD
V on RMS
-----------------------V LCD
static
V on RMS
D = -----------------------V off RMS
1
2
static
0
1
1:2 multiplex 2
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:3 multiplex 3
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated with Equation 2
1
--------------------1 + a bias
(2)
The values for abias are:
abias = 1 for 1⁄2 bias
abias = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3:
V on RMS =
V LCD
2
a bias
+ 2a bias + n MUX
---------------------------------------------------2
n MUX 1 + a bias
(3)
where the values for n are
nMUX = 1 for static drive mode
nMUX = 2 for 1:2 multiplex drive mode
nMUX = 3 for 1:3 multiplex drive mode
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40 × 4 LCD segment driver
nMUX = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 4:
V off RMS =
V LCD
2 –2 a
a bias
bias + n MUX
-------------------------------------------------2
n MUX 1 + a bias
(4)
Discrimination is a term which is defined as the ratio of the on and off RMS voltages
(Von(RMS) to Voff(RMS)) across a segment. It can be thought of as a measurement of
contrast. Discrimination is determined from Equation 5:
V on RMS
D = ----------------------- =
V off RMS
2
a bias + 2a bias + n MUX
-----------------------------------------------------2
a bias – 2a bias + n MUX
(5)
Using Equation 5, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 V off RMS = 2.449V off RMS
4 3
- = 2.309V off RMS
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off RMS when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
9.2.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 9. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(6)
V off RMS V th off
(7)
Von(RMS) (see Equation 3) and Voff(RMS) (see Equation 5) are properties of the display
driver and are affected by the selection of abias, nMUX, and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
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It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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PCF8553
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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40 × 4 LCD segment driver
9.2.2 LCD drive mode waveforms
9.2.2.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (COMn) and segment (SEGn) drive waveforms for this mode are shown in
Figure 10.
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Vstate1(t) = VSEGn(t) VCOM0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(SEGn + 1)(t) VCOM0(t).
Voff(RMS) = 0 V.
Fig 10. Static drive mode waveforms
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40 × 4 LCD segment driver
9.2.2.2
1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8553 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 11 and
Figure 12.
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Vstate1(t) = VSEGn(t) VCOM0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSEGn(t) VCOM1(t).
Voff(RMS) = 0.354VLCD.
Fig 11. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8553
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
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Vstate1(t) = VSEGn(t) VCOM0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSEGn(t) VCOM1(t).
Voff(RMS) = 0.333VLCD.
Fig 12. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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NXP Semiconductors
40 × 4 LCD segment driver
9.2.2.3
1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 13.
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Vstate1(t) = VSEGn(t) VCOM0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSEGn(t) VCOM1(t).
Voff(RMS) = 0.333VLCD.
Fig 13. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
9.2.2.4
1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 14.
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Vstate1(t) = VSEGn(t) VCOM0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSEGn(t) VCOM1(t).
Voff(RMS) = 0.333VLCD.
Fig 14. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
9.3 Backplane and segment outputs
9.3.1 Backplane outputs
The LCD drive section includes four backplane outputs COM0 to COM3, which must be
directly connected to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, COM3 carries the same signal as COM1, therefore these
two outputs can be tied together to give enhanced drive capabilities
• In 1:2 multiplex drive mode, COM0 and COM2, respectively, COM1 and COM3 all
carry the same signals and may also be paired to increase the drive capabilities
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements
9.3.2 Segment outputs
The LCD drive section includes 40 segment outputs SEG0 to SEG39, which must be
directly connected to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display registers.
When less than 39 segment outputs are required, the unused segment outputs must be
left open-circuit.
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40 × 4 LCD segment driver
10. Power Sequencing
10.1 Power-on
To avoid unwanted artifacts on the display, VLCD must never be asserted before VDD, it is
permitted to assert VDD and VLCD at the same time.
10.2 Power-off
Before turning the power to the device off, the display must be disabled by setting bit DE
to logic 0. To avoid unwanted artifacts on the display, VLCD must never be connected,
while VDD is switched off. It is permitted to switch off VDD and VLCD simultaneously.
10.3 Power sequences
Figure 15 depicts the recommended power-up and power-off sequence.
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(1) Can be simultaneous with VDD.
(2) Can be simultaneous with VLCD.
Fig 15. Recommended power-up and power-off sequence
PCF8553
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40 × 4 LCD segment driver
11. Bus interfaces
11.1 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs. The two
lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy. Both data and clock lines remain HIGH when the bus is not
busy. The PCF8553 acts as a slave receiver when being written to and as a slave
transmitter when being read from.
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Fig 17. I2C read and write signaling
11.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
are interpreted as STOP or START conditions.
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40 × 4 LCD segment driver
11.1.2 START and STOP conditions
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 17).
11.1.3 Acknowledge
Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as
logic 0. A not-acknowledge is defined as logic 1.
When written to, the slave will generate an acknowledge after the reception of each byte.
After the acknowledge, another byte may be transmitted. It is also possible to send a
STOP or START condition.
When read from, the master receiver must generate an acknowledge after the reception
of each byte. When the master receiver no longer requires bytes to be transmitted, it must
generate a not-acknowledge. After the not-acknowledge, either a STOP or START
condition must be sent.
Remark: The PCF8553 omits the not-acknowledge. After the last byte read, the end of
transmission is indicated by a STOP or START condition from the master.
A detailed description of the I2C-bus specification is given in Ref. 12 “UM10204”.
11.1.4 I2C interface protocol
The PCF8553 uses the I2C interface for data transfer. Interpretation of the data is
determined by the interface protocol.
11.1.4.1
Write protocol
After the I2C slave address is transmitted, the PCF8553 requires that the register address
pointer is defined. It can take the value 00h to 17h. Values outside of that range will result
in the transfer being ignored, however the slave will still respond with acknowledge
pulses.
After the register address has been transmitted, write data is transmitted. The minimum
number of data write bytes is 0 and the maximum number is unlimited. After each write,
the address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
•
•
•
•
•
•
•
•
PCF8553
Product data sheet
I2C START condition
I2C slave address + write
start register pointer
write data
write data
:
write data
I2C STOP condition; an I2C RE-START condition is also possible.
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40 × 4 LCD segment driver
11.1.4.2
Read protocol
When reading the PCF8553, reading starts at the current position of the address pointer.
The address pointer for read data should first be defined by a write sequence.
•
•
•
•
I2C START condition
I2C slave address + write
start address pointer
I2C STOP condition; an I2C RE-START condition is also possible.
After setting the address pointer, a read can be executed. After the I2C slave address is
transmitted, the PCF8553 will immediately output read data. After each read, the address
pointer increments by one. After address 17h, the address pointer stops incrementing at
18h.
•
•
•
•
•
11.1.4.3
I2C START condition
I2C slave address + read
read data (master sends acknowledge bit)
read data (master sends acknowledge bit)
:
I2C-bus slave address
Device selection depends on the I2C-bus slave address. Four different I2C-bus slave
addresses can be used to address the PCF8553 (see Table 13).
Table 13.
I2C slave address byte
Slave address
Bit
7
MSB
6
5
4
3
2
1
0
LSB
0
1
1
1
0
A1
A0
R/W
The least significant bit of the slave address byte is bit R/W (see Table 14).
Table 14.
R/W-bit description
R/W
Description
0
write data
1
read data
Bit 1 and bit 2 of the slave address are defined by connecting the input pins A0 and A1 to
either VSS (logic 0) or VDD (logic 1). Therefore, four instances of PCF8553 can be
distinguished on the same I2C-bus.
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40 × 4 LCD segment driver
11.2 SPI-bus interface
Data transfer to the device is made via a 3-line SPI-bus (see Table 15). There is no
dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin CE
is pulled down.
Table 15.
Serial interface
Symbol Function
Description
input[1];
CE
chip enable
SCL
serial clock input
input may be higher than VDD
SDIO
serial data input/output
input data are sampled on the rising edge of SCL,
output data are valid after the falling edge of SCL
[1]
active LOW when HIGH, the interface is reset
The chip enable must not be wired permanently LOW.
11.2.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a byte
with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal CE. The first byte
transmitted is the register address comprising of the address pointer and the R/W bit.
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Table 16.
Address byte definition
Bit
Symbol
7
R/W
6 to 5
-
4 to 0
AP[4:0]
Value
Description
data read or write selection
0
write data
1
read data
00
default value
pointer to register start address
00h to 17h
valid range; other addresses are ignored
After the register address byte, the register contents follows with the address pointer
being auto-incremented after every eighth bit sent (see Section 8.1 on page 6).
11.2.1.1
Write protocol
After the CE is set LOW, the PCF8553 requires that R/W and the register address pointer
is defined. It can take the value 00h to 17h. Values outside of that range will result in the
transfer being ignored.
After the register address has been transmitted, write data is transmitted. The minimum
number of data write bytes is 0 and the maximum number is unlimited. After each write,
the address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
PCF8553
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
•
•
•
•
•
•
•
CE set LOW
R/W = 0 and register address
write data
write data
:
write data
CE set HIGH
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Data transfers are terminated by de-asserting CE (set CE to logic 1).
Fig 19. SPI-bus write example: writing two data bytes to registers 00h and 01h
11.2.1.2
Read protocol
When reading the PCF8553, reading starts at the defined position of the address pointer.
After setting the address pointer, the read can be executed. After each read, the address
pointer increments by one. After address 17h, the address pointer stops incrementing at
18h.
•
•
•
•
•
•
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R/W = 1 and register address
read data
read data
:
CE set HIGH
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Data transfers are terminated by de-asserting CE (set CE to logic 1).
Fig 20. SPI-bus read example: reading two data bytes from registers 04h and 05h
PCF8553
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40 × 4 LCD segment driver
11.3 EMC detection
The PCF8553 is ruggedized against EMC susceptibility; however it is not possible to
cover all cases. To detect if a severe EMC event has occurred, it is possible to check the
responsiveness of the device by reading its registers.
12. Internal circuitry
6&/6'$&(
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9''
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Fig 21. Device protection diagram
13. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
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40 × 4 LCD segment driver
14. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
0.5
+6.5
V
VLCD
LCD supply voltage
0.5
+6.5
V
VI
input voltage
0.5
+6.5
V
VO
output voltage
0.5
+6.5
V
II
input current
10
+10
mA
IO
output current
10
+10
mA
IDD
supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
100
mW
Po
output power
-
100
mW
-
2000
V
VESD
electrostatic discharge
voltage
Conditions
[1]
HBM
on pins SCL and SDA/CE
-
5000
V
[2]
-
1500
V
latch-up current
[3]
-
200
mA
Tstg
storage temperature
[4]
55
+150
C
Tamb
ambient temperature
40
+85
C
on all other pins
CDM
Ilu
operating device
[1]
Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”.
[2]
Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[3]
Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
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40 × 4 LCD segment driver
15. Characteristics
Table 18. Electrical characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
1.8
-
5.5
V
IDD
supply current
-
0.6
-
A
-
1.2
2.7
A
-
3.2
4.5
A
BOOST = 0;
no display load
-
2.5
-
A
BOOST = 0;
display enabled;
display load CL = 1.6 nF
-
5.0
-
A
BOOST = 1;
display enabled;
display load CL = 1.6 nF
-
6.0
-
A
VSS
-
0.3VDD
V
0.7VDD
-
VDD
V
ffr = 64 Hz; no bus activity
VDD = 3.3 V; Tamb = 25 C
VDD = 5.5 V; Tamb = 85 C
IDD(LCD)
LCD supply current
ffr = 64 Hz; no bus activity
[1]
VLCD = 5.5 V;
Tamb = 85 C;
BOOST = 0;
no display load
VLCD = 3.3 V;
Tamb = 25 C
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
[2]
output sink current;
VOL = 0.4 V; VDD = 5 V
on pin CLK
2
-
-
mA
on pin SDIO
2
-
-
mA
on pin SDA
3
-
-
mA
IOH
HIGH-level output current
output source current;
on pins SDIO, CLK;
VOH = 4.6 V; VDD = 5 V
2
-
-
mA
IL
leakage current
any input pin except for RST
-
0
-
nA
after ESD event
500
-
+500
nA
-
100
-
k
100
-
+100
mV
-
1.5
3
k
Rpu(RST_n)
pull-up resistance on pin
RST_N
LCD outputs (pins SEG0 to SEG39 and COM0 to COM3)
Vo
output voltage variation
output resistance
Ro
VLCD = 5 V
VLCD = 5 V
[1]
For typical values, also see Figure 22 to Figure 24.
[2]
I2C pins SCL and SDA have no diode to VDD and may be driven up to 5.5 V.
[3]
Outputs measured one at a time.
PCF8553
Product data sheet
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PCF8553
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40 × 4 LCD segment driver
DDD
,''
Q$
,''/&'
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7DPE&
VDD = 5.5 V, VLCD = 5.5 V; power-down mode.
(1) IDD.
(2) IDD(LCD).
Fig 22. Typical IDD and IDD(LCD) in power-down mode as function of temperature
DDD
,''/&'
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&/Q)
Tamb = 25 C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0.
(1) Static, all segments/elements off.
(2) Static, all segments/elements on.
(3) MUX 1:2, bias level 1⁄2, all segments/elements off.
(4) MUX 1:2, bias level 1⁄2, all segments/elements on.
(5) MUX 1:3, bias level 1⁄3, all segments/elements off.
(6) MUX 1:3, bias level 1⁄3, all segments/elements on.
(7) MUX 1:4, bias level 1⁄3, all segments/elements off.
(8) MUX 1:4, bias level 1⁄3, all segments/elements on.
Fig 23. Typical IDD(LCD) as function of display load
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PCF8553
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40 × 4 LCD segment driver
DDD
,''/&'
ȝ$
IIU+]
Tamb = 25 C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0, CL = 1.6 nF.
(1) Static, all segments/elements off.
(2) Static, all segments/elements on.
(3) MUX 1:2, bias level 1⁄2, all segments/elements off.
(4) MUX 1:2, bias level 1⁄2, all segments/elements on.
(5) MUX 1:3, bias level 1⁄3, all segments/elements off.
(6) MUX 1:3, bias level 1⁄3, all segments/elements on.
(7) MUX 1:4, bias level 1⁄3, all segments/elements off.
(8) MUX 1:4, bias level 1⁄3, all segments/elements on.
Fig 24. Typical IDD(LCD) as function of ffr
Table 19. Frequency characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ffr
frame frequency
FF[1:0] = 00
-
32
-
Hz
FF[1:0] = 01
42
64
86
Hz
FF[1:0] = 10
-
96
-
Hz
Hz
FF[1:0] = 11
128
-
-
1024
-
Hz
[1]
-
-
4096
Hz
fclk(int)
internal clock frequency
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
external clock
60
-
-
s
tclk(L)
LOW-level clock time
external clock
60
-
-
s
tw(rst)
reset pulse width
on pin RST
10
-
-
s
[1]
ffr = 64 Hz, nMUX = 4
[1]
f clk int = 2 f fr n MUX or f clk ext = 2 f fr n MUX respectively (see Table 6 and Table 7).
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
DDD
IFON
+]
IIU+]
(1) nMUX = 1.
(2) nMUX = 2.
(3) nMUX = 3.
(4) nMUX = 4.
Fig 25. Relation of frame frequency (ffr), clock frequency (fclk) and multiplex-rate (nMUX)
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PCF8553
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40 × 4 LCD segment driver
Table 20. I2C-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified; all timing values are valid within the
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tr
rise time of both SDA and
SCL signals
-
-
0.3
s
tf
fall time of both SDA and
SCL signals
-
-
0.3
s
Cb
capacitive load for each
bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
[1]
fSCL = 400 kHz
on the I2C-bus
The I2C-bus interface of PCF8553 is 5 V tolerant.
PCF8553
Product data sheet
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
6'$
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Fig 26. I2C-bus timing waveforms
Table 21. SPI-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified; all timing values are valid within the
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pin SCL
fSCL
SCL clock frequency
-
-
5
MHz
tLOW
LOW period of the SCL
clock
150
-
-
ns
tHIGH
HIGH period of the SCL
clock
80
-
-
ns
tr
rise time
-
-
100
ns
tf
fall time
-
-
100
ns
Pin CE
tsu(CE_N)
CE_N set-up time
30
-
-
ns
th(CE_N)
CE_N hold time
10
-
-
ns
trec(CE_N)
CE_N recovery time
70
-
-
ns
Pin SDIO
tsu
set-up time
write data
5
-
-
ns
th
hold time
write data
50
-
-
ns
td(R)SDIO
SDIO read delay time
CL = 50 pF
-
-
150
ns
tdis(SDIO)
SDIO disable time
no load
-
-
50
ns
tt(SDI-SDO)
transition time from SDI to
SDO
write to read mode
0
-
-
ns
PCF8553
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
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E
E
E
E
E
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KLJK=
6'2
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Fig 27. SPI-bus timing waveforms
16. Application information
16.1 Power-on with a slowly starting power supply
The built-in POR block acts on the rising edge of the VDD supply voltage. It is designed to
react to fast slopes. If the system supply starts slowly, it is recommended to initiate a
software reset immediately after power-on.
16.2 I2C acknowledge after power-on
If the bus does not show an acknowledge at the first access, the command should be sent
a second time.
16.3 Resistors on I/O pins
The pins A0, A1, PORE, and IFS comprise internal, latching pull-down devices, which
keep these inputs at a low potential when left open. If an input is supposed to be at logic 0
potential, this pin can be either connected to VSS or left open.
In case a pin is supposed to be at logic 1 potential, it must be connected to VDD to avoid
any cross-current during power-up. A series resistance between VDD and the associated
pin must not exceed 1 k to ensure proper functionality.
PCF8553
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PCF8553
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40 × 4 LCD segment driver
17. Package outline
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Fig 28. Package outline SOT364-1 (TSSOP56) of PCF8553DTT
PCF8553
Product data sheet
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PCF8553
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40 × 4 LCD segment driver
18. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
19. Packing information
19.1 Tape and reel information
For tape and reel packing information, see Ref. 11 “SOT364-1_118” on page 48.
20. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
20.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
20.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
20.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
20.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 22 and 23
Table 22.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 23.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 29.
PCF8553
Product data sheet
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF8553
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PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
21. Footprint information
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Fig 30. Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCF8553DTT
PCF8553
Product data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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NXP Semiconductors
PCF8553
Product data sheet
22. Appendix
22.1 LCD segment driver selection
Table 24.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
PCA8553DTT
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
88
-
-
-
Rev. 3 — 27 March 2015
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA85134H
PCA8543AHL
60
60
-
176 -
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
PCA8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
I2C
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
PCF8537BH
44
88
-
176 276 352 -
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
Y
Y
40 to 95
TQFP64
Y
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
PCA9620H
60
120 -
240 320 480 -
2.5 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 105 I2C
LQFP80
Y
2.5 to 5.5 2.5 to 9
300[1]
Y
40 to 105
I2C
Bare die
Y
PCA9620U
60
120 -
240 320 480 -
60 to
Y
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
N
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
PCF8553
PCF8576DU
I2C
40 × 4 LCD segment driver
45 of 55
© NXP Semiconductors N.V. 2015. All rights reserved.
PCA8537AH
I2C
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Rev. 3 — 27 March 2015
All information provided in this document is subject to legal disclaimers.
[1]
Software programmable.
[2]
Hardware selectable.
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
NXP Semiconductors
PCF8553
Product data sheet
Table 24.
PCF8553
40 × 4 LCD segment driver
46 of 55
© NXP Semiconductors N.V. 2015. All rights reserved.
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
23. Abbreviations
Table 25.
PCF8553
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
DC
Direct Current
EMC
ElectroMagnetic Compatibility
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit bus
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
MUX
Multiplexer
PCB
Printed-Circuit Board
POR
Power-On Reset
RC
Resistance-Capacitance
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface-Mount Device
SPI
Serial Peripheral Interface
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
47 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
24. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10853 — ESD and EMC sensitivity of IC
[3]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[4]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9]
JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] SOT364-1_118 — TSSOP56; Reel pack; SMD, 13", packing information
[12] UM10204 — I2C-bus specification and user manual
[13] UM10569 — Store and transport requirements
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
48 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
25. Revision history
Table 26.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8553 v.3
20150327
Product data sheet
-
PCF8553 v.2
Modifications:
•
•
Fixed typo
Added Figure 4
PCF8553 v.2
20150216
Product data sheet
-
PCF8553 v.1
PCF8553 v.1
20141205
Objective data sheet
-
-
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
49 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
26. Legal information
26.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
26.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
26.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF8553
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
50 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
26.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
27. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
51 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
28. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description of PCF8553DTT (TSSOP56) . .5
Registers of the PCF8553 . . . . . . . . . . . . . . . . .6
Device_ctrl - device control command register
(address 01h) bit description . . . . . . . . . . . . . . .7
Display_ctrl_1 - display control command 1
register (address 02h) bit description . . . . . . . .8
Display_ctrl_2 - display control command 2
register (address 03h) bit description . . . . . . . .9
Software_reset - software reset command
register (address 00h) bit description . . . . . . . 11
Register to segment and backplane mapping .12
Selection of possible display configurations . . .14
Biasing characteristics . . . . . . . . . . . . . . . . . . .16
I2C slave address byte . . . . . . . . . . . . . . . . . . .28
R/W-bit description . . . . . . . . . . . . . . . . . . . . . .28
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .29
Address byte definition . . . . . . . . . . . . . . . . . . .29
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Electrical characteristics . . . . . . . . . . . . . . . . .33
Frequency characteristics . . . . . . . . . . . . . . . .35
I2C-bus characteristics . . . . . . . . . . . . . . . . . . .37
SPI-bus characteristics . . . . . . . . . . . . . . . . . .38
SnPb eutectic process (from J-STD-020D) . . .42
Lead-free process (from J-STD-020D) . . . . . .42
Selection of LCD segment drivers . . . . . . . . . .45
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47
Revision history . . . . . . . . . . . . . . . . . . . . . . . .49
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
52 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
29. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Block diagram of PCF8553 . . . . . . . . . . . . . . . . . .3
Pin configuration of PCF8553DTT (TSSOP56) . . .4
Address counter incrementing . . . . . . . . . . . . . . . .7
Reset pulse timing . . . . . . . . . . . . . . . . . . . . . . . .10
Display RAM organization bitmap for MUX 1:4 . .13
Example of displays suitable for PCF8553 . . . . .14
Typical system configuration using I2C-bus,
internal power-on reset enabled . . . . . . . . . . . . .15
Typical system configuration using SPI-bus,
internal power-on reset disabled . . . . . . . . . . . . .15
Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .18
Static drive mode waveforms . . . . . . . . . . . . . . . .19
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Recommended power-up and power-off
sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
I2C read and write protocol . . . . . . . . . . . . . . . . .26
I2C read and write signaling. . . . . . . . . . . . . . . . .26
Data transfer overview . . . . . . . . . . . . . . . . . . . . .29
SPI-bus write example: writing two data bytes
to registers 00h and 01h . . . . . . . . . . . . . . . . . . .30
SPI-bus read example: reading two data bytes
from registers 04h and 05h . . . . . . . . . . . . . . . . .30
Device protection diagram . . . . . . . . . . . . . . . . . .31
Typical IDD and IDD(LCD) in power-down mode
as function of temperature . . . . . . . . . . . . . . . . . .34
Typical IDD(LCD) as function of display load . . . . .34
Typical IDD(LCD) as function of ffr . . . . . . . . . . . . . .35
Relation of frame frequency (ffr), clock
frequency (fclk) and multiplex-rate (nMUX) . . . . . .36
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .38
SPI-bus timing waveforms . . . . . . . . . . . . . . . . .39
Package outline SOT364-1 (TSSOP56)
of PCF8553DTT. . . . . . . . . . . . . . . . . . . . . . . . . .40
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Footprint information for reflow soldering
of SOT364-1 (TSSOP56) of PCF8553DTT . . . . .44
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
53 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
30. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.1.1
8.2.2
8.2.2.1
8.2.2.2
8.2.3
8.2.3.1
8.2.3.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
9
9.1
9.2
9.2.1
9.2.2
9.2.2.1
9.2.2.2
9.2.2.3
9.2.2.4
9.3
9.3.1
9.3.2
10
10.1
10.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Registers of the PCF8553 . . . . . . . . . . . . . . . . 6
Command registers of the PCF8553 . . . . . . . . 7
Command: Device_ctrl . . . . . . . . . . . . . . . . . . . 7
Internal oscillator and clock output . . . . . . . . . . 7
Command: Display_ctrl_1. . . . . . . . . . . . . . . . . 8
Enhanced power drive mode . . . . . . . . . . . . . . 8
Multiplex drive mode. . . . . . . . . . . . . . . . . . . . . 8
Command: Display_ctrl_2. . . . . . . . . . . . . . . . . 9
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Line inversion
(driving scheme A)
and frame inversion
(driving scheme B) . . . . . . . . . . . . . . . . . . . . . . 9
Starting and resetting the PCF8553 . . . . . . . . 10
Power-down mode . . . . . . . . . . . . . . . . . . . . . 10
Power-On Reset
(POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware reset: RST pin . . . . . . . . . . . . . . . . 11
Command: Software_reset . . . . . . . . . . . . . . . 11
Display data register mapping . . . . . . . . . . . . 11
Possible display configurations. . . . . . . . . . . 14
LCD bias generator . . . . . . . . . . . . . . . . . . . . 16
LCD voltage selector . . . . . . . . . . . . . . . . . . . 16
Electro-optical performance . . . . . . . . . . . . . . 17
LCD drive mode waveforms . . . . . . . . . . . . . . 19
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 19
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 20
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 22
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 23
Backplane and segment outputs . . . . . . . . . . 24
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 24
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 24
Power Sequencing. . . . . . . . . . . . . . . . . . . . . . 25
Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.3
Power sequences . . . . . . . . . . . . . . . . . . . . .
11
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . .
11.1
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . .
11.1.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2
START and STOP conditions. . . . . . . . . . . . .
11.1.3
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4
I2C interface protocol . . . . . . . . . . . . . . . . . . .
11.1.4.1 Write protocol . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4.3 I2C-bus slave address . . . . . . . . . . . . . . . . . .
11.2
SPI-bus interface . . . . . . . . . . . . . . . . . . . . . .
11.2.1
Data transmission . . . . . . . . . . . . . . . . . . . . .
11.2.1.1 Write protocol . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.1.2 Read protocol. . . . . . . . . . . . . . . . . . . . . . . . .
11.3
EMC detection . . . . . . . . . . . . . . . . . . . . . . . .
12
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
13
Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
15
Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
16
Application information . . . . . . . . . . . . . . . . .
16.1
Power-on with a slowly starting power supply
16.2
I2C acknowledge after power-on . . . . . . . . . .
16.3
Resistors on I/O pins . . . . . . . . . . . . . . . . . . .
17
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
18
Handling information . . . . . . . . . . . . . . . . . . .
19
Packing information . . . . . . . . . . . . . . . . . . . .
19.1
Tape and reel information . . . . . . . . . . . . . . .
20
Soldering of SMD packages . . . . . . . . . . . . . .
20.1
Introduction to soldering. . . . . . . . . . . . . . . . .
20.2
Wave and reflow soldering. . . . . . . . . . . . . . .
20.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
20.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
21
Footprint information . . . . . . . . . . . . . . . . . . .
22
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.1
LCD segment driver selection . . . . . . . . . . . .
23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
24
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Revision history . . . . . . . . . . . . . . . . . . . . . . .
26
Legal information . . . . . . . . . . . . . . . . . . . . . .
26.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
26.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
26.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Contact information . . . . . . . . . . . . . . . . . . . .
25
26
26
26
27
27
27
27
28
28
29
29
29
30
31
31
31
32
33
39
39
39
39
40
41
41
41
41
41
41
42
42
44
45
45
47
48
49
50
50
50
50
51
51
continued >>
PCF8553
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
54 of 55
PCF8553
NXP Semiconductors
40 × 4 LCD segment driver
28
29
30
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 March 2015
Document identifier: PCF8553