dm00099309

UM1688
User manual
EVAL6470H, EVAL6470PD, EVAL6472H and EVAL6472PD: fully
integrated microstepping motor drivers
Introduction
The EVAL6470H, EVAL6470PD, EVAL6472H and EVAL6472PD are four demonstration
boards based on the L6470 and L6472 devices implementing a complete stepper motor
driver solution. They are designed for operate with a supply voltage ranging from 8 V to 45 V
and can drive up to 3 Ar.m.s. for each phase.
In combination with the STEVAL-PCC009V2 demonstration board and the SPINFamily
evaluation tool, the boards provide a complete and easy to use evaluation environment
allowing the user to investigate all the features of the L6470 and L6472 devices. Both the
boards support the daisy chain configuration making them suitable for the evaluation of the
devices in multi motor applications.
April 2015
DocID025471 Rev 2
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www.st.com
41
Contents
UM1688
Contents
1
Boards description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
EVAL6470H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
EVAL6470H - thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2
EVAL6470PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EVAL6470PD - thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3
EVAL6472H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EVAL6472H - thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
EVAL6472PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EVAL6472PD - thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
Evaluation environment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1
Voltage mode driving (EVAL6470H/PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2
Advanced current control (EVAL6472H/PD) . . . . . . . . . . . . . . . . . . . . . . 37
3.3
Overcurrent and stall detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4
Speed profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4
How to change the supply configuration of the board . . . . . . . . . . . . 39
5
Daisy chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/41
DocID025471 Rev 2
UM1688
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
EVAL6470H - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
EVAL6470H - jumpers and connectors description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
EVAL6470H - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
EVAL6470H - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EVAL6470H - bill of material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EVAL6470PD - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EVAL6470PD - jumper and connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EVAL6470PD - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EVAL6470PD - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EVAL6470PD - bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
EVAL6472H - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EVAL6472H - jumpers and connectors description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EVAL6472H - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EVAL6472H - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EVAL6472H - bill of material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
EVAL6472PD - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EVAL6472PD - jumper and connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EVAL6472PD - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
EVAL6472PD - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
EVAL6472PD - bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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41
List of figures
UM1688
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
4/41
EVAL6470H - jumpers and connectors location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
EVAL6470H - schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EVAL6470H - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EVAL6470H - layout (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EVAL6470H - layout (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EVAL6470H - layout (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EVAL6470H - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EVAL6470PD - jumper and connector location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EVAL6470PD - schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
EVAL6470PD - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EVAL6470PD - layout (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EVAL6470PD - layout (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EVAL6470PD - layout (bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EVAL6470PD - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EVAL6472H - jumpers and connectors location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EVAL6472H - schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EVAL6472H - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EVAL6472H - layout (inner layer2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EVAL6472H - layout (inner layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EVAL6472H - layout (bottom layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EVAL6472H - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EVAL6472PD - jumper and connector location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EVAL6472PD - schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EVAL6472PD - layout (inner layer2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EVAL6472PD - layout (inner layer3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EVAL6472PD - layout (bottom layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
EVAL6472PD - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID025471 Rev 2
UM1688
Boards description
1
Boards description
1.1
EVAL6470H
Table 1. EVAL6470H - specifications
Parameter
Value
Supply voltage (VS)
8 to 45 V
Maximum output current (each phase)
3 Ar.m.s.
Logic supply voltage (VREG)
Externally supplied: 3.3 V, internally supplied: 3 V
(typ.)
Logic interface voltage (VDD)
Externally supplied: 3.3 V or 5 V, internally
supplied: VREG
Low level logic inputs voltage
0V
High level logic input voltage
VDD(1)
Operating temperature
-25 to +125 °C
L6470H thermal resistance junction to ambient
21 °C/W (typ.)
1. All logic inputs are 5 V tolerant.
Figure 1. EVAL6470H - jumpers and connectors location
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Boards description
UM1688
Table 2. EVAL6470H - jumpers and connectors description
Name
Type
Function
J1
Power supply
Motor supply voltage
J5
Power output
Bridge A outputs
J6
Power output
Bridge B outputs
J2
SPI connector
Master SPI
J3
SPI connector
Slave SPI
J4
NM connector
OSCIN and OSCOUT pins
J7
NM connector
External switch input
TP1 (VS)
Test point
Motor supply voltage test point
TP4 (VDD)
Test point
Logic interface supply voltage test point
TP5 (VREG)
Test point
Logic supply voltage/L6470 internal regulator test point
TP6 (GND)
Test point
Ground test point
TP2 (STCK)
Test point
Step-clock input test point
TP3 (STBY/RES)
Test point
Standby/reset input test point
TP7 (FLAG)
Test point
FLAG output test point
TP8 (BUSY/SYNC)
Test point
BUSY/SYNC output test point
Table 3. EVAL6470H - master SPI connector pinout (J10)
6/41
Pin number
Type
Description
1
Open drain output
L6470 BUSY/SYNC output
2
Open drain output
L6470 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to L6470 SDO
output through daisy-chain termination jumper JP2)
6
Digital input
SPI serial clock signal (connected to L6470 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6470 SDI
input)
8
Digital input
SPI slave select signal (connected to L6470 CS input)
9
Digital input
L6470 step-clock input
10
Digital input
L6470 STBY/RST input
DocID025471 Rev 2
UM1688
Boards description
Table 4. EVAL6470H - slave SPI connector pinout (J11)
Pin number
Type
Description
1
Open drain output
L6470 BUSY/SYNC output
2
Open drain output
L6470 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to pin 5 of J10)
6
Digital input
SPI serial clock signal (connected to L6470 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6470 SDO
output)
8
Digital input
SPI slave select signal (connected to L6470 CS input)
9
Digital input
L6470 step-clock input
10
Digital input
L6470 STBY/RST input
DocID025471 Rev 2
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41
8/41
5
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DocID025471 Rev 2
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Boards description
UM1688
Figure 2. EVAL6470H - schematic
$0Y
UM1688
Boards description
Table 5. EVAL6470H - bill of material
Item
Quantity
Reference
Value
Package
1
1
C1
220 nF/16 V
CAPC-0603
2
2
C2,C4
100 nF/6.3 V
CAPC-0603
3
1
C3
10 µF/6.3 V
CAPC-3216
4
1
C5
47 µF/6.3 V
CAPC-3216
5
1
C6
10 nF/50 V
CAPC-0603
6
4
C7, C8, C15, C16
100 nF/50 V
CAPC-0603
7
1
C9A
100 µF/63 V
CAPE-R8H12-P35
8
1
C9
100 µF/63 V
CAPES-R10HXX
9
3
C10, C11, C12
100 pF/6.3 V
CAPC-0603
10
1
C13
3.3 nF/6.3 V
CAPC-0603
11
1
C14
10 nF/6.3 V
CAPC-0603
12
1
DL1
LED diode (red)
LEDC-0805
13
1
DL2
LED diode (amber)
LEDC-0805
14
1
D1
BAV99
SOT23
15
1
D2
BZX585-B3V6(1)
SOD523
16
1
JP1
Jumper - OPEN
JP2SO
17
2
JP2, JP3
Jumper - CLOSED
JP2SO
18
3
J1, J5, J6
Screw connector 2 poles
MORSV-508-2P
19
2
J2,J3
Pol. IDC male header vertical 10
poles
CON-FLAT-5X2-180M
20
2
J4,J7
N.M.
STRIP254P-M-2
21
1
R1
31.6 k
RESC-0603
22
1
R2
200 k
TRIMM-100X50X11064W
23
1
R3
8.2 k
RESC-0603
24
3
R4, R5, R6
39 k
RESC-0603
25
2
R7, R9
470 
RESC-0603
26
1
R8
100 
RESC-0603
27
8
TP1, TP2, TP3, TP4, TP5,
TP6, TP7, TP8
Test point
TH
28
1
U1
L6470
HTSSOP28
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41
Boards description
UM1688
Figure 3. EVAL6470H - layout (top layer)
$0Y
Figure 4. EVAL6470H - layout (inner layer 2)
$0Y
10/41
DocID025471 Rev 2
UM1688
Boards description
Figure 5. EVAL6470H - layout (inner layer 3)
$0Y
Figure 6. EVAL6470H - layout (bottom layer)
$0Y
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41
Boards description
UM1688
EVAL6470H - thermal data
Figure 7. EVAL6470H - thermal impedance graph
Zth
25
Zth(°C/W)
20
15
10
5
0
1
10
Time(seconds)
1000
100
AM11339v1
1.2
EVAL6470PD
Table 6. EVAL6470PD - specifications
Parameter
Value
Supply voltage (VS)
8 to 45 V
Maximum output current (each phase)
3 Ar.m.s.
Logic supply voltage (VREG)
Externally supplied: 3.3 V internally supplied: 3 V typical
Logic interface voltage (VDD)
Externally supplied: 3.3 V or 5 V internally supplied: VREG
Low level logic input voltage
0V
High level logic input voltage
VDD(1)
Operating temperature
-25 to +125 °C
L6470PD thermal resistance junction to ambient
12 °C/W typical
1. All logic inputs are 5 V tolerant.
12/41
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UM1688
Boards description
Figure 8. EVAL6470PD - jumper and connector location
AM11330v1
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41
Boards description
UM1688
Table 7. EVAL6470PD - jumper and connector description
Name
Type
Function
M1
Power supply
Motor supply voltage
M2
Power output
Bridge A outputs
M3
Power output
Bridge B outputs
CN1
SPI connector
Master SPI
CN2
SPI connector
Slave SPI
CN3
NM connector
OSCIN and OSCOUT pins
CN4
NM connector
External switch input
TP1 (VS)
Test point
Motor supply voltage test point
TP2 (VDD)
Test point
Logic interface supply voltage test point
TP3 (VREG)
Test point
Logic supply voltage/L6470 internal regulator test point
TP5 (GND)
Test point
Ground test point
TP6 (GND)
Test point
Ground test point
TP8 (STCK)
Test point
Step-clock input test point
TP9 (STBY/RES)
Test point
Standby/reset input test point
TP10 (FLAG)
Test point
FLAG output test point
TP11 (BUSY/SYNC)
Test point
BUSY/SYNC output test point
Table 8. EVAL6470PD - master SPI connector pinout (J10)
14/41
Pin number
Type
Description
1
Open drain output
L6470 BUSY/SYNC output
2
Open drain output
L6470 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to the L6470 SDO
output through the daisy chain termination jumper JP2)
6
Digital input
SPI serial clock signal (connected to L6470 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6470 SDI input)
8
Digital input
SPI slave select signal (connected to L6470 CS input)
9
Digital input
L6470 step-clock input
10
Digital input
L6470 STBY/RST input
DocID025471 Rev 2
UM1688
Boards description
Table 9. EVAL6470PD - slave SPI connector pinout (J11)
Pin number
Type
Description
1
Open drain output
L6470 BUSY/SYNC output
2
Open drain output
L6470 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to pin 5 of J10)
6
Digital input
SPI serial clock signal (connected to L6470 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6470 SDO output)
8
Digital input
SPI slave select signal (connected to L6470 CS input)
9
Digital input
L6470 step-clock input
10
Digital input
L6470 STBY/RST input
DocID025471 Rev 2
15/41
41
16/41
VS
3
1
VDD
2
1
DocID025471 Rev 2
1
FLAG
470
2
1
BUSY
1
2
N.M.
CN4
SW
37
2
DL2
R8
10K
28
470
R7
L6470
DGND
DL1
TP11
BUSY
3
C3
10nF/50V
1
SPI_OUT
CN2
2
4
6
8
10
OUT2B
OUT2B
OUT1B
OUT1B
OUT2A
OUT2A
OUT1A
OUT1A
SW
C13
10nF/6.3V
20
21
17
18
35
36
2
3
C2
C5
47uF/6.3V
C14
GND
TP5
GND
C15
TP6
100nF/50V
C16
VS
C6
100nF/6.3V
JP1
+
C1
VREG
MISO
EXT_VDD
VREG
1
TP3
100nF/50V 100nF/50V
VDD
100nF/50V
C4
100nF/6.3V
1
EXT_VDD
CK
nCS
STBY_RESET
FLAG
VDD
TP2
PGND
PGND 19
AGND
1
12
R6
VDD
C12
3.3nF/6.3V
CS
CK
SDI
SDO
VBOOT
TP10
FL AG
C11
1nF/6.3V
30
26
27
25
STCK
STBY_RES
FLAG
BUSY_SYNC
ADCIN
SW
OSCOUT
OSCIN
14
32
6
31
29
8
7
VREG
BAV99
D1
CP
nCS
CK
SDI
SDO
ADCIN
SW
11
10
U1
VDD
2
1
3
5
7
9
C8
220nF/16V
MISO
SDO
STCK
BUSY
13
D2
BZX585-B3V6
C10
100pF/6.3V
CN3
N.M.
STBY
TP9
EXT_VDD
CK
nCS
STBY_RESET
FLAG
OSCOUT OSCIN
2
4
6
8
10
2
1
C9
100pF/6.3V
R5
39K
SPI_IN
CN1
VREG
9 VDD
24
R4
39K
VDD
C1A
100uF/63V
STCK
1
3
5
7
9
VSB
VSB
VSB
VSB
VSA
VSA
VSA
VSA
R3
39K
+
VS
OPTION
TP8
MISO
SDI
STCK
BUSY
23
22
16
15
34
33
5
4
STCK
STBY_RESET
FLAG
BUSY
R2
8K2
TR1
200k
TP1
Application reference
VS
1
R1
31K6
1
2
VS
1
VS
GND
M1
100uF/63V
C7
10uF/6.3V
JP3
VDD
2
1
1
2
M3
M2
SDO
JP2
1B
2B
1A
2A
VREG
Boards description
UM1688
Figure 9. EVAL6470PD - schematic
1
1
E_PAD
1
1
AM12921v1
UM1688
Boards description
Table 10. EVAL6470PD - bill of material
Index Quantity
Reference
Value
Package
1
1
CN1
Pol. IDC male header vertical 10 poles
(black)
CON-FLAT-5X2-180M
2
1
CN2
Pol. IDC male header vertical 10 poles
(gray)
CON-FLAT-5X2-180M
3
2
CN3, CN4
N. M.
STRIP254P-M-2
4
1
C1A
100 µF/63 V (option)
CAPE-R10HXX-P5
5
1
C1
100 µF/63 V
CAPES-R10HXX
6
4
C2, C14, C15, C1
100 nF/50 V
CAPC-0603
7
1
C3
10 nF/50 V
CAPC-0603
8
2
C4, C6
100 nF/6.3 V
CAPC-0603
9
1
C5
47 µF/6.3 V
CAPC-1206
10
1
C7
10 µF/6.3 V
CAPC-0805
11
1
C8
220 nF/16 V
CAPC-0603
12
2
C9, C10
100 pF/6.3 V
CAPC-0603
13
1
C11
1 nF/6.3 V
CAPC-0603
14
1
C12
3.3 nF/6.3 V
CAPC-0603
15
1
C13
10 nF/6.3 V
CAPC-0603
16
1
DL1
LED red
LEDC-0805
17
1
DL2
LED amber
LEDC-0805
18
1
D1
BAV99
SOT23
19
1
D2
BZX585-B3V6
SOD523
20
1
JP1
Jumper OPEN
JP2SO
21
2
JP2, JP3
Jumper CLOSED
JP2SO
22
3
M1, M2, M3
Screw connector 2 poles
MORSV-508-2P
23
1
R1
31.6 k
RESC-0603
24
1
R2
8.2 k
RESC-0603
25
3
R3, R4, R5
39 k
RESC-0603
26
2
R6, R7
470 k
RESC-0603
27
1
R8
10 k
RESC-0603
28
9
TP1, TP2, TP3, TP5, TP6,
TP8, TP9, TP10, TP11
TPTH-RING-1MM
TH
29
1
TR1
200 k
TRIMM-100x50x110-64W
30
1
U1
L6470
PowerSO36
DocID025471 Rev 2
17/41
41
Boards description
UM1688
Figure 10. EVAL6470PD - layout (top layer)
AM12923v1
Figure 11. EVAL6470PD - layout (inner layer 2)
AM12924v1
18/41
DocID025471 Rev 2
UM1688
Boards description
Figure 12. EVAL6470PD - layout (inner layer 3)
AM12925v1
Figure 13. EVAL6470PD - layout (bottom layer
AM12926v1
DocID025471 Rev 2
19/41
41
Boards description
UM1688
EVAL6470PD - thermal data
Figure 14. EVAL6470PD - thermal impedance graph
Zth
12
10
Zth
(°C/W)
8
6
4
2
0
1
10
100
1000
10000
Time (seconds)
AM11337v1
20/41
DocID025471 Rev 2
UM1688
1.3
Boards description
EVAL6472H
Table 11. EVAL6472H - specifications
Parameter
Value
Supply voltage (VS)
8 to 45 V
Maximum output current (each phase)
3 Ar.m.s.
Logic supply voltage (VREG)
Externally supplied: 3.3 V
Internally supplied: 3 V typical
Logic interface voltage (VDD)
Externally supplied: 3.3 V or 5 V
Internally supplied: VREG
Low level logic input voltage
0V
High level logic input voltage
VDD(1)
Operating temperature
-25 to +125 °C
L6472H thermal resistance junction to ambient
21 °C/W typical
1. All logic inputs are 5 V tolerant.
Figure 15. EVAL6472H - jumpers and connectors location
FLAG LED
(Red)
Power supply connector
(8 V - 45 V)
Application reference
area
JP1: VDD supply from
master SPI connector
BUSY LED
(Amber)
JP3: Daisy chain
termination
Slave SPI
connector
Master SPI
connector
JP2: VDD to VREG
connection
External switch connector
(SW input)
OSCIN/OSCOUT
connector
Motor supply voltage
compensation
partitioning regulation
(ADCIN input)
Phase A connector
Phase B connector
AM10289V1
DocID025471 Rev 2
21/41
41
Boards description
UM1688
Table 12. EVAL6472H - jumpers and connectors description
Name
Type
Function
M1
Power supply
Motor supply voltage
M2
Power output
Bridge A outputs
M3
Power output
Bridge B outputs
CN1
SPI connector
Master SPI
CN2
SPI connector
Slave SPI
CN3
NM connector
OSCIN and OSCOUT pins
CN4
NM connector
External switch input
TP1 (VS)
Test point
Motor supply voltage test point
TP2 (VDD)
Test point
Logic interface supply voltage test point
TP3 (VREG)
Test point
Logic supply voltage/L6470 internal regulator test point
TP5 (GND)
Test point
Ground test point
TP6 (GND)
Test point
Ground test point
TP8 (STCK)
Test point
Step-clock input test point
TP9 (STBY/RES)
Test point
Standby/reset input test point
TP10 (FLAG)
Test point
FLAG output test point
TP11 (BUSY/SYNC)
Test point
BUSY/SYNC output test point
Table 13. EVAL6472H - master SPI connector pinout (J10)
22/41
Pin number
Type
Description
1
Open drain output
L6472 BUSY output
2
Open drain output
L6472 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to L6472 SDO
output through daisy chain termination jumper JP2)
6
Digital input
SPI serial clock signal (connected to L6472 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6472 SDI
input)
8
Digital input
SPI slave select signal (connected to L6472 CS input)
9
Digital input
L6472 step-clock input
10
Digital input
L6472 standby/reset input
DocID025471 Rev 2
UM1688
Boards description
Table 14. EVAL6472H - slave SPI connector pinout (J11)
Pin number
Type
Description
1
Open drain output
L6472 BUSY output
2
Open drain output
L6472 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to pin 5 of J10)
6
Digital input
SPI serial clock signal (connected to L6472 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6472 SDO output)
8
Digital input
SPI slave select signal (connected to L6472 CS input)
9
Digital input
L6472 step-clock input
10
Digital input
L6472 standby/reset input
DocID025471 Rev 2
23/41
41
1
2
VDD
2
VS
DocID025471 Rev 2
1
470
2
YELLOW
DL2
1
BUSY
J4
NM
J7
SW
NM
1
2
23
19
20
18
nCS
CK
SDI
SDO
C13
3.3nF/6V3
25
3
24
22
STCK
8
7
U1
VREG
5
4
VDD
ADCIN
SW
OSCOUT
C9A
100uF/63V
MISO
SDO
STCK
BUSY
R8
100
CS
CK
SDI
SDO
STCK
STBY_RES
FLAG
BUSY_SYNC
ADCIN
SW
OSCOUT
OSCIN
2
4
6
8
10
L6472
3
C14
10nF/6V3
SW
1
VS
OUT2B
OUT1B
OUT2A
OUT1A
15
14
28
1
TP6
EXT_VDD
CK
nCS
STBY_RESET
FLAG
C6
10nF/50V
220nF/16V
D1
C1
SPI _ OUT
J3
BAV99
2
1
3
5
7
9
29
FLAG
R7
TP8
+
OSCIN
BUSY
C12
100pF/6V3
R6
39k
D2
BZX585-B3V6
C11
100pF/6V3
R4
39k
C9
100uF/63V
+
VS
OPTION
TP3
EXT_VDD
STBY/ RES
CK
nCS
STBY_RESET
FLAG
21
VDD
VDD
C8
100nF/50V
2
4
6
8
10
DGND
FL AG
C10
100pF/6V3
R5
39k
C7
100nF/50V
VS
SPI _ I N
J2
VREG
VDD
TP7
STBY_RESET
FLAG
BUSY
C15
100nF/50V
1
TP2
1
3
5
7
9
6
17
EPAD
RED
DL1
C16
100nF/50V
STCK
MISO
SDI
STCK
BUSY
11
VBOOT
470
2
1
Application reference
VS
CP
R9
R3
8k2
R2
200K
R1
31k6
GNDMORSV-508-2P
VS
3
1
1
VS
10
PGND
PGND
AGND
1
VSB
VSB
VSA
VSA
1
J1
2
1
24/41
16
12
26
2
1
TP1
1
TP4
1
C2
100nF/6V3
VDD
GND
TP5
C4
100nF/6V3
VREG
JP1
VDD
VREG
MISO
EXT_VDD
+
+
C3
10uF/6V3
C5
47uF/6V3
JP3
VDD
SDO
JP2
2
1
1
2
1A
2A
J6
1B
2B
MORSV-508-2P
MORSV-508-2P
J5
VREG
Boards description
UM1688
Figure 16. EVAL6472H - schematic
27
13
9
AM10295V1
UM1688
Boards description
Table 15. EVAL6472H - bill of material
Index
Quantity
Reference
Value
Package
1
1
C1
220 nF/16 V
CAPC-0603
2
2
C2, C4
100 nF/6.3 V
CAPC-0603
3
1
C3
10 µF/6.3 V
CAPC-3216
4
1
C5
47 µF/6.3 V
CAPC-3216
5
1
C6
10 nF/50 V
CAPC-0603
6
4
C7, C8, C15, C16
100 nF/50 V
CAPC-0603
7
1
C9A
100 µF/6.3 V (option)
CAPE-R10HXX-P5
8
1
C9
100 µF/6.3 V
CAPES-R10HXX
9
3
C10, C11, C12
100 pF/6.3 V
CAPC-0603
10
1
C13
3.3 nF/6.3 V
CAPC-0603
11
1
C14
10 nF/6.3 V
CAPC-0603
12
1
DL1
LED diode (red)
LEDC-0805
13
1
DL2
LED diode (amber)
LEDC-0805
14
1
D1
BAV99
SOT23
15
1
D2
BZX585-B3V6
SOD323
16
1
JP1
Jumper - open
JP2SO
17
2
JP2, JP3
Jumper - closed
JP2SO
18
3
J1, J5, J6
Screw connector 2 poles
MORSV-508-2P
19
2
J2,J3
Pol. IDC male header vertical 10
poles
CON-FLAT-5X2-180M
20
2
J4, J7
NM
STRIP254P-M-2
21
1
R1
31.6 k
RESC-0603
22
1
R2
200 k
TRIMM-100X50X110-64W
23
1
R3
8.2 k
RESC-0603
24
3
R4, R5, R6
39 k
RESC-0603
25
2
R7, R9
470 
RESC-0603
26
1
R8
100 
RESC-0603
27
7
TP1, TP2, TP3, TP4,
TP5, TP7, TP8
TPTH-ring-1 mm red
TH
28
1
TP6
TPTH-ring-1 mm black
TH
29
1
U1
L6472
HTSSOP28
DocID025471 Rev 2
25/41
41
Boards description
UM1688
Figure 17. EVAL6472H - layout (top layer)
AM10290V1
Figure 18. EVAL6472H - layout (inner layer2)
AM10291V1
26/41
DocID025471 Rev 2
UM1688
Boards description
Figure 19. EVAL6472H - layout (inner layer3)
AM10292V1
Figure 20. EVAL6472H - layout (bottom layer3)
AM10293V1
DocID025471 Rev 2
27/41
41
Boards description
UM1688
EVAL6472H - thermal data
Figure 21. EVAL6472H - thermal impedance graph
25
Zth (°C/W)
20
15
10
5
0
1
100
10
1000
Time (sec)
AM10294V1
1.4
EVAL6472PD
Table 16. EVAL6472PD - specifications
Parameter
Value
Supply voltage (VS)
8 to 45 V
Maximum output current (each phase)
3 Ar.m.s.
Logic supply voltage (VREG)
Externally supplied: 3.3 V
Internally supplied: 3 V typical
Logic interface voltage (VDD)
Externally supplied: 3.3 V or 5 V
Internally supplied: VREG
Low level logic input voltage
0V
High level logic input voltage
VDD(1)
Operating temperature
-25 to +125 °C
L6472PD thermal resistance junction to ambient
12 °C/W typical
1. All logic inputs are 5 V tolerant.
28/41
DocID025471 Rev 2
UM1688
Boards description
Figure 22. EVAL6472PD - jumper and connector location
FLAG LED
(Red)
Power supply connector
(8 V - 45 V)
Application reference
area
BUSY LED
(Amber)
JP1: VDD supply from
master SPI connector
JP3: Daisy chain
termination
Master SPI
connector
Slave SPI
connector
JP2: VDD to VREG
connection
ADCIN input
OSCIN/OSCOUT
connector
External switch connector
(SW input)
Phase A connector
Phase B connector
AM14850v1
Table 17. EVAL6472PD - jumper and connector description
Name
Type
Function
M1
Power supply
Motor supply voltage
M2
Power output
Bridge A outputs
M3
Power output
Bridge B outputs
CN1
SPI connector
Master SPI
CN2
SPI connector
Slave SPI
CN3
NM connector
OSCIN and OSCOUT pins
CN4
NM connector
External switch input
TP1 (VS)
Test point
Motor supply voltage test point
TP2 (VDD)
Test point
Logic interface supply voltage test point
TP3 (VREG)
Test point
Logic supply voltage/L6472 internal regulator test point
TP5 (GND)
Test point
Ground test point
TP6 (GND)
Test point
Ground test point
TP8 (STCK)
Test point
Step-clock input test point
TP9 (STBY/RES)
Test point
Standby/reset input test point
TP10 (FLAG)
Test point
FLAG output test point
TP11 (BUSY/SYNC)
Test point
BUSY/SYNC output test point
DocID025471 Rev 2
29/41
41
Boards description
UM1688
Table 18. EVAL6472PD - master SPI connector pinout (J10)
Pin number
Type
Description
1
Open drain output
L6472 BUSY output
2
Open drain output
L6472 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to L6472 SDO output
through daisy chain termination jumper JP2)
6
Digital input
SPI serial clock signal (connected to L6472 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6472 SDI input)
8
Digital input
SPI slave select signal (connected to L6472 CS input)
9
Digital input
L6472 step-clock input
10
Digital input
L6472 standby/reset input
Table 19. EVAL6472PD - slave SPI connector pinout (J11)
Pin number
Type
Description
1
Open drain output
L6472 BUSY output
2
Open drain output
L6472 FLAG output
3
Ground
Ground
4
Supply
EXT_VDD (can be used as external logic power supply)
5
Digital output
SPI master IN slave OUT signal (connected to pin 5 of J10)
6
Digital input
SPI serial clock signal (connected to L6472 CK input)
7
Digital input
SPI master OUT slave IN signal (connected to L6472 SDO output)
8
Digital input
SPI slave select signal (connected to L6472 CS input)
9
Digital input
L6472 step-clock input
10
Digital input
L6472 standby/reset input
30/41
DocID025471 Rev 2
3
1
VDD
2
1
DocID025471 Rev 2
2
1
FLAG
470
2
1
BUSY
1
2
N.M.
CN4
SW
C3
10nF/50V
L6472PD
R8
10K
28
470
DL2
EP
R7
E_PAD
DL1
TP11
BUSY
3
1
SPI_OUT
CN2
2
4
6
8
10
C13
10nF/6.3V
SW
19
1
12
R6
VDD
CS
CK
SDI
SDO
STCK
STBY_RES
FLAG
BUSY_SYNC
ADCIN
SW
DGND
TP10
FLAG
C12
3.3nF/6.3V
30
26
27
25
32
6
31
29
8
7
OSCOUT
OSCIN
D1
BAV99
VBOOT
PGND
PGND
AGND
D2
BZX585-B3V6
nCS
CK
SDI
SDO
ADCIN
SW
11
VREG
2
1
3
5
7
9
C8
220nF/16V
MISO
SDO
STCK
BUSY
CP
C11
1nF/6.3V
2
1
10
U1
VDD
VREG
VDD
C10
100pF/6.3V
CN3
N.M.
STBY
TP9
EXT_VDD
CK
nCS
STBY_RESET
FLAG
9
24
OSCOUT OSCIN
2
4
6
8
10
14
C9
100pF/6.3V
R5
39K
SPI_IN
CN1
13
R4
39K
VDD
C1A
100uF/63V
STCK
1
3
5
7
9
OUT2B
OUT2B
OUT1B
OUT1B
OUT2A
OUT2A
OUT1A
OUT1A
20
21
17
18
35
36
2
3
C2
C5
47uF/6.3V
C14
GND
TP5
GND
C15
TP6
100nF/50V
C16
VS
C6
100nF/6.3V
JP1
+
C1
VREG
MISO
EXT_VDD
VREG
1
TP3
100nF/50V 100nF/50V
VDD
100nF/50V
C4
100nF/6.3V
1
EXT_VDD
CK
nCS
STBY_RESET
FLAG
VDD
TP2
VSB
VSB
VSB
VSB
VSA
VSA
VSA
VSA
R3
39K
+
VS
OPTION
TP8
MISO
SDI
STCK
BUSY
23
22
16
15
34
33
5
4
STCK
STBY_RESET
FLAG
BUSY
R2
8K2
TR1
200k
TP1
Application reference
VS
1
R1
31K6
1
2
VS
1
VS
GND
VS
M1
100uF/63V
C7
10uF/6.3V
JP3
VDD
2
1
1
2
M3
M2
SDO
JP2
1B
2B
1A
2A
VREG
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Boards description
Figure 23. EVAL6472PD - schematic
1
1
1
1
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Table 20. EVAL6472PD - bill of material
Index Quantity
Reference
Value
Package
1
1
CN1
Pol. IDC male header vertical 10
poles (black)
CON-FLAT-5X2-180M
2
1
CN2
Pol. IDC male header vertical 10
poles (gray)
CON-FLAT-5X2-180M
3
2
CN3, CN4
N.M
STRIP254P-M-2
4
1
C1A
100 µF/63 V
CAPE-R10HXX-P5
5
1
C1
100 µF/63 V
CAPES-R10HXX
6
4
C2, C14, C15, C16
100 nF/50 V
CAPC-0603
7
1
C3
10 nF/50 V
CAPC-0603
8
2
C4, C6
100 nF/6.3 V
CAPC-0603
9
1
C5
47 F/6.3 V
CAPC-1206
10
1
C7
10 F/6.3 V
CAPC-0805
11
1
C8
220 nF/16 V
CAPC-0603
12
2
C9, C10
100 pF/6.3 V
CAPC-0603
13
1
C11
1 nF/6.3 V
CAPC-0603
14
1
C12
3.3 nF/6.3 V
CAPC-0603
15
1
C13
10 nF/6.3 V
CAPC-0603
16
1
JP1
LED red
LEDC-0805
17
1
DL2
LED amber
LEDC-0805
18
1
D1
BAV99
SOT23
19
1
D2
BZX585-B3V6
SOD523
20
1
JP1
Jumper OPEN
JP2SO
21
2
JP2,JP3
Jumper CLOSED
JP2SO
22
3
M1, M2, M3
Screw connector 2 poles
MORSV-508-2P
23
1
R1
31.6 k
RESC-0603
24
1
R2
8.2 k
RESC-0603
25
3
R3, R4, R5
39 k
RESC-0603
26
2
R6, R7
470 
RESC-0603
27
1
R8
10 k
RESC-0603
28
7
TP1, TP2, TP3, TP8,
TP9, TP10, TP11
TPTH-ring-1 mm (red)
TH
29
2
TP5, TP6
TPTH-ring-1 mm (black)
TH
30
1
TR1
200 k
TRIMM-100x50x110-64W
31
1
U1
L6472
PowerSO36
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Boards description
Figure 24. EVAL6472PD - layout (inner layer2)
AM14854v1
Figure 25. EVAL6472PD - layout (inner layer3)
AM14855v1
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Figure 26. EVAL6472PD - layout (bottom layer3)
AM14856v1
EVAL6472PD - thermal data
Figure 27. EVAL6472PD - thermal impedance graph
Zth
12
10
Zth
°C/W
8
6
4
2
0
1
10
100
1000
10000
Time (seconds)
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2
Evaluation environment setup
Evaluation environment setup
The evaluation environment is composed by:

One or more EVAL6470H\PD or EVAL6472H\PD.

One STEVAL-PCC009V2 demonstration board.

A USB cable.

A stepper motor with a small mechanical load (unloaded stepper motors suffer of
strong resonance issues).

A power supply with an output voltage within the operative range of the evaluation
board.

A Windows® 7 or Windows XP PC with a free USB port.

The SPINFamily evaluation tool (the last version can be downloaded from the
STMicroelectronics® website).
In order to start using the evaluation environment the following steps are required:
1.
Install the SPINFamily evaluation tool
2.
Start the SPINFamily evaluation tool (by default it is in Start menu > All programs >
STMicroelectronics > SPINFamily Evaluation Tool).
3.
Select the proper device when requested by the application.
4.
Plug the STEVAL-PCC009V2 demonstration board to a free USB port.
5.
Wait a few seconds for board initialization.
6.
Connect the SPI_IN connector (black) of the demonstration board to the 10-pin
connector of the STEVAL-PCC009V2 board using the provided cable.
For connecting more devices to the same board, please consult the daisy chain
connection paragraph (Section 5: Daisy chaining on page 40).
7.
Power-up the demonstration boards. The FLAG LED should turn on.
8.
Click on the button with the USB symbol to connect the STEVAL-PCC009V2 board to
the PC and initialize the evaluation environment.
The application automatically identifies the number of demonstration boards
connected.
9.
The evaluation environment is ready.
Before start working with the demonstration board, the device must be configured according
to the indications in Section 3: Device configuration.
Warning:
Important - the device configuration is mandatory. The
default configuration is not operative.
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Device configuration
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Device configuration
This section offers an overview of the basic configuration steps which are required for make
the demonstration board operative.
Warning:
Important - the device configuration is mandatory. The
default configuration is not operative.
Important - before changing the device configuration verify
that the device is in high impedance status (power stage is
disabled).
3.1
Voltage mode driving (EVAL6470H/PD)
The configuration parameters of the voltage mode driving can be obtained through the
BEMF compensation tool embedded into the SPINFamily software.
A wrong setup of these parameters could cause several issues, in particular:

The phase current decreases with the speed and the motor will stall.

The wrong voltage is applied to the motor and the system is very noisy.

The phase current reaches the overcurrent limit.
The BEMF compensation form uses the application parameters as inputs in order to
evaluate the proper device setup.
The required inputs are:

Supply voltage.

Target phase current (r.m.s. value) at different motion conditions (acceleration,
deceleration, constant speed and holding).

Target operating speed (maximum speed).

Motor characteristics.
The motor characteristics are: electrical constant (Ke), phase inductance and resistance.
The inductance and the resistance of the phase are given in the motor datasheet. The Ke is
rarely given in the specification and must be measured.
In the help section of the SPINFamily software a step by step procedure is explained. The
same procedure can also be found in the application note “AN4144: Voltage mode control
operation and parameter optimization” on www.st.com.
Click on the “evaluate” button to get the suggested setup for the voltage mode driving. Then
click on “write” button to copy the data in the registers of the device.
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3.2
Device configuration
Advanced current control (EVAL6472H/PD)
The following configuration gives good results with most of motors:

Minimum ON time = 4 µs.

Minimum OFF time = 21 µs.

Max. fast decay = 10 µs.

Max. fast decay at step change = 16 µs.

Target switching time = 48 µs.

Predictive current control enabled.
The impact of the timing parameters are explained in the application note “AN4158: Peak
current control with automatic decay adjustment and predictive current control: basics and
setup”.
The target phase current is set through the TVAL registers. The TVAL determinates the
current corresponding to the peak of the sine wave (microstepping operation).
3.3
Overcurrent and stall detection thresholds
The overcurrent protection and the stall detection (EVAL6470H\PD only) are implemented
measuring the current flowing into each integrated MOSFET.
The overcurrent protection threshold should be set just above the current rating of the
motor:
IOCDth > Imax,r.m.s. × √2
For example: if the maximum phase current of the motor is 2 Ar.m.s., the overcurrent
protection should be set to about 3 A.
Warning:
Important - it is strongly discouraged to disable the
overcurrent shutdown. It may result in critical failures.
The stall detection threshold should be just above the operating peak current of the
application. During the preliminary stages of evaluation, it can be set to the maximum value.
3.4
Speed profile
The max. speed parameter is the maximum speed the motor will run. By default, it is about
1000 step/s. That means, if you send a command to run at 2000 step/s, the motor speed is
limited at 1000 step/s.
This is an important safety feature in the final application, but not necessarily useful to
evaluate the device performances. Setting the parameter to high values (e.g. 6000 step/s)
allows evaluating the maximum speed which can be achieved by the application under test
through the speed tracking command (Run), but it probably limits the possibility to use
positioning commands (Move, GoTo, etc.).
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The Full-step speed parameter indicates the speed at which the system switches from
microstepping to full step operation.
In voltage mode driving devices (EVAL6470H\PD), it is always recommended to operate in
microstepping and not to switch to full step. Hence, this parameter should be greater than
the maximum speed.
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How to change the supply configuration of the board
How to change the supply configuration of the board
The configuration of the supply voltages can be changed through the jumpers from J1 to J6
as listed in Table 21.
Table 21. Device supply configurations
Configuration
JP1
JP2
Logic levels
Notes
Logic supplied by the integrated voltage
regulator and VDD shorted to VREG.
Open
Closed
3.3 V logic
compliant.
Default.
Logic supplied by the integrated voltage
regulator and VDD floating.
Open
Open
According to
VDD voltage.
The VDD must be supplied
through the respective test point.
Logic supplied by the integrated voltage
regulator and VDD supplied through the
SPI connector.
Closed
Open
According to
VDD voltage.
The VDD must be supplied
through the SPI connector.
Logic and VDD supplied through the SPI
connector.
Closed
Closed
3.3 V logic
compliant.
The supply voltage from the SPI
connector must be 3.3 V.
When VREG pin is supplied through an external voltage source, particular care must be
taken in order to avoid that VS voltage falls below the VREG one (e.g. VS is floating and
VREG is supplied). In this case the internal ESD diode is turned on and the device could be
damaged.
Adding a low drop diode between VREG and VS protects the internal ESD diode from this
event.
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Daisy chaining
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Daisy chaining
More demonstration boards can be connected in daisy chain mode.
To drive two or more boards in daisy chain configuration:
1.
Connect the STEVAL-PCC009V2 board 10-pin connector to the SPI_IN connector of
the first demonstration board through the 10-pole flat cable.
2.
Open the termination jumper (see Section 1.1: EVAL6470H on page 5, Section 1.2:
EVAL6470PD on page 12, Section 1.3: EVAL6472H on page 21 and Section 1.4:
EVAL6472PD on page 28).
3.
Connect the SPI_OUT connector of the first demonstration board to the SPI_IN of the
next one through the 10-pole flat cable.
4.
Repeat point 2 and 3 for all the others board of the chain but the last one.
5.
Check the termination jumpers of the demonstration boards: all the jumpers but the last
one should be opened.
Note:
Increasing the number of devices connected in chain could degrade SPI communication
performances. If communication issues occur, try reducing the SPI clock speed.
6
Revision history
Table 22. Document revision history
Date
Revision
15-Nov-2013
1
Initial release.
2
Updated Section : Introduction on page 1 (replaced
“dSPINTM family devices” and “dSPINTM” by “L6470 and
L6472 devices”).
Updated Section : Introduction on page 1 and Section 2:
Evaluation environment setup on page 35 (replaced
“SPIN family evaluation tool” by “SPINFamily evaluation
tool”).
Removed Figure 3. EVAL6470H - layout (silk screen)
from page 10, Figure 11. EVAL6470PD - layout (silk
screen) from page 18, Figure 19. EVAL6472H silkscreen from page 26, and Figure 27. EVAL6472PD silkscreen from page 34.
Updated value in Table 5: EVAL6470H - bill of material
on page 9, and packages in Table 10: EVAL6470PD bill of material on page 17 and Table 20: EVAL6472PD bill of material on page 32.
Minor modifications throughout document.
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