PANASONIC MN66279RSC

MN
L
SIs66fo2r7C
90oR
mSpC
act Disc/CD-ROM Player
MN66279RSC
1. Type
Signal processing LSI for CDs (Compact Discs)
2. Overview
MN662790RSC is a signal processing LSI for CDs which is applicable to 4x-speed playback. It
incorporates optical servo (focus, tracking and traverse servos) processing function, digital signal
processing function (EFM demodulation and error correction), digital servo processing function for
spindle motor, a digital filter and D/A converter. All the processing functions after the head
amplifier (RF amplifier) are incorporated into a single chip. In addition, it incorporates clock
generation and error correction circuits to increase the playability and is applicable to video CD
playback.
3. Functions and features
(Optical servo)
・Focus (Fo), tracking (Tr) and traverse (TRV) servos
(fS: Fo＝44.1 kHz, Tr＝44.1 kHz)
・ Automatic adjustment functions (Fo/Tr gain, Fo/Tr offset, Fo/Tr balance)
・ On-chip D/A converter for drive voltage output
・ Provided with a countermeasure for dropout
・ Provided with anti-shock function
・Provided with track cross detecting function
・ On-chip track cross counter
(Digital signal processing)
・Containing DSL and PLL
・ Provided with a frame synchronous detection/protection/interpolation
・ Subcode data processing
Q-data CRC check
On-chip Q-data register
・CD-TEXT interface function
On-chip CD-TEXT register (144 bits × 2)
・CIRC error correction
C1 decoder：double error correction C2 decoder：triple error correction, quadruple error correction
On-chip de-interleaving 16K RAM
・Audio data interpolation processing
4-sampling average value interpolation and previous value hold
・Digital attenuation (256 levels)
・Soft attenuation (256 levels)
・Soft muting
・Digital audio interface (EIAJ format)
・Audio data serial interface (Input/Output)
・Microcomputer serial interface
・General-purpose I/O port (4 pins)
・Audio data peak level detection function
Publication data: July 2002
SDD00025AEM
1
MN662790RSC
(Spindle motor servo)
・CLV digital servo
・Servo gain setting function
(Audio Circuit)
・ 8x-oversampling digital filter ・ On-chip D/A converter (1-bit DAC) ・ On-chip differential OP amp (2nd-order low-pass filter)
(Others)
・ 4x-speed playback
・ Disc rotation synchronizing playback (jitter-free) function
(4x-speed±50 ％)
・ Oscillation stop mode
・ Power management mode
・ Playback pitch control function
4. Package 80-pin quad flat package (LQFP080-P-1414A)
SDD00025AEM
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
X2
X1
VSS
SBCK
SUBC
VCOF2
PCK/DSLB
EFM/CK384
AVSS2
AVDD2
VCOF
PLLF
DSLF
DRF
IREF
ARF
W V EL
DSLBDA
PLLF2
MN662790RSC
ＭＮ６６２７９０ＲＳＣ
40
39
38
37
36 35
34
33 32 31 30 29 28 27 26 25 24 23
22
21 LD O N
BDO
RFDET
TRCRS
OFT
TEST3
RFENV
TE
FE
TBAL
FBAL
VREF
FOD
TRD
VDETMON
ECS ECM
PC
TV D
TEST2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
BCLK
LRCK
SRDATA
DVDD1
DVSS1
TX
MCLK
MDATA
MLD
SENSE
FLOCK
TLOCK
BLKCK
SQCK/GIO0
SUBQ
DMUTE
STAT
RST
SMCK
CSEL
BYTCK/TRVSTP
GIO1/CLDCK
GIO2/FCLK
IPFLAG
FLAG
CLVS
CRC
DEMPH
RESY/FLAG6
IOSEL
TEST
AVDD1
OUTL
AVSS1
OUTR
RSEL/GIO3
VCC5V
PSEL
MSEL
SSEL
Figure 1 Pin Assignment
SDD00025AEM
3
INPUT PORT
SDD00025AEM
OFT
OUTPUT
PORT CPU
D/A
CONVERTER
SERVO
16K
SRAM
INTERPOLATION CLV DIGITAL
SOFT MUTING AUDIO
DIGITAL SERVO INTERFACE
ATTENUATION
DE-INTERLEAVE
CIRC ERROR CORRECTION
SUBCODE DEMODULATION
CLVS
CRC
BLKCK
GIO1(CLDCK)
SBCK
SUBC
DEMPH
RFDET
BDO
TEST3
A/D CONVERTER
TRCRS
INTERFACE
MICROCOMPUTER
DEMODULATION CD-TEXT
BUFFER
SYNCÅ@ INTERPOLATION
EFM
FLAG6(RESY)
RFENV
CSEL
MSEL
X2
X1
SUBCODE
BUFFER
PWM
(L)
1-bit DAC
PWM LOGIC
PWM
(R)
8xOVERSAMPLING
DIGITAL FILTER
DIGITAL DE-EMPHASIS
LRCKIN(MSEL)
BCLKIN(SSEL)
SRDATAIN(PSEL)
TE
VCOF2
VCOF
BYTCK(TRVSTP)
SMCK
GIO2(FCLK)
DSL / PLL VCO
AVDD2
PCK(DSLB)
EFM(CK384)
PLLF
PLLF2
DSLF
IREF
DRF
ARF
RSEL(GIO3)
PSEL
TIMING
GENERATOR VCO
PITCH CONTROL
SSEL
SQCK(GIO0)
SUBQ
AVSS2
VCC5V
VDD
VSS
DVDD1
DVSS1
RST
TEST
FE
MN662790RSC
5. Block diagram
−
＋
AVSS1
AVDD1
OUTR
IOSEL
−
＋
OUTL
FLAG
IPFLAG
TX
ECM
ECS
PC
LRCK
SRDATA
BCLK
DMUTE
MLD
MCLK
MDATA
DSLBDA
VDETMON
VREF
TVD
TRD
FOD
TBAL
FBAL
TLOCK
FLOCK
LDON
STAT
WVEL
SENSE
SERVO
TIMING GENERATOR
4
MN662790RSC
6. Pin descriptions
No.
Symbol
I/O
Pin for
5-V input
Function
1
BCLK
O
Bit clock output for SRDATA
2
LRCK
O
L/R identification signal output
3
SRDATA
O
Serial data output 4
DVDD1
I
Power supply for digital circuits
5
DVSS1
I
Ground for digital circuits 6
TX
O
Digital audio interface output signal 7
MCLK
I
○
Microcomputer command clock signal input
(Latches the data at a rising edge)
I
○
Microcomputer command data signal input I
○
Microcomputer command load signal input
8
MDATA
9
MLD
L: Load 10
SENSE
O
Sense signal output (OFT, FESL, ACEND, AJEND, SFG)
11
FLOCK
O
Focus servo pull-in signal
(L: Pull-in status)
12
TLOCK
O
Tracking servo pull-in signal
(L: Pull-in status)
13
BLKCK
O
Subcode block clock signal
(fBLKCK＝75 Hz)
At command execution: CD-TEXT data reading enable signal (DQSY) output
14
SQCK/
GIO0
I
15
SUBQ
O
16
DMUTE
I
17
STAT
O
18
RST
I
19
SMCK
O
20
CSEL
I
○
At default value:
External clock input for subcode Q register
At command execution: General-purpose I/O port
In CD-TEXT 2 mode: Clock input for TEXT data reading
Subcode Q-data output
In CD-TEXT 2 mode: TEXT data output
○
Muting input
H: Mute
Status signal (CRC, STCNT, CLVS, TTSTOP, JCLVS, SQOK, FLAG6,
SENSE, FLOCK, TLOCK, rotating speed data, FCLV, SUBQ, SYFLG) In CD-TEXT 3 mode: Subcode Q and TEXT data output
○
Reset input
L: Reset
8.4672-MHz clock signal output at MSEL＝H
4.2336-MHz clock signal output at MSEL＝L
○
Oscillation frequency selection pin
SDD00025AEM
H: 33.8688 MHz
L: 16.9344 MHz
5
MN662790RSC
No.
Symbol
I/O
Pin for
5-V input
Function
21
TEST2
O
TEST pin 2
Normal: OPEN
22
TV D
O
Traverse drive output
23
PC
O
Spindle motor ON signal output
24
ECM
O
Spindle motor drive signal (Forced mode output)
25
ECS
O
Spindle motor drive signal (Servo error signal output) 26
VDETMON
O
Vibration detection monitor output
27
TRD
O
Tracking drive output
28
FOD
O
Focus drive output
29
VREF
I
Reference voltage for D/A output stage
(TVD, ECS, TRD, FOD, FBAL, TBAL, TOFS)
30
FBAL
O
Focus balance adjustment output
31
TBAL
O
Tracking balance adjustment output
32
FE
I
Focus error signal input
(Analog input)
33
TE
I
Tracking error signal input
(Analog input)
34
RFENV
I
RF envelope signal input
(Analog input)
35
TEST3
I
TEST pin 3
Normal: Fixed to "L"
36
OFT
I
Off track signal input
H: Off track 37
TRCRS
I
Track cross signal input
(Analog input)
38
RFDET
I
RF detection signal input
L: Detection
39
BDO
I
Dropout signal input
H: Dropout
40
LDON
O
Laser ON signal output
H: ON
41
PLLF2
I/O
Selector pin for PLL loop filter characteristics
42
DSLBDA
O
DSL balance output (D/A output)
43
WVEL
O
2x-speed status signal output
44
ARF
I
RF signal input
SDD00025AEM
L: ON (default)
3-state output
L: 2x-speed
6
MN662790RSC
No.
Symbol
I/O
Pin for
5-V input
Function
45
IREF
I
Reference current input pin
46
DRF
I
Bias pin for DSL
47
DSLF
I/O
DSL loop filter pin
48
PLLF
I/O
PLL loop filter pin
49
VCOF
I/O
VCO loop filter pin
50
AVDD2
I
Power supply for analog circuits
(For DSL, PLL, D/A output stage and A/D)
51
AVSS2
I
Ground for analog circuits (For DSL, PLL, D/A output stage and A/D)
52
EFM/
CK384
At IOSEL = H: EFM signal output
At IOSEL = L: 16.9344-MHz clock output for crystal oscillation
384fS output for signal processing (VCO clock output in jitter-free
operation)
(Select crystal oscillation or signal processing with command setting)
O
53
PCK/
DSLB
O
PLL extraction clock output or DSL balance output (PWM output)
(fPCK=4.3218 MHz)
54
VCOF2
I/O
VCO loop filter pin for the digital servo clock generation at 33.8688 MHz
The external circuit is required for crystal oscillation at 16.9344 MHz.
55
SUBC
O
Subcode serial output
In CD-TEXT 1 mode: TEXT data output
56
SBCK
I
57
VSS
I
Ground for oscillation circuit
58
X1
I
Crystal oscillation circuit input pin
(f＝16.9344 MHz, 33.8688 MHz)
59
X2
O
Crystal oscillation circuit output pin
(f＝16.9344 MHz, 33.8688 MHz)
60
VDD
I
Power supply for oscillation circuit
61
BYTCK/
TRVSTP
O
At IOSEL = H: Byte clock signal output
At IOSEL = L: Traverse stop signal output
62
GIO1/
CLDCK
O
At default value:
General-purpose I/O port
At command execution: Subcode frame clock signal output (fCLDCK=7.35 kHz)
63
GIO2/
FCLK
O
At default value:
General-purpose I/O port
At command execution: Crystal frame clock signal output (fFCLK=7.35 kHz)
64
IPFLAG
O
Interpolation flag signal output
65
FLAG
O
Flag signal output
○
Clock input for subcode serial output
In CD-TEXT 1 mode: Clock input for TEXT data reading
SDD00025AEM
H: STOP mode
H: Interpolation
7
MN662790RSC
No.
Symbol
I/O
Pin for
5-V input
Function
66
CLVS
O
Spindle servo phase synchronous status signal output
H: CLV
L: Rough servo
67
CRC
O
At default value: Subcode CRC check result output
H: OK L: NG
68
DEMPH
O
De-emphasis detecting signal output
H: ON
69
RESY/
FLAG6
O
At IOSEL = H:
At IOSEL = L:
Frame re-sync signal RESY output
H: Synchronous L: Asynchronous
RAM address reset signal FLAG6 output for error
correction and de-interleave
L: Address reset generated
70
IOSEL
I
Mode selector pin
71
TEST
I
Test pin
(Normal: H)
72
AVDD1
I
Power supply for analog circuits
(For audio output stage)
(Commonly used for L-ch and R-ch)
73
OUTL
O
L-ch audio output
74
AVSS1
I
Ground for analog circuits 75
OUTR
O
R-ch audio output
76
RSEL/
GIO3
I
○
At default value:
77
VCC5V
I
○
5-V power supply applied to pins for 5-V input
78
PSEL
I
○
At IOSEL = H: Test pin
At IOSEL = L: SRDATA input
79
MSEL
I
○
At IOSEL = H: SMCK pin output frequency selector pin
H: SMCK = 8.4672 MHz
L: SMCK = 4.2336 MHz
At IOSEL= L: LRCK input
H: L-ch data, L: R-ch data
SMCK = Fixed at 4.2336 MHz
80
SSEL
I
○
At IOSEL = H: SUBQ pin output mode selector pin
H: Q-code buffer working mode
L: CLDCK synchronous mode
At IOSEL = L: BCLK input
Q-code buffer working mode fixed
(For audio output stage)
(Commonly used for L-ch and R-ch)
RF signal polarity specification pin
When the bright level is "H", RSEL=H.
When the bright level is "L", RSEL=L.
At command execution: General-purpose I/O port
RF signal polarity is specified with command setting.
In CD-TEXT 1 or 2 mode: TEXT data reading enable signal (DQSY) output
SDD00025AEM
(Normal: L)
8
MN662790RSC
7. Function description (Table of contents)
7-0. Contents of functions amended from MN662748 ────────────
P 10
7-0 (1) Digital servo section
7-0 (2) Signal processing section 7-0 (3) Digital filter (DF) and D/A converter (DAC) sections
7-0 (4) The whole system
P 10
P 11
P 12
P 12
7-1. Microcomputer interface ──────────────────────
P 14
List of microcomputer commands Initialization
Data setting for servos
Data setting in signal processing section
Automatic adjustment
P 15
P 19
P 21
P 45
P 57
7-1 (1)
7-1 (2)
7-1 (3)
7-1 (4)
7-1 (5)
7-2. I/O timing ────────────────────────────
7-2 (1) Serial data output
7-2 (2) Serial data output with de-emphasis function ON
7-2 (3) Serial data input format
7-2 (4) Subcode interface
7-2 (5) EDATA error rate monitor function
7-2 (6) CD-TEXT interface
7-2 (7) Digital PLL setting
7-2 (8) Video CD setting
7-2 (9) Digital audio interface Bit V control
7-2 (10) Audio output MUTE
7-2 (11) Error correction SDD00025AEM
P 58
P 58
P 59
P 59
P 61
P 65
P 66
P 70
P 71
P 71
P 71
P 72
9
MN662790RSC
7-0. Contents of functions amended from MN662748
7-0 (1) Digital servo section
1) Initialization
◎ Initialization with SYS command after the standby time (0.1 s) preset by the on-chip timer has
elapsed
2) Automatic adjustment
・ Abolishment of Tr offset external feedback adjustment
・ Fo/Tr offset adjustments batch processing only
・ Setting of the convergence gain for Fo balance adjustment
・ Abolishment of Tr rough gain adjustment with TROFF
・ Selection of the convergence conditions for Tr balance adjustment
◎ Hunting preventive function in Fo balance adjustment
(1/8, 1/4, 1/32, 1/16)
3) Servo
◎ Servo sampling frequency: 44.1 kHz
◎ Vibration detection with software
・ TRV dead-zone amplifier mode selectable
・ Unified Tr servo output (TRD and KICK)
・ Unified TRV servo output (TVD and TRV)
・ TVD output gain selectable
・ Fo servo filter Z-N setting
(N: Fixed to 2)
・ Selecting Fo servo dropout processing
(0 mute only)
・ Selecting Fo disc detecting frequency
(5.4 Hz, 2.6 Hz)
・ Tr servo output stage noise shaver ON/OFF
(Fixed to ON)
・ Selecting Tr servo dropout processing
(0 mute only)
・ Selecting TRV loop filter
(Type A only)
・ Smoothing TRV servo output
・ OFT input noise filter turned ON/OFF with a command
◎ Setting of high-speed Fo pull-in operation when turning Fo ON from OFF state
◎ Setting of dropout processing during KICK operation
◎ Trigger function at vibration detection
・ Abolishment of Fo servo's perfect integral and limited characteristics selection (Perfect integral
characteristic only)
・ Abolishment of Tr servo's perfect integral and limited characteristics selection (Perfect integral
characteristic only)
・ Change of servo parameter exponent part format (FEXP, TEXP)
4) Access
・ TCNT (track count move) processing with software
・ Outputting TRD during TCNT (track count move) (0 only)
5) DTMS, DTSM
・ Possible to set Tr gain constant limiter arbitrarily for initial Tr gain constant and Tr fine gain
adjustments
・ Possible to set Fo gain constant limiter arbitrarily for initial Fo gain constant and Fo fine gain
adjustments
◎ Possible to set band-pass filter constants and a detecting level for vibration detection
SDD00025AEM
10
MN662790RSC
7-0 (2) Signal processing section
1) Signal processing over the system
Applicable for VIDEO CDs
◎ Error correction method
・ Selectable between double (C1) and triple (C2) corrections, and double (C1) and quadruple (C2)
corrections
・ C1 flag discrimination condition at C2 correction selectable
◎ PLL circuit for VIDEO CDs (Digital PLL)
Other functions
◎ Audio interpolation processing 4-sampling interpolation
◎ Addition of CD-TEXT output format 4 mode
◎ Peak data output function (Same as the specification for MN662780)
◎ Audio output level attenuation function
◎ Pitch control function (±50 ％ of 1x-, 2x- and 4x-speed)
◎ Error flag counting function (selectable between FLAG0 and IPFLAG)
◎ TX output generation from audio DAC external input data (Conventional method is also selectable)
2) DSL, PLL
◎ PLLF current selection mode (×1, ×0.75, ×0.5, ×1.25)
◎ PLL frequency dividing function
◎ Digital PLL control
◎ Charge pump current adjusting function
3) Digital audio interface (TX)
◎ Bit V control of TX output
◎ Generation of TX output from DF input data
4) Spindle servo
◎ CLV synchronization establishment detecting flag
SDD00025AEM
11
MN662790RSC
7-0 (3) Digital filter (DF) and D/A converter (DAC) sections
◎ Newly added digital filter calculation constants
・ 1-bit D/A converter
7-0 (4) The whole system
◎ PMCK and PLAY pins eliminated
◎ VCC5V pin for 5-V input added
◎ 3.3-V operation of internal circuit
◎ Digital input pins for 5-V input
SDD00025AEM
12
PSEL
SSEL
MSEL
SERV
SDD00025AEM
LRCK
BCLK
SRDATA
RESY
BYTCK
EFM
PSEL
SSEL
MSEL
PSEL
SSEL
MSEL
SERV
PSEL
SSEL
MSEL
EFM
CK384
BYTCK
TRVSTP
RESY
FLAG6
EFM
CK384
BYTCK
TRVSTP
RESY
FLAG6
LRCK
BCLK
SRDATA
RESY
BYTCK
EFM
MN662790RSC
Setting the LSI Operation Mode by the IOSEL Pin
IOSEL
SIGNAL
PROCESSOR
DF/
DAC
L
H
L
IOSEL
SIGNAL
PROCESSOR
DF/
DAC
L
H
L
13
MN662790RSC
7-1. Microcomputer interface
Each mode can be set by inputting the 16-bit data (D15 to 0) and 8-bit command (B7 to 0) starting from
the MSB in 3 inputs of MDATA, MCLK and MLD at the timing as shown in Figure 7-1-1.
ＭＤＡＴＡ
D15 D14 D13
D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0
∼
∼
ＭＣＬＫ
∼ ∼
∼
∼
MSB LSB
ＭＬＤ
Note）・ Data is determined at the "L" level of MLD.
・ MDATA, MCLK and MLD are invalid while RST is "L".
・ All commands are initialized by setting RST to "L".
・ While MLD is set to "L", MCLK will be canceled if it rises.
（Timing）
ＭＤＡＴＡ B2 B1 B0
ＭＣＬＫ
ＭＬＤ
Mi１
n.
Min.
Min.
Min.
300 ns 300 ns 300 ns 300 ns
Min.
600 ns
Min.
Min.
600 ns 300 ns
Max.
100 µs
Figure 7-1-1
SDD00025AEM
14
MN662790RSC
7-1 (1) List of microcomputer commands
(1-1) Servo processor
Table 7-1-1 (1)
Control
Target
MDATA
Symbol
B7 B6 B5 B4 B3 B2 B1 B0
１１１１０
Initiali０
zation
Automatic １１１１０
１
adjustment １
１
１
１
１
１
１
Data
setting Optical
servo Function
１０１ SYS
１１０
System setting
RESERVED
SENSE
output
Data
SFG
16 bits
１１１ ABC1
０００ ADA
AJEND
AJEND
―
―
０
０１
AJEND
０
０
１
１
１
０
０
１
０
１
０
１
１
１
１
１
０
１
Fo balance adjustment
Stopping automatic
adjustment
Offset adjustment
AOC
(Fo, Tr)
RESERVED
ABC2 Tr balance adjustment
AGC1 Fo rough gain
adjustment
AGC2 Tr rough gain
adjustment
FAGC Fo fine gain adjustment
TAGC Tr fine gain adjustment
１
１１１０
０
０１０ DTMS Data write
１００ DTSM Data read
１
１１００
０
０
０
０
０
０００ STB
００１
０１０ DDT
０１１ TO F
１００ PLY
１０１ PLY2
１１１０１０
TRV
１０
servo
１０
１０
１１
０
０
１
１
０
０
１
０
１
０
TV S
TV F
TV R
TV P
Standby
RESERVED
Disc detection
Fo ON, Tr OFF
Fo ON, Tr ON
Fo ON, Tr ON
(TRVSTP disabled)
TRV stop
RESERVED
TRV forward feed
TRV reverse feed
TRV play
AJEND
AJEND
―
―
―
―
AJEND
―
AJEND
AJEND
―
―
WTEND
DATA
Chapter
16 bits
8 bits
OFT
―
FESL
FESL
OFT
OFT
―
―
―
No change
At
reset
○
○
―
―
Access
１１１１０
０
０
０００ ACA
０
０
０
１
１ KICK
１ TCNT
Stopping access
operation
Kick
Track count move
SDD00025AEM
ACEND
ACEND
ACEND
16 bits
16 bits
15
MN662790RSC
(1-2) Signal processing
Table 7-1-1 (2)
Control
Target
MDATA
Symbol
Function
Data
B7 B6 B5 B4 B3 B2 B1 B0
At
Chapter
reset
Spindle
０００１１ × × ×
０ × × ×
× １ × × TTO N
× ０ × × TTOFF
× × ００ STOP
× × ０１ ACC
× × １０ BRAKE
× × １１ PLAY
RESERVED
RESERVED
Turntable ON (H)
Turntable OFF (L)
Free-running
Acceleration
Deceleration
Normal play
TX
００１０１ × × ×
output
０ × × ×
Audio
× １ × ×
output × ０ × ×
× × ００
× × ０１
× × １０
× × １１
Digital I/F Bit C (28) SET
Digital I/F Bit C (28) RESET
Digital I/F Bit C (29) SET
Digital I/F Bit C (29) RESET
Normal output (0dB)
Soft muting
Digital attenuation
Soft attenuation
―
―
―
―
―
―
―
Audio
００１１ × ０ × × NOS
output × １ × × DOS
× × ０ ×
× × １ ×
０ × × ０
０ × × １
１ × × ０
WVEL=L Normal-speed playback
WVEL=H 2x-speed playback
LRCK signal (R-ch=L, L-ch=H)
LRCK signal (R-ch=H, L-ch=L)
Audio mode (Ⅰ)
Audio mode (Ⅱ)
CD-ROM mode
―
―
―
―
―
―
―
○
―
―
―
―
○
TX
output
０１０００
１
×
×
×
×
０
１
０
０
０
０
０
０
０
０
TX pin output enabled
TX pin output disabled ("L" is fixed)
Digital I/F category code = CD mode
Digital I/F category code = general mode
０１０００
０
０
０
０
０
１
１
１
１
１
０
０
０
１
１
１
０
０
０
１
１
０
１
１
０
１
１
０
１
１
０
１
１
０
１
１
０
１
１
０
１
１
０
Audio output control (I)
Digital/Audio I/F control
General-purpose I/O port control
Spindle control
Audio output control (II)
Audio output control (III)
CLV speed setting
RESERVED
DSL and PLL controls (I)
DSL and PLL controls (II)
Digital PLL control
SDD00025AEM
―
―
―
―
―
―
○
○
○
○
○
○
○
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16
MN662790RSC
Table 7-1-1 (3)
Control
Target
MDATA
B7 B6 B5 B4 B3 B2 B1 B0
SRDATA ０
Audio
０
output
STAT
pin
output
１０１
１１０
０
０
０
０
０
０
１
１
０
１
０
１
００１１
０
０
０
０
１
１
１
１
１
１
１
０
０
０
０
０
１
１
０
０
１
Data
０
１
０
１
０
１
０
STAT output CRC
STAT output STCNT
STAT output CLVS
STAT output TTSTOP
(during TTOFF)
STAT output JCLVS
(during TTON)
STAT output SQOK
STAT output switching
STAT output disc rotating speed
STAT output FCLV
STAT output SUBQ
STAT output SYFLG
STAT output EDATA
SDD00025AEM
At
reset
Chapter
００００
０１００
Attenuation level (lower 4 bits)
Attenuation level (upper 4 bits)
AL3 to 0
AL7 to 4
０１１１０
０
０
０
Function
Symbol
○
3 bits
16 bits
17
MN662790RSC
・SENSE signal
SENSE signal can be monitored through STAT pin. The meaning of SENSE signal varies with the input
command. The meanings are described below.
OFT
Off-track input signal is output as it is.
FESL
It is set to "H" when the absolute value of the focus error signal amplitude exceeds 30
[LSB] by executing the disc detecting command.
ACEND
It is set to "L" when the access terminates and the pull-in operation of the tracking servo
starts.
AJEND
It is set to "L" when automatic adjustment terminates.
WTEND
It is set to "L" when data write terminates normally.
DATA
ＭＤＡＴＡ
The contents of the RAM of the specified address is output beginning with MSB by
inputting MCLK a minimum of 50 ms after MLD is set to "L" with the data read
command, DTSM, sent out for data reading. Refer to Figure 7-1-4.
Disc detection
Fo ON Tr ON
Fo fine AGC
KICK
ＭＬＤ
FESL OFT AJEND ACEND
ＳＥＮＳＥ
(STAT pin)
End of automatic
adjustment
End of
KICK
Figure 7-1-2 Switching of SENSE output
SDD00025AEM
18
MN662790RSC
7-1 (2) Initialization
After clearing RST, the system waits for a data write command (DTMS) and SYS command.
1) After clearing RST, execute the data write command first.
The data write command is composed of the following three bytes, which is different from the regular
format (see page 22).
Ｄ15 Ｄ14 Ｄ13 Ｄ12 Ｄ11 Ｄ10
Ｄ9
Ｄ8
ＳＥＴ０＝×××× ×××１（Ｂ）
Ｄ7
Ｄ6
Ｄ5
Ｄ4
Ｄ3
Ｄ2
Ｄ1
Ｄ0
ＶＳＥＴ＝×××× ××××（Ｂ）
Ｂ7
Ｂ6
Ｂ5
Ｂ4
Ｂ3
Ｂ2
Ｂ1
Ｂ0
ＤＴＭＳ＝１１１１００１０（Ｂ）
That is, SET0 (various system settings) data is stored in the upper 8 bits of the 16-bit data, and VSET
(anti-vibration mode selection) data is stored in the lower 8 bits. 2) After the data write command (DTMS) is processed, the SENSE signal (WTEND) is set to "L" and it is
in the standby status for the SYS command.
Unlike conventional models, no system settings are possible with the SYS command. This is due to the
expansion of the DTMS/DTSM functions. Execute the following command, however, after checking that
the SENSE signal is set to "L". This is for the protocol assurance of the SENSE signal with the
mechanical controller.
When the SYS command MDATA 1111 0101 is accepted, the SENSE signal is set to "H" and processing
of the SYS command starts. When the processing completes, the SENSE signal is set to "L" to enter the
normal operation loop.
Table 7-1-2 indicates the default values of system setting. The default value of each item is changeable
with the DTMS command.
Note)
If the data write command (DTMS) is not executed within 743 ms after starting the standby status for the
data write command (DTMS) and the SYS command, the system setting is performed with the default
value and enters the normal operation loop.
Be aware that initial SET0 data and VSET data are written in a special format that is entirely different
from the format used for writing usual data. In initial setting, SET0 and VSET are set at the same time
only by sending a 3-byte command once, while in normal write, SET0 and VSET are set separately using
a 3-byte command.
Timing chart is shown in Figure 7-1-3.
SDD00025AEM
19
MN662790RSC
743 ms max. ＲＳＴ
※
0.1 s
ＳＥＮＳＥ
(STAT Pin)
ＭＤＡＴＡ
DTMS
Other than
S YS
SYS
ＭＬＤ
Figure 7-1-3 Timing chart in initial setting
※
A 0.1-s standby time is not necessary to send the DTMS command and the SYS command after reset
clearance. To ensure system stability after turning on the power, send the DTMS command and the SYS
command after SENSE is set to "H".
Table 7-1-2
Item
Default value
Gain for tracking variable gain amp
Gain for focus variable gain amp
Output amplitude for focus search
Fail-safe value for tracking servo
Standby time after track count move
Traverse drive constant
Traverse drive dead-zone
Optical servo
Traverse servo
2x-speed mode
Spindle servo
TX pin output
STAT pin output
Note）
＋6 [dB]
＋12 [dB]
±22 [LSB]
±72 [LSB]
50 [ms]
2
±24 [LSB]
Standby
Stop
NOS
Turntable OFF
STOP (Free-running)
Enabled
CRC output
To obtain the waveform shown in the above timing chart, the MLD pulse width should be 10 µs or
less. If it is more than the value, SENSE clear ("H" → "L") by the SYS command in the above
timing may not be performed.
SDD00025AEM
20
MN662790RSC
7-1 (3) Data setting for servos
[1] Data write (DTMS)
Various features can be achieved by writing various characteristics of the optical servo
system from an external microcomputer to this LSI.
DTMS command is used to write the data such as servo parameters.
(Applications)
(A) Setting of automatic adjustment value
(B) Setting of the optical servo loop characteristics including the characteristics for anti-vibration
(C) Setting of gain crossover for the optical servo loop
(D) Mode selection for anti-vibration
(E) Various system settings
(F) Various settings for optical servo system
(MDATA format)
D７ D６ D５ D４ D３ D２ D1 D0
: Data
: Address (Label specified)
A７ A６ A５ A４ A３ A２ A１ A０
１
１
１
１
０
０
１
０
: Command (DTMS)
Note)
・Use the DTMS command in the STANDBY or PLAY mode.
・If you write data successively, wait at least 50 µs after each data writing so that the microcomputer
finishes DSP processing and becomes ready for writing next data.
SDD00025AEM
21
MN662790RSC
[2] Data read (DTSM)
・This LSI can read out the parameters such as automatic adjustment results of the optical servo with the
DTSM command.
(MDATA format)
A7 A6 A5 A4 A3 A2 A1 A0 ：Address (Label specified)
１１１１０１００：Command (DTSM)
(Data output format)
Input an address and a command, and after a lapse of 50 µs or more since setting MLD=L, input MCLK,
thus enabling to read data from STAT pin. (SENSE output)
ＭＤＡＴＡ
DTSM
ＭＬＤ
ＭＣＬＫ
ＳＥＮＳＥ
(STAT pin)
Indefinite Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data 0
Min. 50 µs
Figure 7-1-4 Timing chart for reading data
Note) Perform either in the STANDBY or PLAY mode.
SDD00025AEM
22
MN662790RSC
(List of DTMS addresses)
Table 7-1-3 (1)
Address (HEX)
(A7 to A0)
００
０１
０２
０３
０４
０５
０６
０７
０８
０９
０Ａ
０Ｂ０Ｃ
０Ｄ
０Ｅ
０Ｆ
１０
１１
１２
１３
１４
１５
１６１７１８１９１Ａ１Ｂ
１Ｃ１Ｄ１Ｅ１Ｆ Label
ＦＧ０ＦＥＸＰ０
ＦＢＡＬ
ＦＯＦＳ
ＴＧ０
ＴＥＸＰ０
ＴＢＡＬ
ＴＯＦＳ
ＦＣ
ＦＲ
ＴＣ
ＴＲ
ＦＣ２
ＦＲ２
ＴＣ２
ＴＲ２
ＧＳＥＴ
ＶＳＥＴ
ＳＥＴ０
ＳＥＴ１
ＳＥＴ２
ＳＥＴ５
ＦＥＳ
ＴＥＳ
ＣＲＡＭ２
ＳＤ
ＫＳ
ＴＶＧ
ＣＲＡＭ３
ＣＲＡＭ４
ＳＥＴ３
ＤＥＤ０
Application
Focus gain automatic adjustment value in normal-speed mode (for setting use)
Focus gain automatic adjustment value in normal-speed mode (for setting use)
Focus balance automatic adjustment value
Focus offset automatic adjustment value
Tracking gain automatic adjustment value in normal-speed mode (for setting use)
Tracking gain automatic adjustment value in normal-speed mode (for setting use)
Tracking balance automatic adjustment value
Tracking offset automatic adjustment value
Focus phase compensation constant
Focus low-band compensation constant
Tracking phase compensation constant
Tracking low-band compensation constant
Focus phase compensation constant at vibration
Focus low-band compensation constant at vibration
Tracking phase compensation constant at vibration
Tracking low-band compensation constant at vibration
Gain crossover setting
Mode selection for anti-vibration
Various system settings
Various system settings
Various system settings
Various system settings
Focus gain disturbance amplitude
Tracking gain disturbance amplitude
Focus search amplitude
Search direction
Kick speed / Kick brake timing
Traverse gain constant in tracking brake operation Fail-safe value for tracking servo Tracking balance disturbance adjustment value
Various system settings
Traverse drive dead-zone
SDD00025AEM
Reference
page
25
25
25
25
25
25
25
25
26
26
26
26
26
26
26
26
28
29
31
32
33
35
25
25
38
38
39
40
38
38
34
40
23
MN662790RSC
Table 7-1-3 (2)
Address (HEX)
(A7 to A0)
２Ｄ
２Ｅ３５３６
３９
３Ａ３Ｂ３Ｃ３Ｄ３Ｅ３Ｆ４０４９
４Ａ
４Ｂ
６１
７８
７９
７Ａ
７Ｂ
７Ｃ
８０８１
ＡＡ Label
ＦＧ２ＦＥＸＰ２
ＴＧ２ＴＥＸＰ２
ＧＬＦ１
ＧＬＦ２
ＧＬＦ３
ＧＬＦ４
ＧＬＴ１
ＧＬＴ２
ＧＬＴ３
ＧＬＴ４
ＳＥＴＫＣ
ＳＥＴＴＢ
ＫＣＣＮＴ
ＰＤＫ
ＫＩＣＫ
ＴＲＶ
ＫＩＣＫ２
ＶＳＬＴ
ＰＨＳＵ
−
−
−
Application
Focus gain constant mantissa part at vibration (for setting use)
Focus gain constant exponent part at vibration (for setting use)
Tracking gain constant mantissa part at vibration (for setting use)
Tracking gain constant exponent part at vibration (for setting use)
Focus gain constant upper limit mantissa part
Focus gain constant upper limit exponent part
Focus gain constant lower limit mantissa part
Focus gain constant lower limit exponent part
Tracking gain constant upper limit mantissa part
Tracking gain constant upper limit exponent part
Tracking gain constant lower limit mantissa part
Tracking gain constant lower limit exponent part
Track count and KICK noise elimination width
Various system settings
Inverted pulse width with tracking brake and servo control
turned on
Initial accelerating time with tracking brake turned on
Convergence gain setting in fine gain adjustment
KICK output level in normal operation
Traverse output level
KICK output level when servo is pulled in
Vibration detecting level mantissa part
Number of disturbance waves setting in fine gain adjustment
Focus and tracking gains setting for normal gain
Focus and tracking gains setting for forced gain-up
Software reset
Reference
page
30
30
30
30
43
43
43
43
43
43
43
43
40
36
41
41
42
41
41
41
42
42
37
37
37
※ Do not write illegal data in any of the above addresses, otherwise the existing data in the
address is overwritten and the operation of this LSI is not guaranteed.
SDD00025AEM
24
MN662790RSC
(A) Setting of automatic adjustment value
FG0 (Focus gain mantissa part)
FEXP0 (Focus gain exponent part)
FBAL (Focus balance adjustment value)
(Focus offset adjustment value)
FOFS
(Disturbance amplitude in focus
FES
gain adjustment)
(Disturbance amplitude in
TES
tracking gain adjustment)
,
,
,
,
TG0
TEXP0
TBAL
TOFS
(Tracking gain mantissa part)
(Tracking gain exponent part)
(Tracking balance adjustment value)
(Tracking offset adjustment value)
Table 7-1-3 (3)
Data
(D7 to D0)
Address
Command (HEX)
(HEX)
(B7 to B0)
(A7 to A0)
D7 D6 D5 D4 D3 D2 D1 D0
00
D7 D6 D5 D4 D3 D2 D1 D0
01
D7 D6 D5 D4 D3 D2 D1 D0
02
D7 D6 D5 D4 D3 D2 D1 D0
03
D7 D6 D5 D4 D3 D2 D1 D0
04
D7 D6 D5 D4 D3 D2 D1 D0
05
D7 D6 D5 D4 D3 D2 D1 D0
06
D7 D6 D5 D4 D3 D2 D1 D0
07
D7 D6 D5 D4 D3 D2 D1 D0
16
D7 D6 D5 D4 D3 D2 D1 D0
17
F2
Function
Setting
at reset
Focus gain constant (FG0)
128
(8-bit mantissa) (1 to 255)
Focus gain constant (FEXP0)
32
(8-bit exponent) (16, 32, 64 and 128 only)
(Focus gain constant = mantissa / exponent)
Focus balance constant (FBAL)
0
(8-bit 2' s complement) (−128 to +127)
Focus offset constant (FOFS)
0
(8-bit 2' s complement) (−128 to +127)
Tracking gain constant (TG0)
128
(8-bit mantissa) (1 to 255)
Tracking gain constant (TEXP0)
64
(8-bit exponent) (16, 32, 64 and 128 only)
(Tracking gain constant = mantissa / exponent)
Tracking balance constant (TBAL)
0
(8-bit 2' s complement) (−128 to +127)
Tracking offset constant (TOFS)
0
(8-bit 2' s complement) (−128 to +127)
Disturbance amplitude in focus gain adjustment
85
(FES)
(1 to 127)
Disturbance amplitude in tracking gain 85
adjustment (TES)
(1 to 127)
SDD00025AEM
25
MN662790RSC
(B) Setting of the optical servo characteristics including the characteristics for anti-vibration
・Gain constant
Focus gain mantissa part
FG Tracking gain mantissa part
Focus gain exponent part
FEXP Tracking gain exponent part
TG
TEXP
・Phase compensation and low-band compensation constant
Focus phase compensation constant
FC Tracking phase compensation constant TC
Focus low-band compensation constant FR Tracking low-band compensation constant TR
The above eight constants can be set by writing 8-bit data (0 to 127) directly with the microcomputer
command.
Structure
K
+
Z -1
R
＋
＋
＋
Ｘ
+
+＋
−
＋
C
Z -N
G
Ｙ
・fs of the focus system: 44.1 kHz
・fs of the tracking system: 44.1 kHz
(fs of the low-band compensation filter is 22.05 kHz.)
1
−N
G (Z) ＝G ×R
＋ (1−C×Z )
−1
1−Z
｛ G=
R=
TG
or
TEXP
TR
2
15
FG
FEXP
or
C=
TC
｝
or
128
FC
128
FR
2
15
K＝1
N in Z−N can be replaced with :
always 2 in case of the focus system.
1 in case of the tracking system.
SDD00025AEM
26
MN662790RSC
・Setting of loop filter constants
Table 7-1-3 (4)
Address
Command (HEX)
(HEX)
(B7 to B0)
(A7 to A0)
Data
(D7 to D0)
D7 D6
D5 D4
D3
D2 D1 D0
08
D7 D6
D5 D4
D3
D2 D1 D0
09
D7 D6
D5 D4
D3
D2 D1 D0
0A
D7 D6
D5 D4
D3
D2 D1 D0
0B
D7 D6
D5 D4
D3
D2 D1 D0
0C
D7 D6
D5 D4
D3
D2 D1 D0
0D
D7 D6
D5 D4
D3
D2 D1 D0
0E
D7 D6
D5 D4
D3
D2 D1 D0
0F
F2
Function
Setting
at reset
Focus phase compensation constant : 117
FC
(8-bit) (1 to 127)
Focus low-band compensation constant : 64
FR
(8-bit) (1 to 127)
Tracking phase compensation constant: 122
TC
(8-bit) (1 to 127)
Tracking low-band compensation constant : 64
TR
(8-bit) (1 to 127)
Focus phase compensation constant at 117
vibration : FC2
(8-bit) (1 to 127)
Focus low-band compensation constant at 64
vibration : FR2
(8-bit) (1 to 127)
Tracking phase compensation constant at 122
vibration : TC2
(8-bit) (1 to 127)
Tracking low-band compensation constant at 64
vibration : TR2
(8-bit) (1 to 127) SDD00025AEM
27
MN662790RSC
(C) Setting of gain crossover for optical servo loop
Before performing focus and tracking automatic adjustments, gain crossover after automatic adjustment
can be determined by writing data to the label name GSET (address: 10h) according to the table below.
In the automatic gain adjustment, disturbance is input to the servo loop, and gain is increased or decreased
according to the GSET setting after adjusting the gain so that the feedback gain at the frequency becomes
0 dB (gain crossover is equal to the frequency).
(Setting for focus system)
Data
(D7 to D0)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D3 D2
0 1
0 1
0 1
0 1
0 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 0
1 0
1 0
1 0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Table 7-1-3 (5)
Address (HEX)
Command (HEX)
(A7 to A0)
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
10
F2
(Setting for tracking system)
Data
(D7 to D0)
D7 D6 D5 D4
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Focus gain at the frequency set at 750 Hz
Approx. value： −3.92 dB
Approx. value： −3.36 dB
Approx. value： −2.80 dB
Approx. value： −2.24 dB
Approx. value： −1.68 dB
Approx. value： −1.12 dB
Approx. value： −0.56 dB
＊ Approx. value：
0 dB
Approx. value： 1.05 dB
Approx. value： 2.11 dB
Approx. value： 3.16 dB
Approx. value： 4.21 dB
Approx. value： 5.27 dB
Approx. value： 6.32 dB
Approx. value： 7.37 dB
Approx. value： 8.43 dB
Table 7-1-3 (6)
Address (HEX)
(A7 to A0) Command (HEX)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Function (*: Setting at reset)
10
F2
SDD00025AEM
Function (*: Setting at reset)
Tracking gain at the frequency set at 1 kHz
Approx. value： −3.92 dB
Approx. value： −3.36 dB
Approx. value： −2.80 dB
Approx. value： −2.24 dB
Approx. value： −1.68 dB
Approx. value： −1.12 dB
Approx. value： −0.56 dB
＊ Approx. value：
0 dB
Approx. value：
1.05 dB
Approx. value：
2.11 dB
Approx. value：
3.16 dB
Approx. value：
4.21 dB
Approx. value：
5.27 dB
Approx. value：
6.32 dB
Approx. value：
7.37 dB
Approx. value：
8.43 dB
28
MN662790RSC
(D) Setting for anti-vibration (VSET)
The gain-up amount and gain-up time can be set when VDET=H.
(VDET can be monitored through the VDETMON pin.)
Table 7-1-3 (7)
Address (HEX) Command (HEX)
(B7 to B0)
(A7 to A0)
Data
(D7 to D0)
Function (*: Setting at reset)
Setting of the focus gain-up amount at vibration
Scale factor ：×1.0
(0 dB)
Scale factor ：×1.125 (＋1.0 dB)
Scale factor ：×1.25 (＋1.9 dB)
Scale factor ：×1.375 (＋2.8 dB)
＊ Scale factor ：×1.5
(＋3.5 dB)
Scale factor ：×1.625 (＋4.2 dB)
Scale factor ：×1.75 (＋4.9 dB)
Scale factor ：×2.0
(＋6.0 dB)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ D5
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ 1
Ｘ 1
Ｘ 1
Ｘ 1
D4
0
0
1
1
0
0
1
1
D3
0
1
0
1
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Setting of the tracking gain-up amount at vibration
Scale factor ：×1.0
(0 dB)
Scale factor ：×1.125 (＋1.0 dB)
Scale factor ：×1.25 (＋1.9 dB)
Scale factor ：×1.375 (＋2.8 dB)
Scale factor ：×1.5
(＋3.5 dB)
Scale factor ：×1.625 (＋4.2 dB)
Scale factor ：×1.75 (＋4.9 dB)
＊ Scale factor ：×2.0
(＋6.0 dB)
D7 D6 ＸＸＸＸ
0 0 ＸＸＸＸ
0 1 ＸＸＸＸ
1 0 ＸＸＸＸ
1 1 ＸＸＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Setting of the gain-up time at vibration
Time ： 23.2 ms
Time ： 46.4 ms
＊ Time ： 92.9 ms
Time ：185.8 ms
Note)
11
F2
The gain-up amount set by VSET is valid only when FC2 or FR2 for the focus system or
TC2 or TR2 for the tracking system is written after VSET setting.
(No operation is performed to set servo parameters in the anti-vibration mode only by VSET setting.)
SDD00025AEM
29
MN662790RSC
The gain values can be overwritten when VDET＝H. Table 7-1-3 (8)
Data
(D7 to D0)
Address
( H EX )
(A7 to A0)
D7 D6 D5 D4 D3 D2 D1D0 2D
D7 D6 D5 D4 D3 D2 D1D0 2E
D7 D6 D5 D4 D3 D2 D1D0 35
D7 D6 D5 D4 D3 D2 D1D0 36
Command
(HEX)
(B7 to B0)
F2
Function
Focus gain constant at vibration (FG2)
(8-bit mantissa) (1 to 255)
Focus gain constant at vibration (FEXP2)
(8-bit exponent) (16, 32, 64 and 128 only)
(Focus gain constant = mantissa / exponent)
Tracking gain constant at vibration (TG2)
(8-bit mantissa) (1 to 255)
Tracking gain constant at vibration (TEXP2)
(8-bit exponent) (16, 32, 64 and 128 only)
(Tracking gain constant = mantissa / exponent)
Setting
values at
reset
128
32 128
64
Note) Be aware that the gain set with VSET applies at the time of fine gain adjustment and writing data to the
FC2, FR2, TC2 or TR2.
SDD00025AEM
30
MN662790RSC
(E) Various system settings
(E)-1 SET0 setting Address (HEX) Command (HEX)
(B7 to B0)
(A7 to A0)
Data
(D7 to D0)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D6
Ｘ 0
Ｘ 0
Ｘ 1
Ｘ 1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D4
0
1
0
1
D3 D2
0 0
0 1
1 0
1 1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
12
0
0
0
0
0
0
0
0
F2
Table 7-1-3 (9)
Function (*: Setting at reset)
1
1
1
1
Setting of forced brake operation time
OFF
ON (5.8 ms)
＊ ON (11.6 ms)
ON (23.2 ms)
1
1
1
1
Setting of convergence gain during tracking
balance adjustment
＊ ×1/2048
×1/4096 ×1/1024 ×1/8192 D5
ＸＸ 0 Ｘ
ＸＸ 1 Ｘ
ＸＸ 0 1
ＸＸ 0 1
Tracking balance adjustment output
＊ As usual
Inverted polarity
D7
0 ＸＸＸ
1 ＸＸＸ
ＸＸ 0 1
ＸＸ 0 1
TVD output smoothing ＊ OFF
O N
TVD output
Example of the TVD intermittent drive is as follows.
Smoothing OFF
TVD
Smoothing ON
TVD
2.9 ms
2.9 ms
SDD00025AEM
2.9 ms
2.9 ms
31
MN662790RSC
(E)-2 SET1 setting Table 7-1-3 (10)
Data
(D7 to D0)
D0
ＸＸＸＸＸＸＸ０
ＸＸＸＸＸＸＸ１
Address Command (HEX)
(HEX)
(B7 to B0)
(A7 to A0)
13
F2
Function (*: Setting at reset)
TVD output at the time of kick pulse output in the
traverse stop condition
＊TVD output
No TVD output
D1
ＸＸＸＸＸＸ０Ｘ
ＸＸＸＸＸＸ１Ｘ
Pull-in method when turning focus ON from OFF state
＊ Conventional method
High-speed pull-in
D2
ＸＸＸＸＸ０ＸＸ
ＸＸＸＸＸ１ＸＸ
High-speed kickback ON/OFF
＊ON
OFF
D4
ＸＸＸ０ＸＸＸＸ
ＸＸＸ１ＸＸＸＸ
Focus offset adjustment method
With vibration
＊Without vibration
D5
ＸＸ０ＸＸＸＸＸ
ＸＸ１ＸＸＸＸＸ
Focus offset adjustment method
＊＋direction (Same as MN66271)
−direction
D6
Ｘ０
Ｘ０
Ｘ１
Ｘ１
Standby time after TCNT
＊ 50 ms
100 ms
0 ms
10 ms
D3
ＸＸ０
ＸＸ１
ＸＸ０
ＸＸ１
ＸＸＸ
ＸＸＸ
ＸＸＸ
ＸＸＸ
D7
０ＸＸＸＸＸＸＸ
１ＸＸＸＸＸＸＸ
DAC output limiter
(FABC, TABC)
SDD00025AEM
＊OFF
ON
32
MN662790RSC
(E)-3 SET2 setting Table 7-1-3 (11)
Data
(D7 to D0)
D1 D0
ＸＸＸＸＸＸ０Ｘ
ＸＸＸＸＸＸ１０
ＸＸＸＸＸＸ１１
Address
(HEX)
(A7 to A0)
Command (HEX)
(B7 to B0)
14
F2
Function (*: Setting at reset)
Traverse dead-zone amp
＊ Normal
(Type A)
＋ side only (Type B)
− side only (Type C)
ＸＸＸＸ
ＸＸＸＸ
D2
Ｘ０ＸＸ
Ｘ１ＸＸ
Tracking offset adjustment standby time
None
＊ 30 ms
ＸＸＸＸ
ＸＸＸＸ
D3
０ＸＸＸ
１ＸＸＸ
Convergence judgement condition for
tracking balance adjustment
＊ ±2 LSBs at TBAL output stage
±1 LSB at TE input stage
D5D4
ＸＸ００ＸＸＸＸ
ＸＸ０１ＸＸＸＸ
ＸＸ１０ＸＸＸＸ
ＸＸ１１ＸＸＸＸ
Focus balance adjustment convergence gain
＊ 1／8 1／4
1／32
1／16
D6
Ｘ０ＸＸＸＸＸＸ
Ｘ１ＸＸＸＸＸＸ
Disc detection, focus rough gain adjustment
frequency
＊ 5.4 Hz
2.6 Hz
D7
０ＸＸＸＸＸＸＸ
１ＸＸＸＸＸＸＸ
Traverse intermittent drive
＊ Output enabled
Output disabled
DED0×2
DED0
Figure 1 Traverse dead-zone amp Type A
Figure 2 Traverse dead-zone amp Type B
DED0×2
Figure 3 Traverse dead-zone amp Type C
Note) Refer to 7-1 (4) (F)-6 for the DED0 setting.
SDD00025AEM
33
MN662790RSC
(E)-4 SET3 setting Table 7-1-3 (12)
Data
(D7 to D0)
Address Command (HEX)
(HEX)
(B7 to B0)
(A7 to A0)
D1 D0 1E
ＸＸＸＸＸＸ００ＸＸＸＸＸＸ０１
ＸＸＸＸＸＸ１０
ＸＸＸＸＸＸ１１
F2
Function (*: Setting at reset)
TVD gain variable
＊ 0 dB (×1.0)
3.5 dB (×1.5)
6.0 dB (×2.0)
−2.5 dB (×0.75)
D2
ＸＸＸＸＸ０ＸＸ
ＸＸＸＸＸ１ＸＸ
Cancellation of focus balance adjustment
＊ Reset to the initial value at the start
of adjustment
The adjusting value is on hold
D3
ＸＸＸＸ０ＸＸＸ
ＸＸＸＸ１ＸＸＸ
Tracking rough gain adjustment time
＊ 134 ms
319 ms
D4
ＸＸＸ０ＸＸＸＸ
ＸＸＸ１ＸＸＸＸ
Focus search mode
＊ As usual
Amplitude: 1/4
D5
ＸＸ０ＸＸＸＸＸ
ＸＸ１ＸＸＸＸＸ
Offset readjustment after tracking fine gain
adjustment
＊ Performed automatically
Not performed
D6
Ｘ０ＸＸＸＸＸＸ
Ｘ１ＸＸＸＸＸＸ
Focus balance adjustment output
＊ As usual
Inverted polarity
D7
０ＸＸＸＸＸＸＸ
１ＸＸＸＸＸＸＸ
Focus search frequency
＊ 1.3 Hz
2.6 Hz
SDD00025AEM
34
MN662790RSC
(E)-5 SET5 setting Table 7-1-3 (13)
(Setting of vibration detection band-pass filter constant)
Address
Data
Command (HEX)
(HEX)
(D7 to D0)
(B7 to B0)
(A7 to A0)
D1D0 15
ＸＸＸＸＸＸ００ＸＸＸＸＸＸ０１ＸＸＸＸＸＸ１０ＸＸＸＸＸＸ１１
Function (*: Setting at reset)
Setting of LPF 2nd stage constant C
3
4 ＊ 5 6 F2
D 3D 2
ＸＸＸＸ００ＸＸ
ＸＸＸＸ０１ＸＸ
ＸＸＸＸ１０ＸＸ
ＸＸＸＸ１１ＸＸ
Setting of LPF 1st stage constant B
3
4
＊ 5
6
D5D4
ＸＸ００ＸＸＸＸ
ＸＸ０１ＸＸＸＸ
ＸＸ１０ＸＸＸＸ
ＸＸ１１ＸＸＸＸ
Setting of HPF constant A
3
4
＊ 5
6
D7D6
００ＸＸＸＸＸＸ
０１ＸＸＸＸＸＸ
１０ＸＸＸＸＸＸ
１１ＸＸＸＸＸＸ
Vibration detection level exponent part
×1 Note) Refer to 7-1 (4)
×2
(F)-11 for the
＊ ×4 setting of mantissa
×8
part.
×1 / 2
＋
TRE
＋
＋
−
Ｚ
＋
-1
＋
＋
Ｚ
-1
＋
＋
Ｚ
-1
−
Ｚ
Vibration detection
signal
(VDET)
-1
Detection
level
A
1-2 / 256
HPF
Ｂ
1-2 / 256
Ｃ
1-2 / 256
LPF 1st stage LPF 2nd stage
SDD00025AEM
35
MN662790RSC
(E)-6 SETTB setting Table 7-1-3 (14)
Data
(D7 to D0)
Address Command (HEX)
(HEX)
(B7 to B0)
(A7 to A0)
D0 4A
ＸＸＸＸＸＸＸ０
ＸＸＸＸＸＸＸ１
F2
Function (*: Setting at reset)
Tracking brake damping reinforcement
＊ Damping reinforcement mode 1
Damping reinforcement mode 2
ＸＸＸＸ
ＸＸＸＸ
D2
Ｘ０ＸＸ
Ｘ１ＸＸ
Low-band compensation during tracking brake
operation
＊ Yes
No
Tracking brake timing
＊ Reference at 1/4-track-before
Reference at zero cross
ＸＸＸＸ
ＸＸＸＸ
D3
０ＸＸＸ
１ＸＸＸ
Dropout countermeasure during KICK operation
＊ No
Yes
D1
ＸＸＸＸＸＸ０ＸＸＸＸＸＸＸ１Ｘ
D5
ＸＸ０Ｘ
ＸＸ１Ｘ
ＸＸＸＸ
ＸＸＸＸ
D6
Ｘ０ＸＸ
Ｘ１ＸＸ
ＸＸＸＸ
ＸＸＸＸ
Brake timing countermeasure with OFT noise filter
turned on
＊ No
Ye s
Hunting countermeasure for focus balance
adjustment
No
＊ Ye s
D7
０ＸＸＸ
１ＸＸＸ
ＸＸＸＸ
ＸＸＸＸ
Tracking brake noise elimination
＊ Ye s
No
・Damping Reinforcement
Damping is reinforced by changing the level of KICK pulses, which is set with the KICK2, with
servo control turned on in KICK operation.
Mode 1: The inverted pulse in full brake speed control and servo control is set as KICK2.
Mode 2: In addition to the condition in mode 1, the inverted pulse drive after the target track
is passed is also set as KICK2.
※ Refer to 7-1 (4) (F)-9 for the KICK pulse level setting.
SDD00025AEM
36
MN662790RSC
(E)-7 Software reset
The servo processing is initialized if data of AAh address is accessed. DSP processing starts with the
first address. Table 7-1-3 (15)
Data
(D7 to D0)
Address
(HEX)
(A7 to A0)
Command
(HEX)
(B7 to B0)
ＸＸＸＸＸＸＸＸ AA
F2
Function (*: Setting at reset)
Software reset (Data is disabled.)
(E)-8 Forced gain-up setting
The LSI can be in forced gain-up mode by accessing the data of 81h address.
This mode is reset by accessing the data in 80h address. Table 7-1-3 (16)
Data
(D7 to D0)
Address
(HEX)
(A7 to A0)
ＸＸＸＸＸＸＸＸ
81
ＸＸＸＸＸＸＸＸ
80 Command
(HEX)
(B7 to B0)
Function (*: Setting at reset)
F2 Focus / tracking forced gain-up
(Data is disabled.)
Focus / tracking normal gain
(Data is disabled.)
Note) ・The VDET monitor signal is not set to H when the forced gain-up command is issued.
・The status of the VDET can be monitored through the VDETMON pin.
・The output of the VDETMON pin varies from H to L when vibration is detected even
in the forced gain-up mode. Then, this mode is not reset.
SDD00025AEM
37
MN662790RSC
(F) Optical servo system setting
(F)-1 Focus search setting Address
(8 bits)
Command (HEX)
(B7 to B0)
D6 D5 D4 D3 D2 D1 D0
18
F2
D0
19
Data (8 bits)
0
Table 7-1-3 (17)
Setting
at reset
Function
Focus search amplitude (CRAM2) setting
8-bit data (p-p) (40 to 127)
Focus search/disc detection direction (SD)
setting
8-bit data (0, 1)
(0: Reducing FOD) 45
0
Note 1) In focus search/disc detection direction setting, a value of SD will change automatically according to
execution of a focus search/disc detection. Consequently, the values written by initial setting and DTMS
may have changed when they are read out with DTSM. If you want to perform a focus search/disc detection
from the same direction every time, it is necessary to set with DTMS every time before the focus search/disc
detection.
To make SD settings, check the SD value with the DTSM so that no bit values other than the set bit value
will change.
(F)-2 Setting of tracking servo fail-safe value (CRAM3) Data (8 bits)
0
D6 D5 D4 D3 D2 D1 D0
Address
(8 bits)
Command (HEX)
(B7 to B0)
1C
F2
Table 7-1-3 (18)
Setting
at reset
Function
72
Fail-safe value clip level
8-bit data (0 to 127)
Low-band component of drive output in the
tracking brake mode is clipped at the specified
value.
(F)-3 Setting of disturbance amplitude (CRAM4) in tracking balance adjustment Data (8 bits)
0
D6 D5 D4 D3 D2 D1 D0
Address
(8 bits)
Command (HEX)
(B7 to B0)
1D
F2
SDD00025AEM
Table 7-1-3 (19)
Function
Disturbance amplitude (one side)
8-bit data (0 to 127)
Amplitude of the disturbance waves input in
the tracking balance adjustment is set.
Actual disturbance amplitude is 1/8×CRAM4.
Setting
at reset
72
38
MN662790RSC
(F)-4 KICK setting Data (8 bits)
Address
(8 bits)
Command (8 bits)
ＸＸＸＸ D3 D2 D1 D0
1A
F2
D7 D6 D5 D4 ＸＸＸＸ
Table 7-1-3 (20)
Setting
values at
reset
Function
KICK speed (KS) setting
4-bit data (6 to 15)
KICK brake timing setting
4-bit data (0 to 15)
6
0
・TE cycle in the speed control mode is determined by the KICK speed setting.
KS (D3 to D0)×22.6 µs
TE
・KICK brake output timing delay time is set in the KICK brake timing setting.
(1 count＝22.6 µs delay) Setting value＝0: No delay
〔1/4-track-before Brake Mode〕 SETTB (address: 4Ah) D2=0
① When OFT is turned to "L" before reaching a position
of 1/4 track
OFT
1/4 track
TE
② When OFT is turned to "L" after passing the
position of 1/4 track
OFT
TE
Delay
Delay
KICK
KICK
Brake
Brake
〔Zero Cross Brake Mode〕 SETTB (address: 4Ah) D2=1
OFT
TE
Delay
KICK
Brake
SDD00025AEM
39
MN662790RSC
(F)-5 Traverse drive constant in tracking brake (TVG) Data (8 bits)
Address
(8 bits)
Command (8 bits)
ＸＸＸＸ D 3 D2 D1 D0
1B
F2
Table 7-1-3 (21)
Traverse drive constant
TVG (1 to 15) Only in the tracking brake, traverse will be
driven with the traverse error multiplied by the
required constant.
(F)-6 Traverse drive dead zone setting (DED0)
Data (8 bits)
Address
(8 bits)
0 D6 D5 D4 D3 D2 D1 D0
1F
Setting
at reset
Function
2
Table 7-1-3 (22)
Command
(8 bits)
Setting
at reset
Function
Traverse drive dead zone setting (one
side)
F2
24
DED0 (0 to 127)
(F)-7 TE noise elimination width setting at track count/kick (SETKC)
Data (8 bits)
Address
(8 bits)
Command
(8 bits)
0 D6 D5 D4 D3 D2 D1 D0
49
F2
Table 7-1-3 (23)
Function
TE noise elimination width setting at
track counting/kick
Setting
at reset
3
SETKC (0 to 127)
Target track
TE
SETKC
※ When the TE gradient is inverted
and reaches the level of the SETKC,
braking completes.
KICK
(TRD)
Brake
SDD00025AEM
40
MN662790RSC
(F)-8 KICK pulse width setting (KCCNT) Data (8 bits)
D7 D6 D5 D4 ＸＸＸＸ
Address
(8 bits)
Command (HEX)
(B7 to B0)
4B
F2
ＸＸＸＸ D3 D2 D1 D0
TE
Table 7-1-3 (24)
Setting
at reset
Function
1
Inverted pulse width during servo pull-in
operation in KICK operation.
(Set value×22.6＋11.3) µs
KICK pulse initial accelerating time (0 to 15)
(Set value×22.6) µs 5
TE
Inverted pulse width
KICK
(TRD)
KICK
(TRD)
Brake
Initial accelerating time
Table 7-1-3 (25)
(F)-9 KICK pulse level setting (KICK and KICK2)
Command
Address
(HEX)
Data (8 bits)
(8 bits)
(B7 to B0)
0 D6 D5 D4 D3 D2 D1 D0
78
0 D6 D5 D4 D3 D2 D1 D0
7A
F2
Setting
at reset
Function
Setting KICK pulse level in normal operation
KICK (0 to 127)
84
Setting KICK pulse level during servo pull-in
operation
KICK2 (0 to 127)
84
(F)-10 Traverse output gain setting (TRV)
Table 7-1-3 (26)
Data (8 bits)
Address
(8 bits)
Command
(HEX)
(B7 to B0)
0 D6 D5 D4 D3 D2 D1 D0
79
F2
Function
Traverse output gain setting
TRV (0 to 127)
SDD00025AEM
Setting
at reset
95
41
MN662790RSC
(F)-11 VDET detecting level setting Data (8 bits)
D 7 D 6 D5 D 4 D 3 D 2 D 1 D 0
Address
(8 bits)
Command (HEX)
(B7 to B0)
7B
F2
Table 7-1-3 (27)
Setting
at reset
Function
VDET detection TE threshold level setting
(mantissa part)
VSLT (1 to 255) 57
Threshold level exponent part
(Refer to 7-1 (4) (E)-5.)
SET5 [D7, D6] threshold level
VSLT
TE
〔0，0〕：±VSLT×1
0
〔0，1〕：±VSLT×2
〔1，0〕：±VSLT×4
〔1，1〕：±VSLT×8
VDET
(F)-12 Number of disturbance waves in fine gain adjustment (PHSU) Address Command (HEX)
(8 bits)
(B7 to B0)
Data (8 bits)
D7 D6 D5 D4 D3 D2 D1 D0
7C
F2
Table 7-1-3 (28)
Function
Number of disturbance waves in fine
gain adjustment (See Note.)
PHSU (1 to 255) Setting
at reset
129
Note) The convergence gain increases as the number of disturbance waves increases.
(F)-13 Setting of convergence gain in fine gain adjustment (PDK) Table 7-1-3 (29)
Address Command (HEX)
(8 bits)
(B7 to B0)
Data (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
D7
0
0
0
0
1
1
1
1
D6
0
0
1
1
0
0
1
1
Ｄ5
0
1
0
1
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
61
F2
Function
Convergence gain in Fo fine gain adjustment
× 1
× 2
＊ × 4
× 8
× 16
× 32
× 64
×128
Setting
at reset
66
Convergence gain in Tr fine gain adjustment
× 1
× 2
＊ × 4
× 8
× 16
× 32
× 64
×128
SDD00025AEM
42
MN662790RSC
(F)-14 Setting of automatic adjustment range
The limits of adjustment values can be set arbitrarily in the range of 1/128 to 255/16 (or −42 dB to ＋24 dB).
In order to ensure automatic gain convergence within a limited, narrow adjustment range to prevent
excessive gain change, which has difficulty in convergence control, however, make sure that the maximum
automatic adjustment range is ±9 dB on the basis of the gain set value.
・Tracking gain
Automatic adjustment range GLT3/GLT4 to GLT1/GLT2
Table 7-1-3 (30)
Data (8 bits)
Address
(8 bits)
D7 D6 D5 D4 D3 D2 D1 D0
3D
D7 D6 D5 D4 D3 D2 D1 D0
3E
D7 D6 D5 D4 D3 D2 D1 D0
3F
D7 D6 D5 D4 D3 D2 D1 D0
40
Command
(HEX)
(B7 to B0)
F2
Setting
at reset
Function
Tracking gain upper limit
GLT1 (mantissa) (128 to 255)
GLT2 (exponent) (128, 64, 32, 16)
181
Tracking gain lower limit
GLT3 (mantissa) (128 to 255)
GLT4 (exponent) (128, 64, 32, 16)
91
32
128
GLT1 and GLT3 can be both set to 127 or a smaller value only if GLT2 and GLT4 are both set to 128.
・Focus gain
Automatic adjustment range GLF3/GLF4 to GLF1/GLF2
Data (8 bits)
Address
(8 bits)
Command
(HEX)
(B7 to B0)
F2
D7 D6 D5 D4 D3 D2 D1 D0
39
D7 D6 D5 D4 D3 D2 D1 D0
3A
D7 D6 D5 D4 D3 D2 D1 D0
3B
D7 D6 D5 D4 D3 D2 D1 D0
3C
Table 7-1-3 (31)
Function
Setting
at reset
Focus gain upper limit
GLF1 (mantissa) (128 to 255)
GLF2 (exponent) (128, 64, 32, 16)
181
Focus gain lower limit
GLF3 (mantissa) (128 to 255)
GLF4 (exponent) (128, 64, 32, 16)
181
16
128
GLF1 and GLF3 can be both set to 127 or a smaller value only if GLF2 and GLF4 are both set to 128.
SDD00025AEM
43
MN662790RSC
[3] Access command setting
Table 7-1-3 (32)
Data (16 bits)
Command (8 bits)
0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
KICK-count setting
0
(other than 0)
1 1 1 1 0 0 0 1
KICK-count setting/KICK
operation start
Inner track KICK operation
Outer track KICK operation
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
1
Track-count setting
1 1 1 1 0 0 1 1
Track-count setting / Track
counting start
Inner track counting
Outer track counting
D15 0
0
0
0
1
0
0
0
0
0
0
0
0
0
Function
Note) The track-count means the number of tracks until the brake operation start point is reached.
SDD00025AEM
44
MN662790RSC
7-1 (4) Data setting in signal processing section
(A) Audio output control (I) Data (16 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Address (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ D1 D0
Ｘ 0 0
Ｘ 0 1
Ｘ 1 0
Ｘ 1 1
01000001
ＸＸＸＸＸＸＸＸＸＸＸＸＸ D2 ＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
Ｘ D6 D5
ＸＸ 0
Ｘ 0 1
Ｘ 1 1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Function (*: Setting at reset)
Available for bilingual
＊ Normal stereo
L-ch monaural
R-ch monaural
L-/R-ch reverse
D/A converter output polarity
＊ Normal
Inverse
D4 D3 Ｘ
0 ＸＸ
1 0 Ｘ
1 1 Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Emphasis control
＊ Control by DEMPH output
Forced OFF
Forced ON
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Peak detection
＊ L-ch, R-ch
L-ch
R-ch
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Table 7-1-4 (1)
ＸＸＸＸＸＸＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸ
CLV synchronization stabilized status detection flag control
ＸＸＸＸＸＸ D9 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸ
SRDATA de-emphasis control
＊ Not controlled
Controlled
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D11 D10 ＸＸ
0 0 ＸＸ
0 1 ＸＸ
1 0 ＸＸ
1 1 ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
＊ Accepted at 64 counts of IPFLAG
Accepted at 32 counts of IPFLAG
CD-TEXT control
＊ Not controlled
CD-TEXT mode 1
CD-TEXT mode 2
CD-TEXT mode 3
ＸＸＸ D12 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸＸ
CD-TEXT CRC operation control
＊ CRC operation result output
TEXT data position flag output in BLKCK
ＸＸ D13 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
TEXT data output byte control in CD-TEXT mode 3
＊ TEXT data 16-byte output
TEXT data 18-byte output
D15 ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
0 ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
1 ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
SDD00025AEM
CD-TEXT mode 4 control
＊ Not controlled
CD-TEXT mode 4
45
MN662790RSC
(B) Digital audio interface control
Table 7-1-4 (2)
Data (16 bits) ＸＸ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D3
0
0
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D1 D0
0 0
1 0
1 1
ＸＸ
Address (8 bits)
Function (*: Setting at reset)
0 1 0 0 0 0 1 0
Bit U control of TX output
＊ LDON control
Bit U enabled
Bit U fixed to "H"
Mute control
(Bit U is fixed to "H" with DMUTE pin set
to "H" or with SRDATA mute command.)
ＸＸＸＸＸＸＸＸＸＸＸＸＸ D2 ＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸ
Generation status bit control of TX output
＊ Generation status bit 0
Generation status bit 1
ＸＸＸＸＸＸＸＸＸＸＸ D4 ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸ
TX mute control
＊ Mute OFF
Mute ON
ＸＸＸＸＸＸＸＸＸＸ D5 ＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸ
TX Bit V mode selection (during interpolation)
＊ Bit V is ON
Bit V is not ON
ＸＸＸＸＸＸＸＸＸ D6 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸ
TX data selection
＊ DF input data
As usual
ＸＸＸＸＸＸＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸ
TX Bit V mode selection (during ATT)
＊ Bit V is ON
Bit V is not ON
SDD00025AEM
46
MN662790RSC
(C) General-purpose I/O port control The general-purpose I/O port has four pins, which are GIO0 through GIO3 pins. The default settings of the
GIO0 and GIO3 pins are for the input signals SQCK and RSEL of the LSI respectively.
Command execution makes it possible to make general-purpose I/O port settings of the GIO0 and GIO3 pins.
Unlike the GIO0 and GIO3 pins, the GIO1 and GIO2 pins work as output ports at the time of LSI resetting.
The GIO1 and GIO2 pins have low-level output.
Command execution makes it possible to make general-purpose I/O port settings and CLDCK and FCLK
output signal settings of the LSI.
Note) Do not apply middle-level input if these pins are used as general-purpose input ports.
Table 7-1-4 (3)
Data (16 bits) Address (8 bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X 0 1 1 0 0 1 1 0 X X X X
X
X
X
X
X
X
X
X
X
X
X
X
X X X X X X X X X 0
X X X X X X X X X 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D2
０
０
１
１
D1
０
１
０
１
X
X
X
X
Function (*: Setting at reset)
0 1 0 0 0 0 1 1
＊ Default setting
Port output value setting
0: Output value at "L"
1: Output value at "H"
(Enabled when the port is set as
output port.)
Port designation address
GIO0 designation
GIO1 designation
GIO2 designation
GIO3 designation
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3
X X X X X X ０ X X X
X X X X X X １ X X X
Port output value setting enabled or
disabled
Port output value setting disabled
Port output value setting enabled
X
X
D7 D6 D5 D4
X X G IO3 G IO2 G IO1 G IO0 X X X X
Port I/O mode setting
0: Input port
1: Output port
X
X
X
X
X
X
X
D11 D10 D9 D8
X G IO3 G IO2 G IO1 G IO0 X X X X X X X X
D 15
0 X
1 X
X
X
X
X
X
X
X
X
X X X X X X X X X X
X X X X X X X X X X
D14
0 X
1 X
X
X
X
X
X
X
X X X
X X X
X
X
X X X X X
X X X X X
X X
X X
Function selection mode setting
0: LSI I/O mode
1: General-purpose I/O port mode
Mode setting enabled or disabled
0: I/O mode setting and function
selection mode setting disabled
1: I/O mode setting and function
selection mode setting enabled
RF signal polarity control
RF polarity bright level "L"
＊ RF polarity bright level "H"
If D15 disables mode setting, the command is disabled except the port output signal level setting data.
Therefore, changes in the output signal level are made with ease.
After all settings, the input signals (or output signals if the port is so set) of the GIO3 through GIO0 pins are
output from the STAT pin in series. The signals are output in synchronization with the falling edge of the
MCLK as shown in the following timing chart.
SDD00025AEM
47
MN662790RSC
0 1 0 0 0 0 1 1
MDATA
Data
NOP
MCLK
MLD
STAT output
GIO3
GIO0 GIO1 GIO2 GIO3
General-purpose I/O port output timing
SDD00025AEM
48
MN662790RSC
(D) Spindle control Table 7-1-4 (4)
Data (16 bits) Address (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ D10
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D4
0
0
1
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D0
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ D10
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ 0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D2
0
0
1
1
D1
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0 1 0 0 0 1 0 1
Function (*: Setting at reset)
f0 frequency setting
＊ f0 ＝24 Hz
f0 ＝ 6 Hz
f0 ＝12 Hz
f0 ＝ 3 Hz
Spindle gain setting
＊ Normal gain
Gain ＋ 6 dB
Gain ＋12 dB
Gain − 6 dB
ＸＸＸＸＸ D10 ＸＸＸＸＸＸ D3 ＸＸＸ
ＸＸＸＸＸ 0 ＸＸＸＸＸＸ 0 ＸＸＸ
ＸＸＸＸＸ 0 ＸＸＸＸＸＸ 1 ＸＸＸ
4x-speed playback mode setting
＊ 4x-speed playback mode canceled
4x-speed playback mode setting
ＸＸＸＸＸ D10 ＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 ＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 ＸＸ 1 ＸＸＸＸＸＸＸ
SRF/EFM input selection
＊ SRF input
EFM input
ＸＸＸＸＸ D10 Ｘ D8 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 Ｘ 0 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 Ｘ 1 ＸＸＸＸＸＸＸＸ
PC pin polarity setting
＊ When spindle monitor output is
ON, PC pin=L.
When spindle monitor output is
ON, PC pin=H.
ＸＸＸＸ D11 D10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ 0 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ 1 0 ＸＸＸＸＸＸＸＸＸＸ
Jitter-free mode
＊ OFF
ON
ＸＸＸ D12 Ｘ D10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 0 Ｘ 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 1 Ｘ 0 ＸＸＸＸＸＸＸＸＸＸ
PLL phase comparison output (PLLF)
＊ ON
OFF (Only when tracking is OFF)
ＸＸ D13 ＸＸ D10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸ 0 ＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸ 1 ＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
STAT output selection
＊ OFF (Normal )
ON (FCLV→RESY)
ＸD14 ＸＸＸ D10 ＸＸＸＸＸＸＸＸＸＸ
Ｘ 0 ＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
Ｘ 1 ＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
Power-down mode setting
＊ Normal mode
Power-down mode
(DF/DAC clock stopped)
Note) f0 frequency:
Considering the gain crossover point to
be fV, the point shown on the right is
described as f0.
Phase component
Velocity component
f0
SDD00025AEM
fV
49
MN662790RSC
(E) Audio output control (II)
Data (16 bits) Table 7-1-4 (5)
Address (8 bits)
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ D0
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ 0
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ 1
0 1 0 0 0 1 1 0
Function (*: Setting at reset)
Correction CPU reset control
＊ Not controlled
Reset
ＸＸＸＸＸＸＸＸＸ D6 ＸＸＸ D2 D1 Ｘ
ＸＸＸＸＸＸＸＸＸ 0 ＸＸＸ 0 0 Ｘ
ＸＸＸＸＸＸＸＸＸ 1 ＸＸＸ 1 1 Ｘ
C2 correction selection
＊ C2 triple correction
C2 quadruple correction
ＸＸＸＸＸＸＸＸＸＸＸＸ D3 ＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸ
CLDCK output duty control
＊ Normal
50 % output duty
ＸＸＸＸＸＸＸＸＸＸＸ D4 ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸ
SRDATA attenuation control
＊ Not controlled
Attenuation (−12 dB)
ＸＸＸＸＸＸＸＸＸＸ D5 ＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸ
PCK and EFM output control
＊ Normal output
PCK and EFM output fixed to L
ＸＸＸＸＸＸＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸ
CK384 control (at IOSEL=L)
＊ CK384 output (Xtal)
384fs output for signal processing
(VCO output in jitter-free mode)
ＸＸＸＸＸＸＸ D8 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸ
Spindle gain-down
＊ No gain-down
−3.5 dB (One per three ECS outputs is not
output.)
ＸＸＸＸＸＸ D9 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸ
EDATA flag selection
＊ FLAG0
IPFLAG
ＸＸＸＸＸ D 10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ１ＸＸＸＸＸＸＸＸＸＸ
Serial data mute control
＊ Mute OFF
Mute ON
ＸＸＸＸ D11 ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸ
DF/DAC output mute
＊ Mute OFF
Mute ON
ＸＸＸ D12 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ１ＸＸＸＸＸＸＸＸＸＸＸＸ
PLL pull-in mode selection
＊ 12T detection output width: 64 PCK
12T detection output width: 32 PCK
Note) Set the C2 correction selection to the triple correction mode for audio CD playback.
Note) When using C2 quadruple correction, set the selection (2T or 5T) of 4Dh command PLL detection to 2T.
SDD00025AEM
50
MN662790RSC
Data (16 bits) Ｘ D14 D13 Ｘ
Ｘ 0 0 Ｘ
Ｘ 0 １Ｘ
Ｘ 1 0 Ｘ
Ｘ 1 1 Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Address (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0 1 0 0 0 1 1 0
Function (*: Setting at reset)
PLLF2 pin control (on-chip switch)
＊ Forced OFF
Forced ON
ON with RESY set to "H"
ON with RESY set to "L"
PCK pin output mode
＊ PLL clock output
DSL balance output
D15 ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
0 ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
１ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
(F) Audio output control (III) Data (16 bits) Address (8 bits)
ＸＸＸＸ D11 ＸＸＸＸＸ D5 ＸＸＸＸ D0
ＸＸＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸＸ 0
ＸＸＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸＸ 1
0 1 0 0 0 1 1 1
Table 7-1-4 (6)
Function (*: Setting at reset)
RFDET processing control of servo CPU
＊ RFDET normal processing
Data processed as L-level signal
regardless of input
ＸＸＸＸ D11 ＸＸＸＸＸ D5 ＸＸＸ D1 Ｘ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸ 0 Ｘ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸ 1 Ｘ
STAT output selection
(with output selected with MCLK)
＊ OFF (Normal)
ON (FLOCK → RFDET)
ＸＸＸＸ D11 ＸＸＸＸＸ D5 ＸＸ D2 ＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸＸＸＸ 0 ＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸＸＸＸ 1 ＸＸ
DSLBDA pin output mode
＊ Not controlled
DSLB DAC output
ＸＸＸＸ D11 ＸＸＸＸＸ D5 Ｘ D3 ＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 Ｘ 0 ＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 Ｘ 1 ＸＸＸ
SUBQ output control (SSEL＝H)
＊ MSB-first output
LSB-first output in the unit of byte
ＸＸＸＸ D11 ＸＸＸＸＸ D5 D4 ＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 0 ＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸＸ 0 1 ＸＸＸＸ
Oscillation stop control (See Note.)
＊ Normal
Oscillation stop
ＸＸＸＸ D11 ＸＸＸＸ D6 D5 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸ 0 0 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸＸ１ 0 ＸＸＸＸＸ
DSL balance compensation circuit setting
＊ Operation stop (with output on hold)
Compensation value retrieval
ＸＸＸＸ D11 ＸＸＸ D7 Ｘ D5 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸ 0 Ｘ 0 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸＸ１Ｘ 0 ＸＸＸＸＸ
TRV pin intermittent drive control
＊ Normal mode (continuous drive)
Intermittent drive (at 44.1 kHz)
ＸＸＸＸ D11 ＸＸ D8 ＸＸ D5 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸ 0 ＸＸ 0 ＸＸＸＸＸ
ＸＸＸＸ 0 ＸＸ１ＸＸ 0 ＸＸＸＸＸ
DSL offset function with Tr OFF
＊ With DSL offset
With no DSL offset
ＸＸＸＸ D11 Ｘ D9 ＸＸＸ D5 ＸＸＸＸＸ
ＸＸＸＸ 0 Ｘ 0 ＸＸＸ 0 ＸＸＸＸＸ
ＸＸＸＸ 0 Ｘ 1 ＸＸＸ 0 ＸＸＸＸＸ
LSI clock control
＊ Clock enabled
Clock disabled
ＸＸＸＸ D11 D10 ＸＸＸＸ D5 ＸＸＸＸＸ
ＸＸＸＸ 0 0 ＸＸＸＸ 0 ＸＸＸＸＸ
ＸＸＸＸ 0 1 ＸＸＸＸ 0 ＸＸＸＸＸ
Power down control
＊ Not controlled
VCO, A/D, DF/DAC disabled
Note) Oscillation stop control can be reset with RST.
SDD00025AEM
51
MN662790RSC
Data (16 bits) Ｘ
Ｘ
Ｘ
Ｘ
Ｘ D13D12 D11
Ｘ 0 0 0
Ｘ 0 1 0
Ｘ 1 1 0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D5
0
0
0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Address (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0 1 0 0 0 1 1 1
Function (*: Setting at reset)
Track cross operation control
＊ Not controlled
Noise elimination at 4 MHz
Noise elimination at 2 MHz
KICK pulse width control
＊ Not controlled
Controlled
Ｘ D14 ＸＸ D11 ＸＸＸＸＸ D5 ＸＸＸＸＸ
Ｘ 0 ＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸＸＸ
Ｘ 1 ＸＸ 0 ＸＸＸＸＸ 0 ＸＸＸＸＸ
(G) CLV speed setting
Data (16 bits) ＸＸ
ＸＸ
ＸＸ
ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Address (8 bits)
Ｘ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 0 1
Ｘ 0 0 0 0 0 0 0 0 0 0
Ｘ 0 0 1 0 0 0 0 0 0 0
Ｘ 1 1 0 1 1 1 1 1 1 1
Table 7-1-4 (7)
Function (*: Setting at reset)
Setting of variable pitch data (D9 to D0)
＊0％
＋51.1 ％ (maximum value)
−51.2 ％ (minimum value)
ＸＸＸＸＸ D10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸ
Variable pitch selection
＊ Variable pitch OFF
Variable pitch ON
ＸＸＸＸ D 11 ＸＸＸＸＸＸＸＸＸＸＸ
ON/OFF setting of VCO oscillation for
variable pitch control (See Note.)
＊ VCO oscillation OFF
VCO oscillation ON
ＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸ D11 ＸＸＸ D7 D6 D5 D4 D3 D2 D1 D0
ＸＸＸＸ 1 ＸＸＸ D7 D6 D5 D4 D3 D2 D1 D0
Disc rotation speed judgement data setting
(in jitter-free mode)
8-bit data
ＸＸＸ D 12 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸＸ
DF/DAC clock lock setting
＊ Normal
Locked
ＸＸ D13 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸ 0 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸ 1 ＸＸＸＸＸＸＸＸＸＸＸＸＸ
VCO charge pump current source control
＊ Current ON
Current OFF
Note) In jitter-free mode, turn VCO on.
SDD00025AEM
52
MN662790RSC
(H) DSL and PLL control (I)
Data (16 bits) Address (8 bits)
Table 7-1-4 (8)
Function (*: Setting at reset)
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
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Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D1
0
0
1
1
D0 0 1 0 0 1 0 1 1
0
1
0
1
PLLF current selection
＊ ×1
×1.25
×0.5
×0.75
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
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Ｘ
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Ｘ
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Ｘ
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Ｘ
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Ｘ
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Ｘ
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Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D3 D2
0 0
0 1
1 0
1 1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
PLLF current selection (Linked with value
＊ ×1 set in D1 and D0)
×1.25
×0.5
×0.75
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D5 D4
0 0
0 1
1 Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
OFT noise filter control
＊ Not controlled
Control mode 1
Control mode 2
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸＸＸＸＸＸＸＸ D6 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸ
VCO control
＊ Pitch control and servo VCO operation
VCO stopped
ＸＸＸＸＸＸＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸ
PLL frequency-dividing control (See Note.)
＊ Not controlled
Controlled
D6 of address 4Bh and D11 of address 49h are available to a command each for controlling the VCO for pitch
control and/or that for servo use. Refer to the following for available control modes according to the command.
4Bh D6
(VCO control)
49h D11
(Pitch control VCO oscillation)
Pitch control VCO
Servo VCO
０
１
１
−
０
１
Oscillation
Stop
Oscillation
Oscillation
Stop
Stop
Note) In principle, set the bit to 1 to enable PLL frequency-dividing control.
SDD00025AEM
53
MN662790RSC
(I) DSL and PLL control (II)
Data (16 bits) Address (8 bits)
ＸＸＸＸＸＸＸＸＸＸＸＸ D3 Ｘ D1 D0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
0 0 0 0
0 ＸＸＸＸＸＸ D2 ＸＸ
0 ＸＸＸＸＸＸ 0 ＸＸ
0
0
0 0 0 0
0 ＸＸＸＸＸＸ
0
0
0
0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
0 ＸＸＸＸ D4 ＸＸＸＸ
0 ＸＸＸＸ 0 ＸＸＸＸ
0 ＸＸＸＸ 1 ＸＸＸＸ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 D8
0 0
0 1
0 1
0 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D7
0
1
0
0
D6
0
0
1
0
D5
0
1
1
0
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0
Ｘ
Ｘ
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0
Ｘ
1
Ｘ
0 1 0 0 1 1 0 1
0
1
Ｘ
Ｘ
1 ＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Table 7-1-4 (9)
Function (*: Setting at reset)
Dropout operation
(CLV)
(PLL)
＊ Enable
Enable
─
─
─
Stop
Stop
─
(DSL)
Enable
Stop
─
─
PLL gain control
＊ Normal mode
(Tracking OFF→Gain-up at ON)
Gain-up mode
PLL 2T or 5T detection selection
2T ＊ 5T
PLL pull-in mode selection
＊ 2T and 5T detecting output width
32 PCK
44 PCK
52 PCK
64 PCK
Note) The following formula is available for setting 2T and 5T detecting output widths.
2T or 5T detecting output width = D8×32＋D7×16＋D6×8＋D5×4＋4
Note) When using C2 quadruple correction, set the selection (2T or 5T) of 4Dh command PLL detection to 2T.
SDD00025AEM
54
MN662790RSC
(J) DIGTAL PLL control
Data (16 bits) Address (8 bits)
ＸＸＸＸＸＸＸＸＸＸＸＸＸ D2 D1 D0
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 0 0 0
⋮
ＸＸＸＸＸＸＸＸＸＸＸＸＸ 1 1 1
0 1 0 0 1 1 1 0
ＸＸＸＸＸＸＸＸＸＸＸＸ D3 ＸＸＸ
Table 7-1-4 (10)
Function (*: Setting at reset)
Increment/Decrement counter limit setting
＊ Limit value 14 (See Note.)
⋮
Limit value 0
ＸＸＸＸＸＸＸＸＸＸＸＸ 0 ＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸＸ 1 ＸＸＸ
Increment/Decrement counter clear mode
setting
＊ 1/2
Cleared to be 0.
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
PCK delay value setting
＊ PCK delay 0
PCK delay 1 clock
PCK delay 2 clock
PCK delay 3 clock
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
D5
0
0
1
1
D4
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸＸＸＸＸＸＸＸ D6 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸ
Resolution selection
＊ 1/8
1/16
ＸＸＸＸＸＸＸＸ D7 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸ
VCO oscillation frequency selection
＊ 67 MHz
138 MHz
ＸＸＸＸＸＸＸ D8 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸ
PCK generation PLL selection
＊ Analog PLL
Digital PLL
ＸＸＸＸＸＸ D9 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸ
VCO selection
＊ Pitch control and jitter-free
Digital PLL
ＸＸＸＸＸ D10 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 0 ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ 1 ＸＸＸＸＸＸＸＸＸＸ
Digital PLL operating frequency setting
＊ Normal
×2
Note) Limit value＝8×D2＋4×D1＋2×D0
When the VCO is set to digital PLL use (i.e., D9 of the above command is set to 1), pitch control or
jitter-free function is not available.
SDD00025AEM
55
MN662790RSC
(K) STAT pin control
Table 7-1-4 (11)
Data (16 bits) Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Unnecessary for this command (8 bits)
ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸＸ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
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Ｘ
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Ｘ
Ｘ
Ｘ
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Ｘ
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Ｘ
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Ｘ
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Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Address (8 bits)
Ｘ
Ｘ
Ｘ
Ｘ
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
ＸＸＸＸＸＸＸＸＸＸＸＸＸ D2 D1 Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
Ｘ
0
0
1
1
0
1
0
1
0 1 1 10 10 1
Ｘ
Ｘ
Ｘ
Ｘ
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ D0
0
0
0
0
0
0
0 D7 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
STAT pin output
： CRC
： STCNT
： CLVS
： TTSTOP (TTOFF)
JCLVS (TTON)
： SQOK
： FCLV
： SUBQ
： SYFLG
： ED A TA
STAT pin output setting
STAT pin output： FLAG6
： SENSE
： FLOCK (RFDET)
： TLOCK
Control of FLAG6 output from STAT
pin NOP
Reset of FLAG6
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ 0
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ 1
0
Function (*: Setting at reset)
0 1 1 1 0 1 1 0
SDD00025AEM
Disc rotation speed data output from
STAT pin
＊ Frame memory address reset OFF
Frame memory address reset ON
56
MN662790RSC
7-1 (5) Automatic adjustment
Following is a list of automatic adjustment.
Command
B7 B6 B5 B4 B3 B2 B1 B0
Description
Table 7-1-5
Time Traverse
required operation
Fo/Tr
offset
AOC
１１１１１００１
Averages and corrects the focus error values and 50 ms
FWD/
to
tracking error values as offset when the laser is
REV
140 ms enabled
turned on or off.
Fo
balance
ABC1
１１１１０１１１
Inputs the disturbance into the focus servo loop, Within
0.5 s
and make corrections so that the envelope ripple
for the 3T component of the RF signal in the
positive and negative parts of the FE signal
should be balanced. The output pin for
corrections is FBAL.
STOP
Tr
balance
ABC2
１１１１１０１１
The average tracking error value without the
tracking servo is used as a balancing value to
make corrections. The output pin for corrections
is TBAL.
Within
1s
STOP
Fo
rough
gain
AGC1
１１１１１１００
Focus search is performed at approx. 5.4 Hz or
1.3 Hz, and the disturbance input amount for the
fine AGC is determined by using focus error Scurve [P-P] value. The gain will be unchanged.
FWD/
Set
between
REV
190 ms enabled
and
780 ms
Tr
rough
gain
AGC2
１１１１１１０１
The [P-P] value of the tracking error in the
tracking servo off status determines the
disturbance input amount for the fine AGC. The
gain will be unchanged.
Set
between
135 ms
and
350 ms
STOP
Fo
fine
gain
FAGC
１１１１１１１０
Inputs the disturbance into the focus servo loop, Within
0.5 s
and adjusts the gain crossover to the frequency
set by the microcomputer command.
STOP
Tr
fine
gain
TAGC
１１１１１１１１
Inputs the disturbance into the tracking servo
loop, and adjusts the gain crossover to the
frequency set by the microcomputer command.
STOP
Within
0.5 s
Note) If focus balance adjustment is stopped due to automatic adjustment stoppage or focus failure, only the next
focus pull-in operation will be delayed.
In order to prevent this phenomenon from occurring, it is necessary to write "0" to D2 of the SD (19F2h) after
focus balance adjustment (i.e., after checking that the SENSE is set to low level).
For SD settings, refer to page 38.
SDD00025AEM
57
MN662790RSC
7-2. I/O timing
7-2 (1) Serial data output
When LRCK＝"L"ÅFR-ch
When LRCK＝"H"：L-ch
LRCK
BCLK
0
SRDATA
0
15
R-ch MSB
IPFLAG
(Audio-I)
L-ch
R-ch
IPFLAG
(Audio-II)
15
LS B
R-ch
L-ch
L-ch Upper 8 bits L-ch Lower 8 bits
t1
Figure 7-2-1 LRCK, BCLK, SRDATA and IPFLAG output timing
The value of t1 is 11.34 µs at normal-speed, 5.67 µs at 2x-speed and 11.34 µs × (100 + shift amount)÷100
when the pitch controller is used.
BCLK
BYTCK
SRDATA 13 14 15
0 1 2 3 4 5 6 7
R-ch LSB
IPFLAG
8 9 10 11 12 13 14 15
L-ch
MSB
L-ch Lower L-ch Upper
Figure 7-2-2 Output timing in CD-ROM mode SDD00025AEM
58
MN662790RSC
7-2 (2) Serial data output with de-emphasis function ON
t
R-ch
L- c h
LRCK
BCLK
SRDATA
D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8
Disabled data MSB
D7
D6
D5
D4
D3
D 2 D1 D0
D 15 D 14 D 13 D12 D 11 D10 D 9
MSB
LSB
D
i
s
a
bled data
(0.75t)
D8
D7 D6
D5
D4
D3
D2
D1 D0
LSB
(0.75t)
Disabled
data
Figure 7-2-3 LRCK, BCLK and SRDATA output timing with de-emphasis function ON
The SRDATA signal is output at 32 fs and the LSB data after each LRCK change includes 0.25t disabled data.
The phase relation with the IPFLAG is not guaranteed. 7-2 (3) Serial data input format
The input data for the DF + DAC section can be given from the outside by setting the IOSEL pin to the L
level. When this is done, give an LRCK input through the MSEL pin, BCLK input through the SSEL pin and
SRDATA input through the PSEL pin. At this time, the internal settings of the conventional MSEL, SSEL and
PSEL pins will be MSEL = L, SSEL = H and PSEL = L, respectively.
・The LRCK input frequency is fixed at 44.1 kHz. When the 2x-speed mode or jitter-free is used, a serial
data input is not available in other than the DF/DAC clock fixed mode, because the performance of a
D/A converter audio output is not assured. (See Table 7-1-38.)
・The BCLK input can be arbitrarily set between 16 and 32 clocks per half an LRCK cycle. However,
LRCK should be changed synchronously with the falling edge of BCLK.
・The SRDATA input is an MSB-first, 2's complement type input. It should be changed synchronously
with the falling edge of BCLK. Also, check that the contents of the SRDATA are L-ch data when
LRCK is at the H level.
As described above, the number of BCLK clocks can be 17 or more for each sampled data. If this is the
case, the contents of the SRDATA should be back-aligned with respect to an LRCK change point, and
LRCK must change before the rising edge of the next BCLK signal, after sampling the LSB of the
SRDATA at the rising edge of BCLK.
・D/A converter output muting, D/A converter output polarity switching, emphasis control and peak
detection DF output mode can be applied to a serial data input from an external source.
Bilingual switching only works on a serial data output, not on a serial data input.
SDD00025AEM
59
MN662790RSC
LRCK
Input
16 Clocks to 32 Clocks
BCLK
Input
SRDATA 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don't care
Input
R-ch MSB L-ch LSB
R-ch
Figure 7-2-4 LRCK input (MSEL), BCLK input (SSEL) and SRDATA input (PSEL) timing when IOSEL＝L SDD00025AEM
60
MN662790RSC
7-2 (4) Subcode interface
A. Read SUBQ data
You can read subcode data in two ways according to the setting of the SSEL pin. The timing is shown in
Figure 7-2-5.
When SSEL=L:
When SSEL pin is at L level, this LSI and the microcomputer serve as master and slave, respectively, to
read SUBQ data. BLKCK and CLDCK are output at fixed frequencies of 75 Hz and 7.35 kHz,
respectively. SUBQ output varies in synchronization with the falling edge of CLDCK output.
The microcomputer receives SUBQ output at the timing of the rising edge of CLDCK output. If the CRC
output is OK, it is processed as correct data. The result of CRC check can be read by CRC or STAT pin.
The content of SUBQ is output as follows: S0 and S1 signals are output in synchronization with BLKCK
output. Then, 80-bit subcode data are output. Then 8-bit peak detection data on the left or right channel is
output twice continuously. When SSEL=L, SUBQ output is inverse one.
When SSEL=H:
When SSEL pin is at H level, this LSI and the microcomputer serve as slave and master, respectively, to
read SUBQ data. The LSI receives an output signal from the microcomputer regardless of CLDCK output,
and changes SUBQ output. Then, by entering 96 clocks of SQCK, all SUBQ output can be read.
The microcomputer starts the interrupt operation at the rising edge of BLKCK output. First, it checks the
result of CRC of SUBQ output. If it is OK, SQCK is input to read SUBQ data.
The contents of SUBQ are synchronized with the rising edge of BLKCK. First, a CRC result is output,
and then, 80-bit subcode data are output every falling edge of SQCK. Then 8-bit peak detection data on the
left or right channel is output twice continuously. At SSEL = H, SUBQ output is positive one.
By inputting the microcomputer command 000847h as shown in Table 7-1-4 (6), subcode data in the unit
of byte is output beginning with the LSB at every falling edge of SQCK.
Read subcode data from STAT with command
By inputting the microcomputer command 78H as shown in Table 7-1-4 (11), subcode data can be read
from STAT pin in synchronization with the falling edge of MCLK on condition that the SSEL pin is at H
level. This mode is available only immediately after issuance of the microcomputer command 78h. This
mode is cancelled when other commands are issued.
SDD00025AEM
61
MN662790RSC
When SSEL=L (SUBQ output is inverse one):
BLKCK
S0
S1
Q1
Q2
Q3
Q4
∼
∼
SUBQ ∼ ∼
∼∼
∼ ∼
∼∼
∼ ∼
∼∼
∼ ∼
∼∼
∼ ∼
∼
∼
CLDCK
Q79
Q80
L15
R8
CRC H: CRC=OK L: CRC=NG
STAT
(=CRC)
L: CRC=NG
H: CRC=OK DEMPH
S0
S1
Q1
※ H and L for all data are inverted.
When SSEL=H:
BLKCK
∼
∼
CLDCK
SUBQ CRC
Q 1 Q2 Q 3 Q4
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼
∼ ∼
∼ ∼
∼ ∼
∼
SQCK
Q 79 Q 80 L 15
R10 R9 R8
CRC
H: CRC=OK L: CRC=NG
STAT
(=CRC)
H: CRC=OK DEMPH
SQOK
CRC
L: CRC=NG
8.7 ms
Figure 7-2-5 BLKCK, CLDCK, SQCK, SUBQ, CRC and DEMPH timing
SDD00025AEM
62
MN662790RSC
When SSEL＝H: (When microcomputer command 000847h is input)
BLKCK
∼
∼
CLDCK
CRC
Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q16 Q15
CRC
H: CRC=OK L: CRC=NG
STAT
(=CRC)
H: CRC=OK L: CRC=NG
DEMPH
SQOK
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼
∼
∼
SUBQ
∼ ∼
∼
∼ ∼
∼
∼
∼
SQCK
Q73 L8
R15
CRC
8.7 ms
B. Read subcode data
By inputting a clock from SBCK pin, subcode data, P to W, can be read from SUBC pin. The timing is
shown in Figure 7-2-5.
Since subcode data varies every falling edge of CLDCK, input 8 clocks of SBCK every falling edge of
CLDCK, and switch the content of SUBC output to P to W.
Then you should receive SUBC output which varies in synchronization with the falling edge of SBCK at the
timing of the rising edge of SBCK. You can read all subcode data by repeating the operation above for each
CLDCK.
By inputting SBCK, the content of FLAG output will change. So you cannot measure the error rate when
reading subcode. You must consider it in system designing.
Use of SQOK Signal
Usually the BLKCK signal is used as a trigger to start reading SUBQ data.
The data is output from the SUBQ pin in synchronization with the SQCK signal. The necessary bits of data
(i.e., usually 80 bits) need to be read before the next BLKCK signal output is turned on.
The SQOK signal is set to H level for approximately 8.7 ms in the first half of the BLKCK-synchronous
period. There is no need to finish reading the data while the SQOK is at H level.
The SQOK signal is used for reading SUBQ data without using BLKCK interruption. The SQCK signal is
monitored by software scanning and the reading of SUBQ data is started on detection of the H-level signal.
At that time, the data must be read for a maximum approx. 2 ms because the period until the next BLKCK
signal output is turned on is approx. 4.6 ms.
SDD00025AEM
63
MN662790RSC
Typ. Typ.
136 µs 1.5 µs
BLKCK
CLDCK
SBCK
SUBC S0 S1
P1 to W1 P2 to W2 P3 to W3 P4 to W4 P5 to W5 P6 to W6 P7 to W7
CLDCK
Min. Min.
400 ns
400 ns
SBCK
Min. 1 µs
SUBC P
Max.
300 ns
Q
R
S
T
U
V
W
Max.
300 ns
Figure 7-2-6 CLDCK, SUBC and SBCK timing
SDD00025AEM
64
MN662790RSC
7-2 (5) EDATA error rate monitor function
The error rate can be monitored through the STAT pin. The error rate is the number of frames (FLAG0=H),
where C1 errors are detected, out of 2048 frames of data. The rate monitored is within an output
range between 0 and 255.
By changing the command, the number of interpolation flag (IPFLAG) signals out of 2048 frames
of data is monitored within an output range between 0 and 255.
Flag definite delay
tD=Max. 1.0 µs
Monitoring method
MCLK
MDATA
46h〔b9Ål
7Ah
MLD
STAT
Flag
D7 D6 D5 D4 D3 D2 D1 D0
The EDATA output command 7Ah is input after setting the EDATA change command in 46h(b9).
The flag must be checked after the point of the flag definite delay.
If the flag is set to L level, there is no need to read the error rate data because the rate is the same as the
error rate data previously read.
Input the MCLK signal and read the error rate if the flag is set to H level.
SDD00025AEM
65
MN662790RSC
7-2 (6) CD-TEXT interface
CD-TEXT mode 1
BLKCK
GIO3/RSEL
(DQSY)
16 or 18 bytes
tD= 23.0 ms
SBCK
SUBC
When CRC error is occurred
TEXT CRC or the top position flag
CD-TEXT mode 2
BLKCK
GIO3/RSEL
(DQSY)
SQCK
SUBQ
Fixed to H
TEXT CRC
Fixed to H
TEXT data
TEXT CRC
T EX T data
TEXT CRC
TEXT data
TEXT CRC
TEXT data
MCLK
STAT
SUBQ
SUBQ
SUBQ CRC
SUBQ CRC
SDD00025AEM
66
MLD
SDD00025AEM
78
Indefinite
B
Indefinite
C
Indefinite
D
D6
D5
D4
D3
D2
D1
D0
CD-TEXT data CRC (or 1's flag in position B above)
SUBQ data CRC
Start pack flag (set to 1 in position A above only)
CLVS or RESY
TLOCK
FLOCK
SENSE
FLAG6
CD-TEXT (18 or 16 bytes) command selection
22 or 20 bytes
Indefinite
Note) In data D , only single-byte
header of SUBQ data is valid.
SUBQ (3 bytes)
This command starts data reading with STAT. This command need not be set again unless any other command is issued.
Status (1 byte)
D7
tD≧3.0 µs
1.63 ms (×2)
Fix the SQCK pin to high level when the CD-TEXT mode 3 is used.
Data A
(Contents of Data)
MDATA
STAT
MCLK
BLKCK
(DQSY)
Original
BLKCK
CD-TEXT M Mode 3
MN662790RSC
67
SDD00025AEM
STAT
MLD
MDATA
MCLK
BLKCK
78h
78h
Command
78h
22 or 20 bytes in total
It is impossible to determine whether this is for command issuance or data reading purpose.
Command
・Case 3: Command issuance while data reading
STAT
MLD
MDATA
MCLK
BLKCK
Command
22 or 20 bytes in total
Status byte + TEXT data + SUBQ
data
End of reading
22 or 20 bytes
・Case 2: Command issuance before data reading
STAT
MLD
MDATA
MCLK
BLKCK
・Case 1: Command issuance at the end of data reading
(Mode 3 Command Issuance)
The command needs to be set again if commands other than 78h
are issued because such commands clear the TEXT and SUBQ
data settings of STAT pin.
MN662790RSC
68
MN662790RSC
CD-TEXT Mode 4
Internal BLKCK
BLKCK
SQCK
SU B Q
SUBQ
SU B Q
CRC
TE X T C R C TE X T data
TE X T C R C
TEX T
data
TEXT CRC
TEXT
data
TEXT CRC
TEX T
data
SU B Q C R C
MCLK
MDATA
Mode 4 setting
Mode 4 released
MLD
Mode 4 must be released before the rising edge of BLKCK.
SDD00025AEM
69
MN662790RSC
7-2 (7) Digital PLL setting
For an improvement in playability of this LSI, a digital PLL circuit is built in so that the LSI will be in
stable operation without being influenced by digital noise. The lock range of this PLL circuit is not as wide
as an analog PLL circuit. Therefore, a system controller is required with an analog PLL circuit employed so
that the analog PLL circuit will be used in access operation and switched over to the digital PLL circuit at
the end of the access operation.
The digital PLL is available in normal- and 2x-speed playback modes.
The following mode combinations can be set.
Data
Address
D10
4E
2x-speed playback
Normal-speed playback
Function
Digital PLL operating
frequency
0
×1
1
×2
1
×2
1
×2
D7
Resolution
0
1/8
1
1/16
0
1/8
1
1/16
D6
VCO oscillation
frequency
0
67 MHz
0
67 MHz
0
67 MHz
1
138 MHz
Use the SYFLG (i.e., the CLV synchronous establishment detecting flag) in the following sequence to switch
over the analog PLL circuit to digital PLL circuit.
Kick
Kick
ARF
Q read
Q read
Access end judgement
STAT (SYFLG)
↑ SYFLG at H level
detected
IPFLAG
・・・・・・
Digital PLL set command issued
Note 1) Change the digital PLL circuit over to the analog PLL circuit at the start point of the access operation.
Change the digital PLL circuit over to the analog PLL circuit when the reading of the Q-code fails
while the LSI is in PLAY operation. Use a sequence like the one shown above to change the digital
PLL circuit over to the analog PLL circuit.
Note 2) The SYFLG can be used in playback mode after a short track jump, such as a single-track jump, or a
kick. In that case, make sure that the Q-code is read properly in a sequence like the one shown above
after the track jump or kick is performed.
SDD00025AEM
70
MN662790RSC
7-2 (8) Video CD setting
It is desirable to increase the probability of correction rather than decrease the probability of error correction
for video CD in playback mode. Therefore, set the C2 correction to quadruple correction.
Set the C2 correction to triple correction when playing back an audio CD.
Data
Address
D6
46
Function
Selection of C2
correction
Video CD
1
Audio CD
Quadruple correction
0
D2
1
0
D1
1
0
Triple correction
7-2 (9) Digital audio interface Bit V control
D7 and D5 of microcomputer command address 42h are used for the Bit V control of the digital audio interface.
Data (16 bits) Address (8 bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ＸＸＸＸＸＸＸＸＸＸ０ＸＸＸＸＸ
ＸＸＸＸＸＸＸＸＸＸ１ＸＸＸＸＸ
Function (*: Setting at reset)
TX Bit V change (in interpolation mode)
＊ Bit V ON
Bit V OFF
42h
TX Bit V change (in ATT mode)
＊ Bit V ON
Bit V OFF
ＸＸＸＸＸＸＸＸ０ＸＸＸＸＸＸＸ
ＸＸＸＸＸＸＸＸ１ＸＸＸＸＸＸＸ
Note 1) The LSI in ATT mode means that the LSI is in digital attenuation, soft attenuation, or soft muting mode.
The Bit V is, however, always off if the LSI is under −12 dB control for serial data attenuation with
D4 of 46h set to on.
If the Bit V is set to off in ATT mode for a TX Bit V change, the Bit V is on when the digital or soft
attenuation level is set to 0 (i.e., −∞ dB).
Note 2) The Bit V is always on in TX mute control or mute control through the DMUTE pin.
7-2 (10) Audio output MUTE
The microcomuputer command makes it possible to mute SRDATA output, DF/DAC output, or TX output
independently.
All outputs can be muted through the DMUTE pin.
SRDATA
DMUTE
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address
pin
output
L
H
DF/DAC
output
TX output
ＸＸＸＸＸ０ＸＸＸＸＸＸＸＸＸＸ
ＸＸＸＸＸ１ＸＸＸＸＸＸＸＸＸＸ
46
MUTE OFF MUTE OFF MUTE OFF
MUTE ON MUTE OFF MUTE OFF
ＸＸＸＸＸＸＸＸＸ０Ｘ０ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ０Ｘ１ＸＸＸＸ
ＸＸＸＸＸＸＸＸＸ１Ｘ０ＸＸＸＸ
42
MUTE OFF MUTE OFF MUTE OFF
MUTE OFF MUTE OFF MUTE ON
MUTE OFF MUTE ON MUTE OFF
ＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸＸ
ＸＸ MUTE ON
SDD00025AEM
MUTE ON MUTE ON
71
MN662790RSC
7-2 (11) Error correction
This LSI performs double correction for the C1 decoder and triple correction/quadruple correction for the C2
decoder.
・ For the C2 decoder, when the data is judged impossible to correct or not highly reliable (having a high
probability of erroneous correction or overlooking), it is interpolated by the interpolation circuit.
(In the case of audio mode I)
・ For the C1 and C2 decoders, correction results are output from the FLAG pin as FLAG0 to FLAG5.
When the C1 decoder detects an error for FLAG0, "H" is output for approx. 4.6 µs, starting from the
rising edge of FCLK.
FLAG1 to FLAG6 are output from FLAG pin in synchronization with the falling edge of SBCK input from
the outside.
<Meanings of FLAGs>
FLAG5
FLAG4
FLAG3
FLAG2
FLAG1
FLAG0
×
×
×
０
０
０
C1 no error
×
×
×
０
１
１
C1 single error correction
×
×
×
１
０
１
C1 double error correction
×
×
×
１
１
１
C1 correction impossible
０
０
０
×
×
×
C2 no error
０
０
１
×
×
×
C2 single error correction
０
１
０
×
×
×
C2 double error correction
０
１
１
×
×
×
C2 double correction
impossible
１
０
０
×
×
×
C2 triple error correction
１
０
１
×
×
×
C2 triple correction
impossible
１
1
０
×
×
×
C2 quadruple error
correction
１
1
1
×
×
×
C2 quadruple correction
impossible
SDD00025AEM
72
MN662790RSC
Flag Output Timings (At Normal-Speed)
136 µs (7.35 kHz)
FCLK
Min.
400 ns
Min.
400 ns
354 Min.
0 ns
ns
SBCK
Min. 1 µs
FLAG1
FLAG0
FLAG2
FLAG3 FLAG4
FLAG5
FLAG6
FLAG0
FLAG
4.6 µs
Max.
300 ns
4.6 µs
Max.
300 ns
※ If the falling edge of clock is input to SBCK while FLAG0 is being output, an output from FLAG pin
will be switched from FLAG0 to FLAG1.
SDD00025AEM
73
MN662790RSC
PRODUCT STANDARDS
A. ABSOLUTE MAXIMUM RATINGS
Parameter
Ta = 25 ℃
Symbol
Rating
Unit
A1
Supply voltage
VDD
AVDD
−0.3 to +4.6
V
A2
5-V reference voltage
VCC5V
−0.3 to +5.7
V
A3
Input voltage
VI
A4
Output voltage
VO
VSS−0.3 to VDD+0.3
AVSS−0.3 to AVDD+0.3
VSS−0.3 to VDD+0.3
AVSS−0.3 to AVDD+0.3
V
V
A5
Power dissipation
PD
580
mW
A6
Operating ambient
temperature
Topr
−30 to +85
℃
A7
Storage temperature
Tstg
−55 to +125
℃
Note
VSS=0 V
AVSS=0 V
VSS=0 V
AVSS=0 V
VSS=0 V
AVSS=0 V
VSS=0 V
AVSS=0 V
VSS=0 V
AVSS=0 V
Ta = 85 ℃
(Note 7)
Note 1) The absolute maximum ratings are the limit values beyond which the device may be broken.
They do not assure operations.
Note 2) Each of VSS, DVSS1, AVSS1 and AVSS2 pins should be directly connected to the ground and used at the
same voltage.
Note 3) Each of VDD, DVDD1, AVDD1 and AVDD2 pins should be directly connected to the specified power supply
and used at the same voltage.
Note 4) VDD, DVDD1, AVDD1 and AVDD2 should be powered up at the same time.
Note 5) Connect a bypass capacitor (0.1 µF or more) between VDD and VSS pins, between DVDD1 and DVSS1 pins,
between AVDD1 and AVSS1 pins, between AVDD2 and AVSS2 pins and between VREF and VSS pins.
Note 6) The operation of the audio D/A converter is guaranteed only for operation in normal-speed playback
mode.
Note 7) Condition: This LSI shall be mounted on a standard glass epoxy board (75 mm×75 mm×0.8 mm).
SDD00025AEM
74
MN662790RSC
Ta＝−30 ℃ to ＋85 ℃,VSS＝0 V
AVSS＝0 V
B. OPERATING CONDITIONS
Limits
Parameter
B4
Digital system supply
voltage
Analog system supply
voltage
Digital system supply
voltage
Analog system supply
voltage
B5
5-V reference voltage
B1
B2
B3
Note 9)
Symbol
Conditions
Unit
min
typ
max
3.0
3.3
3.6
V
3.0
3.3
3.6
V
AVDD
Normal-and 2x-speed playback
modes
Normal-and 2x-speed playback
modes
VDD1
4x-speed playback mode
3.2
3.3
3.6
V
AVDD1
4x-speed playback mode
3.2
3.3
3.6
V
4.75
5.0
5.25
V
VDD
VCC5V
It is recommended to basically use AVDD at the same voltage as DVDD.
Ta＝−30 ℃ to ＋85 ℃,VSS＝0 V
VDD＝3.3 V, AVSS＝0 V
Self-excited Oscillation 1 (Note 10)
B6
Crystal frequency
fxtal
B7
External capacitance 1
C1
B8
External capacitance 2
C2
CSEL＝L
16.9344
MHz
5
pF
5
pF
16.9344
MHz
External Clock Input 1 (Note 11), (Note 12)
B9
Clock input frequency
fX1
B10
Clock input amplitude
VX1
B11
High-level pulse width
tX1H
B12
Low-level pulse width
tX1L
B13
External capacitance 3
C3
V[P-P]
2.0
CSEL＝L
C3＝1000 pF
Switching level VX1/2
26
29.5
ns
26
29.5
ns
pF
1000
External Clock Input 2 (Note 11), (Note 12)
B14
Clock input frequency
fX1
B15
Clock input amplitude
VX1
B16
High-level pulse width
tX1H
B17
Low-level pulse width
tX1L
B18
External capacitance 3
C3
33.8688
V[P-P]
2.0
CSEL＝H
C3＝1000 pF
Switching level VX1/2
13
14.8
ns
13
14.8
ns
1000
SDD00025AEM
MHz
pF
75
MN662790RSC
Ta＝−30 ℃ to ＋85 ℃,VSS＝0 V
VDD＝3.3 V, AVSS＝0 V
Note 10)
Oscillation circuit
C2
X2
Xtal
MN662790RSC
X1
C1
The appropriate capacitors' values differ according to the oscillator used. Use the values
specified by the oscillator manufacturer.
Note 11)
External clock input 1
X2
OPEN
MN662790RSC
C3
X1
Note 12)
External clock
External clock
1 / fX1
VX1/2
VX1
tX1H
tX1L
SDD00025AEM
76
MN662790RSC
VCC5V＝5.0 V
VSS＝0 V
AVDD＝VDD, AVSS＝0 V
Ta＝−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz
C. Electrical Characteristics
(1) DC Characteristics
Limits
Parameter
Symbol
Conditions
Unit
min
C1
Supply current
IDD
C2
Total
power consumption
Ptot
C3
Supply current
I DD
C4
Total
power consumption
Ptot
C5
Supply current
IDD
C6
Total
power consumption
Ptot
VDD=3.3 V
No external load during normalspeed playback mode
Ta=25 ℃ fX1=16.9344 MHz
CSEL=L
VDD=3.3 V
No external load during 2xspeed playback mode
Ta=25 ℃ fX1=16.9344 MHz
CSEL=L
When DF/DAC clock fixed
mode is set.
VDD=3.3 V
No external load during 4xspeed playback mode
Ta=25 ℃ fX1=16.9344 MHz
CSEL=L
When DF/DAC clock fixed
mode is set.
SDD00025AEM
t yp
max
45
1 00
mA
150
330
mW
50
103
mA
170
340
mW
60
105
mA
200
345
mW
77
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Unit
Conditions
min
Input Pins (1) ＊1
Input voltage
VIH1
C7 high level
Input voltage
C8 low level
VIL1
ILK1
C9 Input leakage
current
Input Pins (2) ＊2
Input voltage
VIH2
C10 high level
VIL2
C11 Input voltage
low level
C12 Input leakage
I LK2
current
Input Pin (3) SBCK
Input voltage
VIH3
C13 high level
VIL3
C14 Input voltage
low level
C15 Input leakage
I LK3
current
＊1
＊2
max
typ
0.7VDD
VDD
V
0
0.3VDD
V
±1
µA
2.0
VCC5V
V
0
0.8
V
±1
µA
2.0
5.25
V
0
0.8
V
±1
µA
VIN＝0 to VDD
VIN＝0 to VCC5V
VIN＝0 V to 5.25 V
TEST3, OFT, RFDET, BDO, TEST, IOSEL
MCLK, MDATA, MLD, SQCK/GIO0, DMUTE, RST, RSEL/GIO3, CSEL,
PSEL, SSEL, MSEL
SDD00025AEM
78
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
typ
max
Output Pins (1) ＊3
Output voltage
high level
Output voltage
C17
low level
C16
VOH1
IOH1＝−2.0 mA
VOL1
IOL1＝2.0 mA
V
VDD−0.6
0.4
V
Output Pins (2) ＊4
Output voltage
high level
Output voltage
C19
low level
VOH2
IOH2＝−2.0 mA
VOL2
IOL2＝2.0 mA
0.4
V
C20 Output leakage
current (ECM)
ILK2
Hi-Z
Vo＝0 V to 3.3 V
±1
µA
C18
V
VDD−0.6
＊3
BCLK, LRCK, SRDATA, SENSE, FLOCK, SUBQ, STAT, SMCK, PC, LDON, WVEL,
EFM, PCK, SUBC, BYTCK/TRVSTP, GIO1/CLDCK, GIO2/FCLK, IPFLAG, CLVS,
CRC, DEMPH, TX, BLKCK, FLAG, RESY/FLAG6
＊4
ECM
SDD00025AEM
79
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Parameter
Symbol
Analog System Input Pin (1)
C21 Input current
IREF
Analog System Input Pin (2)
C22 Input signal amplitude
VARF
C23 Input leakage current
ILKA
Analog System Input Pin (3)
C24 Input leakage current
RDRF
DRF pins
Unit
min
typ
max
11
20
28
0.5
1.0
IREF
When pulled up by a 120-kΩ resistor
µA
ARF
Input level of the EFM signal in the
application circuit of the DSL circuit
block
V[P-P]
±1
µA
±1
µA
10
kΩ
DRF
ILKA
Internal resistance
C25 between ARF and
Limits
Conditions
2x-speed playback mode
ARF＝1.65 V
Analog System Output Pin (1) DSLF (IREF pin is pulled up to AVDD by a 120-kΩ resistor) (Note 13)
C26 Output current (N)
IDSH
BDO＝L, Tracking ON-state
DSLF＝1.65 V, ARF＝3.3 V
＋45
＋59
＋75
µA
C27 Output current (P)
IDSL
BDO＝L, Tracking ON-s tate
DSLF＝1.65 V, ARF＝0 V
−45
−59
−75
µA
−7.0
−1.0
＋5.0
µA
Output unbalance
C28 current
IDSH+IDSL DSLF＝1.65 V
Normal current output mode
Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD by a 120-kΩ resistor)
Phase comparison
C29 output current (N)
IPFH
BDO＝L, Tracking OFF-state
52
67
89
µA
Phase comparison
IPFL
BDO＝L, Tracking OFF-state
−52
−67
−89
µA
IPFH+IPFL
BDO＝L, Tracking OFF-state
Normal current output mode
−8.55
−2.55
＋4.45
µA
±1
µA
4.92
MHz
C30 output current (P)
C31
Phase comparison
output unbalance
current
C32 Leakage current
ILKP1
Hi-Z
CO oscillation
C33 V
frequency 1
fVCO1
Normal-speed playback mode
(With IREF pin as shown in the
recommended circuit diagram)
SDD00025AEM
3.71
80
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Parameter
Symbol
Conditions
Limits
min
typ
max
Unit
Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD by a 120-kΩ resistor)
VCO oscillation
fVCO2
2x-speed playback mode
(With IREF pin as shown in the
recommended circuit diagram)
7.42
9.84
MHz
VCO oscillation
fVCO3
4x-speed playback mode
(With IREF pin as shown in the
recommended circuit diagram)
14.84
25.93
MHz
C34 frequency 2
C35 frequency 3
Analog System Output Pin (3) VCOF (IREF pin is pulled up to AVDD by a 120-kΩ resistor)
Phase comparison
C36 output current (N)
Phase comparison
C37 output current (P)
IVFH
40
54
71
µA
IVFL
−40
−54
−71
µA
C38 Input leakage current
ILKV
Hi-Z
±1
µA
fVCO4
With IREF pin as shown in the recommended
circuit diagram (4x-speed mode)
With IREF pin as shown in the recommended
circuit diagram (2x-speed mode)
With IREF pin as shown in the recommended
circuit diagram (Normal-speed mode)
Jitter-free VCO
C39 oscillation frequency
19.6438 33.8688 50.8032
9.8219
16.9344 25.4016
4.9109
8.4672 12.7008
MHz
Analog System Output Pin (4) PLLF2 (IREF pin is pulled up to AVDD by a 120-kΩ resistor)
C40 Leakage current
C41
Internal resistance between
PLLF and PLLF2 pins
ILKP2
RPLLF
Analog System Input Pin (4)
C42 Input signal amplitude
VTRC
C43 Input leakage current
ILKT
PLLF＝1.65 V
±1
µA
250
Ω
TRCRS
TRCRS signal input level
(with VREF level as a center)
V[P-P]
2
±1
µA
Analog System Output Pin (5) VCOF2 (IREF pin is pulled up to AVDD by a 120-kΩ resistor)
Phase comparison
IVFH2
40
54
71
µA
C45 output current (P)
IVFL2
−40
−54
−71
µA
C46 Input leakage current
ILKV2
Hi-Z
±1
µA
fVCO5
With IREF pin as shown in the
recommended circuit diagram
C44 output current (N)
Phase comparison
VCO oscillation
C47 frequency
SDD00025AEM
33.8688
MHz
81
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
VDD
68 kΩ
IREF
0.022 µF
VARF
1.0 V[P-P]
(typ.)
0.001 µF
ARF
27 kΩ
DRF
100 kΩ
DSLF
100 kΩ
0.068 µF
PLLF
330 Ω
1200 pF
PLLF2
0.33 µF
220 kΩ
PCK / DSLB
VCOF*
2.7 kΩ
0.33 µF
VCOF2
2.7 kΩ
0.33 µF
Recommended Circuit Diagram to DSL / PLL and Jitter-free VCOF Blocks
* When 4x-speed playback mode with a 16.9344-MHz clock or a jitter-free function is not used, connect the
VCOF pin to VDD or ground.
* It is necessary to change a value of the resistor connected to IREF pin to adjust the oscillation frequency in 4xspeed playback mode.
Note 13)
Insert a 100-kΩ resistor between the DSLF and PCK / DSLB pins or between the DSLF and
DSLBDA pins to use the DSL balance correction function.
Note 14)
This recommended circuit is typical, so it is necessary to choose external components' values with due
regard to playability.
SDD00025AEM
82
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Unit
Conditions
min
Analog System Input Pins (5)
Input voltage
C48 high level
Input voltage
C49
low level
Input voltage
Load
C51 characteristic
AVDD
VIL4
V O4
V
V
0
VREF
V I5
Analog System Output Pins (6)
max
TE, FE, RFENV
V I H4
Analog System Input Pin (6)
C50
typ
V
0.5AVDD
TVD, TRD, FOD, TBAL, FBAL, ECS, DSLBDA
Load:±300 µA
Difference from no load state
at 20 %, 50 % and 80 % of fullscale.
SDD00025AEM
±4.0
LSB
83
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Unit
Conditions
min
t yp
max
A/D Converter Desired Values (for Servo)
C52
C53
C54
Resolution
Integral
nonlinearity
Differential
nonlinearity
8
bit
±2
LSB
±3
LSB
RES
8
bit
INL
±2
LSB
DNL
±0.82
LSB
DOFF1 Value to 1.65-V output
±10
LSB
No load
Value at 25 % of the full-scale
DOFF2
No load
DOFF3 Value at 75 % of the full-scale
No load
±10
LSB
±10
LSB
RES
INL
DNL
A/D output=80 to 7F
(2's complement )
D/A Converter Desired Values (for Servo)
C55 Resolution
C57
Integral
nonlinearity
Differential
nonlinearity
C58
Offset
C56
Digital input 0 (2's complement)
C59
Offset
C60
Offset
SDD00025AEM
84
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
D/A Converter Desired Values Analog Characteristics
t yp
max
(Note 15), (Note 18)
C61 Signal to noise ratio
S/N
EIAJ
90
97
dB
C62 Dynamic range
D.R.
EIAJ
80
88
dB
THD+N
EIAJ
C63
Total
harmonic distortion
C64
Crosstalk
C65 Output level 1
0.007
EIAJ
f=1 kHz Full-scale output
(Note 16)
C66
Output level
difference
Difference of OUTL and
OUTR pins at output level 1.
20 log (VR/VL)
C67
Output level 2
f=1 kHz Full-scale output
(Note 17)
70
80
1.12
1.32
−0.99
0.68
0.79
0.013
%
dB
1.55
Vrms
＋0.99
dB
0.93
Vrms
Note 15)
The analog characteristics indicate the values measured by inserting a 15-Ω resistor
between the AVDD1 pin and power supply. The typical values are only reference
values. They are not guaranteed.
Note 16)
The output level 1 shows the measured value at the output pins of the application
circuit.
Note 17)
The output level 2 shows a value at the output pin of this LSI and is calculated by
taking the measured value of output level 1, dividing it by the external circuit gain of
the application circuit.
Note 18)
Use the D/A converter only in the normal-speed playback mode. Operation of the
D/A converter cannot be guaranteed when it is used in the 2x-and 4x-speed modes.
SDD00025AEM
85
DVDD1 AVDD2
SDD00025AEM
VSS AVSS2
AVSS2
DVSS1 DVSS
MN662790RSC
VDD OUTR
AVSS1
OUTL
AVDD1
15 Ω
+
−
0.0018 µF
1 kΩ
1 µF
0.0018 µF
AVSS1
47 µF 100 µF
−
+
1 kΩ
AVDD1
−
＋
−
＋
100 pF
2.2 kΩ
1.5 kΩ
47 kΩ
100 pF
2.2 kΩ
1.5 kΩ
22 µF 47 kΩ 47 kΩ 100 pF
47 kΩ
22 µF 47 kΩ 47 kΩ 100 pF
−
＋
AVDD2
−
＋
DVDD
0.001 µF
22 µF 560 Ω
0.001 µF
22 µF 560 Ω
47 kΩ
47 kΩ
MN662790RSC
[D/A Converter Application Circuit]
86
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Unit
Conditions
min
typ
max
C68 Rise time
tRA
250
ns
C69 Fall time
tFA
250
ns
C70 Rise time
tRB
100
ns
C71 Fall time
tFB
100
ns
C72 Rise time
tRC
100
ns
C73 Fall time
tFC
100
ns
MLD
There should be no noise
greater than 20 mV[P-P] in
signal lines and power supply.
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
tRA
SBCK
tFA
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
tRB
MCLK
tFB
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
tRC
tFC
SDD00025AEM
87
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Unit
Conditions
min
t yp
max
Microcomputer Instruction Input Timing
C74 Clock frequency
fMCLK
1
MHz
C75 Clock pulse width
tCH,
tCL
300
ns
C76 Data setup time
tDSU
300
ns
C77 Data hold time
tDH
300
ns
C78 Delay time
t LD D
600
ns
C79 Latch pulse width
tLDW
0.6
100
µs
1/f MCLK
MCLK
tCH
tCL
MDATA
tDSU
tDH
MLD
tLDD
SDD00025AEM
tLDW
88
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
t yp
max
Subcode Interface (1)
C80 Clock width
High-level
pulse width
Low-level
C82
pulse width
C81
tCK
1
µs
tCKH
400
ns
tCKL
400
ns
C83 Delay time
tSBD
300
ns
C84 Setup delay time
tSD
300
ns
tCK
tCKL
SBCK
tCKH
SUBC
tSD
tSBD
CLDCK
SDD00025AEM
89
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
t yp
max
Subcode Interface (2)
C85 Clock width
tSQ
500
ns
High-level
pulse width
Low-level
C87
pulse width
tSQH
200
ns
tSQL
200
ns
C88 Delay time
tSQD
C86
150
ns
tSQ
tSQL
tSQH
SQCK
SUBQ
tSQD
SDD00025AEM
90
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
High-level
C90 pulse width
Low-level
C91 pulse width
max
＊5
D/A Output Interface 1
C89 Clock width
t yp
tBCLK
354
ns
tBCLKH
177
ns
177
ns
tBCLKL
Normal-speed playback mode
C92 Setup time
tST
70
ns
C93 Hold time
tHD
70
ns
＊5
D/A Output Interface 2
C94 Clock width
High-level
C95 pulse width
Low-level
C96 pulse width
tBCLK
177
ns
tBCLKH
88.5
ns
tBCLKL 2x-speed playback mode
88.5
ns
C97 Setup time
tST
30
ns
C98 Hold time
t HD
30
ns
＊5
D/A Output Interface 3
C99 Clock width
High-level
pulse width
Low-level
C101
pulse width
C100
tBCLK
88.5
ns
tBCLKH
44.2
ns
tBCLKL 4x-speed playback mode
44.2
ns
C102 Setup time
tST
15
ns
C103 Hold time
t HD
15
ns
SDD00025AEM
91
MN662790RSC
＊5
D/A Output Interface
tBCLK
tBCLKL
tBCLKH
tST
tHD
BCLK
SRDATA
LRCK
SDD00025AEM
92
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
typ
max
D/A Converter Input Timing
C104 BCLK frequency
fBCLK
C105 BCLK pulse width
tCH,
tCL
70
ns
C106 Data setup time
tDSU
70
ns
C107 Data hold time
t DH
70
ns
C108 LRCK frequency
fLRCK
C109 BCLK-LRCK timing
4
44.1
tBL,
tLB
70
MHz
kHz
ns
1/f BCLK
BCLKIN
tCH
tCL
SRDATAIN
tDSU
tDH
LRCKIN
tBL
tLB
tBL
tLB
1/f LRCK
SDD00025AEM
93
MN662790RSC
VCC5V＝5.0 V
VDD＝3.3 V, VSS＝0 V
AVDD＝3.3 V, AVSS＝0 V
Ta=−30 ℃ to ＋85 ℃
fX1＝16.9344 MHz or 33.8688 MHz
Limits
Parameter
Symbol
Conditions
Unit
min
t yp
max
Reset Timing (Note 19)
C110 RST pulse width
tNRSTL
tRD
C111 Rise time
µs
200
100
ns
Power Supply Ripple Noise (Note 20)
C112 Ripple amplitude
VRIP
15
mV[P-P]
C113 Ripple noise
amplitude
V NZ
50
mV[P-P]
Note 19)
When the power is turned on, reset with the RST pulse which is equal to or
exceeds the above pulse width only after the clock oscillation is stabilized within
±10 % of error of the specified oscillation frequency.
tNRSTL
RST
0.8 VDD
0.2 VDD
0.2 VDD
tRD
Note 20)
The standard ripple noise values of the LSI are guaranteed on condition that the
values apply to typical 50-Hz to 100-Hz ripples with 500-kHz typical noise and
that both the ripples and noise are in sine waveform as shown below.
The values, however, vary under the influence of other parts located on the PCB.
Therefore, be sure to check the actual values before applying the LSI to practical
applications.
Noise frequency 500 kHz
VRIP
VNZ
Ripple frequency 50 Hz to 100 Hz
SDD00025AEM
94
MN662790RSC
Package Dimensions (Unit: mm)
• LQFP080-P-1414A (lead-free package)
16.00±0.20
14.00±0.20
60
41
40
80
21
0.30±0.05
0.13 M
0.10
16.00±0.20
(1.00)
0.15±0.05
0.65
0.10±0.10
(0.825)
20
1.40±0.10
1
1.70 max.
14.00±0.20
(0.825)
61
0° to 10°
0.50±0.20
Seating plane
SDD00025AEM
95
Request for your special attention and precautions in using the technical information
and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government
if any of the products or technologies described in this material and controlled under the "Foreign
Exchange and Foreign Trade Law" is to be exported or taken out of Japan.
(2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license.
(3) We are not liable for the infringement of rights owned by a third party arising out of the use of the
product or technologies as described in this material.
(4) The products described in this material are intended to be used for standard applications or general
electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
• Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment,
combustion equipment, life support systems and safety devices) in which exceptional quality and
reliability are required, or if the failure or malfunction of the products may directly jeopardize life or
harm the human body.
• Any applications other than the standard applications intended.
(5) The products and product specifications described in this material are subject to change without
notice for modification and/or improvement. At the final stage of your design, purchasing, or use of
the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that
the latest specifications satisfy your requirements.
(6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of
incidence of break down and failure mode, possible to occur to semiconductor products. Measures
on the systems such as redundant design, arresting the spread of fire or preventing glitch are
recommended in order to prevent physical injury, fire, social damages, for example, by using the
products.
(7) When using products for which damp-proof packing is required, observe the conditions (including
shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets
are individually exchanged.
(8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written
permission of Matsushita Electric Industrial Co., Ltd.
2002 JUL

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