TOSHIBA TC9444F

TC9444F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9444F
Single-Chip karaoke IC II
The TC9444F is a karaoke chip for such applications as
equipment for CD/LD players, mini component stereo sets,
radio-cassette players, and VTRs.
With its internal AD/DA converter system, the TC9444F can
offer such karaoke functions as echo, vocal canceling, and key
control on a single chip in addition to such digital signal
processing (DSP) features as sound field control and bass/treble
control.
Because the program and coefficients are stored on internal
ROM, the IC can be controlled by simple settings.
Features
·
Weight: 1.08 g (typ.)
Incorporates an AD converter (three channels) with 2 times oversampling.
THD: −65dB
S/N ratio: 80dB (typ.)
built-in pre-filter op-amp
·
Incorporates a 1-bit Σ∆-type DA converter (two channels).
THD: −86dB
S/N ratio: 93dB (typ.)
built-in tertiary analog post filter
·
Supports one port for digital input and one for digital output.
·
Incorporates 64 Kbits of delay RAM
·
Microcontroller interface: I2C bus mode as well as Toshiba’s original three-lead mode
·
Built-in boot ROM initializes coefficients at reset or via a boot command.
[Compatible Software]
·
Microphone echo: Variable delay time/level
·
Vocal cancellation: Attenuates only vocals from standard source
·
Vocal change: Vocals fade in/out depending on whether there is input from microphone
·
Vocal key control: For chorus and duet functions
·
Supports multi-sound sources: Various modes
·
Pseudo stereo: Monaural sources enhanced by sense of spaciousness
·
Key control: 14-step (max ±1 octave) stereo key control
·
Compressor or bass boost: Compression ratio selectable in range 6 to 36dB.
Compression effect (amount of boost) can be varied smoothly.
·
Sound field control: Uses delay RAM to simulate such acoustic environments as churches, halls, sports
stadiums, and discos.
·
Equalizer: Characteristics switchable by coefficient or I/F bit settings
·
3D sound field: Offers 3-D sound.
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4
5
6
7
8
9
10
11
12
13
14
15
GNDL
VDL
VDA1
LPFO1
MICI
VRA1
AIL
LPFO2
VRA2
LPFO3
AIR
GNDA1
2
24
23
22
21
20
19
Key
control
´2
18
Analog
post
filter
Multiplier/adder
Data RAM
17
2-ch 1 bit DAC
AOUT
16
Analog
post
filter
1/2
decimation
filter
Digital filter
and
åD-type modulator
16-bit AD
converter
(three shared
channels)
GNDAL
3
AOL
EXTF
54
64 kbit DRAM
4096 w ´ 16 b
55
VRL
2
56
57
VDA2
EXTE
58
EXTB
VRR
1
EXTA
59
EXT9
AOR
EXTO
EXTC
60
EXT8
GNDAR
48
47
46
26
30
29
28
27
Timing Gene.
Program ROM
Data I/O
Microcontroller interface
49
Coefficient ROM
50
Boot ROM
51
EMP
52
CS
Coefficient-offset
RAM
SDA
25
Compressor
53
SCL
XI
Block Diagram/Pin Assignment
GNDX
EXT7
DZ
IFSEL
GNDD1
GNDD2
VDX
RESET
EXT0
TEST
Selector
XO
VDD2
EXT1
LRCKI
BCKI
SDI
LRCKO
BCKO
SDO
VDD1
MCKO
MCKS
CKS
EXT6
EXT5
EXT4
EXT3
EXT2
45
44
43
42
41
40
39
38
37
36
35
34
33
32
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TC9444F
TC9444F
Pin Descriptions
Pin No.
Pin Name
I/O
Function
1
EXTO
O
Extended output port D
2
EXTE
O
Extended output port E
3
EXTF
O
Extended output port F
4
GNDL
¾
DRAM ground
5
VDL
¾
DRAM power supply
6
VDA1
¾
ADC power supply
7
LPFO1
O
Op-amp output for microphone input
8
MICI
I
Op-amp input for microphone input
9
VRA1
¾
10
AIL
I
Op-amp input for line L-channel
11
LPFO2
O
Op-amp output for line L-channel
12
VRA2
¾
ADC reference voltage 2
13
LPFO3
O
Op-amp output for line R-channel
14
AIR
I
Op-amp input for line R-channel
15
GNDA1
¾
ADC ground
16
GNDAL
¾
DAC L-channel ground
17
AOL
O
DAC L-channel output
18
VRL
¾
DAC reference voltage
19
VDA2
¾
DAC power supply
20
VRR
¾
DAC reference voltage
21
AOR
O
DAC R-channel output
22
GNDAR
¾
DAC R-channel ground
23
DZ
O
Digital zero input detection (“H” = zero detection)
24
VDX
¾
Oscillator block power supply
25
XO
O
Oscillator connection
26
XI
I
Oscillator connection or clock input
27
GNDX
¾
Oscillator block ground
28
GNDD1
¾
Digital ground 1
29
EXT0
O
Extended output port 0
30
EXT1
O
Extended output port 1
31
EXT2
O
Extended output port 2
32
EXT3
O
Extended output port 3
33
EXT4
O
Extended output port 4
34
EXT5
O
Extended output port 5
35
EXT6
O
Extended output port 6
Remarks
ADC reference voltage 1
36
CKS
I
System clock selection (“H” = 512 fs, “L” = 384 fs)
Schmitt input
37
MCKS
I
MCKO output clock selection (“H” = 1/1, “L” = 1/2 divider)
Schmitt input
38
MCKO
O
System clock output
39
VDD1
¾
Digital power supply 1
40
SDO
O
Digital audio data output
41
BCKO
O
Bit clock output
42
LRCKO
O
Channel clock output
43
SDI
I
Digital audio data input
Schmitt input
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TC9444F
Pin No.
Pin Name
I/O
Function
Remarks
44
BCKI
I
Bit clock input
Schmitt input
45
LRCKI
I
Channel clock input
Schmitt input
46
VDD2
¾
47
RESET
I (U)
48
IFSEL
I
49
CS
I
Digital power supply 2
Reset (“L” = reset)
With pull-up resistor
Schmitt input
Microcontroller interface selection
(“H” = three-lead mode, “L” = I2C mode)
Schmitt input
Three-lead mode: Command send start signal
Schmitt input
2
I C: chip select
50
SCL
I
Microcontroller interface serial clock
Schmitt input
51
SDA
O
Microcontroller interface serial data
Schmitt input
52
EMP
¾
De-emphasis setting (“H” = ON)
Schmitt input
53
TEST
I (U)
Test mode setting (“H” = fixed)
With pull-up resistor
Schmitt input
54
GNDD2
I
Digital ground 2
55
EXT7
O
Extended output port 7
56
EXT8
O
Extended output port 8
57
EXT9
O
Extended output port 9
58
EXTA
O
Extended output port A
59
EXTB
O
Extended output port B
60
EXTC
O
Extended output port C
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TC9444F
Block Operations
1. Operating Clocks
The master clock can be selected between 512 or 384 fs using the CKS pin. The master clock uses
oscillator or external clock input, through the XI pin.
Regardless of a master clock, the number of digital signal processing steps are predetermined. However,
the DA converter’s operating clock varies according to the master clock mode.
The MCKS pin sets the MCKO output, selecting 1/1 or 1/2 divider of the XI pin.
Table 1.1
Operating Clock Selection and DA Converter Oversampling Rate
CKS Pin
XI Input
MCKS Pin
L
L
MCKO Output
DAC Oversampling Rate
192 fs
384 fs
H
192 fs
384 fs
L
256 fs
H
512 fs
256 fs
H
512 fs
2. Digital Audio Data Input/Output
2.1
Sync Mode
The data input/output bit clock and internal sync (master) mode or external sync (slave) mode are
set using microcontroller interface bits SYNM1 and SYNM2. Initialization by reset sets master mode.
Table 2.1 Sync Mode and Input/Output Bit Clock Settings
SYNM2
SYNM1
SYNC Mode
0
0
Master
BCKI
BCKO
64 fs
(Note 1)
(Note 2)
0
1
Slave
32 fs
BCKI
1
0
Slave
48 fs
BCKI
1
1
Slave
64 fs
BCKI
Note 1: See Table 2.2.
Note 2: XI input divider clock
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TC9444F
2.2
Data Input Formats
Table 2.2 and Figure 2.1 show the data input formats. Microcontroller interface bits IBIT1, IBIT2,
and IBIT3 select the format.
In master mode, the BCKI clock rate varies through the range shown in 2.2.
In slave mode, the BCKI input clock is directly output through the IC internal buffer as the data
output bit clock (BCKO). Therefore, when using the digital data output, input the clock shown in
Table 2.2.
The IIS-compatible format can accept up to 24 bits of data. When inputting data shorter than 24
bits, fix the lower bits to 0.
Table 2.2
Data Input Formats
SYNM2
SYNM1
IBIT3
IBIT2
IBIT1
Format
0
0
0
0
0
MSB first, Right-Justified mode,
16-bit data
32 fs to 128 fs
0
0
0
0
1
MSB first, Right-Justified mode,
18-bit data
36 fs to 128 fs
MSB first, Right-Justified mode,
20-bit data
40 fs to 128 fs
48 fs to 128 fs
Master
mode
BCKI
0
0
0
1
0
0
0
0
1
1
MSB first, Right-Justified mode,
24-bit data
0
0
1
0
0
IIS-compatible, 24 bits
64 fs
0
1
0
0
0
MSB first, Right-Justified mode,
16-bit data
32 fs
0
1
0
0
1
Prohibited
32 fs
0
1
0
1
0
Prohibited
32 fs
0
1
0
1
1
Prohibited
32 fs
0
1
1
0
0
IIS-compatible, 16 bits
32 fs
1
0
0
0
0
MSB first, Right-Justified mode,
16-bit data
48 fs
1
0
0
0
1
MSB first, Right-Justified mode,
18-bit data
48 fs
1
0
0
1
0
MSB first, Right-Justified mode,
20-bit data
48 fs
1
0
0
1
1
MSB first, Right-Justified mode,
24-bit data
48 fs
1
0
1
0
0
IIS-compatible, 24 bits
48 fs
1
1
0
0
0
MSB first, Right-Justified mode,
16-bit data
64 fs
1
1
0
0
1
MSB first, Right-Justified mode,
18-bit data
64 fs
1
1
0
1
0
MSB first, Right-Justified mode,
20-bit data
64 fs
1
1
0
1
1
MSB first, Right-Justified mode,
24-bit data
64 fs
1
1
1
0
0
IIS-compatible, 24 bits
64 fs
Slave
mode
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2002-01-11
TC9444F
a) (IBIT3, IBIT2, IBIT1) = (0, 0, 0): MSB first, Right-Justified mode, 16-bit data
LRCKI
BCKI
LSB
MSB
LSB
MSB
LSB
0
15
0
15
0
SDI
b) (IBIT3, IBIT2, IBIT1) = (0, 0, 1): MSB first, Right-Justified mode, 18-bit data
LRCKI
BCKI
LSB
MSB
LSB
MSB
LSB
0
17
0
17
0
SDI
c) (IBIT3, IBIT2, IBIT1) = (0, 1, 0): MSB first, Right-Justified mode, 20-bit data
LRCKI
BCKI
LSB
MSB
LSB
MSB
LSB
0
19
0
19
0
SDI
d) (IBIT3, IBIT2, IBIT1) = (0, 1, 1): MSB first, Right-Justified mode, 24-bit data
LRCKI
BCKI
LSB
MSB
LSB
MSB
LSB
0
23
0
23
0
SDI
e) (IBIT3, IBIT2, IBIT1) = (1, 0, 0): IIS-compatible, 24 bits max
LRCKI
BCKI
MSB
LSB
MSB
LSB
MSB
23
0
23
0
23
SDI
Note 3: In either mode, sections where “SDI” is omitted are don’t care (no internal data loading).
Figure 2.1
Data Input Formats (BCK = 64 fs)
The microcontroller interface RLS bit controls the polarity of the input/output channel clock (LRCKI, LRCKO).
Table 2.3
Channel Clock Polarity
RLS
Operation
0
L-channel data input/output when LRCKI and LRCKO =
“H”
1
L-channel data input/output when LRCKI and LRCKO =
“L”
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TC9444F
2.3
Zero Data Detection Function Common to L/R
The TC9444F incorporates a function to output a zero detection flag from the DZ pin when input
data contain a string of digital zeros. This is used to forcibly mute the analog output.
Table 2.4 shows the time that elapses until data are detected as zero data. If digital zeros continue
to be output during this period, a zero detection flag is set.
Moreover, setting the DZINH bit in the microcontroller interface mode command to “H” halts zero
detection, fixing the DZ pin to “L” and disabling the zero detection function (see the microcontroller
interface section below).
Table 2.4
Digital Zero Data Detection Time
fs
32 kHz
44.1 kHz
48 kHz
Detection Time
1024 ms
743 ms
683 ms
A reset sets the DZ signal to “H”.
2.4
Data Output Formats
Table 2.5 and Figure 2.2 show the data output formats. Microcontroller interface bits OBIT1 and
OBIT2 select the format.
In master mode, the BCKI clock rate varies through the range shown in Table 2.2. Note, however,
that BCKO is fixed to 64 fs.
In slave mode, the BCKI input clock is directly output as the data output bit clock (BCKO) through
the IC internal buffer (see section 2.2).
Table 2.5
Data Output Formats
SYNM2
SYNM1
IBIT2
IBIT1
Format
BCKI
0
0
0
0
MSB first, Right-Justified mode, 16-bit
data
64 fs
0
0
0
1
MSB first, Right-Justified mode, 20-bit
data
64 fs
0
0
1
0
MSB first, Right-Justified mode, 24-bit
data
64 fs
0
0
1
1
IIS-compatible, 24 bits
64 fs
0
1
0
0
MSB first, Right-Justified mode, 16-bit
data
32 fs (= BCKI)
0
1
0
1
Prohibited
32 fs (= BCKI)
0
1
1
0
Prohibited
32 fs (= BCKI)
0
1
1
1
IIS-compatible, 16 bits
32 fs (= BCKI)
1
0
0
0
MSB first, Right-Justified mode, 16-bit
data
48 fs (= BCKI)
1
0
0
1
MSB first, Right-Justified mode, 20-bit
data
48 fs (= BCKI)
MSB first, Right-Justified mode, 24-bit
data
48 fs (= BCKI)
Master
mode
Slave
mode
1
0
1
0
1
0
1
1
IIS-compatible, 24 bits
48 fs (= BCKI)
1
1
0
0
MSB first, Right-Justified mode, 16-bit
data
64 fs (= BCKI)
1
1
0
1
MSB first, Right-Justified mode, 20-bit
data
64 fs (= BCKI)
1
1
1
0
MSB first, Right-Justified mode, 24-bit
data
64 fs (= BCKI)
1
1
1
1
IIS-compatible, 24 bits
64 fs (= BCKI)
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2002-01-11
TC9444F
(SYNM2, 1) = (0, 0) or (1, 1) BCKO = 64 fs
LRCKO
BCKO
a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data
LSB
MSB
LSB
MSB
LSB
0
15
0
15
0
SDO
b) (OIBIT2, OBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data
LSB
MSB
LSB
MSB
LSB
0
19
0
19
0
SDO
c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data
LSB
MSB
LSB
MSB
LSB
0
23
0
23
0
SDO
d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max
MSB
LSB
MSB
LSB
MSB
23
0
23
0
23
SDO
(SYNM2, 1) = (1, 0) BCKO = 48 fs
LRCKO
BCKO
a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data
LSB
MSB
LSB
MSB
LSB
0
15
0
15
0
SDO
b) (OIBIT2, OIBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data
LSB
MSB
LSB
MSB
LSB
0
19
0
19
0
SDO
c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data
LSB MSB
LSB MSB
LSB MSB
SDO
0
23
0
23
0
23
d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max
LSB MSB
LSB MSB
LSB MSB
SDO
0
0
23
23
0
23
(SYNM2, 1) = (0, 1) BCKO = 32 fs
LRCKO
BCKO
a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data
LSB MSB
LSB MSB
LSB MSB
SDO
0
15
0
15
0
15
b) (OIBIT2, OBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data…Prohibited
c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data…Prohibited
d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max
LSB MSB
LSB MSB
LSB MSB
SDO
0
15
0
Figure 2.2
15
0
15
Data Output Formats
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TC9444F
3. Microcontroller Interface
Consisting of commands and data, the microcontroller interface block is designed as a simple and
easy-to-use interface. This interface has two modes: I2C bus mode and three-lead mode. I2C bus mode can
be switched by a DC setting via a pin.
3.1
Commands
One-byte (8-bit) commands are used to perform a range of settings. Some commands are followed by
one to three bytes of data.
An initial reset sets the microcontroller interface block to master mode. Boot ROM data can be used
to output a sound at reset (analog through mode).
After power-on, reset at least once by setting the RESET pin to low level.
Table 3.1
Command
List of Commands
CH
CL
Data
Setting Contents
BOOT
0
0
¾
Initializes coefficient RAM.
MUTE
1
0 to 3
¾
Turns soft mute and RAMCLR on/off.
KEYCON
2
0 to F
¾
Key control; amount of key shift
VC
3
0 to F
¾
16-page bank vocal cancel/change, multi-sound source
BKSA
4
0 to 3
¾
4-page bank function reserve
BKSB
5
0, 1
¾
2-page bank function reserve
EMP
6
0 to F
¾
De-emphasis
DECI
7
0 to 3
¾
Delay RAM decimation rate
ATIME
8
0 to 3
¾
Level detection attack time
RTIME
9
0 to 6
¾
Level detection release time
COMP
A
0 to F
¾
Compressor function
ATTA
B
0
2-byte
Digital attenuator level A
ATTB
B
1
2-byte
Digital attenuator level B
KEYCON2
B
2
2-byte
Controls an independent key or sets vibrato.
EXTO
B
3
2-byte
Extended output port data
CRAM
C
0, 1
3-byte
Writes coefficient RAM.
MODE
D
0 to 3
1-byte
Sets IC operating mode.
Note 4: The functions of some commands vary according to the internal program.
Also, some programs contain commands that need not be set.
Refer to the separate software datasheet.
The commands are described below. The values in the table marked by an asterisk are the initial
values at a reset.
Setting RESET to “L” also mutes the DA converter output (op-amp feed-back causes the DA
converter to output VREF). Accordingly, to completely mute the analog output during operation,
digitally mute the output using the MUTE command, then set RESET to “L”.
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2002-01-11
TC9444F
3.2
BOOT Command
One-byte command to initialize coefficient RAM.
Initializes coefficient RAM values to the internal BOOT ROM values, retaining the other command
interface settings.
After the BOOT command is received, initialization completes in a 1-fs cycle. Boot release is not
required.
When reset is made by setting the RESET pin to “L”, boot is still executed.
3.3
MUTE Command
One-byte command to clear data RAM and delay RAM, and to execute a soft mute using the digital
attenuator.
Table 3.2
MUTE Command
CL
CH
1
3
2
1
0
0
0
RAMCLR
MUTE
Note 5: At a reset, the initial value is CL = 0H.
MUTE: MUTE = “H” sets soft mute.
RAMCLR: RAMCLR = “H” clears data RAM and delay RAM.
At a soft mute, the time constant is determined by the operation sampling frequency and the time
constant selection bit set by the ATTA command. After the soft mute is released, the digital
attenuator is restored to the set level.
In data RAM, sequentially writing all-zero data (fixing the input data to 000000H) while RAMCLR
= “H” clears data RAM. Therefore, the number of fs cycles required to completely clear data RAM
depends on the program. Normally, several cycles are required.
For a program which is written to in one place only, a 128-word update takes no more than 3 ms.
In delay RAM, after RAMCLR = H, 0000H is sequentially written to delay RAM at subsequent
write operations (INIT operation).
When using delay RAM to significantly change the effect of the SFC processing, to clear the data in
RAM, take the following steps. First set the MUTE bit. Then, after waiting only the length of the
digital attenuator time constant, set RAMCLR to “H” to clear the data in RAM. Then set the
RAMCLR and MUTE bits to “L”. This will enable you to change the signal processing content without
any switching noise.
3.4
KEYCON Command
One-byte command to control the amount of key shift. The CL value indicates the amount of key
shift.
The difference between the 20H command and the 28H command is the point at which key control
processing completely stops. Using the 20H command to turn key control off disables the use of
internal delay RAM in the key control processing, thus allowing delay RAM to be allocated to other
processing.
The amount of key shift set by the KEYCON command applies to both L and R stereo key control
and to monaural key control. The key shift is set in semitone steps.
As delay RAM is used in key control processing, when switching the key shift setting between 0 and
a value other than 0, the signal is intermittent. The soft mute automatically comes on to avoid
switching noise at this time. After the command is issued, the following steps are performed
automatically.
Mute ® Internal settings switched ® Mute released
This series of processing operations takes around 46 ms to execute.
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2002-01-11
TC9444F
Table 3.3 Setting Key Shift Amount
3.5
CH
CL
Setting Content
2
0
Key shift 0 (key control off)
2
1
+1200 cent
2
2
+600 cent
2
3
+500 cent
2
4
+400 cent
2
5
+300 cent
2
6
+200 cent
2
7
+100 cent
*2
8
Key shift 0
2
9
-100 cent
2
A
-200 cent
2
B
-300 cent
2
C
-400 cent
2
D
-500 cent
2
E
-600 cent
2
F
-1200 cent
VC Command
One-byte command to set through, vocal cancel, and vocal change for each input source.
Refer to the separate software datasheet.
3.6
BKSA Command
One-byte command to set four-page bank switching.
3.7
BKSB Command
One-byte command to set two-page bank switching.
3.8
EMPH Command
This command selects an internal de-emphasis digital filter.
The filter is either a digital filter selected, via software, by switching a DSP coefficient bank, or an
internal DA converter digital filter selected via hardware.
The filter is set through the microcontroller interface. The filter is on only when the EMP pin goes
high. This command sets the filter on/off directly from the CD processor EMP flag without passing
through the microcontroller.
As well as a de-emphasis filter, the DSP block filter can also be used as a high-pass filter for
canceling DC offset. (the CROM data determines the filter’s function.)
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2002-01-11
TC9444F
Table 3.4 EMPH Command
CL
CH
6
3
2
1
0
ESB2
ESB1
ESA2
ESA1
Note 6: At a reset, the initial value is CL = 5H.
Table 3.5 Settings with EMPH Command
CL
CH
Setting Block
Filter Characteristics
ESB2
ESB1
ESA2
ESA1
6
¾
¾
0
0
DSP block
Bank 0 (fs = 44.1 kHz)
*6
¾
¾
0
1
DSP block
Bank 1 (off)
6
¾
¾
1
0
DSP block
Bank 2 (fs = 48 kHz)
6
¾
¾
1
1
DSP block
Bank 3 (fs = 32 kHz)
6
0
0
¾
¾
Output DAC block
fs = 44.1 kHz
*6
0
1
¾
¾
Output DAC block
Off (through)
6
1
0
¾
¾
Output DAC block
fs = 48 kHz
6
1
1
¾
¾
Output DAC block
fs = 32 kHz
3.9
DECI Command
One-byte command to select the decimation filter for delay processing in delay RAM.
At a reset, the initial value is 1/3 decimation (CL = 2).
This command determines only the decimation filter band. The decimation rate in delay RAM is
determined by the OFRAM command value.
Table 3.6
DECI Command
CH
CL
Setting Content
7
0
1/1 decimation
7
1
1/2 decimation
*7
2
1/3 decimation
7
3
1/4 decimation
3.10 ATIME Command
One-byte command to set the compressor block attack time.
Table 3.7
CH
CL
ATK1
ATK0
8
0
L
8
1
*8
8
ATIME Command
Attack Time [ms]
CB2, 1 = 0, 0
CB2, 1 = 0, 1
CB2, 1 = 1, 0
CB2, 1 = 1, 1
L
4
3
2
1
L
H
8
6
4
2
2
H
L
16
12
8
4
3
H
H
32
24
16
8
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2002-01-11
TC9444F
3.11 RTIME Command
One-byte command to set the compressor block release time.
Table 3.8
CH
CL
REL1
REL1
REL0
9
0
L
L
*9
1
L
9
2
9
RTIME Command [s]
Release Time
CB2, 1 = 0, 0
CB2, 1 = 0, 1
CB2, 1 = 1, 0
CB2, 1 = 1, 1
L
1.1
0.5
0.3
0.1
L
H
1.6
1.0
0.7
0.3
H
L
L
2.6
2.0
1.3
0.6
3
L
H
H
4.6
4.1
2.6
1.1
9
4
H
L
L
8.7
8.2
5.2
2.2
9
5
H
L
H
16.9
16.3
10.4
4.5
9
6
H
H
L
33.3
32.6
20.8
9.0
3.12 COMP Command
One-byte command to select the compressor function.
Table 3.9
COMP Command
CL
CH
A
3
2
1
0
VCHG
CBS
CB2
CB1
Note 7: At a reset, the initial value is CL = 8H.
VCHG: VCHG = “H” selects (turns on) the vocal change function.
CBS: Selects the compression ratio. CBS = “L” selects a ratio of 24dB;
CBS = “H” selects 36dB (refer to the table)
CB2, 1: Used for precise selection of the compression ratio.
Table 3.10
Compression Ratio Settings
CBS
CB2
CB1
Compression
Ratio
0
0
0
24dB
0
0
1
18dB
0
1
0
12dB
0
1
1
6dB
1
0
0
36dB
1
0
1
27dB
1
1
0
18dB
1
1
1
9dB
Noise can result when CB2, 1 are used to switch the compression ratio.
To switch the ratio without clunking, refer to the software datasheet.
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2002-01-11
TC9444F
3.13 ATTA Command
Command to set the digital attenuator level by adding two-byte data.
When the lower 14 bits of the data are set to 2000H, the attenuator level is 0dB.
The upper two bits are the attenuator time constant selection bits. These bits select the soft mute
time constants.
When switching using the MUTE or KEYCON command, the value set by ATTA is also valid for the
automatic mute function.
Table 3.11
CH
CL
B
0
ATTA Command
D1
DSA2
DSA1
ALA13
ALA12
D0
ALA11
ALA10
ALA09
ALA08
ALA07
~
ALA00
Note 8: At a reset, the initial values are DSA = 0H (23 ms) and ALA [13:00] = 2000H (0dB).
The following formula determines the data ALA [13:00] depending on the level (LEVEL [dB]) to be
set.
ALA [13:00] = 2000H*10^ (LEVEL/20).
Table 3.12
ALA [13:00]
Output Level
3FFFH
+6.020dB
……
……
3000H
+3.523dB
……
……
2000H
-0.000dB
1FFFH
-0.001dB
1FFEH
-0.002dB
……
……
16A7H
-3.000dB
……
……
1000H
-6.021dB
……
……
0002H
-72.247dB
0001H
-78.268dB
0000H
-¥dB
Table 3.13
DSA2
DSA1
L
Attenuator Setting Level
Attenuator Time Constants
Time Constant
fs = 32 kHz
fs = 44.1 kHz
fs = 48 kHz
L
32 ms
23 ms
21 ms
L
H
128 ms
92 ms
86 ms
H
L
256 ms
186 ms
171 ms
H
H
512 ms
372 ms
341 ms
Time required for change from 0dB to -¥dB.
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2002-01-11
TC9444F
3.14 ATTB Command
Command to set the cross fade level for the vibrato function on/off by adding two-byte data.
When the lower 14 bits of the data are set to 2000H, the attenuator level is 0dB. The upper two bits
are the attenuator time constant selection bits. These bits select the soft mute time constants.
Table 3.14
CH
CL
B
1
ATTB Command
D1
DSB2
DSB1
ALB13
ALB12
D0
ALB11
ALB10
ALB09
ALB08
ALB07
~
ALB00
Note 9: At a reset, the initial values are DSB = 0H (23 ms) and ALB [13:00] = 2000H (0dB).
The values are set in the same way as the settings for the ATTA command.
3.15 KEYCON2 Command
Command to set the independent key control right channel or to set the vibrato function by adding
two-byte data.
Because the initial reset sets ENA to “L”, L/R common key control by KEYCON is enabled at an
initial reset.
Table 3.15
CH
CL
B
2
KEYCON2 Command
D1
0
0
ENA
VIB
D0
K2R11
K2R10
K2R09
K2R08
K2R07
~
K2R00
Note 10: At a reset, the initial values are D1 = D2 = 0H.
ENA: Set to “H” when using independent key control or vibrato.
VIB: Set to “H” when using the vibrato function.
K2R [11:00]: When KEYCON2 is used for independent key control, these bits set the key control rate.
When KEYCON2 is used to select the vibrato function, these bits set the step value that
determines the vibrato cycle.
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2002-01-11
TC9444F
Table 3.16
Key Control Set by KEYCON2 (ENA = “H”, VIB = “L”)
Amount of Key Shift
K2R [11:00]
D1
D0
+1200 cent
400
24
00
+600 cent
1A8
21
A8
+500 cent
157
21
57
+400 cent
10A
21
0A
+300 cent
0C2
20
C2
+200 cent
07D
20
7D
+100 cent
03D
20
3D
+50 cent
01E
20
1E
+40 cent
018
20
18
+30 cent
012
20
12
+20 cent
00C
20
0C
+10 cent
006
20
06
-10 cent
FFA
2F
FA
-20 cent
FF4
2F
F4
-30 cent
FEE
2F
EE
-40 cent
FE9
2F
E9
-50 cent
FE3
2F
E3
……
……
-100 cent
EC7
2F
C7
-200 cent
F90
2F
90
-300 cent
F50
2F
50
-400 cent
F2D
2F
2D
-500 cent
EFF
2E
FF
-600 cent
ED4
2E
D4
-1200 cent
E00
2E
00
K2R [11:00] = (2^ (N/1200 [cent]) - 1.0) *400H
Vibrato Cycle Set by KEYCON2 (ENA = “H”, VIB = “H”)
Table 3.17
Cycle [Hz]
K2R [11:00]
D1
D0
05D
30
5D
0BA
30
BA
175
31
75
……
2
……
4
……
8
……
K2R [11:00] = N/22500 [Hz] *100000H
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2002-01-11
TC9444F
3.16 EXTO Command
Command to set the output data of the extended output port by adding two-byte data.
The two-byte data are output in parallel directly from the EXT0 to EXTF pins.
The command is used to control the LEDs which display the key control on/off status and the
amount of key shift.
Table 3.18
CH
CL
B
3
EXTO Command
D1
EXTF
EXTE
EXTD
EXTC
D0
EXTB
EXTA
EXT9
EXT8
EXT7
~
EXT0
Note 11: At a reset, the initial values are D1 = D0 = 0H.
3.17 CRAM Command
Command to write coefficient RAM data by adding three-byte data.
As in the following table, the value of the MSB of the address is assigned to the LSB of the CL bits.
Table 3.19
CH
C
CRAM Command
CL
0
0
D2
0
AD6
AD5
AD4
AD3
AD2
D1
AD1
D2
AD0
AD17
D1
DT15
~
AD16
D0
DT08
DT07
~
DT00
Note 12: A reset or a boot command sets the coefficient RAM value to its initial value.
The R/W offset addresses of coefficient RAM and delay RAM are written as 18 bits of data. An
address consists of three memory allocation bits, three decimation rate bits, and 12 offset address bits.
Because the content of these settings depends on the internal program, refer to the separate software
datasheet.
Table 3.20
CH
C
OFRAM Command
CL
0
0
D2
0
AD6
AD5
AD4
D2
AD3
AD2
D1
AD1
AD0
MAL2
D1
MAL0
DECI2
DECI1
DECI0
MAL1
D0
DTI1
~
DT08
DT07
~
DT00
Note 13: A reset or a boot command sets the offset RAM value to its initial value.
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2002-01-11
TC9444F
In addition Delay RAM is properly used by MAL [2:0] as RAM of 1024, 2048, and 4096 word, as
shown in the following figure.
FFFH
1024 word
D
C00H
F
1024 word
C
G
800H
1024 word
B
E
400H
1024 word
A
000H
Note 14: Since C block is assigned to Keycontrol R-ch, and D block is assingned to Keycontrol L-ch, it is neseccary
to be set to KEY = 0H when using it here.
Figure 3.1
Table 3.21
Block Division of Delay RAM
Block Assignment and Address Range of Delay RAM
MAL2
MAL1
MAL0
Block
Address Range
0
0
0
A
3FFh to 000h
0
0
1
B
7FFh to 400h
0
1
0
C
BFFh to 800h
0
1
1
D
FFFh to C00h
1
0
0
E
7FFh to 000h
1
0
1
F
FFFh to C00h
1
1
¾
G
FFFh to 000h
Table 3.22
Setting of Decimation Ratio
DECI2
DECI1
DECI0
Decimation Ratio
0
0
0
1/1
0
0
1
1/2
0
1
0
1/3
0
1
1
1/4
The same or overlapping block cannot be accessed by different decimation ratio.
Moreover, decimation ratio set up here and decimation ratio set up by DECI command need to be
fundamentally made in agreement.
DECI bit set up with an offset address determines decimation ratio of memory access, and a setup
to DECI command determines the band of a decimation filter.
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2002-01-11
TC9444F
3.18 MODE Command
Command to set the IC operating mode by adding one-byte data.
This command bundles parameters so that they need be set once only at power-on.
The CL bits are also used to make settings.
Table 3.23
CH
D
MODE Command
CL
D0
3
2
1
0
7
6
5
4
3
2
1
0
0
SYMM2
SYMM1
RLS
OBIT2
OBIT1
IBIT3
IBIT2
IBIT1
MCKINH
DZINH
ADPD
Note 15: At a reset, the initial values are SYNM2 = SYNM1 = 0, RLS = 1, D0 = 00H.
(master mode, 16-bit input/output)
SYNM1, 2: Select sync mode
RLS: Selects the channel clock polarity (when RLS = “H” and LRCK = “L” or when RLS = “L” and LRCK =
“H”, L-channel data selected).
OBIT1, 2: Select the digital audio output format.
IBIT1, 2, 3: Select the digital audio input format.
MCKINH: When “H”, disables the MCKO pin output (MCK pin is fixed to low).
DZINH: When “H”, disables the digital zero detection output (DZ pin is fixed to low).
ADPD: When “H”, the AD converter power save and output are masked by setting them to digital zeros.
The MCKINH bit is used to halt the XI input clock (or the halved input clock) output from the
MCKO pin. The MCKO pin uses a large output buffer for high-speed clock output. However, to
suppress unnecessary output without using this pin, set MCKINH to High.
A function is supported to forcibly mute the DAC output by checking whether digital data input
from the SDI pin are all zeroes and by setting the DZ pin high if all-zero input continues for a
specified detection time (Table 2.4).
When digital input and analog input are switched, digital input zero detection becomes active,
setting the DZ pin to High. The DZINH bit is used to inhibit the DZ pin from going High.
Setting the ADPD bit to High halts the AD converter internal circuits and masks the AD converter
output by setting to digital zeros. As some circuitry is halted at this time, the power dissipation drops
slightly.
4. AD Converter
The TC9444F incorporates a successive approximation 16-bit AD converter with a two times
oversampling rate. The AD converter performs three-channel interleave processing for the line input
L/R-channels and the microphone input.
The microphone input is designed to internally generate an echo effect. The microphone main signal and
the microphone echo signal are combined outside the IC. The microphone main signal and the microphone
echo component can also be added internally using a microphone through-path in the IC.
When not using an AD converter, connect jumpers between the MICI-LPFO1, AIL-LPFO2, and
AIR-LPFO3 pins.
5. DA Converter
Incorporates a SD-type modulation 1-bit DA converter and a tertiary analog post filter.
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2002-01-11
TC9444F
6. Reset Timing
After turning on the power supply, always perform a reset by setting the /RESET pin to Low.
Figure 6.1 shows the reset and boot timing.
When performing a power-on reset, note the timing shown in Figure 6.2.
RESET
tRw > 0.2 ms
tBOOT < 50 ms
Boot operation completed. Do not write to
the coefficient or offset RAM until boot is
complete.
Figure 6.1
VDD
Reset and Boot
80%
RESET
40%
tRST > 1 ms
Figure 6.2
Power-On Reset Timing
7. Microcontroller Interface Signal Timing
Microcontroller interface signal timing supports three-lead mode and I2C bus mode.
7.1
Three-Lead Bus Mode
Setting IFSEL = “H” sets the microcontroller interface to three-lead bus mode.
Setting the CS signal = “L” enables control from the microcontroller.
Figure 7.1 shows the interface timing when three-lead mode is selected.
When transmitting two or more commands, be sure to set CS to H between each command.
When writing to coefficient or offset RAM, be sure to write the data word by word in 1 fs per word.
As coefficient or offset RAM cannot be updated in multiple-word batches, take particular care when
updating filter coefficients.
7.2
2
I C Bus Mode
Setting IFSEL = “L” sets the microcontroller interface to I2C bus mode.
In I2C bus mode, the CS pin can be fixed to “L”. Note that the CS pin signal can also be used as
the chip select signal.
The I2C slave address is:
MSB
LSB
1101
1000
^^^^^^^^^^^^^
Data can only be written to this address. Therefore, fix the LSB of read/write mode bits to 0.
As I2C bus mode does not permit continuous writing, insert an END condition after each command,
then a START condition to start writing data again.
21
2002-01-11
SDA
SCL
●
SDA
SCL
CS
●
●
●
d.c.
C7
C6
C5
T2 T3
C4
C3
C2
T4
C1
C0
T5
d.c.
d.c.
C6
C4
C3
ID6
ID5
ID4
ID3
ID2
Fixed to “L” (usable as chip select)
ID1
C2
ID7
ID6
ID5
ID4
ID3
ID2
ID1
When transmitting multiple commands
ID7
T8
C5
Coefficient data 1 transmitted
C7
Two-Byte Commands
CSN
SDA
SCL
CS
ID0
ID0
C1
C0
DA6
DA6
DA5
DA5
DA4
DA4
DA3
DA3
Figure 7.1
Coefficient data 2 transmitted
DA7
DA7
DA1
DA1
DA0
DA0
d.c.
T7
d.c.
Figure 7.2
DA6
ID7
DA4
ID6
DA3
ID5
DA2
ID4
DA1
22
ID3
DA0
ID1
ID0
d.c.
d.c.
d.c.
T6
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
T8 > 1/fs: Coefficient, offset RAM write cycle
T7 > 0.2 ms: CS signal “H” duration
T6 > 0.2 ms: Interface hold time
T5 > 0.2 ms: Data hold time
T4 > 0.2 ms: Data setup time
T3 > 0.2 ms: Shift clock “H” time
T2 > 0.2 ms: Shift clock “L” time
T1 > 0.2 ms: Interface setup time
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
Insert an END condition after each command, then transmit a START condition followed by ID.
DA5
I C Interface Timing (IFSEL = “L”)
2
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
DA7
Three-Lead Interface Timing (IFSEL = “H”)
ID2
When transmitting two or more commands, be
sure to set CS to “H” between the commands.
C0
DB0
C1
DB1
C2
DB2
C3
DB3
C4
DB4
C5
DB5
C6
DB6
C7
DB7
Write the data to coefficient or offset
RAM word by word in 1 fs per word.
DA2
DA2
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
d.c.
When consecutively transmitting two or more commands:
d.c.: don’t care
SDA
SCL
CS
T1
Four-Byte Commands
2002-01-11
TC9444F
TC9444F
8. Digital Data Input/Output Timing
● Rising Edge, Falling Edge
90%
MCKO
10%
tr
90%
LRCKO
BCKO
SDO
tf
10%
tr
tf
● Master Clock
The MCKO pin outputs the XI input clock or the XI input clock divided by two.
XI
MCKO when
MCKS = “H”
MCKO when
MCKS = “L”
td1
td1
● SDO Output
SDO is output on the BCKO falling edge with both internal and external synchronization.
BCKO
SDO
td2
● Master Mode
BCKO and LRCKO are divided from the XI input clock.
At 512 fs
XI
BCKO
td3
LRCKO
td4
● Slave Mode
At 512 fs
XI
LRCKI
Synchronization width
BCKI
BCO
tdls
LRCKI
LRCKO
td6
● Data Input
LRCKI
tLRh
tLRs
BCKI
SDI
tDls
tDlh
Figure 7.3
Digital Data Input/Output Timing
23
2002-01-11
TC9444F
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
VDD
-0.3 to 6.0
V
Input voltage
Vin
-0.3 to VDD + 0.3
V
Power dissipation
PD
500
mW
Operating temperature
Topr
-40 to 85
°C
Storage temperature
Tstg
-55 to 150
°C
Power supply voltage
Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = 5.0 V)
DC Characteristics
Symbol
Test
Circuit
Operating voltage
VDD
¾
Ta = -40 to 85°C
Current consumption
IDD
¾
XI = 16.9 MHz, 384 fs mode
Characteristics
“H” level
¾
“L” level
VIL
“H” level
IIH
“L” level
IIL
“H” level
IOH1
(Note 16) “L” level
IOL1
Output current 1
Output current 2
“H” level
IOH2
(Note 17) “L” level
IOL2
Pull-up resistors
Rup
¾
¾
¾
¾
Min
Typ.
Max
Unit
4.5
5.0
5.5
V
mA
¾
57
80
VDD
´ 0.8
¾
¾
0
¾
VDD
´ 0.2
¾
¾
1.0
-1.0
¾
¾
When VOH = 4.5 V
-2.0
¾
¾
When VOH = 0.5 V
¾
¾
2.0
When VOH = 4.5 V
-4.0
¾
¾
When VOH = 0.5 V
¾
¾
4.0
RESET , TEST pin
¾
50
¾
VIH
Input voltage
Input current
Test Condition
Digital input pins
Digital input pins
V
mA
mA
mA
kW
Note 16: DZ, EXT0 to F, LRCKO, BCKO, SDO, SDA pins
2
In I C bus mode, the SDA pin is “L” output only (open drain).
Note 17: MCKO pin
24
2002-01-11
TC9444F
AC Characteristics
AD Converter
Symbol
Test
Circuit
Ain
1
S/(N + D) ratio
S/N (AD)
THD + N
Crosstalk
Characteristics
Maximum input level
Test Condition
Min
Typ.
Max
Unit
VDD = 5.0 V
¾
1.15
1.20
Vrms
1
-50dB, 1 kHz sine wave input
72
80
¾
dB
THD (AD)
1
-0dB, 1 kHz sine wave input
¾
-65
-57
dB
CT (AD)
1
¾
¾
-68
-60
dB
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Aout
1
¾
¾
1.2
¾
Vrms
S/N (DA)
1
-30dB, 1 kHz sine wave input
84
93
¾
dB
dB
DA Converter
Characteristics
Output level
S/N ratio
THD + N
THD (DA)
1
-0dB, 1 kHz sine wave input
¾
-86
-78
THD (DA)
1
-0dB, 10 kHz sine wave input
¾
-83
-75
CT (DA)
1
¾
¾
-90
-82
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
tr
¾
CL = 50 pF, LRCKO, BCKO,
SDO
¾
¾
30
MCKO
¾
¾
20
CL = 50 pF, LRCKO, BCKO,
SDO
¾
¾
30
MCKO
¾
¾
20
td1
XI ® MCKO
¾
¾
20
td2
BCKO ® SDO
¾
¾
5
XI ® BCKO
¾
¾
15
XI ® LRCKO
¾
¾
30
td5
BCKI ® BCKO
¾
¾
30
td6
LRCKI ® LRCKO
¾
¾
30
Crosstalk
dB
Timings
Characteristics
Rise time
Fall time
tf
Common
Delay time
In master mode
td3
td4
In slave mode
¾
¾
Unit
ns
ns
ns
SDI setup time
tDIs
¾
¾
50
¾
¾
ns
SDI hold time
tDIh
¾
¾
50
¾
¾
ns
LRCKI setup time
tLRs
¾
¾
50
¾
¾
ns
LRCKI hold time
tLRh
¾
¾
50
¾
¾
ns
T1
¾
¾
0.2
¾
¾
ms
T2, T3
¾
¾
0.2
¾
¾
ms
Interface data setup time
T4
¾
¾
0.2
¾
¾
ms
Interface data hold time
T5
¾
¾
0.2
¾
¾
ms
Interface hold time
T6
¾
¾
0.2
¾
¾
ms
Interface CS signal “H” duration
T7
¾
¾
0.2
¾
¾
ms
Coefficient and offset RAM write cycle
T8
¾
¾
1/fs
¾
¾
s
Power-on reset time
tRST
¾
¾
1
¾
¾
ms
Reset pulse width
tRw
¾
¾
0.2
¾
¾
ms
tBOOT
¾
¾
¾
50
ms
Interface setup time
Interface shift clock pulse width
Boot time
Time required for boot
25
2002-01-11
R-ch out
L-ch out
R-ch in
L-ch in
MIC in
3.3 mF
3.3 mF
3.3 mF
10 kW
10 kW
10 kW
47 mF
47 mF
3.3 mF
3.3 mF
470 W
19
18
100 mF
17
0.1 mF
16
15 GNDA1
14 AIR
13 LPFO3
12 VRA2
11 LPFO2
10 AIL
9 VRA1
8 MICI
7 LPFO1
6 VDA1
470 W
51 W 560 pF
10 kW
10 kW
51 W 560 pF
10 kW
10 kW
51 W 560 pF
10 kW
10 kW
5 VDL
4 GNDL
3 EXTF
2 EXTE
1 EXTO
57
EXTA
VRL
58
EXT9
59
56
55
21
20
0.1 mF
100 mF
53
52
22
51
26
50
26
0.1 mF
0.1 mF
25
16.9 MHz
23
24
TC9444F
54
49
48
28
27
CS
60
EMP
VDX
400 Hz HPF
20 kHz LPF
30 kHz HPF
33 pF
Shibasoku
AM51A
Analog input
Analog output
1200 pF
10 kW
10 kW
220
pF
220
pF
220
pF
1200 pF
1200 pF
2200 pF
2200 pF
GNDD2
GNDAR
EXTC
GNDAL
TEST
DZ
EXTB
0.1 mF
0.1 mF
AOL
EXT8
VRR
47 mF
VDA2
47 mF
EXT7
AOR
IFSEL
GNDX
SDA
XO
47
29
30
EXT2 31
EXT3 32
EXT4 33
EXT5 34
EXT6 35
CKS 36
MCKS 37
MCKO 38
VDD1 39
SDO 40
BCKO 41
LRCKO 42
SDI 43
BCKI 44
LRCKI 45
46
Microcontroller interface
RESET
EXT0
SCL
XI
33 pF
0.1 mF
GNDD1
VDD2
EXT1
SDA
SCL
CS
RST
GND
0.1
mF
Test Circuit
8 GND
7 3A
6 3Y
5 2A
4 2Y
3 1A
2 1Y
1 VCC
TC4HC4050AP
4A 9
4Y 10
5A 11
5Y 12
NC 13
6A 14
6Y 15
NC 16
2002-01-11
Digital data input
SDO
SDI
BCKI
LRCKI
MCKO
Digital data input
Anritsu
MG22A
TC9444F
TC9444F
Package Dimensions
Weight: 1.08 g (typ.)
27
2002-01-11
TC9444F
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
28
2002-01-11
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.