Si5020 SiPHY™ M ULTI -R ATE SONET/SDH C LOCK AND D ATA R ECOVERY IC Features Complete high speed, low power, CDR solution includes the following: ! ! ! ! ! Supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC Low Power—270 mW (TYP OC-48) Small Footprint: 4 mm x 4 mm DSPLL™ Eliminates External Loop Filter Components 3.3 V Tolerant Control Inputs ! ! ! ! ! Exceeds All SONET/SDH Jitter Specifications Jitter Generation 3.0 mUIRMS (TYP) Device Power Down Loss-of-Lock Indicator Single 2.5 V Supply Ordering Information: See page 14. Applications Description 20 19 18 VDD 2 GND 3 REFCLK+ 4 REFCLK– 5 CLKOUT– 17 16 15 PWRDN/CAL 14 VDD GND Pad 13 DOUT+ 12 DOUT– 11 VDD 6 7 8 9 10 DIN– 1 DIN+ The Si5020 is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). DSPLL™ technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. REXT CLKOUT+ GND ! Si5020 RATESEL0 ! GND ! ! Pin Assignments SONET/SDH Test Equipment Optical Transceiver Modules SONET/SDH Regenerators Board Level Serial Links RATESEL1 ! ! VDD ! SONET/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Gigabit Ethernet Interfaces LOL ! Top View The Si5020 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40°C to 85°C). Functional Block Diagram LOL DIN+ DIN– 2 BUF DSPLL™ Phase-Locked Loop Retimer BUF 2 DOUT+ DOUT– PWRDN/CAL Bias REXT 2 RATESEL1–0 Preliminary Rev. 0.8 12/00 BUF 2 2 CLKOUT+ CLKOUT– REFCLK+ REFCLK– Copyright © 2000 by Silicon Laboratories Si5020-DS08 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5 02 0 2 Preliminary Rev. 0.8 Si5020 TA B L E O F C O N T E N T S Section Page Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Rev. 0.8 4 5 9 9 9 9 9 9 10 10 11 11 11 11 11 13 15 16 18 3 S i5 02 0 Detailed Block Diagram DOUT+ R e tim e DOUT– c D IN + Phase D e te c to r D IN – A /D VCO DSP CLK D ivid e r CLKOUT+ c CLKOUT– n REFCLK+ Lock D e te c to r REFCLK– LOL 2 R A T E S E L 1-0 REXT C a lib ratio n B ias G en e ra tio n P W R D N /C A L Figure 1. Detailed Block Diagram 4 Preliminary Rev. 0.8 Si5020 Electrical Specifications Table 1. Recommended Operating Conditions Symbol Parameter Ambient Temperature Si5020 Supply Voltage2 Test Condition Min1 Typ Max1 Unit TA –40 25 85 °C VDD 2.375 2.5 2.625 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The Si5020 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 9. V SIGNAL+ VICM,VOCM Differential I/Os SIGNAL– VIS Single-Ended Voltage (SIGNAL+) – (SIGNAL–) VID,VOD (VID = 2VIS) Differential Voltage Swing Differential Peak-to-Peak Voltage t Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) tCf-D tCr-D DOUT CLKOUT Figure 3. Clock to Data Timing 80% DOUT, CLKOUT 20% tF tR Figure 4. DOUT and CLKOUT Rise/Fall Times Preliminary Rev. 0.8 5 S i5 02 0 Table 2. DC Characteristics (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Supply Current OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Power Dissipation OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Single Ended Input Voltage (DIN, REFCLK) Differential Input Voltage Swing (DIN, REFCLK) Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Short to GND (DOUT,CLKOUT) Output Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current 6 Symbol Test Condition Min Typ Max Unit — — — — 108 113 117 124 118 123 127 134 mA — — — — — 100 200 270 283 293 310 .80*VDD — — 310 323 333 352 — 750 1500 mW 84 TBD 100 940 116 TBD TBD 900 TBD mV (pk-pk) — VDD – 0.20 — V 84 — TBD — 2.0 — — — 2.0 10 TBD 100 25 –15 — — — — — — — 25 116 TBD — .8 — 10 10 0.4 — — TBD Ω mA mA V V µA µA V V kΩ µA IDD PD VICM VIS VID varies with VDD See Figure 2 See Figure 2 RIN VOD Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line Single-ended VOD VOCM ROUT ISC(–) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN IO = 2 mA IO = 2 mA VPWRDN ≥ 0.8 V Preliminary Rev. 0.8 V mV mV (pk-pk) Ω mV (pk-pk) Si5020 Table 3. AC Characteristics (Clock & Data) (VA 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit .15 — 2.7 GHz Output Clock Rate fCLK Output Rise Time tR Figure 4 — 100 TBD ps Output Fall Time tF Figure 4 — 100 TBD ps Clock to Data Delay FEC (2.7 GHz) OC-48 GigE OC-12 OC-3 tCr-D Figure 3 TBD TBD TBD TBD TBD 250 255 500 890 4100 TBD TBD TBD TBD TBD ps Clock to Data Delay FEC (2.7 GHz) OC-48 tCf-D TBD TBD 51 50 TBD TBD ps 18.7 TBD — — — — dB dB Input Return Loss Figure 3 100 kHz – 2.5 GHz 2.5 GHz – 4.0 GHz Preliminary Rev. 0.8 7 S i5 02 0 Table 4. AC Characteristics (PLL Characteristics) (VA 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance (OC-48)* JTOL(P–P) f = 600 Hz 40 TBD — UIp-p f = 6000 Hz 4 TBD — UIp-p f = 100 kHz 4 TBD — UIp-p f = 1 MHz 0.4 TBD — UIp-p f = 30 Hz 40 TBD — UIp-p f = 300 Hz 4 TBD — UIp-p * Jitter Tolerance (OC-12 Mode) * Jitter Tolerance (OC-3 Mode) JTOL(P–P) JTOL(P–P) f = 25 kHz 4 TBD — UIp-p f = 250 kHz 0.4 TBD — UIp-p f = 30 Hz 60 TBD — UIp-p f = 300 Hz 6 TBD — UIp-p f = 6.5 kHz 6 TBD — UIp-p f = 65 kHz 0.6 TBD — UIp-p Jitter Tolerance (Gigabit Ethernet) Receive Data Total Jitter Tolerance TJT(P-P) IEEE 802.3z Clause 38.68 600 TBD — ps Jitter Tolerance (Gigabit Ethernet) Receive Data Deterministic Jitter Tolerance DJT(P-P) IEEE 802.3z Clause 38.69 370 TBD — ps JGEN(rms) with no jitter on serial data — 3.0 5.0 mUI JGEN(rms) with no jitter on serial data — 25 55 mUI JBW OC-48 Mode — — 2.0 MHz OC-12 Mode — — 500 kHz OC-3 Mode — — 130 kHz — 0.03 0.1 dB After falling edge of PWRDN/CAL 1.45 1.5 1.7 ms From the return of valid data 40 60 150 µs 40 50 60 % RMS Jitter Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth* Jitter Transfer Peaking* Acquisition Time Input Reference Clock Duty Cycle JP TAQ CDUTY Reference Clock Range 19.44 — 168.75 MHz Input Reference Clock Frequency Tolerance CTOL –100 — 100 ppm Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL TBD 600 TBD ppm Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK TBD 300 TBD ppm *Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 – 1 data pattern. 8 Preliminary Rev. 0.8 Si5020 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 2.8 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA °C Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 Storage Temperature Range TSTG –55 to 150 °C 300 °C 1 kV Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Symbol Test Condition Value Unit ϕJA Still Air 38 °C/W Thermal Resistance Junction to Ambient LVTTL Control Inputs Loss-of-Lock Indicator LOL RATESEL1-0 High Speed Serial Input PWRDN/CAL 2 DOUT+ DIN+ DOUT– DIN– Recovered Data Si5020 CLKOUT+ REFCLK– CLKOUT– Ω 10kΩ (1%) VDD VDD Recovered Clock GND REFCLK+ REXT System Reference Clock 0.1 µF 2200pF 20pF Figure 5. Si5020 Typical Application Circuit Preliminary Rev. 0.8 9 S i5 02 0 Functional Description The Si5020 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLL™ technology to eliminate the noise entry points caused by external PLL loop filter components. DSPLL™ The phase-locked loop structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL™ technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain. PLL Self-Calibration The Si5020 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on power-up. A self-calibration can be initiated by forcing a high-tolow transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 µS before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories’ “AN42: Controlling the Si5018/20 Self-Calibration.” Multi-Rate Operation The Si5020 supports clock and data recovery for OC-48 and STM-16 data streams. In addition, the PLL was designed to operate at data rates up to 2.7 Gbps to support OC-48/STM-16 applications that employ forward error correction (FEC). RATESEL0-1 pins. The RATESEL0-1 configuration and associated data rates are given in Table 7. Table 7. Multi-Rate Configuration SDH Gigabit Ethernet OC-48 with 15/14 FEC 2.488 Gbps — 2.67 Gbps 1 10 1.244 Gbps 1.25 Gbps — 2 01 622.08 Mbps — — 4 11 155.52 Mbps — — 16 RATESEL [0:1] SONET/ 00 Reference Clock Detect The Si5020 uses the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream. The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output of between 2.5 GHz and 2.7 Ghz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 8. Table 8. Typical REFCLK Frequencies SONET/SDH Gigabit Ethernet SONET/ SDH with Ratio of 15/14 FEC REFCLK VCO to 19.44 MHz 19.53 MHz 20.83 MHz 128 77.76 MHz 78.125 MHz 83.31 MHz 32 155.52 MHz 156.25 MHz 166.63 MHz 16 Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The divide factor is configured by the 10 CLK Divider Preliminary Rev. 0.8 Si5020 Forward Error Correction (FEC) The Si5020 supports FEC in SONET OC-48 (SDH STM-16) applications for data rates up to 2.7 Gbps. In FEC applications, the appropriate reference clock frequency is determined by dividing the input data rate by 16, 32, or 128. For example, if an FEC code is used that produces a 2.70 Gbps data rate, the required reference clock would be 168.75 MHz, 84.375 MHz, or 21.09 MHz. Sinusoidal Input Jitter (UI p-p) Slope = 20 dB/Decade 15 1.5 0.15 Lock Detect f0 The Si5020 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 8, the PLL is declared out of lock, and the loss-oflock (LOL) pin is asserted “high.” In this state, the DSPLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock, CLKOUT, will drift over a ±600 ppm range relative to the supplied reference clock. The LOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 4. Note: LOL is not asserted during PWRDN/CAL. PLL Performance The PLL implementation used in the Si5020 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The Si5020’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 6. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. f1 f2 f3 ft Frequency SONET Data Rate OC-48 OC-12 OC-3 F0 (Hz) 10 10 10 F1 (Hz) 600 30 30 F2 (Hz) 6000 300 300 F3 (kHz) 100 25 6.5 Ft (kHz) 1000 250 65 Figure 6. Jitter Tolerance Specification Jitter Transfer The Si5020 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 7). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 6. Jitter Generation The Si5020 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5020 typically generates less than 3.0 mUI rms of jitter when presented with jitter-free input data. Note: There are no entries in the mask table for the data rate corresponding to OC-24 as that rate is not specified by either GR-253 or G.958. Preliminary Rev. 0.8 11 S i5 02 0 When PWRDN/CAL is released (set to “low”) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream. Jitter Transfer 0.1 dB Device Grounding 20 dB / Decade Slope The Si5020 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. Acceptable Range Bias Generation Circuitry Fc Frequency SONET Data Rate OC-48 OC-12 OC-3 The Si5020 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. Fc (kHz) 2000 500 130 Differential Input Circuitry Figure 7. Jitter Transfer Specification Power Down The Si5020 provides a power down pin, PWRDN/CAL, that disables the output drivers (DOUT, CLKOUT). When the PWRDN/CAL pin is driven “high”, the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. Differential Driver The Si5020 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6. Si5020 VDD 0.1 µF µ Zo = 50 Ω DIN+, REFCLK+ Zo = 50 Ω DIN–, REFCLK– 2.5 kΩ Ω 10 kΩ Ω 0.1 µF µ 2.5 kΩ Ω 102 Ω 10 kΩ Ω GND Figure 8. Input Termination for DIN and REFCLK (AC Coupled) 12 Preliminary Rev. 0.8 Si5020 Differential Output Circuitry The Si5020 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. Si5020 VDD VDD 100 Ω 100 Ω 50 Ω DOUT+, CLKOUT+ 0.1 µF DOUT–, CLKOUT– 0.1 µF Zo = 50 Ω Zo = 50 Ω 50 Ω VDD VDD Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled) Preliminary Rev. 0.8 13 S i5 02 0 20 19 18 REXT 1 VDD 2 CLKOUT– CLKOUT+ GND RATESEL0 RATESEL1 Pin Descriptions: Si5020 17 16 15 PWRDN/CAL 14 VDD GND Pad 11 VDD LOL 7 8 9 10 DIN– 5 DIN+ 12 DOUT– REFCLK– 6 13 DOUT+ GND 3 4 VDD GND REFCLK+ Top View Figure 10. Si5020 Pin Configuration Table 9. Si5020 Pin Descriptions Pin # Pin Name 1 REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. 4, 5 6 REFCLK+, REFCLK– I LOL O See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. LVTTL Loss of Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 8. 9, 10 DIN+, DIN– I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. 12, 13 14 DOUT–, DOUT+ O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. Preliminary Rev. 0.8 Si5020 Table 9. Si5020 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 15 PWRDN/CAL I LVTTL Description Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration‚" on page 10.) Note: This input has a weak internal pulldown. 16, 17 19, 20 CLKOUT–, CLKOUT+ O RATESEL1, RATESEL0 I CML Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK. LVTTL Data Rate Select. These pins configure the onboard PLL for clock and data recovery at one of four user selectable data rates. See Table 7 for configuration settings. Note: These inputs have weak internal pulldowns. 2, 7, 11, 14 VDD 2.5 V Supply Voltage. Nominally 2.5 V. 3, 8, 18, and GND Pad GND GND Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground. Preliminary Rev. 0.8 15 S i5 02 0 Ordering Guide Table 10. Ordering Guide 16 Part Number Package Temperature Si5020-BM 20-pin MLP –40°C to 85°C Preliminary Rev. 0.8 Si5020 Package Outline Figure 11 illustrates the package details for the Si5020. Table 11 lists the values for the dimensions shown in the illustration. 2X TO P VIEW 0 .2 5 BO TTO M VIEW A C D A 10 D /2 0 .0 5 D1 C 4 4X P b A D 1 /2 0 .1 0 D 2 /2 A3 0 .2 5 C C A B D2 A2 2X N M R A1 8. N B 4X P 5 6 E 1 /2 1 0 .5 0 D IA . 1 E /2 2 2 E1 3 4X Q E (N e-1 )X e 3 E2 REF. E 2 /2 L 0 .2 0 C B 2X 0 B 0 .2 0 C e C A S E A T IN G PLANE 2X A1 b REF. 11 NO TES: 4 C CL 1. C 2. CL SEC TIO N "C -C " SCALE: NONE e (N d -1 )X e e DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. 3. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. 4. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP. T E R M IN A L T IP FO R O D D TER M IN AL/SID E 5. THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY. FO R EVEN TER M IN AL/SID E 6. EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. 7. ALL DIMENSIO N S ARE IN MILLIMETERS. 8. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . 9. PACKAG E W AR PAG E MAX 0.05mm. 10. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING . 11. APPLIED O NLY FO R TERMINALS. Figure 11. 20-pin Micro Leaded Package (MLP) Table 11. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Millimeters Min — 0.00 — 0.23 1.95 Nom 0.85 0.01 0.65 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Symbol Max 1.00 0.05 0.80 0.35 2.25 Millimeters Min E1 E2 N Nd Ne L P Q R θ Preliminary Rev. 0.8 1.95 0.50 0.24 0.30 0.13 — Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 — Max 2.25 0.75 0.60 0.65 0.23 12° 17 S i5 02 0 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 18 Preliminary Rev. 0.8