TS3003 A 1.55V to 5.25V, 1.9µA, 9kHz to 300kHz Silicon Timer FEATURES DESCRIPTION The TS3003 is a single-supply, second-generation oscillator/timer fully specified to operate at a supply voltage range of 1.55 V to 5.25 V while consuming less than 2.4 μA(max) supply current. Requiring only a resistor to set the base output frequency (or output period) at 25 kHz (or 40 µs) with a 50% duty cycle, the TS3003 timer/oscillator is compact, easy-to-use, and versatile. Optimized for ultra-long life, low frequency, battery-powered/portable applications, the TS3003 joins the TS3001, TS3002, TS3004, and TS3006 in the CMOS timer family of “NanoWatt Analog™” high-performance analog integrated circuits. Ultra Low Supply Current: 1.9μA at 25kHz Supply Voltage Operation: 1.55V to 5.25V Single Resistor Sets FOUT at 50% Duty Cycle Programmable FOUT Period: 9kHz ≤ FOUT ≤ 300kHz FOUT Period Accuracy: 3% FOUT Period Drift: 0.02%/ºC Single Resistor Sets Output Frequency Separate PWM Control and Buffered Output FOUT/PWMOUT Output Driver Resistance: 160Ω APPLICATIONS Portable and Battery-Powered Equipment Low-Parts-Count Nanopower Oscillator Compact Micropower Replacement for Crystal and Ceramic Oscillators Micropower Pulse-width Modulation Control Micropower Pulse-position Modulation Control Micropower Clock Generation Micropower Sequential Timing The TS3003 output frequency can be user-adjusted from 9 kHz to 300 kHz with a single resistor. In addition, the TS3003 represents a 25% reduction in pcb area and a factor-of-10 lower power consumption over other CMOS-based integrated circuit oscillators/timers. When compared against industrystandard 555-timer-based products, the TS3003 offers up to 84% reduction in pcb area and over three orders of magnitude lower power consumption. The TS3003 is fully specified over the -40°C to +85°C temperature range and is available in a low-profile, 10-pin 3x3 mm TDFN package with an exposed back-side paddle. TYPICAL APPLICATION CIRCUIT Page 1 © 2014 Silicon Laboratories, Inc. All rights reserved. TS3003 ABSOLUTE MAXIMUM RATINGS VDD to GND................................................................. -0.3V to +5.5V PWM_CNTRL to GND ................................................ -0.3V to +5.5V FOUT, PWMOUT to GND .......................................... -0.3V to +5.5V RSET to GND............................................................. -0.3V to +2.5V CPWM to GND ........................................................... -0.3V to +5.5V FDIV to GND .............................................................. -0.3V to +5.5V Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (Derate at 13.48mW/°C above +70°C) ... 1078mW Operating Temperature Range ................................. -40°C to +85°C Storage Temperature Range .................................. -65°C to +150°C Lead Temperature (Soldering, 10s)...................................... +300°C Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART CARRIER QUANTITY MARKING TS3003ITD1033 Tape & Reel ----- Tape & Reel 3000 3003I TS3003ITD1033T Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges. Page 2 TS3003 Rev. 1.0 TS3003 ELECTRICAL CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, unless otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1. PARAMETER Supply Voltage SYMBOL VDD CONDITIONS CPWM = VDD Supply Current IDD MIN 1.55 TYP 1.9 -40°C ≤ TA ≤ 85°C 3.3 -40°C ≤ TA ≤ 85°C FOUT Period FOUT Period Line Regulation tFOUT ∆tFOUT/V -40°C ≤ TA ≤ 85°C 1.55V ≤ VDD ≤ 5.25V 49 ∆tFOUT/∆T PWMOUT Duty Cycle DC(PWMOUT) PWMOUT Duty Cycle Line Regulation ΔDC(PWMOUT)/V CPWM Sourcing Current ICPWM UVLO Hysteresis FOUT, PWMOUT Rise Time FOUT, PWMOUT Fall Time VUVLO FDIV Input Current 37 15 51 1.55V < VDD < 5.25V, FDIV2:0 = 000 41.6 (VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE) 930 810 150 µs % %/°C 48 24 -3 -40°C ≤ TA ≤ 85°C µA %/V 0.02 VPWM_CNTRL= 0V UNITS V % % 1050 1150 250 nA mV tRISE See Note 2, CL = 15pF 10 ns tFALL See Note 2, CL = 15pF 10 ns 0.001 % FOUT Jitter RSET Pin Voltage 40.1 0.17 FOUT Duty cycle FOUT Period Temperature Coefficient 39 38 MAX 5.25 2.4 2.7 3.6 4.5 41.2 42 See Note 3 V(RSET) IFDIV 0.3 V 10 -40°C ≤ TA ≤ 85°C nA 20 Maximum Oscillator Fosc RSET= 360K 300 kHz Frequency High Level Output Voltage, FOUT and VDD - VOH IOH = 1mA 160 mV PWMOUT Low Level Output Voltage, FOUT and VOL IOL = 1mA 140 mV PWMOUT Dead Time TDT FOUT edge falling and PWMOUT edge rising 106 ns Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based on lab bench characterization and is not tested in production. Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench characterization and is not tested in production. TS3003 Rev. 1.0 Page 3 TS3003 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = VDD, unless otherwise noted. Values are at TA = 25°C unless otherwise noted. FOUT Period vs Temperature Supply Current vs FOUT Period 14 41 40.5 10 PERIOD - µs SUPPLY CURRENT - µA 12 8 6 4 39.5 2 0 39 0 20 40 60 80 100 -40 35 60 Supply Current vs CLOAD(FOUT) Supply Current vs Temperature 85 2.5 SUPPLY CURRENT - µA SUPPLY CURRENT - µA 10 TEMPERATURE - ºC 6 4 2 2.3 2.1 1.9 1.7 0 0 10 30 20 40 -40 10 35 60 TEMPERATURE - ºC FOUT Period vs Supply Voltage Start-up Time vs Supply Voltage 85 11 START-UP TIME - ms 40.18 40.16 40.14 40.12 40.1 1.55 -15 CLOAD- pF 40.2 10 9 8 7 6 5 2.29 3.03 3.77 4.51 SUPPLY VOLTAGE - Volt Page 4 -15 PERIOD - µs 8 PERIOD - µs 40 5.25 1.55 2.29 3.03 3.77 4.51 5.25 SUPPLY VOLTAGE - Volt TS3003 Rev. 1.0 TS3003 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = VDD , unless otherwise noted. Values are at TA = 25°C unless otherwise noted. Supply Current Distribution 120 35% 100 30% PERCENT OF UNITS - % PERIOD - µs Period vs RSET 80 60 40 20 25% 20% 15% 10% 5% 0% 0 0 2 4 6 8 10 12 1.95 RSET - MΩ 1.97 1.99 2.01 SUPPLY CURRENT - µA FOUT VDD = 5V, CLOAD = 15pF FOUT 1V/DIV FOUT 1V/DIV FOUT VDD = 3V, CLOAD = 15pF FOUT and PWMOUT VDD = 3V, CLOAD = 15pF, VPWM CNTRL= VDD, CPWM = 47pF FOUT and PWMOUT VDD = 5V, CLOAD = 15pF, VPWM CNTRL= VDD, CPWM = 47pF PWMOUT 2V/DIV PWMOUT 2V/DIV FOUT 2V/DIV 5µs/DIV FOUT 2V/DIV 5µs/DIV 5µs/DIV TS3003 Rev. 1.0 5µs/DIV Page 5 TS3003 PIN FUNCTIONS Page 6 PIN NAME 1 FOUT 2,3, NC 5 PWMOUT 6 PWM_CNTRL 4,7 GND 8 CPWM 9 VDD 10 RSET FUNCTION Fixed Frequency Output. A push-pull output stage with an output resistance of 160Ω. FOUT pin swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. Non-Connect. Pulse-width Modulated Output. A push-pull output stage with an output resistance of 160Ω, the PWMOUT pin is wired antiphase with respect to FOUT and swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. PWM Output Pulse Control Pin. Applying a voltage between GND and VRSET will reduce the duty cycle of the PWMOUT output that is set by the capacitor connected to the CPWM pin. Connect PWM_CNTRL to VDD for fixed PWMOUT output pulse time (determined only by capacitor at CPWM). Ground. Connect this pin to the system’s analog ground plane. PWMOUT Pulse Width Programming Capacitance Input. A target capacitance connected from this pin to GND sets the duty cycle of the PMW output. Minimize any stray capacitance on this pin. The voltage on this pin will swing from GND to VRSET. Connect CPWM to VDD to disable PWM function (saves PWM current). Power Supply Voltage Input. The supply voltage range is 1.55V ≤ VDD ≤ 5.25V. Bypass this pin with a 0.1uF ceramic coupling capacitor in close proximity to the TS3003. FOUT Programming Resistor Input. A 4.32MOhm resistor connected from this pin to ground sets the T3003’s internal oscillator’s output period to 40µs (25KHz). For optimal performance, the composition of the RSET resistor shall be consistent with a tolerance of 1% or lower. The RSET pin voltage is approximately 0.3V. TS3003 Rev. 1.0 TS3003 BLOCK DIAGRAM THEORY OF OPERATION RSET (MΩ) The TS3003 is a user-programmable oscillator where the period of the square wave at its FOUT terminal is generated by an external resistor connected to the RSET pin. The output frequency is given by: FOUT (kHz) 1.08E11 RSET Equation 1. FOUT Frequency Calculation TS3003 Rev. 1.0 FOUT (kHz) 0.360 300 1 108 2.49 43.37 4.32 25 6.81 15.86 9.76 11.07 12 9 Table 1: FOUT vs RSET Page 7 TS3003 With an RSET = 4.32MΩ, the output frequency is approximately 25kHz with a 50% duty cycle. As design aids, Tables 1 lists TS3003’s typical FOUT for various standard values for RSET. APPLICATIONS INFORMATION The output frequency can be user-adjusted from 9kHz to 300kHz with a single resistor. The TS3003 also provides a separate PWM output signal at its PWMOUT terminal that is anti-phase with respect to FOUT. A dead time of approximately 106ns exists between FOUT and PWMOUT. To adjust the pulse width of the PWMOUT output, a single capacitor can be placed at the CPWM pin. To determine the capacitance needed for a desired pulse width, the following equation is to be used: To keep the TS3003’s power consumption low, resistive loads at the FOUT and PWMOUT terminals increase dc power consumption and therefore should be as large as possible. Capacitive loads at the FOUT and PWMOUT terminals increase the TS3003’s transient power consumption and, as well, should be as small as possible. CPWM(F)= Pulse Width(s) x ICPWM VCPWM ≅300mV Equation 2. CPWM Capacitor Calculation where ICPWM and VCPWM is the current supplied and voltage applied to the CPWM capacitor, respectively. The pulse width is determined based on the period of FOUT and should never be greater than the period at FOUT. Make sure the PWM_CNTRL pin is set to at least 400mV when calculating the pulse width of PWMOUT. Note VCPWM is approximately 300mV, which is the RSET voltage. Also note that ICPWM is approximately 1µA. The PWMOUT output pulse width can be adjusted further after selecting a CPWM capacitor. This can be achieved by applying a voltage to the PWM_CNTRL pin between VRSET and GND. With a voltage of at least VRSET, the pulse width is set based on Equation 2. For example, with a period of 40µs( 25kHz) a 47pF capacitor at the CPWM pin generates a pulse width of approximately 16µs. This can be calculated using equation 2. By reducing the PWM_CNTRL voltage from VRSET ≅ 300mV to GND, the pulse width is reduced from 16µs to approximately 8µs. This is a pulse width reduction of 50%. Note that as the FOUT frequency increases, the amount of pulse width reduction reduces and vice versa. Furthermore, if the PWMOUT output is half the frequency of the FOUT output, this means your CPWM capacitor is too large and as a result, the pulse width is greater than the FOUT period. In this case, use Equation 2 and reduce the capacitor value to less than the period. Connect CPWM to VDD to disable the PWM function and in turn, save power. Connect PWM_CNTRL to VDD for a fixed PWMOUT output pulse width, which is determined by the CPWM pin capacitor only. Page 8 Minimizing Power Consumption One challenge to minimizing the TS3003’s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. Most instruments exhibit an input capacitance of 15pF or more. Unless buffered, the increase in transient load current can be as much as 400nA. To minimize capacitive loading, the technique shown in Figure 1 can be used. In this circuit, the principle of Figure 1: Using an External Capacitor in Series with Probes Reduces Effective Capacitive Load. series-connected capacitors can be used to reduce the effective capacitive load at the TS3003’s FOUT and PWMOUT terminals. To determine the optimal value for CEXT once the probe capacitance is known by simply solving for CEXT using the following expression: CEXT = 1 1 1 - CLOAD(EFF) CPROBE Equation 3:External Capacitor Calculation For example, if the instrument’s input probe capacitance is 15pF and the desired effective load capacitance at either or both FOUT and PWMOUT terminals is to be ≤5pF, then the value of CEXT should be ≤7.5pF. TS3003 Rev. 1.0 TS3003 TS3003 Start-up Time As the TS3003 is powered up, its FOUT terminal (and PWMOUT terminal, if enabled) is active once the applied VDD is higher than 1.55V. Once the applied VDD is higher than 1.55V, the master oscillator achieves steady-state operation within 8ms. Divide the PWMOUT Output Frequency by Two with the TS3003 Using a single resistor and capacitor, the TS3003 can be configured to a divide by two circuit as shown in Figure 2. To achieve a divide by two function with the TS3003, the pulse width of the PWMOUT output must be at least a factor of 2 greater than the period set at FOUT by resistor RSET. The CPWM capacitor selected must meet this pulse width requirement and can be calculated using Equation 2. In Figure 3, a value of 4.32MΩ for RSET sets the FOUT output period to 40µs. A CPWM capacitor of 265pF was chosen, which sets the pulse width of PWMOUT to approximately 80µs. This is well above the required minimum pulse width of 40µs. Using the TS3003 and a Potentiometer to Dim an LED The TS3003 can be configured to dim an LED by modulating the pulse width of the PWMOUT output. With an RSET= 2MΩ, the FOUT output frequency is approximately 51kHz (or 19.5µs period). Refer to Figure 3. The CPWM capacitor was calculated using Equation 2 with a pulse width of 15µs. To reduce the pulse width from 15µs and in turn, dim the LED, a 1MΩ potentiometer is used. The potentiometer is connected to the PWM_CNTRL pin in a voltage divider configuration. The supply voltage of the circuit is 5V. . Figure 3: TS3003 Configured to Dim an LED with a Potentiometer Figure 2: Configuring the TS3003 into a Divide by Two Frequency Divider TS3003 Rev. 1.0 Page 9 TS3003 PACKAGE OUTLINE DRAWING 10-Pin TDFN33 Package Outline Drawing (N.B., Drawings are not to scale) Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. 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