TS3006 A 1.55V to 5.25V, 1.9µA, 9kHz to 300kHz Silicon Timer FEATURES Ultra Low Supply Current: 1.9μA at 25kHz Supply Voltage Operation: 1.55V to 5.25V Single Resistor Sets FOUT at 50% Duty Cycle FOUT Period: 9kHz ≤ FOUT ≤ 300kHz Single Resistor Sets Output Frequency FOUT Period Accuracy: 3% FOUT Period Drift: 0.02%/ºC FOUT Output Driver Resistance: 160Ω APPLICATIONS Portable and Battery-Powered Equipment Low-Parts-Count Nanopower Oscillator Compact Micropower Replacement for Crystal and Ceramic Oscillators Micropower Pulse-width Modulation Control Micropower Pulse-position Modulation Control Micropower Clock Generation Micropower Sequential Timing DESCRIPTION The TS3006 is a single-supply, second-generation oscillator/timer fully specified to operate at a supply voltage range of 1.55V to 5.25V while consuming less than 2.4μA(max) supply current. Requiring only a resistor to set the base output frequency (or output period) at 25kHz (or 40µs) with a 50% duty cycle, the TS3006 timer/oscillator is compact, easy-to-use, and versatile. Optimized for ultra-long life, low frequency, battery-powered/portable applications, the TS3006 joins the TS3001, TS3002, TS3004, and TS3005 in the CMOS timer family of “NanoWatt Analog™” highperformance analog integrated circuits. The TS3006 output frequency can be user-adjusted from 9kHz to 300kHz with a single resistor. In addition, the TS3006 represents a 25% reduction in pcb area and a factor-of-10 lower power consumption over other CMOS-based integrated circuit oscillators/timers. When compared against industrystandard 555-timer-based products, the TS3006 offers up to 84% reduction in pcb area and over three orders of magnitude lower power consumption. The TS3006 is fully specified over the -40°C to +85°C temperature range and is available in a low-profile, 8-pin 3x3mm TDFN package with an exposed backside paddle. TYPICAL APPLICATION CIRCUIT Page 1 © 2014 Silicon Laboratories, Inc. All rights reserved. TS3006 ABSOLUTE MAXIMUM RATINGS VDD to GND................................................................. -0.3V to +5.5V PWM_CNTRL to GND ................................................ -0.3V to +5.5V FOUT, PWMOUT to GND .......................................... -0.3V to +5.5V RSET to GND............................................................. -0.3V to +2.5V CPWM to GND ........................................................... -0.3V to +5.5V FDIV to GND .............................................................. -0.3V to +5.5V Continuous Power Dissipation (TA = +70°C) 8-Pin TDFN (Derate at 23.8mW/°C above +70°C) ....... 1951mW Operating Temperature Range ................................. -40°C to +85°C Storage Temperature Range .................................. -65°C to +150°C Lead Temperature (Soldering, 10s)...................................... +300°C Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART CARRIER QUANTITY MARKING TS3006ITD833 Tape & Reel ----- Tape & Reel 3000 3006I TS3006ITD833T Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges. Page 2 TS3006 Rev. 1.0 TS3006 ELECTRICAL CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1. PARAMETER SYMBOL Supply Voltage VDD Supply Current IDD FOUT Period FOUT Period Line Regulation CONDITIONS -40°C ≤ TA ≤ 85°C -40°C ≤ TA ≤ 85°C UVLO Hysteresis 40.1 38 UNITS 5.25 V 2.4 1.55V ≤ VDD ≤ 5.25V 41.2 42 0.17 49 ΔtFOUT/ΔT VUVLO MAX 2.7 39 FOUT Duty cycle FOUT Period Temperature Coefficient TYP 1.9 tFOUT ΔtFOUT/V MIN 1.55 51 150 µs %/V 0.02 (VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE) µA % %/°C 250 mV FOUT Rise Time tRISE See Note 2, CL = 15pF 10 ns FOUT Fall Time tFALL See Note 2, CL = 15pF 10 ns 0.001 % 0.3 V FOUT Jitter RSET Pin Voltage See Note 3 V(RSET) Maximum Oscillator Fosc RSET= 360K 300 kHz Frequency High Level Output VDD - VOH IOH = 1mA 160 mV Voltage, FOUT Low Level Output VOL IOL = 1mA 140 mV Voltage, FOUT Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based on lab bench characterization and is not tested in production. Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench characterization and is not tested in production. TS3006 Rev. 1.0 Page 3 TS3006 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. FOUT Period vs Temperature Supply Current vs FOUT Period 14 41 40.5 10 PERIOD - µs SUPPLY CURRENT - µA 12 8 6 4 39.5 2 0 0 20 40 60 80 39 100 35 60 Supply Current vs Temperature 85 2.5 SUPPLY CURRENT - µA SUPPLY CURRENT - µA 10 Supply Current vs CLOAD(FOUT) 4 2 0 10 20 30 2.1 1.9 -40 -15 10 35 60 CLOAD- pF TEMPERATURE - ºC FOUT Period vs Supply Voltage Start-up Time vs Supply Voltage 85 11 START-UP TIME - ms 40.18 40.16 40.14 40.12 40.1 1.55 2.3 1.7 40 40.2 10 9 8 7 6 5 2.29 3.03 3.77 4.51 SUPPLY VOLTAGE - Volt Page 4 -15 TEMPERATURE - ºC 6 0 -40 PERIOD - µs 8 PERIOD - µs 40 5.25 1.55 2.29 3.03 3.77 4.51 5.25 SUPPLY VOLTAGE - Volt TS3006 Rev. 1.0 TS3006 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. Supply Current Distribution 120 35% 100 30% PERCENT OF UNITS - % PERIOD - µs Period vs RSET 80 60 40 20 0 0 2 4 6 8 10 20% 15% 10% 5% 0% 12 RSET - MΩ 1.95 1.97 1.99 2.01 SUPPLY CURRENT - µA FOUT VDD = 5V, CLOAD = 15pF FOUT 1V/DIV FOUT 1V/DIV FOUT VDD = 3V, CLOAD = 15pF 5µs/DIV TS3006 Rev. 1.0 25% 5µs/DIV Page 5 TS3006 PIN FUNCTIONS PIN NAME 1 FOUT 2 NC 3,4,5,6 GND 7 VDD 8 RSET FUNCTION Fixed Frequency Output. A push-pull output stage with an output resistance of 160Ω. FOUT pin swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. Non-Connect. Ground. Connect this pin to the system’s analog ground plane. Power Supply Voltage Input. The supply voltage range is 1.55V ≤ VDD ≤ 5.25V. Bypass this pin with a 0.1uF ceramic coupling capacitor in close proximity to the TS3006. FOUT Programming Resistor Input. A 4.32MOhm resistor connected from this pin to ground sets the T3003’s internal oscillator’s output period to 40µs (25KHz). For optimal performance, the composition of the RSET resistor shall be consistent with a tolerance of 1% or lower. The RSET pin voltage is approximately 0.3V. BLOCK DIAGRAM Page 6 TS3006 Rev. 1.0 TS3006 THEORY OF OPERATION The TS3006 is a user-programmable oscillator where the period of the square wave at its FOUT terminal is generated by an external resistor connected to the RSET pin. The output frequency is given by: FOUT (kHz) = To minimize capacitive loading, the technique shown in Figure 1 can be used. In this circuit, the principle of series-connected capacitors can be used to reduce the effective capacitive load at the TS3006’s FOUT and PWMOUT terminals. 1.08E11 RSET Equation 1. FOUT Frequency Calculation With an RSET = 4.32MΩ, the output frequency is approximately 25kHz with a 50% duty cycle. As design aids, Tables 1 lists TS3006’s typical FOUT for various standard values for RSET. RSET (MΩ) FOUT (kHz) 0.360 300 1 108 2.49 43.37 4.32 25 6.81 15.86 9.76 11.07 12 9 Table 1: FOUT vs RSET Connect CPWM to VDD to disable the PWM function and in turn, save power. Connect PWM_CNTRL to VDD for a fixed PWMOUT output pulse width, which is determined by the CPWM pin capacitor only. APPLICATIONS INFORMATION Minimizing Power Consumption To keep the TS3006’s power consumption low, resistive loads at the FOUT and PWMOUT terminals increase dc power consumption and therefore should be as large as possible. Capacitive loads at the FOUT and PWMOUT terminals increase the TS3006’s transient power consumption and, as well, should be as small as possible. Figure 1: Using an External Capacitor in Series with Probes Reduces Effective Capacitive Load. To determine the optimal value for CEXT once the probe capacitance is known by simply solving for CEXT using the following expression: CEXT = 1 1 1 CLOAD(EFF) CPROBE Equation 2: External Capacitor Calculation For example, if the instrument’s input probe capacitance is 15pF and the desired effective load capacitance at either or both FOUT and PWMOUT terminals is to be ≤5pF, then the value of CEXT should be ≤7.5pF. TS3006 Start-up Time As the TS3006 is powered up, its FOUT terminal (and PWMOUT terminal, if enabled) is active once the applied VDD is higher than 1.55V. Once the applied VDD is higher than 1.55V, the master oscillator achieves steady-state operation within 8ms. One challenge to minimizing the TS3006’s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. Most instruments exhibit an input capacitance of 15pF or more. Unless buffered, the increase in transient load current can be as much as 400nA. TS3006 Rev. 1.0 Page 7 TS3006 Using a Potentiometer to Trim the TS3006’s Output Frequency . By using a fixed resistor and a potentiometer, the output frequency of the TS3006 can be trimmed as shown in Figure 2. By selecting a fixed resistor R1 with a tolerance of 0.1% and a potentiometer P1 with a 5% tolerance, the output frequency can be trimmed to provide a ±2% trimming range Figure 2: Using a Fixed Resistor and a Potentiometer to Trim the TS3006’s Output Frequency. Page 8 TS3006 Rev. 1.0 TS3006 PACKAGE OUTLINE DRAWING 8-Pin TDFN33 Package Outline Drawing (N.B., Drawings are not to scale) 0.80 Max 0.70 Min 0.25 Ref 1.85 Max 1.65 Min 3.05 Max 2.95 Min 1.60 Max 1.40 Min PIN 1 MARKING 0.5 Max 0.3 Min 0.35 Ref 0.65 ref 0.35 Max 0.25 Min 0.05 Max 0.00 min 3.05 Max 2.95 Min BOTTOM VIEW TOP VIEW 0.80 Max 0.70 Min 0.05 Max 0.00 Min 0.05 Max 0.00 Min 0.20 REF DETAIL A 0.20 REF DETAIL A SIDE VIEW NOTE: CONTROLLING DIMENTIONS IN MILIMETERS Compliant with JEDEC MO-229 Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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