T5096P www.vishay.com Vishay Semiconductors Silicon NPN Phototransistor E: emitter FEATURES • Package type: chip • Package form: chip • Dimensions (L x W x H in mm): 0.39 x 0.39 x 0.185 • High photo sensitivity • High collector current E • Small size • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 21704 DESCRIPTION T5096P is an epitaxial phototransistor especially designed for optocoupler applications. Despite its small size it has a high sensitivity and ability to drive high currents even under saturation. GENERAL INFORMATION The datasheet is based on Vishay optoelectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. Customers are encouraged to perform testing in actual proposed packaged and used conditions. Vishay optoelectronics die products are tested using Vishay optoelectronics based quality assurance procedures and are manufactured using Vishay optoelectronics established processes. Estimates such as those described and set forth in this datasheet for semiconductor die will vary depending on a number of packaging, handling, use, and other factors. Therefore sold die may not perform on an equivalent basis to standard package products. PRODUCT SUMMARY Ica (μA) ϕ (deg) λ0.1 (nm) 200 to 310 ± 60 480 to 1080 PACKAGING REMARKS PACKAGE FORM Wafer sawn on foil with disco frame MOQ: 200 000 pcs Chip COMPONENT T5096P Note • Test conditions see table “Basic Characteristics” ORDERING INFORMATION ORDERING CODE T5096P-SD-F Note • MOQ: minimum order quantity ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL VALUE Collector emitter voltage TEST CONDITION VCEO 85 UNIT V Emitter collector voltage VECO 7.8 V mA Collector current IC 50 Junction temperature Tj 125 °C Operating temperature range Tamb -55 to +125 °C Storage temperature range Tstg1 -55 to +150 °C Rev. 1.5, 05-Nov-14 Document Number: 84190 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T5096P www.vishay.com Vishay Semiconductors BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER Collector emitter breakdown voltage TEST CONDITION SYMBOL MIN. E = 0 mW/cm2; IC = 10 μA V(BR)CEO 85 VCE = 50 V, E = 0 lx ICEO <1 λp 910 nm λ0.1 480 to 1080 nm Collector emitter dark current Wavelength of peak sensitivity Range of spectral bandwidth TYP. MAX. UNIT V 50 nA Note • The measurements are based on samples of die which are mounted on a TO-header without resin coating CCEO - Collector Emitter Capacitance (pF) BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) S(λ)rel - Relative Spectral Sensitivity 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 21703 600 700 800 900 1000 1100 λ - Wavelength (nm) Fig. 1 - Relative Spectral Sensitivity vs. Wavelength 8 f = 1 MHz 7 6 5 4 3 2 1 0 0.1 1 10 100 VCE - Collector Emitter Voltage (V) Fig. 2 - Collector Emitter Capacitance vs. Collector Emitter Voltage MECHANICAL DIMENSIONS PARAMETER SYMBOL MIN. TYP. Length of chip edge (x-direction) Lx 0.39 Length of chip edge (y-direction) Ly 0.39 Die height H Bond pad emitter d 0.170 MAX. UNIT mm mm 0.185 0.200 Ø 0.10 (bonding area) mm mm ADDITIONAL INFORMATION Frontside metallization, emitter Backside metallization, collector Dicing Die bonding technology AlSi 1.2 μm AuSb 0.4 μm Sawing Epoxy bonding Note • All products are checked in accordance with the Vishay Semiconductor, specification of visual inspection FVOV6870. The visual inspection shall be made in accordance with the “specification of visual inspection as referenced”. The visual inspection of wafer backside is performed with stereo microscope with incident light and 40x to 80x magnification. The quality inspection (final visual inspection) is performed by production. An additional visual inspection step as special release procedure by QM is not installed. Rev. 1.5, 05-Nov-14 Document Number: 84190 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T5096P www.vishay.com Vishay Semiconductors CHIP DIMENSIONS in millimeters Orientation of wafer flat 0.256 (0.37) (1) Z E technical drawings according to DIN specifications 0.256 (0.37) (1) Z 400:1 Ø 0.12 metallization E: Emitter Opt. active area: 0.057 mm2 Bonding area: E: Ø 100 μm Ø0 E .1 b ond ing are Bonding restricted to this area in order to avoid damage of adjacent structures a Thickness: 185 μm ± 15 μm Drawing-No.: 9.000-5077.3-4 Issue: 2; 03.05.2011 Note • Not indicated tolerances: ± 0.005 (1) Only for information: dimension of sawn die under consideration of 30 μm saw kerf HANDLING AND STORAGE CONDITIONS • The hermetically sealed shipment lots shall be opened in temperature and moisture controlled cleanroom environment only. It is mandatory to follow the rules for disposition of material that can be hazardous for humans and environment. • Product must be handled only at ESD safe workstations. Standard ESD precautions and safe work environments are as defined in MIL-HDBK-263. • Singulated die are not to be handled with tweezers. A vacuum wand with non metallic ESD protected tip should be used. PACKING Chips are fixed on adhesive foil. For shipment, the wafers are arranged to stacks and hermetically sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). Use for recycling reliable operators only. We can help getting in touch with your nearest sales office. By agreement we will take back packing material, if it is sorted. You will have to bear the costs of transport. We will invoice you for any costs incurred for packing material that is returned unsorted or which we are not obliged to accept. Rev. 1.5, 05-Nov-14 Document Number: 84190 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000