TI TMS320P25PH

TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
CLKR
CLKX
V CC
V CC
63
VSS
VSS
VCC
3
62
A15
VCC
4
61
A14
CLKX
5
60
A13
VSS
6
59
A12
CLKR
7
58
VSS
RS
8
57
A11
READY
9
56
A10
HOLD
10
55
A9
BIO
11
54
A8
MP / MC
12
53
D15
13
52
VCC
VCC
VSS
14
51
A7
D14
15
50
A6
64
D13
16
49
VSS
VCC
17
48
A5
D12
18
47
A4
D11
19
46
A3
D10
20
45
A2
D9
21
44
A1
D8
22
43
NC
VSS
23
42
VSS
VSS
24
41
A0
FSR
DR
VCC
INT2
INT1
INT0
SYNC
D0
D1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Copyright  1994, Texas Instruments Incorporated
• HOUSTON, TEXAS 77251–1443
1
ADVANCE INFORMATION
DS
IS
PS
R/W
STRB
BR
X1
X2 / CLKIN
FSX
DX
V SS
HOLDA
XF
CLKOUT2
2
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
READY
D8
D9
D10
D11
D12
D13
D14
D15
VCC
V SS
With a 100-ns instruction cycle time and an
innovative memory configuration, the ’320P25
performs operations necessary for many real-time
digital signal processing algorithms. Since most
instructions require only one cycle, the
TMS320P25 is capable of executing ten million
instructions per second. On-chip programmable
data /program RAM of 544 words of 16 bits,
on-chip program EPROM of 4K words (one-time
programmable memory), direct addressing of up
1
D2
The TMS320P25 digital signal processor is a
member of the TMS320 family of VLSI digital
signal processors and peripherals. The TMS320
family supports a wide range of digital signal
processing
applications,
such
as
telecommunications,
modems,
image
processing, speech processing, spectrum
analysis, audio processing, digital filtering,
high-speed control, graphics, and other
computation intensive applications.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
IACK
D3
description
PH PACKAGE
( TOP VIEW )
D4
•
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D5
•
•
•
IACK
MSC
CLKOUT1
CLKOUT2
XF
HOLDA
DX
FSX
X2 CLKIN
X1
BR
STRB
R/W
PS
IS
DS
VSS
V SS
A1
A2
A3
A4
A5
A6
A7
V CC
A8
A9
A10
A11
A12
A13
A14
A15
•
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CLKOUT1
•
•
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
INT0
INT1
INT2
VCC
DR
FSR
A0
MSC
•
FN PACKAGE
( TOP VIEW )
D6
•
•
•
•
•
•
Instruction Cycle Time of 100 ns (40 MHz)
4K Words of On-Chip Secure Program
EPROM
544 Words of On-Chip Data RAM
128K Words of Data/Program Space
16 Parallel I/O Ports
32-Bit ALU/Accumulator
16 × 16-Bit Multiplier With a 32-Bit Product
Block Moves for Data/Program
Management
Repeat Instructions for Efficient Use of
Program Space
Serial Port for Direct Codec Interface
Synchronization Input for Synchronous
Multiprocessor Configurations
Wait States for Communication to Slow
Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations
Single 5-V Supply
Packaging:
– 68-Lead Plastic J-Leaded Chip Carrier
(FN Suffix)
– 80-Lead Plastic Quad Flatpack
(PH Suffix)
68-to-28-Lead Conversion Adapter Socket
for EPROM Programming
D7
•
•
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
description (continued)
to 64K words of external program and 64K words of data memory space, and multiprocessor interface features
for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the
processor.
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
VCC
VSS
I
5-V supply
I
Ground
X1
O
Output from internal oscillator for crystal
X2/CLKIN
I
Input to internal oscillator from crystal or external clock
CLKOUT1
O
Master clock-output (crystal or CLKIN frequency/4)
CLKOUT2
O
A second clock-output signal
ADVANCE INFORMATION
D15-D0
I/O/Z
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces.
A15-A0
O/Z
16-bit address bus A15 (MSB) through A0 (LSB)
PS, DS, IS
O/Z
Program, data, and I/O space select signals
R/W
O/Z
Read/write signal
STRB
O/Z
Strobe signal
RS
I
Reset input
INT2-INT0
I
External user interrupt inputs
MP/MC
I
Microprocessor/microcomputer mode select
MSC
O
Microstate complete signal
IACK
O
Interrupt acknowledge signal
READY
OI
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
BR
O
Bus request. Asserted when the TMS320P25 requires access to an external global data memory space.
XF
O
External flag output (latched software-programmable signal)
HOLD
I
Hold input. When asserted, TMS320P25 goes into an idle mode and places the data, address, and control lines in
the high-impedance state.
HOLDA
O
Hold acknowledge
SYNC
I
Synchronization input
BIO
I
Branch control input. Polled by BIOZ instruction.
DR
I
Serial data receive input
CLKR
I
Clock for receive input for serial port
I
Frame synchronization pulse for receive input
FSR
DX
CLKX
O/Z
I
Serial-data-transmit output
Clock for transmit output for serial port
FSX
I / O / Z Frame synchronization pulse for transmit. Configuration as either an input or an output.
† I = input, O = output, Z = high-impedance state
2
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
architecture
The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard
architecture, program and data memory reside in two separate spaces permitting a full overlap of instruction
fetch and execution. The TMS320 family’s modification of the Harvard architecture allows transfers between
program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients
stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also
makes available immediate instructions and subroutines based on computed values.
Increased throughput on the TMS320P25 devices for many DSP applications is accomplished by means of
single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
ADVANCE INFORMATION
The architectural design of the TMS320P25 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
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3
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
functional block diagram
SYNC
IS
DS
PS
X1
X2 / CLKIN
CLKOUT1
CLKOUT2
Program Bus
R/W
STRB
READY
BR
XF
HOLD
HOLDA
MSC
BIO
RS
IACK
16
16
16
16
PFC(16)
QIR(16)
IR(16)
16
STO(16)
Controller
MUX
ST1(16)
16
16
MCS(16)
16
Address
16
MP/MC
RSR(16)
Program
EPROM
(4096 × 16)
MUX
A15 – A0
16
16
(8 × 16)
16
XSR(16)
16
16
MUX
ADVANCE INFORMATION
16
16
D15 – D0
DRR(16)
16
Instruction
EPROM
RBIT
DR
CLKR
FSR
DX
CLKX
FSX
16
Stack
3
16
IFR(6)
PC(16)
12
INT(2 – 0)
RPTC(8)
16
16
DXR(16)
16
TIM(16)
16
PRD(16)
6
IMR(6)
8
GREG(8)
16
16
Program Bus
Data Bus
16
16
16
16
AR0(16)
AR2(16)
ARP(3)
TR(16)
MUX
DP(9)
9
AR4(16)
16
Multiplier
AR3(16)
3
16
16
16
7 LSB
From IR
AR1(16)
3
16
9
3
Shifter
(0 – 16)
AR5(16)
PR(32)
AR6(16)
32
AR7(16)
32
Program Bus
16
ARB(3)
Data Bus
Shifter(-6, 0, 1, 4)
16
3
16
MUX
ARAU(16)
32
MUX
16
16
MUX
32
MUX
16
32
16
ALU(32)
32
DATA/PROG
RAM (256 × 16)
Block B0
Block B2
(32 × 16)
Data RAM
Block B1
(256 × 16)
C
ACCH(16)
Shifters (0 – 7)†
MUX
16
ACCL(16)
32
16
16
16
16
Data Bus
Legend:
ACCH
ACCL
ALU
ARAU
ARB
ARP
DP
DRR
DXR
4
=
=
=
=
=
=
=
=
=
Accumulator high
Accumulator low
Arithmetic logic unit
Auxiliary-register-arithmetic unit
Auxiliary-register-pointer buffer
Auxiliary register pointer
Data memory page pointer
Serial-port data-receive register
Serial-port data-transmit register
IFR
IMR
IR
MCS
QIR
PR
PRD
TIM
TR
=
=
=
=
=
=
=
=
=
Interrupt-flag register
Interrupt-mask register
Instruction register
Microcall stack
Queue-instruction register
Product register
Period register for timer
Timer
Temporary register
POST OFFICE BOX 1443
PC
PFC
RPTC
GREG
RSR
XSR
AR0–AR7
ST0, ST1
C
• HOUSTON, TEXAS 77251–1443
=
=
=
=
=
=
=
=
=
Program counter
Prefetch counter
Repeat-instruction counter
Global-memory-allocation register
Serial-port receive-shift register
Serial-port transmit-shift register
Auxiliary registers
Status registers
Carry bit
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
32-bit ALU/accumulator
The 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and logical
instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following
capabilities:
•
•
•
Branch to an address specified by the accumulator
Normalize fixed-point numbers contained in the accumulator
Test a specified bit of a word in data memory
One input to the ALU is always provided from the accumulator, and the other input can be provided from the
product register (PR) of the multiplier or the input scaling shifter that has fetched data from the RAM on the data
bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator.
scaling shifter
The TMS320P25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the
instruction. The LSBs of the output are filled with zeros, and the MSBs can be either filled with zeros or sign
extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register
ST1.
16 × 16-bit parallel multiplier
The 16 × 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single
machine cycle. The multiplier has the following two associated registers:
•
•
A 16-bit temporary register (TR) that holds one of the operands for the multiplier
A 32-bit product register (PR) that holds the product
Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands
to be processed simultaneously. The data for these operations can reside anywhere in internal or external
memory and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the product register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The TMS320P25 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1 on the TMS320P25. A timer interrupt (TINT)
is generated every time the timer decrements to zero. The timer is reloaded with the value contained in the period
(PRD) register within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular
intervals of PRD + 1 cycles of CLKOUT1 on the TMS320P25.
memory control
The TMS320P25 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory and 256 words
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the
TMS320P25 to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can
be downloaded from external program memory into on-chip RAM and then executed.
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5
ADVANCE INFORMATION
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
memory control (continued)
When using on-chip program RAM, EPROM, or high-speed external program memory, the TMS320P25 runs
at full speed without wait states. However, the READY line can be used to interface the TMS320P25 to slower,
less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM
speeds processing while cutting system costs.
The TMS320P25 provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon
the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure
block B0 as program memory) instructions allow dynamic configuration of the memory maps through software.
Regardless of the configuration, the user can still execute from external program memory.
The TMS320P25 has six registers that are mapped into the data memory space: a serial-port data-receive
register, serial-port data-transmit register, timer register, period register, interrupt-mask register, and
global-memory-allocation register.
ADVANCE INFORMATION
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Program
0(0000h)
Program
Data
0(0000h)
Interrupts
and Reserved
(external)
31(001Fh)
32(0020h)
31(001Fh)
32(0020h)
0(0000h)
On-Chip
Memory-Mapped
Registers
Interrupts
and Reserved
(on-chip EPROM)
5(0005h)
6(0006h)
Reserved
On-Chip
EPROM
Page 0
95(005Fh)
96(0060h)
4015(0FAFh)
4016(0FB0h)
On-Chip
Block B2
127(007Fh)
128(0080h)
Reserved
4095(0FFFh)
4096(1000h)
Reserved
Pages 1 – 3
On-Chip
Block B0
Pages 4 – 5
On-Chip
Block B1
Pages 6 – 7
External
Pages 8 – 511
511(01FFh)
512(0200h)
External
767(02FFh)
768(0300h)
External
65 535(0FFFFh)
65 535(0FFFFh)
65 535(FFFFh)
If MP/MC = 1
(microprocessor mode)
ADVANCE INFORMATION
1023(03FFh)
1024(0400h)
If MP/MC = 0
(microcomputer mode)
(a) MEMORY MAPS AFTER A CNFD INSTRUCTION
Program
0(0000h)
Interrupts
and Reserved
(external)
Program
On-Chip
Memory-Mapped
Registers
Interrupts
and Reserved
(on-chip EPROM)
31(001Fh)
32(0020h)
31(001Fh)
32(0020h)
Data
0(0000h)
0(0000h)
4015(0FAFh)
4016(0FB0h)
5(0005h)
6(0006h)
On-Chip
EPROM
Reserved
95(005Fh)
96(0060h)
Reserved
4095(0FFFh)
4096(1000h)
Page 0
On-Chip
Block B2
127(007Fh)
128(0080h)
Reserved
Pages 1 – 3
Does Not
Exist
Pages 4 – 5
511(01FFh)
512(0200h)
External
767(02FFh)
768(0300h)
External
On-Chip
Block B1
Pages 6 – 7
External
Pages 8 – 511
1023(03FFh)
1024(0400h)
65 279(0FEFFh)
65 280(0FF00h)
65 279(0FEFFh)
65 280(0FF00h)
On-Chip
Block B0
65 535(0FFFFh)
If MP/MC = 1
(microprocessor mode)
On-Chip
Block B0
65 535(0FFFFh)
65 535(0FFFFh)
If MP/MC = 0
(microcomputer mode)
(b) MEMORY MAPS AFTER A CNFP INSTRUCTION
Figure 1. Memory Maps
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7
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
external interface
The TMS320P25 supports a wide range of system-interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data buses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are
made with slower devices, the TMS320P25 processor waits until the other device completes its function and
signals the processor via the READY line. Then, the TMS320P25 continues execution.
A full-duplex serial port provides communication with serial devices such as codecs, serial A/D converters, and
other serial systems. The interface signals are compatible with codecs and many other serial devices with a
minimum of external hardware. The serial port can also be used for communication between processors in
multiprocessing applications.
ADVANCE INFORMATION
The serial port has two memory-mapped registers: the data-transmit register (DXR) and the data-receive
register (DRR). Both registers operate in either the byte mode or 16-bit word mode and can be accessed in the
same manner as any other data memory location. Each register has an external clock, a framing
synchronization pulse, and associated shift registers. One method of multiprocessing can be implemented by
programming one device to transmit while the others are in the receive mode. The serial port on the TMS320P25
is double buffered and fully static.
interrupts and subroutines
The TMS320P25 has three external maskable user interrupts INT2 – INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial-port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-word boundaries so that branch instructions can be accommodated in those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to
instructions that are repeated and to instructions that become multicycle because of the READY signal.
multiprocessing
The flexibility of the TMS320P25 allows configurations to satisfy a wide range of system requirements and can
be used as follows:
•
•
•
•
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the TMS320P25 has the capability of allocating global data-memory space
and communicating with that space via the bus request (BR) and READY control signals. Global data-memory
is data memory shared by more than one processor. Global data-memory access must be arbitrated. The 8-bit
memory-mapped global memory-allocation register (GREG) specifies part of the TMS320P25 data memory as
global external memory. The contents of the register determine the size of the global memory space. If the
current instruction addresses an operand within that space, BR is asserted to request control of the bus. The
length of the memory cycle is controlled by the READY line.
The TMS320P25 supports direct memory access (DMA) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the TMS320P25’s external memory by
asserting HOLD low. This causes the TMS320P25 to place its address data and control lines in the
high-impedance state and assert HOLDA. On the TMS320P25, program execution from on-chip EPROM can
proceed concurrently when the device is in the hold mode.
8
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
instruction set
The TMS320P25 microprocessor implements a comprehensive instruction set that supports both
numeric-intensive signal processing operations as well as general-purpose applications, such as
multiprocessing and high-speed control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data / program or I/O space, the number of cycles can
vary depending upon whether the next data operand fetch is from internal or external memory. Highest
throughput is achieved by maintaining data memory on-chip and using either internal or fast external program
memory.
The TMS320P25 instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing. Both direct and indirect addressing can be used to access data memory. In direct memory
addressing, the instruction word contains the lower seven bits of the data memory address. This field is
concatenated with the nine bits of the data-memory page pointer to form the full 16-bit address. Memory is paged
in the direct addressing mode with a total of 512 pages, each page containing 128 words. Indirect addressing
accesses data memory through the auxiliary registers. In immediate addressing, the data is based on a portion
of the instruction word(s).
Eight auxiliary registers (AR0 – AR7) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7,
respectively.
There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding
or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, following which the current auxiliary register and ARP can
be modified.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
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9
ADVANCE INFORMATION
addressing modes
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
instruction set summary
Table 1 lists the symbols and abbreviations used in Table 2. Table 2 consists primarily of single-cycle,
single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle. The instruction
set summary is arranged according to function and alphabetized within each functional grouping. The symbol
† indicates those instructions that are not included in the TMS320C1x instruction set.
Table 1. Instruction Symbols
SYMBOL
DEFINITION
B
CM
D
FO
I
K
PA
4-bit field specifying a bit code
2-bit field specifying compare mode
Data memory address field
Format status bit
Addressing mode bit
Immediate operand field
Port address (PA0 through PA15 are predefined assembler symbols
equal to 0 through 15, respectively.)
2-bit field specifying P register output shift code
3-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field
ADVANCE INFORMATION
PM
AR
S
X
10
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 2. TMS320P25 Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
DESCRIPTION
INSTRUCTION BIT CODE
NO
NO.
WORDS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
0
ABS
Absolute value of accumulator
ADD
Add to accumulator with shift
1
0
0
0
0
I
D
ADDC
Add to accumulator with carry
1
0
1
0
0
0
0
1
1
I
D
ADDH
Add to high accumulator
1
0
1
0
0
1
0
0
0
I
D
ADDK
Add to accumulator short immediate
1
1
1
0
0
1
1
0
0
ADDS
Add to low accumulator with sign extension
suppressed
1
0
1
0
0
1
0
0
1
I
D
ADDT
Add to accumulator with shift specified by
T register
1
0
1
0
0
1
0
1
0
I
D
ADLK†
Add to accumulator long immediate with shift
2
1
1
0
1
AND
AND with accumulator
1
0
1
0
0
ANDK†
AND immediate with accumulator with shift
2
1
1
0
1
CMPL†
Complement accumulator
1
1
1
0
0
LAC
Load accumulator with shift
1
0
0
1
0
LACK
Load accumulator immediate short
1
1
1
0
0
1
0
1
0
LACT†
Load accumulator with shift specified by
T register
1
0
1
0
0
0
0
1
0
LALK†
Load accumulator long immediate with shift
2
1
1
0
1
0
0
0
0
NEG†
Negate accumulator
1
1
1
0
0
1
1
1
0
0
0
1
0
NORM†
Normalize contents of accumulator
1
1
1
0
0
1
1
1
0
1
X
X
X
OR
OR with accumulator
1
0
1
0
0
1
1
0
1
ORK†
OR immediate with accumulator with shift
2
1
1
0
1
0
0
0
0
ROL
Rotate accumulator left
1
1
1
0
0
1
1
1
0
0
0
1
ROR
Rotate accumulator right
1
1
1
0
0
1
1
1
0
0
0
1
SACH
Store high accumulator with shift
1
0
1
1
0
1
SACL
Store low-order accumulator with shift
1
0
1
1
0
0
SBLK†
Subtract from accumulator long immediate
with shift
2
1
1
0
1
SFL†
Shift accumulator left
1
1
1
0
0
1
1
1
SFR†
Shift accumulator right
1
1
1
0
0
1
1
1
SUB
Subtract from accumulator with shift
1
0
0
0
1
SUBB
Subtract from accumulator with borrow
1
0
1
0
0
1
1
1
SUBC
Conditional subtract
1
0
1
0
0
0
1
SUBH
Subtract from high accumulator
1
0
1
0
0
0
1
SUBK
Subtract from accumulator short immediate
1
1
1
0
0
1
SUBS
Subtract from low accumulator with sign
extension suppressed
1
0
1
0
0
0
S
0
S
1
1
1
1
K
1
0
1
0
S
0
0
0
0
I
D
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
1
I
S
S
S
D
K
I
D
I
D
X
I
D
X
I
D
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
S
I
D
1
I
D
1
1
I
D
0
0
I
1
0
1
1
0
1
S
D
K
I
D
† These instructions are not included in the TMS320C1x instruction set.
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11
ADVANCE INFORMATION
MNEMONIC
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 2. TMS320P25 Instruction Set Summary (Continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
MNEMONIC
DESCRIPTION
INSTRUCTION BIT CODE
NO
NO.
WORDS
15
14
13
12
11
10
9
8
7
6
5
4
3
ADVANCE INFORMATION
SUBT†
Subtract from accumulator with shift
specified by T register
1
0
1
0
0
0
1
1
0
I
D
XOR
Exclusive-OR with accumulator
1
0
1
0
0
1
1
0
0
I
D
XORK†
Exclusive-OR immediate with accumulator
with shift
2
1
1
0
1
ZAC
Zero accumulator
1
1
1
0
0
1
0
1
ZALH
Zero low accumulator and load high
accumulator
1
0
1
0
0
0
0
ZALR
Zero low accumulator and load high
accumulator with rounding
1
0
1
1
1
1
ZALS
Zero accumulator and load low accumulator
with sign extension suppressed
1
0
1
0
0
0
2
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
I
D
0
1
1
I
D
0
0
1
I
D
2
1
0
0
CM
S
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC
DESCRIPTION
NO
NO.
WORDS
INSTRUCTION BIT CODE
15
14
13
12
11
10
9
8
ADRK
Add to auxiliary register short immediate
1
0
1
1
1
1
1
1
0
CMPR†
Compare auxiliary register with auxiliary
register AR0
1
1
1
0
0
1
1
1
0
LAR
Load auxiliary register
1
0
0
1
1
0
R
LARK
Load auxilliary register short immediate
1
1
1
0
0
0
R
LARP
Load auxilliary register pointer
1
0
1
0
1
0
1
0
1
1
LDP
Load data memory page pointer
1
0
1
0
1
0
0
1
0
I
LDPK
Load data memory page pointer immediate
1
1
1
0
0
1
0
0
LRLK†
Load auxiliary register long immediate
2
1
1
0
1
0
MAR
Modify auxiliary register
1
0
1
0
1
0
SAR
Store auxiliary register
1
0
1
1
1
0
SBRK
Subtract from auxiliary register short
immediate
1
0
1
1
1
1
† These instructions are not included in the TMS320C1x instruction set.
12
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0
1
5
4
3
K
0
1
0
1
0
D
K
0
0
0
1
R
D
DP
0
1
R
1
6
I
R
1
7
1
0
0
0
0
I
D
I
D
K
0
0
0
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 2. TMS320P25 Instruction Set Summary (Continued)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
DESCRIPTION
INSTRUCTION BIT CODE
NO.
NO
WORDS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
1
0
1
APAC
Add P register to accumulator
1
1
1
0
0
1
1
1
0
0
LPH†
Load high P register
1
0
1
0
1
0
0
1
1
I
D
LT
Load T register
1
0
0
1
1
1
1
0
0
I
D
LTA
Load T register and accumulate previous
product
1
0
0
1
1
1
1
0
1
I
D
LTD
Load T register, accumulate previous
product, and move data
1
0
0
1
1
1
1
1
1
I
D
LTP†
Load T register and store P register in
accumulator
1
0
0
1
1
1
1
1
0
I
D
LTS†
Load T register and subtract previous
product
1
0
1
0
1
1
0
1
1
I
D
MAC†
Multiply and accumulate
2
0
1
0
1
1
1
0
1
I
D
MACD†
Multiply and accumulate with data move
2
0
1
0
1
1
1
0
0
I
D
MPY
Multiply (with T register, store product in P
register)
1
0
0
1
1
1
0
0
0
I
D
MPYA
Multiply and accumulate previous product
1
0
0
1
1
1
0
1
0
I
D
MPYK
Multiply immediate
1
1
0
1
MPYS
Multiply and subtract previous product
1
0
0
1
1
1
0
1
1
I
D
MPYU
Multiply unsigned
1
1
1
0
0
1
1
1
1
I
D
PAC
Load accumulator with P register
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
SPAC
Subtract P register from accumulator
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
1
0
SPH
Store high P register
1
0
1
1
1
1
1
0
1
I
SPL
Store low P register
1
0
1
1
1
1
1
0
0
I
SPM†
Set P register output shift mode
1
1
1
0
0
1
1
1
0
0
0
PM
SQRA†
Square and accumulate
1
0
0
1
1
1
0
0
1
I
D
0
1
0
1
1
0
1
0
I
D
SQRS†
Square and subtract previous product
1
† These instructions are not included in the TMS320C1x instruction set.
POST OFFICE BOX 1443
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13
ADVANCE INFORMATION
MNEMONIC
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 2. TMS320P25 Instruction Set Summary (Continued)
BRANCH/CALL INSTRUCTIONS
MNEMONIC
DESCRIPTION
NO
NO.
WORDS
INSTRUCTION BIT CODE
ADVANCE INFORMATION
15
14
13
12
11
10
9
8
7
B
Branch unconditionally
2
1
1
1
1
1
1
1
1
1
6
5
4
3
BACC†
Branch to address specified by
accumulator
1
1
1
0
0
1
1
1
0
0
BANZ
Branch on auxiliary register not zero
2
1
1
1
1
1
0
1
1
1
D
BBNZ†
Branch if TC bit ≠ 0
2
1
1
1
1
1
0
0
1
1
D
BBZ†
Branch if TC bit = 0
2
1
1
1
1
1
0
0
0
1
D
BC
Branch on carry
2
0
1
0
1
1
1
1
0
1
D
BGEZ
Branch if accumulator ≥ 0
2
1
1
1
1
0
1
0
0
1
D
BGZ
Branch if accumulator > 0
2
1
1
1
1
0
0
0
1
1
D
BIOZ
Branch on I/O status = 0
2
1
1
1
1
1
0
1
0
1
D
BLEZ
Branch if accumulator ≤ 0
2
1
1
1
1
0
0
1
0
1
D
BLZ
Branch if accumulator < 0
2
1
1
1
1
0
0
1
1
1
D
BNC
Branch on no carry
2
0
1
0
1
1
1
1
1
1
D
BNV†
Branch if no overflow
2
1
1
1
1
0
1
1
1
1
D
BNZ
Branch if accumulator ≠ 0
2
1
1
1
1
0
1
0
1
1
D
BV
Branch on overflow
2
1
1
1
1
0
0
0
0
1
D
BZ
Branch if accumulator = 0
2
1
1
1
1
0
1
1
0
1
D
CALA
Call subroutine indirect
1
1
1
0
0
1
1
1
0
0
CALL
Call subroutine
2
1
1
1
1
1
1
1
0
1
RET
Return from subroutine
1
1
1
0
0
1
1
1
0
0
2
1
0
1
0
1
1
0
0
D
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
4
3
2
1
0
1
1
FO
D
I/O AND DATA MEMORY OPERATIONS
MNEMONIC
DESCRIPTION
INSTRUCTION BIT CODE
NO
NO.
WORDS
15
14
13
12
11
10
9
8
7
6
5
BLKD†
Block move from data memory to data
memory
2
1
1
1
0
1
1
0
1
I
D
BLKP†
Block move from program memory to data
memory
2
1
1
1
1
1
1
0
0
I
D
DMOV
Data move in data memory
1
0
1
0
1
0
1
1
0
I
FORT†
Format serial port registers
1
1
1
0
0
1
1
1
0
0
IN
Input data from port
1
1
0
0
0
PA
I
D
OUT
Output data to port
1
1
1
1
0
PA
I
D
RFSM
Reset serial port frame synchronization
mode
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
0
RTXM†
Reset serial port transmit mode
1
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
RXF†
Reset external flag
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
0
SFSM
Set serial port frame synchronization
mode
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
STXM
Set serial port transmit mode
1
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
1
SXF†
Set external flag
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
1
TBLR
Table read
1
0
1
0
1
1
0
0
0
I
D
TBLW
Table write
1
0
† These instructions are not included in the TMS320C1x instruction set.
1
0
1
1
0
0
1
I
D
14
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 2. TMS320P25 Instruction Set Summary (Continued)
CONTROL INSTRUCTIONS
DESCRIPTION
INSTRUCTION BIT CODE
NO
NO.
WORDS
15
14
13
12
11
10
9
BIT†
Test bit
1
1
0
0
1
BITT†
Test bit specified by T register
1
0
1
0
1
0
1
1
CNFD†
Configure block as data memory
1
1
1
0
0
1
1
CNFP†
Configure block as program memory
1
1
1
0
0
1
DINT
Disable interrupt
1
1
1
0
0
EINT
Enable interrupt
1
1
1
0
0
IDLE†
Idle until interrupt
1
1
1
0
LST
Load status register STO
1
0
1
LST1†
Load status register ST1
1
0
1
NOP
No operation
1
0
POP
Pop top of stack to low accumulator
1
POPD†
Pop top of stack to data memory
1
PSHD†
Push data memory value onto stack
PUSH
RC
8
7
6
5
4
3
2
1
0
I
D
1
I
D
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
I
0
1
0
0
0
1
I
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
0
1
1
1
1
0
1
0
I
D
1
0
1
0
1
0
1
0
0
I
D
Push low accumulator onto stack
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
Reset carry bit
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
RHM
Reset hold mode
1
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
0
ROVM
Reset overflow mode
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
0
RPT†
Repeat instruction as specified by data
memory value
1
0
1
0
0
1
0
1
1
I
RPTK†
Repeat instruction as specified by
immediate value
1
1
1
0
0
1
0
1
1
RSXM†
Reset sign-extension mode
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
RTC
Reset test / control flag
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
SC
Set carry bit
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
SHM
Set hold mode
1
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
1
SOVM
Set overflow mode
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
1
SST
Store status register ST0
1
0
1
1
1
1
0
0
0
I
D
SST1†
Store status register ST1
1
0
1
1
1
1
0
0
1
I
D
SSXM†
Set sign-extension mode
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
STC
Set test / control flag
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
TRAP†
Software interrupt
1
† These instructions are not included in the TMS320C1x instruction set.
POST OFFICE BOX 1443
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15
ADVANCE INFORMATION
MNEMONIC
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
VSS
ADVANCE INFORMATION
VIH
Supply voltage
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Supply voltage
0
Hi h l
l input
i
t voltage
lt
High-level
V
All inputs except
CLKIN / CLKX / CLKR / INT0 – INT2
2.35
VCC + 0.3
CLKIN / CLKX / CLKR
3.65
VCC + 0.3
VCC + 0.3
INT0 – INT2
2.5
V
All inputs except MP / MC
– 0.3
0.8
V
MP / MC
– 0.3
0.8
V
VIL
Low level input voltage
Low-level
IOH
IOL
High-level output current
300
µA
Low-level output current
2
mA
TA
Operating free-air temperature
70
°C
0
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
VOH
VOL
High-level output voltage
Three-state current
VCC = MIN, IOH = MAX
VCC = MIN, IOL = MAX
VCC = MAX
IZ
II
Input current
VI = VSS to VCC
Low-level output voltage
ICC
Supply current
Ci
Input capacitance
Normal
IDLE, HOLD
TA = 0°C,
0°C
VCC = MAX,
MAX
MIN
2.4
TYP§
3
0.3
fx = MAX
MAX
UNIT
V
0.6
V
– 20
20
µA
– 10
10
µA
110
185
mA
50
100
mA
15
pF
Co
Output capacitance
15
pF
‡ For test conditions shown as MIN / MAX, use the appropriate value listed in the recommended operating conditions or the internal clock option
table.
§ All typical values are at VCC = 5 V, TA = 25°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either
V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
CLOCK CHARACTERISTICS AND TIMING
The TMS320P25 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2 / CLKIN (see Figure 2). The
frequency of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be fundamental
mode and parallel resonant with an effective series resistance of 30 Ω, a power dissipation of 1 mW, and be
specified at a load capacitance of 20 pF.
fx
fxs
TEST CONDITIONS
MIN
TA = 0°C to 70°C
TA = 0°C to 70°C
6.7
0†
Input clock frequency
Serial port frequency
NOM†
MAX
UNIT
40.96
MHz
5.12
MHz
C1, C2
Load capacitance
TA = 0°C to 70°C
10
pF
† The serial port is tested at a minimum frequency of 1.25 MHz. However, the serial port is fully static and properly functions down to a clock rate
of fsx = 0 Hz.
X1
X2/CLKIN
Crystal
C1
C2
Figure 2. Internal Clock Option
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics for external clock option (see Note 2)
PARAMETER
MIN
MAX
UNIT
97.7
TYP
597
ns
5
30
ns
Fall time, CLKOUT1/CLKOUT2/STRB
5
ns
Rise time, CLKOUT1/CLKOUT2/STRB
5
ns
tc(C)
td(CIH-C)
Cycle time, CLKOUT1/CLKOUT2
tf(C)
tr(C)
tw(CL)
tw(CH)
Pulse duration, CLKOUT1/CLKOUT2 low
2Q – 8
2Q
2Q + 8
ns
Pulse duration, CLKOUT1/CLKOUT2 high
2Q – 8
2Q
2Q + 8
ns
Q–8
Q
Q+2
ns
td(C1-C2)
Delay time, CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
Delay time, CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high,
etc.
NOTE 2: Q = 1/4tc(C)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
ADVANCE INFORMATION
recommended operating conditions for internal clock option
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
timing requirements for external clock option (see Note 2)
MIN
MAX
UNIT
ns
Fall time, CLKIN
150
5†
Rise time, CLKIN
5†
ns
tc(CI)
tf(CI)
Cycle time, CLKIN
24.4
tr(CI)
tw(CIL)
Pulse duration, CLKIN low, tc(CI) = 50 ns (see Note 3)
20
tw(CIH)
tsu(S)
Pulse duration, CLKIN high, tc(CI) = 50 ns (see Note 3)
20
Setup time, SYNC before CLKIN low
5
th(S)
Hold time, SYNC from CLKIN low
† Value is derived from characterization data and not tested.
NOTES: 2. Q = 1/4tc(C)
3. CLKIN duty cycle [tr(CI) + tw(CIH)] / tc(CI) must be within 40-60%.
5V
TMS320P25
ns
ns
ns
Q–8
8
ns
ns
fcrystal
ADVANCE INFORMATION
10 kΩ
74HC04
4.7 kΩ
F11
CLKIN
47 pF
C = 20 pF
74AS04
0.1 µF
10 kΩ
L
TMS320P25
fcrystal (MHz)
L (µH)
40.96
1.8
Figure 3. External Clock Option
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions (see Note 2)
td(C1-S)
td(C2-S)
Delay time, STRB from CLKOUT1 (if STRB is present)
td(MSC)
Delay time, MSC valid from CLKOUT1
tdis(D)
Disable time, data bus in the high-impedance state after STRB high
(write cycle)
ten(D)
Enable time, data bus starts being driven after STRB low
(write cycle)
th(A)
th(D)W
MIN
TYP
Q–6
Q
Delay time, CLKOUT2 to STRB (if STRB is present)
–6
– 12
0
Q
MAX
Q+6
ns
6
ns
12
ns
Q + 15†
0†
Hold time, address after STRB high (see Note 4)
ns
Q – 10
Q
ns
tw(SL)
tw(SH)
Pulse duration, STRB low (no wait states, see Note 5)
2Q – 5
2Q + 5†
Pulse duration, STRB high (between consecutive cycles, see Note 5)
2Q – 5
2Q + 5
tsu(A)
Setup time, address before STRB low (see Note 4)
Q – 12
tsu(D)W
time data write before STRB high (no wait states)
Setup time,
TMS320P25FN
2Q – 20
TMS320P25PH
2Q – 23
ns
ns
Q–8
Hold time, data write from STRB high
UNIT
ns
ns
ns
ns
† Value is derived from characterization data and not tested.
NOTES: 2. Q = 1/4tc(C)
4. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
5. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with
no wait states.
timing requirements over recommended operating conditions (see Note 2)
MIN
ta(A)
Access time, read data from address time (read cycle, see Notes 4 and 6)
td(SL-R)
d(SL R)
Dela time,
Delay
time READY valid
alid after STRB low
lo (no wait
ait states)
td(C2H-R)
td(M-R)
Delay time, READY valid after CLKOUT2 high
th(D)R
th(SL-R)
Hold time, data read from STRB high
th(C2H-R)
th(M-R)
MAX
UNIT
3Q – 35
ns
TMS320P25FN
Q – 20
TMS320P25PH
Q – 22
Delay time, READY valid after MSC valid
ns
Q – 20
ns
2Q – 25
ns
0
ns
Hold time, READY after STRB low (no wait states)
Q+3
ns
Hold time, READY after CLKOUT2 high
Q+3
ns
0
ns
23
ns
Hold time, READY after MSC valid
tsu(D)R
Setup time, data read before STRB high
† Value is derived from characterization data and not tested.
NOTES: 2. Q = 1/4tc(C)
4. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
6. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
ADVANCE INFORMATION
PARAMETER
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
RS, INT, BIO, AND XF TIMING
switching characteristics over recommended operating conditions (see Notes 2 and 7)
PARAMETER
td(RS)
td(IACK)
MIN
TYP
MAX
22†
–6
0
12
Delay time, CLKOUT1 low to reset state entered
Delay time, CLKOUT1 to IACK valid
UNIT
ns
ns
td(XF)
Delay time, XF valid before falling edge of STRB
Q – 15
ns
NOTES: 2. Q = 1/4tc(C)
7. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagrams occurs.
timing requirements over recommended operating conditions (see Note 7)
MIN
ADVANCE INFORMATION
tsu(IN)
th(IN)
Setup time, INT/BIO/RS before CLKOUT1 high
tf(IN)
tw(IN)
Fall time, INT/BIO
MAX
32
Hold time, INT/BIO/RS after CLKOUT1 high
UNIT
ns
0
ns
8†
ns
Pulse duration, INT/BIO low
tc(C)
ns
tw(RS)
Pulse duration, RS low
3tc(C)
ns
† Value is derived from characterization data and not tested.
NOTE 7: RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,
the exact sequence shown in the timing diagrams occurs.
HOLD TIMING
switching characteristics over recommended operating conditions
td(C1L-AL)
td(HH-AH)
PARAMETER
MIN
Delay time, HOLDA low after CLKOUT1 low
0
TYP
Delay time, HOLD high to HOLDA high
MAX
ns
25
ns
0†
tdis(AL-A)
Disable time, HOLDA low to address 3-state
tdis(C1L-A)
Disable time, address in the high-impedance state after CLKOUT1 low (HOLD mode,
see Note 8)
ten(A-C1L)
Enable time, address driven before CLKOUT1 low (HOLD mode, see Note 8)
† Value is derived from characterization data and not tested.
NOTE 8: A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as address.
UNIT
10
ns
20†
ns
8†
ns
timing requirements over recommended operating conditions (see Note 2)
MIN
td(C2H-H) Delay time, HOLD valid after CLKOUT2 high
NOTE 2: Q = 1/4tc(C)
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MAX
UNIT
Q – 24
ns
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
SERIAL PORT TIMING
switching characteristics over recommended operating conditions
PARAMETER
MIN
MAX
UNIT
td(CH-DX)
Delay time, DX valid after CLKX rising edge (see Note 9)
75
ns
td(FL-DX)
Delay time, DX valid after FSX falling edge (TXM = 0, see Note 9)
40
ns
40
ns
td(CH-FS)
Delay time, FSX valid after CLKX rising edge (TXM = 1)
NOTE 9: The last occurrence of FSX falling and CLKX rising
timing requirements over recommended operating conditions
MAX
200
UNIT
Cycle time, serial port clock (CLKX/CLKR)
tr(SCK)
tw(SCK)
Rise time, serial port clock (CLKX/CLKR)
Pulse duration, serial port clock (CLKX/CLKR) low (see Note 10)
80
ns
tw(SCK)
tsu(FS)
Pulse duration, serial port clock (CLKX/CLKR) high (see Note 10)
80
ns
Setup time, FSX/FSR before CLKX/CLKR falling edge (TXM = 0)
18
ns
th(FS)
tsu(DR)
Hold time, FSX/FSR after CLKX/CLKR falling edge (TXM = 0)
20
ns
Setup time, DR before CLKR falling edge
10
ns
20
ns
th(DR)
Hold time, DR after CLKR falling edge
† Value is derived from characterization data and not tested.
NOTE 10: The duty cycle of the serial port clock must be within 40 – 60%.
POST OFFICE BOX 1443
ns
25†
25†
Fall time, serial port clock (CLKX/CLKR)
• HOUSTON, TEXAS 77251–1443
ns
ns
ADVANCE INFORMATION
MIN
tc(SCK)
tf(SCK)
21
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
2.15 V
RL = 825 Ω
From Output
Under Test
Test
Point
CL = 100 pF
Figure 4. Test Load Circuit
ADVANCE INFORMATION
2V
VIH (min)
1.88 V
0.92 V
VIL (max)
0.8 V
0
(a) INPUT
2.4 V
VOH (min)
2.2 V
0.8 V
VOL (max)
0.6 V
0
(b) OUTPUT
NOTE A. Timing measurements are referenced to and from a low voltage
of 0.8 V and a high voltage of 2 V, unless otherwise noted.
Figure 5. Voltage Reference Levels
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
tc(CI)
tf(CI)
tr(CI)
X2 / CLKIN
tw(CIH )
th(S)
tsu(S)
tw(CIL )
tsu(S)
SYNC
tc(C)
tw(CL )
td(CIH-C)
td(CIH-C)
CLKOUT1
tr(C)
td(CIH-C)
ADVANCE INFORMATION
tw(CH )
tf(C)
STRB
td(CIH-C)
tc(C)
tw(CL )
CLKOUT2
td(C1-C2)
td(C1-C2)
td(C1-C2)
tf(C)
tr(C)
tw(CH )
td(C1-C2)
Figure 6. Clock Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
td(C1-S)
CLKOUT1
td(C1-S)
CLKOUT2
td(C2-S)
td(C2-S)
STRB
tw(SH )
tsu( A )
th( A )
ADVANCE INFORMATION
tw(SL )
A15 – A0,
BR, PS, DS,
or IS
Valid
ta( A )
R/W
td(SL-R)
tsu(D)R
READY
th(SL-R)
th(D)R
Data In
D15 – D0
Figure 7. Memory-Read-Cycle Timing
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
th( A )
tsu( A )
A15 – A0,
BR, PS, DS,
or IS
ADVANCE INFORMATION
Valid
R/W
READY
tsu(D)W
D15 – D0
th(D)W
Data Out
ten(D)
tdis(D)
Figure 8. Memory-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
th(C2H-R)
A15 – A0, BR,
PS, DS, R / W,
or IS
Valid
td(C2H-R)
th(C2H-R)
td(C2H-R)
ADVANCE INFORMATION
READY
td(M-R)
D15 – D0
(for read
operation)
th(M-R)
th(M-R)
td(M-R)
Data In
D15 – D0
(for write
operation)
Data Out
td(MSC)
td(MSC)
MSC
Figure 9. One-Wait-State Memory-Access-Cycle Timing
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
tsu(IN)
td(RS)
tsu(IN)
th(IN)
RS
tw(RS)
A15 – A0
Valid
Fetch
Location 0
D15 – D0
PS
Begin
Program
Execution
ADVANCE INFORMATION
Valid
STRB
Control
Signals†
IACK
Serial Port
Control‡
† Control signals are DS, IS, R / W, and XF.
‡ Serial port controls are DX and FSX.
Figure 10. Reset Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
STRB
tsu(IN)
th(IN)
tw(IN)
INT2 – INT0
td(IACK )
tf(IN)
A15 – A0
FETCH N
FETCH N + 1
FETCH I
FETCH I + 1
td(IACK )
ADVANCE INFORMATION
IACK
Figure 11. Interrupt Timing
tc(SCK )
tr(SCK )
tw(SCK )
CLKR
th(DR)
tf(SCK )
th(FS)
tw(SCK )
FSR
tsu(FS)
tsu(DR)
DR
Figure 12. Serial-Port Receive Timing
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
tc(SCK )
tr(SCK )
tw(SCK )
CLKX
td(CH-DX )
tf(SCK )
tw(SCK )
th(FS)
FSX
(input,
TXM = 0)
tsu(FS)
td(CH-DX )
td(FL-DX )
N=1
DX
N = 8, 16
ADVANCE INFORMATION
td(CH-FS)
td(CH-FS)
FSX
(output,
TXM = 1)
Figure 13. Serial-Port Transmit Timing
CLKOUT1
STRB
Fetch Branch Address
Fetch Next Instruction
Fetch
BIOZ
A15 – A0
PC = N
PC = N + 1
PC = N + 2
PC = N + 3
or Branch Address
tsu(IN)
th(IN)
BIO
Valid
Figure 14. BIO Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
STRB
td( XF )
A15 – A0
Valid
Fetch
SXF/ RXF
Valid
Valid
PC = N – 1
PC = N
PC = N + 1
PC = N + 2
Valid
XF
Figure 15. External Flag Timing
ADVANCE INFORMATION
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
td(C2H-H )†
HOLD
N
N+1
PS, DS,
or IS
Valid
Valid
N+2
ADVANCE INFORMATION
A15 – A0
R/W
tdis(C1L-A )
D15 – D0
In
In
tdis( AL-A )
HOLDA
td(C1L-AL )
FETCH
N
N+1
N/A
N/A
N–1
N
Dummy
Dead
EXECUTE
† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence
shown occurs; otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 16. HOLD Timing (Part A )
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
ten( A-C1L )
STRB
td(C2H-H )†
HOLD
Valid
ADVANCE INFORMATION
A15 – A0
Valid
PS, DS,
or IS
In
R/W
In
td( HH-AH )
D15 – D0
N+2
HOLDA
FETCH
N/A
N /A
N+2
N+3
N+3
Dead
Dead
N+1
N+2
EXECUTE
† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence
shown occurs; otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 17. HOLD Timing (Part B)
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
programming the TMS320P25 EPROM cell
The TMS320P25 incorporates a one-time programmable (OTP) 4K × 16-bit EPROM, which is implemented from
a standard TMS27C128 EPROM cell. This expands the capabilities of the TMS320P25 in the areas of
prototyping, early field testing, and production.
A key feature of the EPROM cell is its use of standard programming techniques with verification capability of
all bits. The EPROM cell has an internal security mechanism that prevents all proprietary data from being read
and thereby protects privileged information against possible copyright violations. An adapter socket (e.g., part
number TMDX3270120 for FN package) provides the 68-lead to 28-lead or 80-lead to 28-lead conversion that
is necessary when programming the TMS320P25.
using the EPROM-programmer-adapter socket
Figure 18 shows an example of a PLCC-type adapter socket for the device and the portion that plugs into the
EPROM programmer.
TMS320P25 Device Plugs
Into This Socket
Plugs Into an EPROM Programmer or
the R-Bit Programmer
Figure 18. An Example of an EPROM-Programmer Adapter Socket
supplying external power
The adapter socket has two sets of jumpers that indicate whether the power supply is internal (from the EPROM
programmer) or external. The adapter socket is shipped from the factory with the jumpers at the internal power
setting. In some cases, the EPROM programmer cannot supply the VCC power needs of the TMS320P25
device, so it becomes necessary to supply external VCC. The following conditions determine whether external
power is needed:
•
•
The TMS320P25’s clock must be disabled during programming. Because the device uses dynamic logic
for much of its internal circuitry, the ICC requirements for VCC are significantly greater than a typical
’27C128-type EPROM. As a result, many EPROM programmers sense this condition and erroneously
indicate that the chip is plugged in backwards. To prevent this from occurring, a jumper connection and test
point are available for an external 5-V logic supply. This effectively bypasses the EPROM programmer’s ICC
test and allows the device to be programmed.
Additionally, a jumper and test point are available for the VPP supply. The VPP signal is a pulsed signal and
fully complies with the standards for a ’27C128 EPROM device. This option is never needed, and the
jumpers should be left in the internal position at all times.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
ADVANCE INFORMATION
Most EPROM programmers have a 28-lead DIP-type socket for use with EPROM devices such as the
TMS27C128. In order to use this type of programmer to program the EPROM of a TMS320 device, you must
use a special adapter that converts the programmer socket into a socket that can accept a TMS320 device.
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
supplying external power (continued)
To supply external VCC:
•
•
Find the jumper nearest the VCC terminal on the adapter socket and move the jumper so that it is over the
EXT and center terminals.
Connect the external VCC to the terminal labeled VCC.
Figure 19 shows the jumper-setting placement for internal and external power. The VCC and VPP terminals are
also shown.
VCC Setting
VPP Setting
ADVANCE INFORMATION
VCC
VPP
EXT
EXT
INT
INT
Figure 19. VCC and VPP Jumper Settings for External Power
CAUTION:
Whenever supplying an external VCC, you must connect a common ground lead between the
power supply and the programmer adapter.
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
programming and verification
The TMS320P25, like the TMS27C128, requires a 5-V supply for reading and a 12.5-V supply for programming.
All programming signals are TTL-level signals. Locations can be systematically or randomly programmed as
a single or blocked address. Unlike some EPROM cells that can require the high byte before the low byte, each
byte of data must be loaded into the TMS320P25 EPROM cell with the low byte preceding the high byte (see
Figure 20). To avoid memorization of the proper order, an inverter is placed in the circuit of Figure 21 and
performs the necessary byte reversal for the TMS320P25.
0(0000h)
1(0001h)
2(0002h)
3(0003h
.
.
.
4095(0FFFh)
1234h
5678h
9ABCh
DEF0h
.
.
.
TMS320P25 On-Chip
Program Memory
(byte format)
0(0000h)
1(0001h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)
.
.
.
34h
12h
78
56
BCh
9Ah
F0h
DEh
.
.
.
EPROM-Programmer
Memory
Byte Format With
Adapter Socket
0(0000h)
1(0001h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)
.
.
.
8191(1FFFh)
12h
34h
56h
78h
9Ah
BCh
DEh
F0h
.
.
.
Figure 20. EPROM-Programming Data Format
Figure 21 shows the wiring diagram when the TMS320P25 is programmed with the TMS27C128 in its 28-lead
output form for the FN package. The illustration furnishes a table for each pin nomenclature on the TMS27C128
with a description of that terminal. Programming the code into the device should be done in the serial mode.
CAUTION:
Although acceptable by some EPROM programmers, the signature mode cannot be used on
the TMS320P25 device. The signature mode will input a high-level voltage (12.5 VDC) onto
pin A9. Because the TMS320P25 EPROM cell is not designed for high voltage, the cell will
be damaged in this mode. To prevent an accidental application of voltage, TI has inserted
a 3.9-kΩ resistor between A9 of the TI programmer socket and the programmer itself.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
ADVANCE INFORMATION
TMS320P25 On-Chip
Program Memory
(word format)
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
11 D7
12 D6
EPT 26
A8 25
59
58
13 D5
57
14 D4
56
15 D3
A9 24
A11 23
55
TMS320P25
68 Pin
( FN )
16 D2
17 D1
22
18 D0
A10 21
54
53
CLKIN 52
19
51
A12(MSB) – A0 (LSB)
CLKIN
E
EPT
G
GND
PGM
Q8(MSB) – Q1(LSB)
RS
VCC
VPP
I
I
I
I
I
I
I
I/O
I
I
I
42 G
40 A12
41 PGM
39 A11
W
4
5
6
7
8
A6
A5
A4
A3
A2
Q3 13
GND 14
2
3
A12
A7
Q2 12
1
V PP
TMS27C128
I/O
45
44
3.9 k
8
SIGNALS
38 A10
46
Q1 11
27
25
26
47
A1 9
A0 10
Q4 15
29 A2
30 A3
24
36 A8
37 A9
Q5 16
48
35 V CC
23
33 A6
34 A7
22 E
Q6 17
50
49
VPP
A0
VSS
A1
32 A5
Q8 19
Q7 18
EPT
28
ADVANCE INFORMATION
20
21
31 A4
E 20
61
62
64
63
60
43
VCC 28
PGM 27
66
RS 65
1
68
67
3
2
4
5
7
6
10
TMS27C128
G
8
9
programming and verification (continued)
DEFINITION
On-chip EPROM programming address lines
Clock oscillator input
EPROM chip select
EPROM test mode select
EPROM read/verify select
Ground
EPROM write/program select
Data lines for byte-wide programming of on-chip 8K bytes of EPROM
Reset for initializing the device
5-V power supply
12.5-V power supply
Figure 21. TMS320P25 EPROM Conversion to TMS27C128 EPROM Pinout Example Using FN Package
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
programming and verification (continued)
Table 3 shows the programming levels that are required when programming, verifying, and reading the EPROM
cell. Following Table 3 are individual descriptions of each programming level.
PROGRAMMING
OPERATION
SIGNAL
NORMAL
OPERATION
SIGNAL
E
TMS320P25
TERMINAL
TMS27C128
TERMINAL
FN
PKG
PH
PKG
INT2
22
37
20
PROGRAM
PROGRAM
VERIFY
READ
EPROM
PROTECT
PROTECT
VERIFY
VIL
PULSE
VIL
PULSE
VIH
VIH
VIL
VIL
G
A14
42
61
22
PGM
A13
41
60
27
VPP
VCC
FSR
25
40
1
VIL
VIH
PULSE
VCC
61,35
38, 52
28
VPP
VIH
VPP
VIH
VCC
VIH
VPP
VIH
VCC + 1
VSS
VSS
27,44,
10
24, 42,
64
14
VCC + 1
VCC + 1
VCC
VCC + 1
VCC + 1
CLKIN
X2 / CLKIN
52
72
14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RS
RS
65
8
14
VSS
VSS
EPT
DR
24
39
26
VSS
VSS
VSS
VSS
VSS
Q8 – Q1
D7 – D0
11–18
25 – 30,
32, 33
19 –15,
13 –11
VSS
VSS
VSS
VPP
VPP
A12 – A7
A12 – A10
40 – 36,
34
59,
57 – 54,
51
2, 23, 21,
24, 25, 3
DIN
QOUT
QOUT
Q8 =
PULSE
Q8 = RBIT
A6
A6
33
50
4
ADDR
ADDR
ADDR
X
A5
A5
32
48
5
ADDR
ADDR
ADDR
X
VIL
X
A4
A4
31
47
6
ADDR
ADDR
ADDR
VIH
X
A3 – A0
30 – 28,
26
46 – 44,
41
7–10
ADDR
ADDR
ADDR
X
X
A3 – A0
Legend:
ADDR
DIN
PULSE
QOUT
RBIT
VPP
VCC + 1
X
=
=
=
=
=
=
=
=
Byte-address bit
Byte to be programmed at ADDR
Low-going TTL pulse
Byte stored at ADDR
ROM-protect bit
12.5 V ± 0.25 V (Fast) or 13 V ± 0.25 V (SNAP! Pulse)
6 V ± 0.25 V (Fast) or 6.5 V ± 0.25 V (SNAP! Pulse)
Don’t care
erasure
The TMS320P25 comes with 4K words of EPROM cells set to a logic 1 and ready to be programmed. Because
of the type of packaging offered for the TMS320P25, the EPROM is only one-time programmable.
Fast programming
Logic 0s must be programmed into their locations. The Fast programming algorithm, illustrated in Figure 22,
is normally used to program the entire EPROM contents, although individual locations can be programmed
separately. Data is presented in parallel (eight bits) from terminals D7– D0 of the TMS320P25 to terminals
Q8 – Q1 of the TMS27C128. Once addresses and data are stable, PGM is pulsed. The programming mode is
achieved when VPP = 12.5 V, PGM = VIL, VCC = 6.0 V, G = VIH, and E = VIL. More than one TMS320P25 can
be programmed simultaneously by connecting the devices in parallel with each other. Locations can be
programmed in any order.
POST OFFICE BOX 1443
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37
ADVANCE INFORMATION
Table 3. TMS320P25 Programming-Mode Levels
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Fast programming (continued)
Fast programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1-ms;
this pulse is applied X times. After each prime pulse, the byte being programmed is verified. If correct data is
read, the final programming pulse is applied; if correct data is not read, an additional 1-ms prime pulse is applied
up to a maximum of 25 times. The final programming pulse is 3X long. This sequence of programming and
verifying is performed at VCC = 6 V, and VPP = 12.5 V. When the full Fast programming routine has been
completed, all bits are verified with VCC = VPP = 5 V.
Start
Address = First Location
VCC = 6 ± 0.25 V
VPP = 12.5 V ± 0.25 V
ADVANCE INFORMATION
X=0
Program One
1-ms Pulse
Increment X
No
Yes
Fail
X = 25
Verify
One Byte
Pass
Program One
Pulse of 3X-ms
Duration
Device
Failed
Last
Address?
No
Increment
Address
Yes
VCC = VPP = 5 V ± 0.25 V
Fail
Compare
All Bytes to
Original Data
Pass
Device
Passed
Figure 22. Fast Programming Flowchart
38
POST OFFICE BOX 1443
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TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
SNAP! Pulse programming
The EPROM can be programmed by using the TI SNAP! Pulse programming algorithm illustrated in Figure 23.
Programming time is greatly reduced to a nominal duration of one second. Actual programming time varies as
a function of the programmer that is being used. Data is presented in parallel (eight bits) on terminals Q8 – Q1.
Once addresses and data are stable, PGM is pulsed.
The SNAP! Pulse programming algorithm uses pulses of 100 µs followed by a byte verification to determine if
the addressed byte has been successfully programmed. Up to ten 100 µs pulses per byte are verified before
a failure is recognized.
The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, and G = VIH, and E = VIL. More than one
TMS320P25 can be programmed simultaneously by connecting the devices in parallel with each other.
Locations can be programmed in any order. When the SNAP! Pulse programming routine has been completed,
all bits are verified with VCC = VPP = 5 V.
Start
VCC = 6.5 V, VPP = 13 V
Program
Mode
Program One Pulse = tw = 100 µs
Last
Address?
ADVANCE INFORMATION
Address = First Location
Increment Address
No
Yes
Address = First Location
X=0
Program One Pulse = tw = 100 µs
No
Verify
One Byte
Increment
Address
Fail
X=X+1
X = 10?
Yes
Pass
No
Interactive
Mode
Last
Address?
Yes
VCC = VPP = 5 V ± 10%
Compare
All Bytes to
Original
Data
Device Failed
Final
Verification
Fail
Pass
Device
Passed
Figure 23. SNAP! Pulse Programming Flowchart
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
program verify
Programmed bits can be verified with VPP = 12.5 V when G = VIL, E = VIL, and PGM = VIH. Figure 24 shows
the timing of the program and verification operations for both Fast and SNAP! Pulse programming.
Program
Verify
VIH
A12 – A0
Q8 – Q1
Address Stable
Data In Stable
Hi-Z
Address N+1
Data Out Valid
VIL
VIH / VOH
VIL / VOL
VPP
VPP
VCC
VCC + 1
VCC
VCC
ADVANCE INFORMATION
VIH
E
VIL
VIH
PGM
VIL
VIH
G
VIL
Figure 24. Programming Timing
program inhibit
Programming can be inhibited by maintaining a high-level input on E or PGM.
read
The EPROM contents can be read outside of the programming cycle if the RBIT (ROM-protect bit) has not been
programmed. The read mode is accomplished by setting E to zero and pulsing G low. The contents of the
EPROM location, selected by the value on the address inputs, appear on D7– D0.
output disable
During the EPROM programming process, the EPROM data outputs can be disabled, if desired, by setting the
output-disable mode. Depending upon the application, the output-disable mode can be selected by setting
either G or E on the TMS320P25 high. The selection of the terminal determines the duration for which the outputs
Q8 – Q1 of the TMS27C128 are in the high-impedance state. During this mode, D7– D0 on the TMS320P25 are
in the high-impedance state.
EPROM protection and verification
An internal mechanism protects the customer’s code from being illegally copied by competitors. Table 4 shows
the programming levels required for protecting the EPROM contents and verifying that protection. Following the
table, individual functions of the protect and verify modes are described.
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
Table 4. TMS320P25 EPROM-Protect and Protect-Verify Mode Levels
PROGRAMMING
OPERATION
SIGNAL
NORMAL
OPERATION
SIGNAL
FN PKG
PH PKG
TMS27C128
TERMINAL
EPROM
PROTECT
PROTECT
VERIFY
E
INT2
22
37
20
G
A14
42
61
22
VIH
VIH
VIL
VIL
PGM
A13
41
60
27
VPP
VCC
FSR
25
40
1
VCC
VSS
61,35
38, 52
28
VIH
VPP
VCC + 1
VIH
VCC + 1
VCC + 1
27,44,10
24, 42, 64
14
X2 / CLKIN
52
72
14
VSS
VSS
VSS
VSS
VSS
CLKIN
TMS320P25 TERMINAL
RS
65
8
14
DR
24
39
26
VSS
VPP
VSS
VPP
Q8 – Q1
D7 – D0
11–18
25 – 30, 32,
33
19 – 15,13 – 11
Q8 = PULSE
Q8 = RBIT
A12 – A10
A12 – A10
38
59, 57, 56
2, 23, 21
X
X
A9 – A7
A9 – A7
37, 36, 34
55, 54, 51
24, 25. 3
X
X
A6
A6
33
50
4
X
A5
A5
32
48
5
X
VIL
X
A4
A4
31
47
6
A3 – A0
A3 – A0
30 – 28,26
46 – 44, 41
7 – 10
VIH
X
Legend:
PULSE
RBIT
VCC + 1
VPP
X
=
=
=
=
=
ADVANCE INFORMATION
RS
EPT
X
X
Low-going TTL level pulse
ROM-protect bit
6 V ± 0.25 V (Fast) or 6.5 V ± 0.25 V (SNAP! Pulse)
12.5 V ± 0.25 V (Fast) or 13 V ± 0.25 V (SNAP! Pulse)
Don’t care
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
EPROM protection
The EPROM-protection mechanism is provided to prevent an intentional or accidental reading of the memory
contents, assuring security of all proprietary algorithms. This special feature is implemented by a unique
EPROM cell called the RBIT (ROM-protect bit) cell. Once the contents are programmed into the EPROM, the
RBIT can be programmed, preventing access to the EPROM contents and disabling the microprocessor mode.
Once programmed, the RBIT can be disabled only by erasing the entire EPROM array with ultraviolet light,
thereby maintaining security of all proprietary algorithms. Programming of the RBIT is accomplished by the
EPROM-protection cycle, which consists of setting E, G, PGM, and A4 to a high level, applying
12.5 V ± 0.25 V to both VPP and EPT, and pulsing Q8 to a low level. The complete sequence of operations is
shown in Figure 25.
Start
Program One
Pulse of 3X-ms
Duration
X=0
ADVANCE INFORMATION
EPROMProtect
Setup
ProtectVerify
Setup
Program One
1-ms Pulse
Device
Failed
Fail
Verify
RBIT
X=X+1
X = 25?
Yes
No
ProtectVerify
Setup
Fail
Verify
RBIT
Pass
EPROMProtect
Setup
Figure 25. EPROM-Protection Flowchart
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Pass
Device
Passed
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
how the RBIT works
When enabled, the RBIT disconnects the internal program-memory bus (PBUS) from the multiplexer that
combines it with the internal data bus (DBUS) to create the external program/data bus. For the TMS320P25,
the internal nodes are left floating. Figure 26 shows a portion of the TMS320P25 block diagram and includes
the RBIT to show how it disconnects the external and internal program spaces.
Program Bus
External
Program/
Data Bus
MUX
RBIT
cell
Data Bus
PREG
16 × 16
Multiplier
TREG
Figure 26. How the RBIT Fits into the TMS320P25 Block Diagram
Programming the RBIT has some side effects that can, at first, give the appearance that the device is not
operating properly. However, because enabling the RBIT protects the EPROM space, this is normal operation.
These side effects include:
•
Instructions. Some instructions that use the external program space for storage will not operate in the
same manner when the RBIT is set.
For example, TBLW, BLKP, and similar commands may seem to work when used to transfer external
program memory to the internal data space connected to DBUS. However, a transfer from the internal
program space to the external bus will not work. This happens because the RBIT feature is protecting this
memory space.
Similarly, the MAC instruction cannot read tables stored in external program space. In this case, the data
and program must be swapped, sacrificing one cycle per repeated instruction.
•
Invalid microprocessor mode. Microprocessor mode cannot be used after enabling the RBIT because
the PBUS is disconnected from the external program space.
protect verify
Following the EPROM-protect mode, the protect-verify mode reviews and verifies the programming of the RBIT
for accuracy. When using this mode, D7 outputs the state of the RBIT. When RBIT = 1, the EPROM is
unprotected; when RBIT = 0, the EPROM is protected. The EPROM protection and verification timings are
shown in Figure 27.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
ADVANCE INFORMATION
4K × 16
Program
EPROM
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
protect verify (continued)
Protect
Verify
VIH
A4
VIL
VPP
VPP
(see Note A)
VCC
VCC + 1
VCC
VCC
VIH
E
VIL
VIH
PGM
VIL
ADVANCE INFORMATION
VIH
G
VIL
Hi-Z
Hi-Z
Q8
Hi-Z
VIH / VOH
VIL / VOL
VPP
EPT
VSS
VIL
A6
VIH
NOTE B. VPP = 12.5 V and VCC = 6 V for Fast programming; for SNAP! Pulse programming, VPP = 13 V and VCC = 6.5 V.
Figure 27. EPROM-Protection Timing
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
MECHANICAL DATA
FN / S-PQCC-J**
PLASTIC J-LEADED CHIP CARRIER
20-PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57)
MAX
D
A1
D1
0.048 (1,22)
0.042 (1,07)
0.120 (3,05) MAX
45°
0.020 (0,51) MIN
3
1
19
0.037 (0,94)
0.023 (0,58)
4
18
E
E1
8
NO. OF
PINS**
D2 / E2
14
9
JEDEC
OUTLINE
ADVANCE INFORMATION
D2 / E2
13
0.050 (1,27) TYP
D/E
A1
D1 / E1
D2 / E2
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MS-018AA
20
0.062
(0,16)
0.083
(0,21)
0.385
(9,78)
0.395
(10,03)
0.350
(8,89)
0.356
(9,04)
0.141
(3,58)
0.169
(4,29)
MS-018AB
28
0.062
(0,16)
0.083
(0,21)
0.485
(12,32)
0.495
(12,57)
0.450
(11,43)
0.456
(11,58)
0.191
(4,85)
0.219
(5,56)
MS-018AC
44
0.062
(0,16)
0.083
(0,21)
0.685
(17,40)
0.695
(17,65)
0.650
(16,51)
0.656
(16,66)
0.291
(7,39)
0.319
(8,10)
MS-018AD
52
0.062
(0,16)
0.083
(0,21)
0.785
(19,94)
0.795
(20,19)
0.750
(19,05)
0.756
(19,20)
0.341
(8,66)
0.369
(9,37)
MS-018AE
68
0.062
(0,16)
0.083
(0,21)
0.985
(25,02)
0.995
(25,27)
0.950
(24,13)
0.956
(24,28)
0.441
(11,20)
0.469
(11,91)
MS-018AF
84
0.059
(0,15)
0.080
(0,20)
1.185
(30,10)
1.195
(30,35)
1.150
(29,21)
1.158
(29,41)
0.541
(13,74)
0.569
(14,45)
4040005 / A–10 / 93
NOTES: C. All linear dimensions are in inches (millimeters).
D. This drawing is subject to change without notice.
E. Falls within JEDEC MS-018
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
TMS320P25
DIGITAL SIGNAL PROCESSOR
SPRS028 – OCTOBER 1994
MECHANICAL DATA
PH/ R-PQFP-G80
PLASTIC QUAD FLATPACK
0,45
0,25
0,80 TYP
64
41
65
40
12,00 TYP
14,20
13,80
ADVANCE INFORMATION
80
18,00
17,20
25
1
24
18,40 TYP
20,20
19,80
0,15 TYP
2,70 TYP
24,00
23,20
0,10 MIN
Seating Plane
0,10
0°– 10°
1,00
0,60
3,10 MAX
4040011 / A–10 / 93
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TMS320P25FNA
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
TMS320P25FNL
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
TMS320P25PH
OBSOLETE
QFP
PH
80
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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