Si5316-EVB Si5319-EVB Si5322/23-EVB Si5324-EVB Si5325/26-EVB Si5327-EVB Si5316, Si5319, Si5322/23, Si5324, Si5325/26, AND Si5327 EVB U SER ’ S G UI DE 1. Introduction The Si5316-EVB, Si5319-EVB, Si5322/23-EVB, Si5324-EVB, Si5325/26-EVB, and Si5327-EVB provide platforms for evaluating Silicon Laboratories' Si5316, Si5319, Si5322/Si5323, Si5324, Si5325/Si5326, and Si5327 Any-Frequency Precision Clock Timing ICs. The Si5316, Si5322, and Si5323 are controlled directly using configuration pins on the devices, while the Si5319, Si5324, Si5325, Si5326, and Si5327 are controlled by a microprocessor or MCU (micro-controller unit) via an I2C or SPI interface. The Si5316 is a jitter attenuator with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5322 and Si5325 are low jitter clock multipliers with a loop bandwidth ranging from 30 kHz to 1.3 MHz. The Si5319, Si5323, and Si5326 are jitter-attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5324 and Si5327 have features and capabilities very similar to the Si5326, but they have much lower loop bandwidths that range from 4 to 525 Hz. The Si5326 device can optionally be configured to operate as a Si5325, so a single evaluation board is available to evaluate both devices. Likewise, the Si5323 can be configured to operate as a Si5322, so the two devices share a single evaluation board. The Si531x/2x Any-Frequency Precision Clocks are based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The devices have excellent phase noise and jitter performance. The Si5316 is a jitter attenuator that supports jitter generation of 0.3 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. The Si5319, Si5323, and Si5326 jitter attenuating clock multipliers support jitter generation of 0.3 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. The Si5324 and Si5327 are jitter attenuating clock multipliers supporting jitter attenuation of 0.3 ps RMS (typ) and 0.5 ps RMS (typ) across the 12 kHz to 20 MHz and 50 kHz to 80 MHz bands. The Si5322 and Si5325 support jitter generation of 0.6 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. For all devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and clock distribution in mid-range and high-performance timing applications. Figure 1. Si532x QFN EVB Rev. 0.6 1/12 Copyright © 2012 by Silicon Labs Si531x/2x-EVB Si531x-EVB Si532x-EVB 1 Si5319 1 1 Si5323 2 2 Si5324 2 2 Si5326 2 2 Si5327 2 2 Any-Frequency Precision Clock Multipliers 15 to 19 to 0.6 ps 30 kHz–1.3 MHz Y N LOS 707 1050 rms typ I2C or 10 to 10 to 0.6 ps 30 kHz–1.3 MHz Y N LOS, FOS SPI 710 1400 rms typ Any-Frequency Precision Clock Multipliers with Jitter Attenuation Pin 19 to 19 to 0.3 ps 60 Hz–8.4 kHz N N LOL, LOS 710 710 rms typ I2C or .002 to .002 to 0.3 ps 60 Hz–8.4 kHz Y N LOL, LOS SPI 710 1400 rms typ Pin .008 to .008 to 0.3 ps 60 Hz–8.4 kHz Y Y LOL, LOS 707 1050 rms typ I2C or .002 to .002 to 0.3 ps 4–525 Hz Y Y LOL, LOS, SPI 710 1400 rms typ FOS I2C or .002 to .002 to 0.3 ps 60 Hz–8.4 kHz Y Y LOL, LOS, SPI 710 1400 rms typ FOS I2C or .002 to .002 to 0.5 ps 4–525 Hz Y Y LOL, LOS SPI 710 808 rms typ Pin Package 2 Alarms Si5316 Hitless Switching 2 Clock Mult. 2 Prog. Loop BW Si5325 Jitter Generation (12 kHz–20 MHz) 2 Output Freq (MHz) # Clock Outputs 2 Input Freq (MHz) # Clock Inputs Si5322 Control Device PN Table 1. Features by Part Number 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 6x6 36-QFN 2. Applications The Si531x/2x Any-Frequency Precision Clocks have a comprehensive feature set, including any-frequency synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input clocks, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), output phase adjustment between output clocks, and output phase adjustment between all output clocks and the selected reference input clock (phase increment/decrement). For more details, consult the Silicon Laboratories timing products website at www.silabs.com/timing. All six evaluation boards (EVBs) have an MCU (C8051F340) that support USB communications with a PC host. For the pin controlled parts (Si5316, Si5322, and Si5323), the pin settings of the devices are determined by the MCU and the PC resident software that is provided with the EVB. For the MCU controlled parts (Si5319, Si5324, Si5325, Si5326, and Si5327), the devices are controlled and monitored through the serial port (either SPI or I2C). A CPLD sits between the MCU and the Any-Frequency Precision Clock device that performs voltage level translation and stores the pin configuration data for the pin controlled devices. Jumper plugs are provided so that the user can bypass the MCU/CPLD to manually control the pin controlled devices. Ribbon headers and SMA connectors are included so that external clock in, clock out, and status pins can be easily accessed by the user. For the MCU controlled devices (Si5319, Si5324, Si5325, Si5326, and Si5327), the user also has the option of bypassing the MCU and controlling the parts from an external serial device. On-board termination is included so that the user can evaluate single-ended or differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (Device Under Test) power supply connector is included so that the Any-Frequency Precision Clocks can be run at either 1.8, 2.5 or 3.3 V, while the USB MCU remains at 3.3 V. LEDs are provided for convenient monitoring of key status signals. 2 Rev. 0.6 Si531x-EVB Si532x-EVB 3. Features The Si5316-EVB, Si5319-EVB, Si5322/23-EVB, Si5324-EVB, Si5325/26-EVB, and Si5327-EVB each include the following: CD with documentation and EVB software including the DSPLLsim configuration software utility USB cable EVB circuit board including an Si5316 (Si5316-EVB), Si5319 (Si5319-EVB), Si5323 (Si5322/23-EVB), Si5324 (Si5324-EVB), Si5326 (Si5325/26-EVB), or Si5327 (Si5327-EVB). User's Guide (this document) 4. Si5316-EVB, Si5319-EVB, Si5322/23-EVB, Si5324-EVB, Si5325/26-EVB, and Si5327-EVB Quick Start 1. A CD-ROM is included with the evaluation board. On this CD, there is a file named “install_instructions.PDF”. This file gives the detailed instructions on how to install the drivers and software that control the evaluation board. 2. Connect the two power supplies to the EVB. One is 3.3 V and the other is 1.8, 2.5, or 3.3 V. The DUT is powered by the 1.8/2.5/3.3 V supply. 3. Turn on the power supplies. 4. Connect a USB cable from the EVB to the PC where the software was installed. 5. Install USB driver. 6. Launch software by clicking on StartProgramsSilicon LaboratoriesPrecision Clock EVB Software and selecting one of the programs. 5. Functional Description The Si531x/2x-EVB software allows for a complete and simple evaluation of the functions, features, and performance of the Si531x/2x Any-Frequency Precision Clocks. 5.1. Narrowband versus Wideband Operation This document describes six evaluation boards: Si5316, Si5319, Si5322/23, Si5324, Si5325/26, and Si5327. The Si5316 and Si5322/23 evaluation boards are for pin controlled clock parts and the Si5319, Si5324, Si5325/26, and Si5327 are for clock parts that are to be controlled by an MCU over a serial port. The Si5316-EVB, Si5319-EVB, Si5324-EVB, and Si5327-EVB support only one part, while the two other boards each support two parts: one that is wideband (the Si5322 and the Si5325) and one that is narrowband (the Si5323 and the Si5326). The narrowband parts are both capable of operating in the wideband mode, so evaluation of the wideband parts can be done by using a narrowband part in wideband mode. As such, these evaluation boards are only populated with narrowband parts. The Si5324-EVB and Si5327-EVB are special cases because the Si5324 and Si5327 have a lower loop bandwidth and do not support wideband operation. Because of the lower loop bandwidth, the lock times are increased and the Si5324 and Si5327 will be more sensitive to XA-XB reference crystal temperature changes. For this reason, a 20 ppm crystal is used on the SI5324-EVB. It should be noted that the 20 ppm crystal is used for its temperature stability, not its absolute accuracy. If the crystal will undergo significant changes in temperature, it is suggested that the crystal be thermally insulated by covering it with foam tape or some other means. To evaluate Si5322 device operation using the Si5322/23-EVB, the RATE[1:0] pins must be set to LL using the jumpers provided. To evaluate Si5325 device operation using the Si5325/26-EVB, the Precision Clock EVB Software should be configured for wideband mode. For details, see the Precision Clock EVB Software documentation. Rev. 0.6 3 Si531x-EVB Si532x-EVB 5.2. Block Diagram Figure 2 is a block diagram of the evaluation board. The MCU communicates to the host PC over a USB connection. The MCU controls and monitors the Si532x through the CPLD. The CPLD, among other tasks, translates the signals at the MCU voltage level of 3.3 V to the Si532x's voltage level, which is nominally 3.3, 2.5, or 1.8 V. The user has access to all of the Si532x's pins using the various jumper settings as well as through the host PC via the MCU and CPLD. Figure 2. Si532x QFN Block Diagram 5.3. Si532x Input and Output Clocks The Si532x has two differential inputs that are ac terminated to 50 and then ac coupled to the part. Single-ended operation can be implemented by simply not connecting to one of the two of the differential pairs bypassing the unused input to ground with a capacitor. When operating with clock inputs of 1 MHz or less in frequency, the appropriate dc blocking capacitors (C39, C41, C34, and C36) located on the bottom of the board should be replaced with 0 resistors. The reason for this is that the capacitive reactance of the ac coupling capacitors becomes significant at low frequencies. It is also important that the CKIN signal meet the minimum rise time of 11 ns (CKNtrf) even though the input frequency is low. The two clock outputs (one for the Si5316-EVB and Si5319-EVB) are all differential, ac-coupled and configured for driving 50 transmission lines. When using single ended outputs, it is important that the unused half of the output be terminated. Two jumpers are provided to assist in monitoring the Si532x power: When R27 is removed, J20 can be used to measure the device current. J12 can be used at any time to monitor the supply voltage at the device. The Si5316, Si5319, Si5323, Si5326, and Si5327 require that an external reference be provided to enable the devices to operate as narrowband jitter attenuators with loop bandwidths as low as 60 Hz (4 Hz for the Si5324 and Si5327). The external reference source can be either a crystal, a standalone oscillator or some other clock source. The range of acceptable reference frequencies is described in the Any-Frequency Precision Clocks Family Reference Manual (Si53xxRM.pdf). The EVBs are shipped with a third overtone 114.285 MHz crystal that is used in the majority of applications. J1 and J2 are used when the Si532x is to be configured in narrowband mode with an external reference oscillator (i.e. without using the 114.285 MHz crystal). The Si5327-EVB is shipped with a 40 MHz fundamental mode crystal. The RATE pins should also be configured for the desired mode, using the jumper plugs at J9 (see Table 6). For unused inputs and outputs, please refer to the Any-Frequency Precision Clocks Family Reference Manual (Si53xxRM.pdf). 4 Rev. 0.6 Si531x-EVB Si532x-EVB Table 2 shows how the various components should be configured for the three modes of operation. Table 2. Reference Input Mode Mode Xtal1 Ext Ref2 Wide Band Input 1 NC3 J1 NC Input 2 NC J2 NC C30 NOPOP4 install install C5 NOPOP install NOPOP R34 NOPOP NOPOP install R15 install NOPOP NOPOP RATE0 M — H RATE1 M — H RATE5 L NC — Notes: 1. Xtal is 114.285 MHz third overtone; 40 MHz fundamental for the Si5327-EVB 2. For external reference frequencies and RATE pin settings, see the Si53xx-RM Any-Frequency Precision Clock Family Reference Manual. 3. NC—No connect. 4. NOPOP—Do not install this component. 5. RATE options for Si5327 only. For a differential external reference, connect the balanced input signals to J1 and J2. For single-ended operation, connect the input signal to J2 and disconnect J1. R35 is provided so that a different termination scheme can be used. If R35 is populated, then remove R9 and R36. 5.4. Two and Three Level Inputs The two-level and three-level inputs can all be manually configured by installing jumper plugs at J9. The two level inputs are either H or L. For the three-level inputs, the M level is achieved by not installing a jumper plug at a given location. J9 can also be used as a connection to an external circuit that controls these pins. J17 is a ten pin ribbon header that is provided so that an external processor can control the Si532x over either the SPI or I2C bus. J14 is another ten pin ribbon header that brings out all of the status outputs from the Si532x. Note that some pins are shared and serve as both inputs and outputs, depending on how the device is configured. For users that wish to remotely access the input and output pins settings as well as serial ports with external hardware, all three of these headers can be connected to ribbon cables. 5.5. CPLD and Power This CPLD is required for the MCU to control the Si532x. The CPLD provides two main functions: it translates the voltage level from 3.3 V (the MCU voltage) to the Si532x voltage (either 1.8, 2.5, or 3.3 V). The MCU communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO (master in, slave out), MOSI (master out, slave in), and SCLK. The MCU can talk to CPLD-resident registers that are connected to pins that control the Si532x's pins, mainly for pin control mode. When the MCU wishes to access a Si532x register, the SPI signals are passed through the CPLD, while being level translated, to the Si532x. The CPLD is an EE device that retains its code and is loaded through the JTAG port (J27). The core of the CPLD runs at 1.8 V, which is provided by voltage regulator U6. The CPLD also logically connects many of the LEDs to the appropriate Si532x pins. Rev. 0.6 5 Si531x-EVB Si532x-EVB DUT_PWR +3.3 V SS_CPLD_B SS_B SCLK SCLK MCU CPLD Si5325, Si5326 MOSI SDI MISO SDO Figure 3. SPI Mode Serial Data Flow This evaluation board requires two power inputs +3.3 V for the MCU and either 1.8, 2.5, or 3.3 V for the Any-Frequency Precision Clock part. The power connector is J30. The grounds for the two supplies are tied together on the EVB. There are eight LEDs, as described in Table 3. The Evaluation board has a serial port connector (J17) that supports the following: Control by the MCU/CPLD of an Any-Frequency part on an external target board. Control of the Any-Frequency part that is on the Eval board through an external SPI or I2C port. For details, see J17 (Table 5). Though they are not needed on this Evaluation Board because the CPLD has low output leakage current, some applications will require the use of external pullup and pulldown resistors when three level pins are being driven by external logic drivers. This is particularly true for the pin-controlled parts: the Si5316, Si5322 and Si5323. Consult the Si53xx-RM Any-Frequency Precision Clock Family Reference Manual for details. 5.6. MCU The MCU is responsible for connecting the evaluation board to the PC so that PC resident software can be used to control and monitor the Si532x. The USB connector is J3 and the debug port, by which the MCU is flashed, is J24. The reset switch, SW1, resets the MCU, but not the CPLD. The MCU is a self-contained USB master and runs all of the code required to control and monitor the Si532x, both in the MCU mode and in the pin-controlled modes. U4 contains a unique serial number for each board and U3 is an EEPROM that is used to store configuration information for the board. The board powers up in free run mode with a configuration that is outlined in "Appendix— Powerup and Factory Default Settings" on page 23. For the pin controlled parts (Si5316-EVB and Si5322/23-EVB), the contents of U3 configure the board on powerup so that jumper plugs may be used. If DSPLLsim is subsequently run, the jumper plugs should be removed before DSPLLsim downloads the configuration to the EVB so that the jumpers do not conflict with the CPLD outputs. For microprocessor parts, U3 configures the EVB for a specific frequency plan as described in "Appendix— Powerup and Factory Default Settings" on page 23. LVPECL outputs will not function at 1.8 V. If the Si532x part is to be operate at 1.8 V, the output format needs to be changed by altering either the SFOUT pins (Si5316/22/23) or the SFOUT register bits (Si5319/ 25/26/27). 6 Rev. 0.6 Si531x-EVB Si532x-EVB 6. Connectors and LEDs 6.1. LEDs There are eight LEDs on the board which provide a quick and convenient means of determining board status. Table 3. LED Status and Description LED Color Label D1 Green 3.3 V D2 Green DUT_PWR D5 Red LOL D4 Red C1B D6 Red C2B D3 Green CA D7 Yellow CPLD D8 Yellow MCU Rev. 0.6 7 Si531x-EVB Si532x-EVB 6.2. User Jumpers and Headers Use the following to locate the jumpers described in Figure 4: Ext Ref, J1, J2 R9, R15, C5 on top; R34, R35, R36, C30 on bot 2 and 3 level Inputs, J9 J20 Status, J14 J18 Serial port, J17 J25, R36 J20, R27 Figure 4. Connectors, Jumper Header Locations J20 assists in measuring the Any-Frequency Precision Clock current draw. If J20 is to be used, R27 should be removed. 8 Rev. 0.6 Si531x-EVB Si532x-EVB J14 is a 10 pin ribbon header that provides an external path to monitor the status pins. Table 4. Status Header, J14 J14 J14.1 J14.3 J14.5 J14.7 J14.9 Pin LOL C1B C2B CS_CA DUT_PWR Comment clock active J17 is a 10 pin ribbon header that provides an external path to serially communicate with the Any-Frequency Precision Clock. To control the Any-Frequency part that is on the Evaluation Board from an external serial port, open the Register Programmer, connect to the Evaluation Board, go to Options in the top toolbar, and select “Switch To External Control Mode”. To control an Any-Frequency part that is on an external target board from the Evaluation Board using its serial port, tie pin 9 of J17 low so that the on-board Any-Frequency part is constantly being held in reset. This will force it to disable its SDA_SDO output buffer. This will work only for Evaluation Boards that have Rev C or higher Any-Frequency parts. Table 5. External Serial Port Connector, J17 J17 J17.1 J17.3 J17.5 J17.7 J17.9 Pin SDA_SDO SCL_SCLK SDI A2_SS DUT_RST_B Comment not reset J9 is a three-pin by twenty header that is used to establish input levels for the pin controlled two and three-level inputs using jumper plugs. It also provides a means of externally driving the two and three-level input signals. Table 6. Two and Three Level Input Jumper Headers, J9 J9 Pin J9 Pin Comment J9.1B AUTOSEL J9.11B — not used J9.2B CMODE J9.12B SFOUT0 J9.3B A0_FRQSEL0 J9.13B SFOUT1 J9.4B A1_FRQSEL1 J9.14B RATE0 J9.5B A2_SS_FRQSEL2 J9.15B RATE1 J9.6B SDI_FRQSEL3 J9.16B DBL2_BY J9.7B SCL_SCLK_BWSEL0 J9.17B — J9.8B SDA_SDO_BWSEL1 J9.18B INC J9.9B CS_CA J9.19B DEC J9.10B FRQTBL J9.20B — not used not used J12 is used to monitor the Any-Frequency Precision Clock voltage. J1 and J2 are edge mount SMA connectors that are used, if so configured, to supply an external single-ended or differential reference oscillator. Rev. 0.6 9 Si531x-EVB Si532x-EVB 7. EVB Software Installation The release notes and the procedure for installing the EVB software can be found on the release CD included with the EVB. These items can also be downloaded from the Silabs web site: www.silabs.com/timing. Follow the links for 1-PLL Jitter attenuators, and look under the Tools tab. 7.1. Precision Clock EVB Software Description There are several programs to control the Precision Clock device. Each provides a different kind of access to the device. Refer to the online help in each program by clicking HelpHelp in the menu for more information on how to use the software. Note: Some of the Precision Clock devices do not have a register map, so some programs may not be applicable to them. Table 7. User Applications Program Description Register Viewer The Register Viewer displays the current register map data in a table format sorted by register address to provide an overview of the device’s state. This program can save and print the register map. Register Programmer The Register Programmer provides low-level register control of the device. Single and batch operations are provided to read from and write to the device. Register map files can be saved and opened in the batch mode. Setting Utility DSPLLsim 10 This application allows for quick access to each control on the Precision Clock device (either pin- or register-based). It can save and open text files as well. The DSPLLsim provides high-level control of the Precision Clock device. It has the frequency planning wizard as well as control of the pins and registers in a organized, intuitive manner. Rev. 0.6 J28 SMA_EDGE 1 J29 SMA_EDGE 1 J23 SMA_EDGE 1 J25 SMA_EDGE 1 DBL2_BY AUTOSEL INC DEC DUT_RST_B CMODE FRQTBL SDI_FRQSEL3 A2_SS_FRQSEL2 A1_FRQSEL1 A0_FRQSEL0 SDA_SDO_BWSEL1 SCL_SCLK_BWSEL0 CKIN2- CKIN2+ CKIN1- CKIN1+ J1 SMA_EDGE 1 2 2 2 Ext Ref In - 3 3 3 Ext Ref In + R48 49.9 C36 C34 R45 100N 100N 49.9 R43 49.9 R46 C41 C39 100N 100N 49.9 C31 10NF C37 10NF 10NF C35 C42 10NF C40 10NF 49.9 R36 GND X1 4 R47 1.5K NOPOP R37 1.5K NOPOP 1 36 2 27 26 25 24 23 22 14 9 20 19 12 13 16 17 6 7 C5 10NF NOPOP U5 RST CMODE FRQTBL SDI_FRQSEL3 A2_SS_FRQSEL2 A1_FRQSEL1 A0_FRQSEL0 INT_C1B C2B SFOUT0 SFOUT1 CKOUT2+ CKOUT2- CKOUT1+ CKOUT1- LOL CKSEL/CK_ACTV Si532x SDA_SDO_BWSEL1 SCL_SCLK_BWSEL0 DBL2_BY AUTOSEL INC DEC CKIN_2+ CKIN_2- CKIN1+ CKIN1- XA XB Note 1 1 2 1 18 21 3 4 33 30 35 34 28 29 C6 100N C33 100N J12 LOL CS_CA C1B C2B SFOUT0 R8 0 ohm NOPOP C19 100N 100N C22 C3 100N 100N C1 J18 SMA_EDGE 1 to power plane to measure DUT supply current SFOUT1 C45 1UF C8 100N 2 DUT_PWR Locate next to U1 1 2 J20 NOPOP Ferrite L2 Notes: 1. Change for Si5322, Si5325, and External Reference. 2. NOPOP for Si5316. install for I2C DUT_PWR R15 0 ohm R34 NOPOP 3 R9 49.9 0 ohm 114.285 MHz 2 1 C30 10NF NOPOP C4 10NF NOPOP 100 R35 R27 0 ohm 15 Rate1 2 2 2 11 Rate0 3 3 3 5 10 32 J16 SMA_EDGE 1 3 J6 SMA_EDGE 1 3 J8 SMA_EDGE 1 3 3 J2 SMA_EDGE 1 CKOUT2- CKOUT2+ CKOUT1- CKOUT1+ #4 H3 Note 2 #4 H4 #4 H1 mounting holes #4 H2 ground pins 1 RATE1 1 2 2 2 2 VDD1 VDD2 VDD3 8 31 37 Rev. 0.6 GND1 GND2 GND5 1 RATE0 J4 J22 J21 J10 J13 J15 J5 J11 1 1 1 1 1 1 1 J7 1 1 Si531x-EVB Si532x-EVB 8. Schematics 11 1 Si531x-EVB Si532x-EVB Figure 5. Si532x 12 Rev. 0.6 DUT_PWR * * * * Rev. 0.6 C15 1UF 10 R17 V3P3 10 C25 330UF MCU_LED1 CPLD_LED0 CPLD_LED1 CPLD_LED2 CPLD_LED3 CPLD_LED4 + J19 1 2 OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 2 3 1 FB Vreg Out 4 5 R21 66.5 TPS76201 Gnd EN In U6 1 18 17 16 15 14 13 12 11 Ferrite 0 ohm 2 BSS138 Q1 O0 O1 O2 Q3 O4 O5 O6 O7 Buffer 74LCX541 BOM = NOPOP R55 10k DUT_PWR 1 19 2 3 4 5 6 7 8 9 U9 C24 33UF R53 R58 1K + R20 0 ohm 1 2 3 Phoenix_4_screw 3.3V 3.3Vreturn DUT_PWRreturn 4 20 Vcc J30 GND 10 DUT_PWR 3 2 EVB main power 1 2 3 4 4 3 2 1 C11 1UF R52 113 R150x4 R25 8 7 6 5 R26 R150x4 5 6 7 8 R59 L1 1 + D3 C Yel C Yel D1 D2 Red V1P8 2C 2C 2 C Red 2 C Red 2 C 2C 2 2 C23 330UF C12 100N C17 33UF + Grn 1 1 1 1 1 1 1 1 C10 1UF C21 1UF C14 10NF 100N C9 3.3V DUT_PWR LOL C1B C2B CA CPLD MCU +3.3V V3P3 C26 33UF 1.8V Grn Grn D5 C43 10NF A A A D4 A D6 A A D7 A D8 A + DUT_PWR C20 100N C44 10NF XC2C128 VCCIO2-1 VCCIO2-2 VCCIO1-1 VCCIO1-2 VCCIO1-3 VCC1 VCC2 U8A C18 10NF 88 98 20 38 51 26 57 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 SMT J27 21 25 31 62 69 75 84 100 1 2 3 4 5 6 VCCAUX TMS TDI TDO TCK Figure 6. CPLD and Power C13 10NF C16 10NF R23 10k JTAG connector DEC C1B C2B INC CS_CA SFOUT1 AUTOSEL FRQTBL SFOUT0 DBL2_BY RATE0 RATE1 CMODE SDI_FRQSEL3 SCL_SCLK_BWSEL0 SDA_SDO_BWSEL1 DUT_RST_B LOL A0_FRQSEL0 A1_FRQSEL1 A2_SS_FRQSEL2 R24 10k 68 67 66 65 85 86 87 89 77 76 74 73 72 71 70 78 79 80 81 82 8 9 10 11 12 13 93 92 91 90 1 2 3 4 6 7 99 97 96 95 94 DUT_PWR U8C 0 ohm R56 FN12_M11 FN12_M13 FN12_M14 FN12_M15 FN11_M11 FN11_M12 FN11_M13 FN11_M14 FN10_M1 FN10_M2 FN10_M3 FN10_M4 FN10_M5 FN10_M6 FN10_M12 FN9_M1 FN9_M2 FN9_M4 FN9_M6 FN9_M12 FN4_M1 FN4_M2 FN4_M3 FN4_M5 FN4_M6 FN4_M13 FN3_M5 FN3_M12 FN3_M14 FN3_M16 5 83 47 48 45 V3P3 FN2_M1_GTS2 FN2_M3_GTS3 FN2_M5_GTS0 FN2_M12_GTS1 FN2_M14 FN2_M15 FN1_M3_GSR FN1_M6 FN1_M12 FN1_M13 FN1_M14 Bank 2 XC2C128 VCCAUX TDO TMS TCK TDI U8B XC2C128 FN16_M5 FN16_M6 FN16_M11 FN16_M12 FN16_M13 FN15_M11 FN15_M12 FN15_M13 FN15_M14 FN15_M15 FN15_M16 FN14_M1 FN14_M3 FN14_M5 FN14_M14 FN14_M15 FN13_M2 FN13_M4 FN13_M6 FN13_M13 FN8_M6 FN8_M11 FN8_M12 FN8_M13 FN8_M14 FN8_M15 FN7_M5 FN7_M6 FN7_M11 FN7_M12 FN7_M13 FN7_M14 FN6_M2_CDRST FN6_M4_GCK2 FN6_M12_DGE FN6_M14 FN6_M16 FN5_M4_GCK1 FN5_M6_GCK0 Bank 1 43 42 41 40 39 58 59 60 61 63 64 52 50 49 46 44 53 54 55 56 32 33 34 35 36 37 19 18 17 16 15 14 24 27 28 29 30 23 22 +3.3V R19 0 ohm NOPOP R18 0 ohm NOPOP CPLD_SPARE16 CPLD_SPARE15 REG_ADR0 REG_ADR1 REG_ADR2 REG_ADR3 REG_ADR4 SS_CPLD_B MOSI MISO SCLK CPLD_IRQ MCU_SPARE1 CPLD_LED2 CPLD_LED1 CPLD_LED0 CPLD_SPARE2 CPLD_SPARE1 CPLD_LED4 CPLD_LED3 CPLD_SPARE4 CPLD_SPARE3 MCU_SPARE2 CPLD_SPARE10 CPLD_SPARE9 CPLD_SPARE8 CPLD_SPARE7 CPLD_SPARE6 CPLD_SPARE5 CPLD_RST_B CPLD_SPARE14 CPLD_SPARE13 CPLD_SPARE12 CPLD_SPARE11 Si531x-EVB Si532x-EVB 13 MISO SCLK CPLD_SPARE10 CPLD_SPARE9 CPLD_SPARE8 CPLD_SPARE7 CPLD_SPARE6 CPLD_SPARE5 CPLD_SPARE4 CPLD_SPARE3 CPLD_SPARE2 CPLD_SPARE1 SS_CPLD_B U3 W CS D Clk 7 3 1 5 6 49.9 49.9 49.9 M95040 HOLD EEPROM Q MOSI CPLD_IRQ MCU_SPARE1 MCU_SPARE2 2 8 Vcc Vss 4 R22 R14 R12 49.9 R11 R5 10k R6 10k BOM = NOPOP J26 10_M_Header_SMT Spares C38 1UF V3P3 C32 100N 46 45 44 43 42 41 40 39 6 5 4 3 2 1 48 47 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 U7 C8051F340 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 Install 1.5K pullups for I2C operation. On MCU: P0.0 = SDA P0.1 = SCL Figure 7. MCU Si8051F340 R44 10k NOPOP R16 1.5K R1 R3 R2 R4 1K NOPOP CPLD_SPARE11 CPLD_SPARE12 CPLD_SPARE13 CPLD_SPARE14 CPLD_SPARE15 CPLD_SPARE16 27.4 27.4 1K J24 10_M_Header_SMT 2 1 4 3 6 5 8 7 10 9 VBUS U2 SN65220 C28 1UF 1K C27 100N USB Clamp 49.9 10 EVB_SER_NUM 3 2 C29 100N 10 U1 R30 1K R32 R31 USB Clamp V Gnd D+ USB D- J3 4 1 C7 NC3 3 4 5 100N NC1 U4 V3P3 USB SN65220 SW1 4 3 CPLD_RST_B Ser No. NC2 I/O NO reset 1 2 DS2411 2 R10 1K serial number R13 MCU_LED1 REG_ADR4 REG_ADR3 REG_ADR2 REG_ADR1 REG_ADR0 R33 R29 0 ohm 2 MCU debug 1 NC1 A 6 R7 10k GND 7 3 C2 100N 10 11 Vdd REGIN 2 Gnd1 V3P3 13 14 RST/C2CK C2D 6 NC2 B 4 1 NC1 A 6 S2 Gnd2 5 3 NC2 B 4 Gnd1 Gnd2 5 S1 5 V3P3 1 3 5 7 9 2 4 6 8 10 12 8 9 VBUS D+ D- P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 38 37 36 35 34 33 32 31 6 Vcc Rev. 0.6 GND 14 1 V3P3 Si531x-EVB Si532x-EVB Rev. 0.6 DUT_RST_B Note 3 10 J17 9 7 5 3 1 10_M_Header_SMT 10 8 6 4 2 SPI, I2C R57 J14 9 7 5 3 1 4 3 2 1 R82x4 R51 INC DEC 8 7 6 5 R41 0 ohm 5 6 7 8 R54 C2B C1B LOL DUT_PWR R40 26.7K DUT_PWR R39 0 ohm NOPOP R38 0 ohm NOPOP R49 10k Figure 8. Two and Three Level Inputs Note: NOPOP for Si5316, Si5322, and Si5323. AUTOSEL CMODE A0_FRQSEL0 A1_FRQSEL1 A2_SS_FRQSEL2 SDI_FRQSEL3 SCL_SCLK_BWSEL0 SDA_SDO_BWSEL1 CS_CA FRQTBL SFOUT0 SFOUT1 RATE0 RATE1 DBL2_BY R82x4 1 2 3 4 10_M_Header_SMT 10 8 6 4 2 Status R50 10k R42 10k R28 100 J9 1C 2C 3C 4C 5C 6C 7C 8C 9C 10C 11C 12C 13C 14C 15C 16C 17C 18C 19C 20C 20x3_M_HDR_SMT 20A 20B 19A 19B 18A 18B 17A 17B 16A 16B 15A 15B 14A 14B 13A 13B 12A 12B 11A 11B 10A 10B 9A 9B 8A 8B 7A 7B 6A 6B 5A 5B 4A 4B 3A 3B 2A 2B 1A 1B DUT_PWR three level inputs two level inputs Si531x-EVB Si532x-EVB 15 Si531x-EVB Si532x-EVB 9. Bill of Materials Table 8. Si531x/2x Bill of Materials Item Qty Reference Part Mfgr MfgrPartNum 1 19 C1,C2,C3,C6,C7,C8,C9,C12,C19, C20,C22,C27,C29,C32,C33,C34, C36,C39,C41 100 nF Venkel C0603X7R160-104KNE 2 12 C4,C13,C14,C16,C18,C31,C35,C 37,C40,C42,C43,C44 10 nF Venkel C0603X7R160-103KNE 4 7 C10,C11,C15,C21,C28,C38,C45 1 µF Venkel C0603X7R6R3-105KNE 5 3 C17,C24,C26 33 µF Venkel TA0006TCM336MBR 6 2 C23,C25 330 µF Panasonic EEE-HA0J331XP 7 3 D1,D2,D3 Grn Lumex SML-LXT0805GW-TR 8 3 D4,D5,D6 Red Lumex SML-LXT0805SRW-TR 9 2 D7,D8 Yel Lumex SML-LXT0805YW-TR 10 4 H1,H2,H3,H4 #4 mounting hole 11 10 J1,J2,J6,J8,J16,J18,J23,J25,J28, J29 SMA_EDGE Johnson 142-0701-801 12 1 J3 USB FCI 61729-0010BLF 13 9 J4,J5,J7,J10,J11,J13,J15,J21,J22 Jmpr_1pin 14 1 J9 20x3_M_HDR_SMT Samtec TSM-120-01-L-TV 15 1 J12 Jmpr_2pin 16 3 J14,J17,J24 10_M_Header_SMT Samtec HTST-105-01-lm-dv-a 19 1 J27 SMT Sullins GZC36SABN-M30 20 1 J30 Phoenix_4_screw Phoenix MKDSN 1.5/4-5.08 21 2 L1,L2 Ferrite Venkel FBC1206-471H 22 1 Q1 BSS138 On Semi BSS138LT1G 23 5 R1,R10,R30,R33,R58 1 k Venkel CR0603-16W-1001FT 24 2 R2,R3 27.4 Venkel CR0603-16W-27R4FT 26 10 R5,R6,R7,R23,R24,R42,R44, R49,R50,R55 10 k Venkel CR603-16W-1002FT 28 11 R9,R11,R12,R13,R14,R22,R36,R 43,R45,R46,R48 49.9 Venkel CR0603-16W-49R9FT 29 7 R15,R20,R27,R29,R51,R56,R59 0 Venkel CR0603-16W-000T 31 5 R17,R31,R32,R53,R57 10 Venkel CR0603-16W-10R0FT 32 1 R21 66.5 Venkel CR0603-16W-66R5FT 33 2 R25,R26 R150x4 Panasonic EXB-38V151JV 34 1 R28 100 Venkel CR0603-16W-1000FT 36 1 R40 26.7 k Venkel CR0603-16W-2672FT 16 Rev. 0.6 Si531x-EVB Si532x-EVB Table 8. Si531x/2x Bill of Materials (Continued) Item Qty Reference Part Mfgr MfgrPartNum 37 2 R41,R54 R82x4 Panasonic EXB-38V820JV 38 1 R52 113 Venkel CR0603-16W-1130FT 39 1 SW1 NO Mountain Switch 101-0161-EV 40 2 U1,U2 SN65220 TI SN65220DBVT 41 1 U3 M95040 ST Micro M95040-WMN6P 42 1 U4 DS2411 Maxim/Dallas DS2411P 43 1 U5 Si5326A-X-GM* Silicon Labs Si5326A-X-GM 44 1 U6 TPS76201 TI TPS76201DBVT 45 1 U7 Si8051F340 Silicon Labs C8051F340-GQ 46 1 U8 XC2C128 Xilinx XC2C128-7VQG100I 47 1 U9 74LCX541 Fairchild 74LCX541MTC_NL 48 1 X1 114.285 MHz TXC 7MA1400014 49 1 X1 for the Si5324 114.285 MHz 20 ppm NDK EXS00A-CS00997 50 1 X1 for the Si5327 40 MHz NDK NX3225SA-40.000000MHZ Venkel C0603X7R160-103KNE Not Populated 3 2 C5,C30 10 nF 17 2 J19,J20 Jmpr_2pin 18 1 J26 10_M_Header_SMT Samtec HTST-105-01-lm-dv-a 25 1 R4 1 k Venkel CR0603-16W-1001FT 27 6 R8,R18,R19,R34,R38,R39 0 Venkel CR0603-16W-000T 30 3 R16,R37,R47 1.5 k Venkel CR0603-16W-1501FT 35 1 R35 100 Venkel CR0603-16W-1000FT Note: X denotes the product revision. Consult the ordering guide in the Si5326 data sheet for the latest product revision. For the Si5322/23-EVB, substitute Si5323A-X-GM. For the Si5316-EVB, substitute Si5316-C-GM. For the Si5319-EVB, substitute Si5319A-X-GM. For the Si5324-EVB, substitute Si5324A-X-GM. For the Si5327-EVB, substitute Si5327A-X-GM. Rev. 0.6 17 Si531x-EVB Si532x-EVB 10. Layout Figure 9. Silkscreen Top Figure 10. Layer 1 18 Rev. 0.6 Si531x-EVB Si532x-EVB Figure 11. Layer 2, Ground Plane Figure 12. Layer 3 Rev. 0.6 19 Si531x-EVB Si532x-EVB Figure 13. Layer 4, 3.3 V Power Figure 14. Layer 5 20 Rev. 0.6 Si531x-EVB Si532x-EVB Figure 15. Layer 6, DUT Power Figure 16. Layer 7, Ground Plane Rev. 0.6 21 Si531x-EVB Si532x-EVB Figure 17. Layer 8 Figure 18. Silkscreen Bottom 22 Rev. 0.6 Si531x-EVB Si532x-EVB APPENDIX—POWERUP AND FACTORY DEFAULT SETTINGS For the Si5324-EVB, Si5325/26-EVB, and Si5327-EVB, the power up settings are as follows: 19.44 MHz input on CKIN1 CKIN2 is not used because of free run mode 155.52 MHz output on CKOUT1 622.08 MHz output on CKOUT2 Loop BW of 70 Hz (Si5325/26-EVB) Loop BW of 7 Hz (Si5324-EVB and Si5327-EVB) LVPECL outputs for CKOUT1 and CKOUT2 For the Si5322/23-EVB, the factory jumper settings are as follows: Pin Jumper Comment AUTOSEL H automatic, revertive — none FRQSEL0 none FRQSEL = LMLM FRQSEL1 L 19.44 MHz input FRQSEL2 none 155.52 MHz output FRQSEL3 L BWSEL0 H BWSEL1 H CS_CA none CS_CA is an output, not an input FRQTBL L SONET frequency table — none SFOUT0 H SFOUT1 none RATE0 none RATE1 none DBL_BY L — none INC none DEC none — none BW is 96 Hz, the minimum PECL outputs 114.285 MHz ref xtal CKOUT2 enabled For the Si5319-EVB, the power up settings are as follows: Free run mode, based on the 114.285 MHz crystal 19.44 MHz on CKOUT Loop BW of 110 Hz LVEPCL output for CKOUT Rev. 0.6 23 Si531x-EVB Si532x-EVB For the Si5316-EVB, the factory jumper settings are as follows: pin jumper — none — none FRQSEL0 L FRQSEL = LL FRQSEL1 L 19.44 MHz input/output CK1DIV L div by 1 CK2DIV L div by 1 BWSEL0 H BW is 100 Hz, the minimum BWSEL1 H CS L — none — none SFOUT0 H SFOUT1 none RATE0 none RATE1 none DBL_BY L — none — none — none 24 comment select CKIN1 PECL output 114.285 MHz ref xtal CKOUT enabled Rev. 0.6 Si531x-EVB Si532x-EVB DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Added Si5319-EVB. Add "Appendix—Powerup and Factory Default Settings" on page 23. Revision 0.2 to Revision 0.3 Updated for free run mode. Revision 0.3 to Revision 0.4 Added Si5324-EVB Revision 0.4 to Revision 0.5 Added Si5327-EVB. Changed any-rate to any-frequency. Revision 0.5 to Revision 0.6 Removed software installation instructions and directed reader to refer to release CD or download from Silicon Labs web site. Rev. 0.6 25 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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