Process Introduction 2um / 36V Bipolar Process Technology Process features Key Design Rules Up-down isolation Deep N+ collector plug N-channel stop NPN transistor Lateral PNP transistor Implant resistor (optional) MOS capacitor 10 Masks Min. Width/Space(um) Diffusion 4 Contact 2 Double metal (optional) Applications: Analog, Power Linear Metal 3/2 Electrical Specification Specification Device Parameter Min Typ Max Unit Hfe(Ic=100uA) 80 140 250 - BVceo(Ic=10uA) 18 - - V 7.2 7.5 7.8 V 6.8 7.3 7.8 V 80 140 250 - BVceo(Ic=10uA) 36 44 - V PBASE-LPNP(LV) Hfe(Ic=10uA) 100 350 600 - (Wb=12um without emitter guarding) BVceo(Ic=10uA) 18 - - V PBASE-LPNP(HV) Hfe(Ic=10uA) 100 350 600 - (Wb=12um with emitter guarding) BVceo(Ic=10uA) 36 50 - V XBASE-LPNP(LV) Hfe(Ic=10uA) 150 500 900 - (Wb=14um without emitter guarding) BVceo(Ic=10uA) 18 - - V XBASE-LPNP(HV) Hfe(Ic=10uA) 150 500 900 - (Wb=16um with emitter guarding) BVceo(Ic=10uA) 36 54 - V PBASE-R 190 215 240 Ω/□ Implant-R 18.4 2.3 27.6 kΩ/□ C(100x100um2) 7.9 9.3 10.7 pF NPN (LV) (5x7 um2 emitter) NPN (HV) (5x7 um2 emitter) Sheet Resistance(20x200um2) Capacitance (Si3N4) BVebo(I=10uA) (without XBASE) BVebo(I=10uA)(with XBASE) Hfe(Ic=100uA) -1- Process Introduction -2- Process Introduction -3- Process Introduction -4- Process Introduction -5-