http://www.elm-tech.com GD25LQ128C DATASHEET GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com - Content 1. FEATURES Page ------------------------------------------------------------------------------------------------- 2. GENERAL DESCRIPTION 4 ----------------------------------------------------------------------------- 5 -------------------------------------------------------------------------- 6 4. DEVICE OPERATION ---------------------------------------------------------------------------------- 7 5. DATA PROTECTION ------------------------------------------------------------------------------------ 8 6. STATUS REGISTER ------------------------------------------------------------------------------------- 10 3. MEMORY ORGANIZATION 7. COMMANDS DESCRIPTION ------------------------------------------------------------------------- 11 7.1. Write Enable (WREN) (06H) ----------------------------------------------------------------------- 15 7.2. Write Disable (WRDI) (04H) ----------------------------------------------------------------------- 16 7.3. Write Enable for Volatile Status Register (50H) -------------------------------------------------- 17 --------------------------------------------- 18 -------------------------------------------------------------- 19 -------------------------------------------------------------------- 20 7.4. Read Status Register (RDSR) (05H or 35H or 15H) 7.5. Write Status Register (WRSR) (01H) 7.6. Read Data Bytes (READ) (03H) 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) ------------------------------------------- 20 7.8. Dual Output Fast Read (3BH) ---------------------------------------------------------------------- 21 7.9. Quad Output Fast Read (6BH) ---------------------------------------------------------------------- 22 7.10. Dual I/O Fast Read (BBH) -------------------------------------------------------------------------- 22 7.11. Quad I/O Fast Read (EBH) -------------------------------------------------------------------------- 23 7.12. Quad I/O Word Fast Read (E7H) ------------------------------------------------------------------ 25 7.13. Set Burst with Wrap (77H) -------------------------------------------------------------------------- 27 7.14. Page Program (PP) (02H) ---------------------------------------------------------------------------- 27 7.15. Quad Page Program (32H) --------------------------------------------------------------------------- 29 ----------------------------------------------------------------------------- 30 7.16. Sector Erase (SE) (20H) 7.17. 32KB Block Erase (BE) (52H) --------------------------------------------------------------------- 31 7.18. 64KB Block Erase (BE) (D8H) --------------------------------------------------------------------- 32 -------------------------------------------------------------------------- 33 --------------------------------------------------------------------- 34 7.19. Chip Erase (CE) (60/C7H) 7.20. Deep Power-Down (DP) (B9H) 7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH) ------------------------- 35 7.22. Read Manufacture ID/Device ID (REMS) (90H) ------------------------------------------------- 37 7.23. Read Manufacture ID/Device ID Dual I/O (92H) ------------------------------------------------ 38 7.24. Read Manufacture ID/Device ID Quad I/O (94H) ----------------------------------------------- 39 ------------------------------------------------------------------ 40 7.26. Program/Erase Suspend (PES) (75H) -------------------------------------------------------------- 41 7.27. Program/Erase Resume (PER) (7AH) -------------------------------------------------------------- 42 7.25. Read Identification (RDID) (9FH) 62 - 2 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.28. Erase Security Registers (44H) ---------------------------------------------------------------------- 43 ------------------------------------------------------------------ 44 ---------------------------------------------------------------------- 45 ------------------------------------------------------------------------- 46 ----------------------------------------------------------------------- 47 7.33. Enable QPI (38H) ------------------------------------------------------------------------------------ 47 7.34. Disable QPI (FFH) ----------------------------------------------------------------------------------- 48 7.29. Program Security Registers (42H) 7.30. Read Security Registers (48H) 7.31. Set Read Parameters (C0H) 7.32. Burst Read With Wrap (0CH) 7.35. Enable Reset (66H) and Reset (99H) --------------------------------------------------------------- 7.36. Read Serial Flash Discoverable Parameter (5AH) ------------------------------------------------ 50 --------------------------------------------------------------- 55 ------------------------------------------------------------------------------------- 55 ---------------------------------------------------------------------------------- 55 8. ELECTRICAL CHARACTERISTICS 8.1. Power-ON timing 49 8.2. Initial delivery state 8.3. Data retention and endurance 8.4. Latch up characteristics 8.5. Absolute maximum ratings ----------------------------------------------------------------------- 55 ----------------------------------------------------------------------------- 55 ------------------------------------------------------------------------- 56 8.6. Capacitance measurement conditions ------------------------------------------------------------- 56 8.7. DC characteristics ----------------------------------------------------------------------------------- 57 8.8. AC characteristics ----------------------------------------------------------------------------------- 58 9. ORDERING INFORMATION ------------------------------------------------------------------------- 60 10. PACKAGE INFORMATION --------------------------------------------------------------------------- 61 ----------------------------------------------------------------------------- 61 ------------------------------------------------------------------------ 62 10.1. Package SOP8 208MIL 10.2. Package WSON8 (6x5MM) 62 - 3 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 1. FEATURES ♦ 128M-bit Serial Flash ♦ Program/Erase Speed - 16384K-byte - 256 bytes per programmable page ♦ Standard, Dual, Quad SPI, QPI - Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - QPI: SCLK, CS#, IO0, IO1, IO2, IO3 ♦ High Speed Clock Frequency - 133MHz for fast read with 30PF load - Dual I/O Data transfer up to 266Mbits/s - Quad I/O Data transfer up to 532Mbits/s - QPI Mode Data transfer up to 532Mbits/s - Continuous Read With 8/16/32/64-byte Wrap ♦ Software/Hardware Write Protection - Write protect all/portion of memory via software - Enable/Disable protection with WP# pin - Top or Bottom, Sector or Block selection - Page Program time: 0.7ms typical - Sector Erase time: 90ms typical - Block Erase time: 0.3/0.5s typical - Chip Erase time: 100s typical ♦ Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte - Erase/Program Suspend/Resume ♦ Low Power Consumption - 20mA maximum active current - 5μA maximum power down current ♦ Advanced security Features - 64-Bit Customer ID - 3*512-Byte Security Registers With OTP Lock ♦ Single Power Supply Voltage - Full voltage range: 1.65~2.0V ♦ Minimum 100,000 Program/Erase Cycles 62 - 4 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 2. GENERAL DESCRIPTION The GD25LQ128C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 266Mbits/s and the Quad I/O & Quad output data is transferred with speed of 532Mbits/s. Connection Diagram 8-LEAD SOP 8-LEAD WSON Pin Description Pin Name I/O CS# SO (IO1) WP# (IO2) I I/O I/O Chip Select Input Data Output (Data Input Output 1) Write Protect Input (Data Input Output 2) I/O Ground Data Input (Data Input Output 0) VSS SI (IO0) SCLK HOLD# (IO3) VCC Description I I/O Serial Clock Input Hold Input (Data Input Output 3) Power Supply Block Diagram Write Control Logic Status Register HOLD#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 62 - 5 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 3. MEMORY ORGANIZATION GD25LQ128C Each device has Each block has Each sector has Each page has 16M 64/32K 4K 256 bytes 64K 256/128 16 - pages 4096 16/8 - - sectors 256/512 - - - blocks Uniform Block Sector Architecture GD25LQ128C 64K Bytes Block Sector Architecture Block Sector 255 4095 ----- FFF000H ----- FFFFFFH ----- 4080 4079 FF0000H FEF000H FF0FFFH FEFFFFH 254 ----4064 ----- ----FE0000H ----- ----FE0FFFH ----- ----- ------------- ------------- ------------- ----- --------47 --------02F000H --------02FFFFH 2 ----32 ----020000H ----020FFFH 31 01F000H 01FFFFH ----16 ----010000H ----010FFFH 15 ----0 00F000H ----000000H 00FFFFH ----000FFFH 1 0 Address range 62 - 6 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 4. DEVICE OPERATION SPI Mode Standard SPI The GD25LQ128C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25LQ128C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25LQ128C supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read”, “Quad I/O Word Fast Read” “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. QPI The GD25LQ128C supports Quad Peripheral Interface (QPI) operations only when the device is switched ftom Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and after software reset using “Reset (99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. 62 - 7 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 1. Hold Condition CS# SCLK HOLD# HOLD HOLD 5. DATA PROTECTION The GD25LQ128C provides the following data protection methods: ♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: - Power-Up - Write Disable (WRDI) - Write Status Register (WRSR) - Page Program (PP) - Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) - Erase Security Registers / Program Security Registers ♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the memory array that can be read but not change. ♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. ♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Table 1. GD25LQ128C Protected area size (CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 × × 0 0 0 0 0 0 0 1 Blocks NONE 252 to 255 Addresses NONE FC0000H-FFFFFFH Density NONE 256KB Portion NONE Upper 1/64 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 248 to 255 240 to 255 224 to 255 F80000H-FFFFFFH F00000H-FFFFFFH E00000H-FFFFFFH 512KB 1MB 2MB Upper 1/32 Upper 1/16 Upper 1/8 0 0 1 0 1 192 to 255 C00000H-FFFFFFH 4MB Upper 1/4 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 128 to 255 0 to 3 0 to 7 800000H-FFFFFFH 000000H-03FFFFH 000000H-07FFFFH 8MB 256KB 512KB Upper 1/2 Lower 1/64 Lower 1/32 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 to 15 0 to 31 0 to 63 000000H-0FFFFFH 000000H-1FFFFFH 000000H-3FFFFFH 1MB 2MB 4MB Lower 1/16 Lower 1/8 Lower 1/4 0 1 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 62 - 8 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com × × 1 1 1 0 to 255 000000H-FFFFFFH 16MB ALL 1 0 0 0 1 255 FFF000H-FFFFFFH 4KB Top Block 1 0 0 1 0 255 FFE000H-FFFFFFH 8KB Top Block 1 0 0 1 1 255 FFC000H-FFFFFFH 16KB Top Block 1 1 0 0 1 1 0 1 × 0 255 255 FF8000H-FFFFFFH FF8000H-FFFFFFH 32KB 32KB Top Block Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 1 1 0 0 1 1 0 1 0 0 000000H-001FFFH 000000H-003FFFH 8KB 16KB Bottom Block Bottom Block 1 1 1 0 × 0 000000H-007FFFH 32KB Bottom Block 1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block Table 1a. GD25LQ128C Protected area size (CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 × × 0 0 0 0 0 0 0 1 Blocks 0 to 255 0 to 251 Addresses 000000H-FFFFFFH 000000H-FBFFFFH Density ALL 16128KB Portion ALL Lower 63/64 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 to 247 0 to 239 0 to 223 000000H-F7FFFFH 000000H-EFFFFFH 000000H-DFFFFFH 15872KB 15MB 14MB Lower 31/32 Lower 15/16 Lower 7/8 0 0 0 0 1 1 0 1 1 0 0 to 191 0 to 127 000000H-BFFFFFH 000000H-7FFFFFH 12MB 8MB Lower 3/4 Lower 1/2 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 4 to 255 8 to 255 16 to 255 040000H-FFFFFFH 080000H-FFFFFFH 100000H-FFFFFFH 16128KB 15872KB 15MB Upper 63/64 Upper 31/32 Upper 15/16 0 0 0 1 1 1 1 1 1 0 0 1 0 1 0 32 to 255 64 to 255 128 to 255 200000H-FFFFFFH 400000H-FFFFFFH 800000H-FFFFFFH 14MB 12MB 8MB Upper 7/8 Upper 3/4 Upper 1/2 × 1 1 × 0 0 1 0 0 1 0 1 1 1 0 NONE 0 to 255 0 to 255 NONE 000000H-FFEFFFH 000000H-FFDFFFH NONE 16380KB 16376KB NONE Lower 4095/4096 Lower 2047/2048 1 1 1 0 0 0 0 1 1 1 0 1 1 × 0 0 to 255 0 to 255 0 to 255 000000H-FFBFFFH 000000H-FF7FFFH 000000H-FF7FFFH 16368KB 16352KB 16352KB Lower 1023/1024 Lower 511/512 Lower 511/512 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 to 255 0 to 255 0 to 255 001000H-FFFFFFH 002000H-FFFFFFH 004000H-FFFFFFH 16380KB 16376KB 16368KB Upper 4095/4096 Upper 2047/2048 Upper 1023/1024 1 1 1 0 × 0 to 255 008000H-FFFFFFH 16352KB Upper 511/512 1 1 1 1 0 0 to 255 008000H-FFFFFFH 16352KB Upper 511/512 62 - 9 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 6. STATUS REGISTER S15 SUS1 S14 CMP S13 LB3 S12 LB2 S11 LB1 S10 SUS2 S9 QE S8 SRP1 S7 SRP0 S6 BP4 S5 BP3 S4 BP2 S3 BP1 S2 BP0 S1 WEL S0 WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1). becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1 and BP0) bits and CMP are all 0 or all 1. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lockdown or one time programmable protection. SRP1 SRP0 #WP 0 0 × 0 1 0 0 1 1 1 0 × Status Register Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) Hardware Protected WP# = 0, the Status Register locked and can not be written to. WP# = 1, the Status Register is unlocked and can be written to Hardware Unprotected after a Write Enable command, WEL=1. Power Supply Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. Lock-Down(1) One Time Program(2) Status Register is permanently protected and can not be written to. Software Protected 1 1 × NOTE: (1). When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. (2). This feature is available on special order. Please contact ELM for details. 62 - 10 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground). LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. CMP bit. The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bits. The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command as well as a power-down, power-up cycle. 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a dataout sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. 62 - 11 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table 2. Commands (Standard/Dual/Quad SPI) Command Name Byte 1 Byte 2 Write Enable Write Disable Volatile SR Write Enable Read Status Register Read Status Register-1 Write Status Register Read Data Fast Read Dual Output Fast Read 06H 04H 50H 05H 35H 01H 03H 0BH 3BH (S7-S0) (S15-S8) (S7-S0) A23-A16 A23-A16 A23-A16 Dual I/O Fast Read BBH A23-A8 (2) Quad Output Fast Read 6BH Quad I/O Fast Read EBH Quad I/O Word Fast Read (7) E7H A23-A16 A23-A0 M7-M0 (4) A23-A0 M7-M0 (4) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 Page Program 02H Quad Page Program 32H Sector Erase 20H Block Erase (32K) 52H Block Erase (64K) D8H Chip Erase C7/60H Enable QPI 38H Enable Reset 66H Reset 99H Set Burst with Wrap 77H Program/Erase Suspend 75H Program/Erase Resume 7AH Release From Deep Power-Down, ABH And Read Device ID Release From Deep ABH Power-Down B9H Deep Power-Down Manufacturer/Device ID 90H Manufacturer/Device ID 92H by Dual I/O Manufacturer/Device ID 94H by Quad I/O Read Identification 9FH Read Serial Flash 5AH Discoverable Parameter (10) Erase Security Registers (8) 44H Program Security Registers (8) 42H Read Security Registers (8) 48H Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) (S15-S8) A15-A8 A15-A8 A15-A8 A7-A0 M7-M0 (2) A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy (Next byte) (continuous) (D7-D0) (continuous) (D7-D0) (1) (continuous) (D7-D0) (1) A7-A0 (continuous) dummy (D7-D0) (3) (continuous) dummy (5) (D7-D0) (3) (continuous) dummy (6) (D7-D0) (3) (continuous) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) Next byte (D7-D0) (3) dummy dummy dummy (ID7-ID0) dummy dummy A7-A0, M[7:0] W6-W4 A23-A8 A23-A0, M[7:0] (M7-M0) (continuous) 00H (M7- M0) (ID7-ID0) (continuous) (M7-M0) (continuous) (ID7-ID0) (M7-M0) dummy (continuous) (ID7-ID0) (ID15- ID8) (ID7- ID0) (continuous) A23-A16 A15-A8 A7-A0 dummy (D7-D0) A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy (D7-D0) (D7-D0) 62 - 12 (continuous) Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table 2a. Commands (QPI) Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Clock Number (0, 1) (2, 3) (4, 5) (6, 7) (8, 9) (10, 11) (S7-S0) (S15-S8) (S1-S0) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A16 (S15-S8) A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) Next byte P7-P0 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 dummy dummy M7-M0 (D7-D0) (D7-D0) (D7-D0) dummy dummy dummy (ID7- ID0) dummy (M7-M0) dummy (ID15- ID8) 00H (ID7- ID0) (M7- M0) (ID7-ID0) A23-A16 A15-A8 A7-A0 dummy (D7-D0) Write Enable 06H Volatile SR Write Enable 50H Write Disable 04H Read Status Register 05H Read Status Register-1 35H Read Status Register-2 15H Write Status Register 01H Page Program 02H Sector Erase 20H Block Erase (32K) 52H Block Erase (64K) D8H Chip Erase C7/60H Program/Erase Suspend 75H Program/Erase Resume 7AH Deep Power-Down B9H Set Read Parameters C0H Fast Read 0BH Burst Read with Wrap 0CH Quad I/O Fast Read EBH Release From Deep Power-Down, ABH and Read Device ID Manufacturer/Device ID 90H Read Identification 9FH Read Serial Flash 5AH Discoverable Parameter (10) Disable QPI FFH Enable Reset 66H Reset 99H NOTE: (1) Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) (2) Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A6, A4, A2, A0, M6, M4, M2, M0 A7, A5, A3, A1, M7, M5, M3, M1 (3) Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 62 - 13 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com (4) Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 (5) Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) (6) Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) (7) Fast Word Read Quad I/O Data: the lowest address bit must be 0. (8) Security Registers Address: Security Register1: A23-A16=00H, A15-A9=000100b, A8-A0=Byte Address; Security Register2: A23-A16=00H, A15-A9=001000b, A8-A0=Byte Address; Security Register3: A23-A16=00H, A15-A9=001100b, A8-A0=Byte Address. (9) QPI Command, Address, Data input/output format: CLK #0 1 IO0 = C4, C0, IO1 = C5, C1, IO2 = C6, C2, IO3 = C7, C3, 2 3 A20, A16, A21, A17, A22, A18, A23, A19, 4 5 A12, A8, A13, A9, A14, A10, A15, A11, 6 7 A4, A0, A5, A1, A6, A2, A7, A3, 8 9 D4, D0, D5, D1, D6, D2, D7, D3, 10 11 D4, D0 D5, D1 D6, D2 D7, D3 (10) Read Serial Flash Discoverable Parameter (SFDP) command is available on special order. Please contact ELM if this function is needed. Table of ID Definitions: GD25LQ128C Operation Code 9FH 90H ABH M7-M0 ID15-ID8 ID7-ID0 C8 C8 60 18 17 17 62 - 14 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.1. Write Enable (WREN)(06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS# goes high. Figure 2. Write Enable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 06H High-Z Figure 2a. Write Enable Sequence Diagram (QPI) CS# SCLK 0 1 Command 06H IO0 IO1 IO2 IO3 62 - 15 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure 3. Write Disable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 04H High-Z Figure 3a. Write Disable Sequence Diagram (QPI) CS# SCLK 0 1 Command 04H IO0 IO1 IO2 IO3 62 - 16 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure 4. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z Figure 4a. Write Enable for Volatile Status Register Sequence Diagram (QPI) CS# SCLK 0 1 Command 50H IO0 IO1 IO2 IO3 62 - 17 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”/“35H”, the SO will output Status Register bits S7~S0/S15~S8. The command code “15H” only supports the QPI mode, the I/O0 will output Status Register S1-S0. (For 133MHz Frequency, the 15H will better than 05H to check the WIP bit.) Figure 5. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Command 05H or 35H High-Z 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 MSB 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 7 MSB Figure 5a. Read Status Register Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 Command 05H or 35H IO0 4 0 4 0 4 IO1 5 1 5 1 5 IO2 6 2 6 2 6 IO3 7 3 7 3 7 S7-S0 or S15-S8 out Figure 5b. Read Status Register Sequence Diagram (QPI)(15H) CS# SCLK 0 1 2 3 4 5 Command 15H IO0 S1 S0 S1 S0 S1-S0 out IO1 IO2 IO3 62 - 18 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.5. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bits will be cleared to 0 in SPI mode, while only CMP will be cleared to 0 in QPI mode. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure 6. Write Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 8 Command SI 01H Status Register in MSB SO 2 3 4 5 6 7 1 0 15 14 13 12 11 10 9 8 High-Z Figure 6a. Write Status Register Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 Command 01H IO0 4 0 12 8 IO1 5 1 13 9 IO2 6 2 14 10 IO3 7 3 15 11 Status Register in 62 - 19 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.6. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 7. Read Data Bytes Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 Command 03H High-Z 9 10 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 23 22 21 3 2 1 0 MSB MSB 7 6 5 Data Out1 4 3 2 1 Data Out2 0 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 8. Read Data Bytes at Higher Speed Sequence Diagram 62 - 20 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Fast Read (0BH) in QPI mode The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. Figure 8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI) CS# 0 SCLK 1 2 3 4 5 6 7 Command 0BH IO0 A23-16 A15-8 20 16 12 8 A7-0 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 11 8 9 10 11 12 13 IOs switch from Input to output Dummy* 4 0 4 0 4 0 4 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 Byte2 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.8. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 9. Dual Output Fast Read Sequence Diagram 62 - 21 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.9. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 10. Quad Output Fast Read Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 Command SI(IO0) 24-bit address 6BH High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z SCLK 3 23 22 21 SO(IO1) CS# 28 29 30 31 2 1 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 7.10. Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. 62 - 22 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) BBH SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure 11a. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0 )) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 5 3 1 7 7 A23-16 A15-8 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 7.11. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. 62 - 23 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure 12. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) CS# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 0 SCLK 1 2 3 4 5 6 7 Command SI(IO0) EBH A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure 12a. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. 62 - 24 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. Quad I/O Fast Read (EBH) in QPI mode The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used. Figure 12b. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0) QPI) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IOs switch from Input to output Command EBH IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 A23-16 A15-8 A7-0 M7-0* Byte1 Byte2 Byte3 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.12. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode” 62 - 25 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure 13. Quad I/O Word Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Figure 13a. Quad I/O Word Fast Read Sequence Diagram (M5-4 = (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 62 - 26 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.13. Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send 24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high. W6, W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 Yes 8-byte No N/A 0, 1 1, 0 1, 1 Yes Yes Yes 16-byte 32-byte 64-byte No No No N/A N/A N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command. Figure 14. Set Burst with Wrap Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK Command SI(IO0) 77H W6-W4 7.14. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Program 62 - 27 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com command → 3-byte address on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is shown in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) is not executed. Figure 15. Page Program Sequence Diagram Figure 15a. Page Program Sequence Diagram (QPI) 2 3 4 5 6 7 8 9 10 11 12 13 519 1 518 0 517 SCLK 516 CS# Command A23-16 A15-8 20 16 12 8 A7-0 4 0 Byte1 Byte2 Byte3 IO0 4 0 4 0 4 0 4 0 4 0 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 02H 62 - 28 Byte255 Byte256 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.15. Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2 and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE = 1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Quad Page Program command is entered by driving CS# Iow, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in, otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) is not executed. Figure 16. Quad Page Program Sequence Diagram CS# 1 0 SCLK 2 3 4 5 6 8 7 24-bit address Command 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 537 542 543 Byte1 Byte2 0 4 538 SI(IO0) 28 29 30 31 32 33 34 35 36 37 38 39 9 10 23 22 21 32H 2 3 1 MSB SO(IO1) 540 541 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 SCLK 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Byte11 Byte12 62 - 29 536 539 CS# Byte256 Byte253 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.16. Sector Erase (SE) (20H) The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-byte address on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed. Figure 17. Sector Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB 20H 1 2 0 Figure 17a. Sector Erase Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 6 7 Command 20H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 62 - 30 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.17. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte address on SI→ CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed. Figure 18. 32KB Block Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB 52H 1 2 0 Figure 18a. 32KB Block Erase Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 6 7 Command 52H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 62 - 31 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.18. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed. Figure 19. 64KB Block Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB D8H 2 1 0 Figure 19a. 64KB Block Erase Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 6 5 7 Command A23-16 A15-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 D8H 62 - 32 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.19. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1 and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure 20. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 60H or C7H Figure 20a. Chip Erase Sequence Diagram (QPI) CS# SCLK 0 1 Instruction IO0 C7H/60H IO1 IO2 IO3 62 - 33 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.20. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep PowerDown Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 21. Deep Power-Down Sequence Diagram CS# SCLK SI tDP 0 1 2 3 4 5 6 7 Command Stand-by mode Deep Power-down mode B9H Figure 21a. Deep Power-Down Sequence Diagram (QPI) CS# SCLK IO0 0 tDP 1 Command B9H IO1 IO2 IO3 Stand-by mode 62 - 34 Deep Power-down mode Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash 7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH) http://www.elm-tech.com The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25LQ128C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 22. Release Power-Down Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 t RES1 7 Command SI ABH Deep Power-down mode Stand-by mode Figure 22a. Release Power-Down Sequence Diagram (QPI) CS# SCLK IO0 0 1 tRES1 Command ABH IO1 IO2 IO3 Deep Power-down mode 62 - 35 Stand-by mode Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 23. Release Power-Down and Read Device ID Sequence Diagram Figure 23a. Release Power-Down and Read Device ID Sequence Diagram (QPI) CS# SCLK 0 1 Command ABH 2 3 4 5 6 7 tRES2 8 IOs switch from Input to Output 3 Dummy Bytes IO0 4 0 IO1 5 1 IO2 6 2 IO3 7 3 Device ID Deep Power-down mode 62 - 36 Stand-by mode Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.22. Read Manufacture ID/Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 24. Read Manufacture ID/Device ID Sequence Diagram Figure 24a. Read Manufacture ID/Device ID Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 6 5 Command 9 8 7 10 IOs switch from Input to Output IO0 20 16 12 8 A7-0 (00H) 4 0 IO1 21 17 13 9 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 IO3 23 19 15 7 3 7 3 7 3 90H A23-16 A15-8 11 4 0 4 0 MID 62 - 37 Device ID Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.23. Read Manufacture ID/Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down/ Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 25. Read Manufacture ID/Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) 92H SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 SO(IO1) 7 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID Device ID 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID (Repeat) Device ID (Repeat) 62 - 38 4 2 0 6 4 2 0 5 3 1 7 5 3 1 MFR ID (Repeat) Device ID (Repeat) Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.24. Read Manufacture ID/Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down/ Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 26. Read Manufacture ID/Device ID Quad I/O Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 SCLK Command SI(IO0) 94H A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID CS# SCLK 24 25 26 27 28 29 30 31 SI(IO0) 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 62 - 39 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.25. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure 27. Read Identification ID Sequence Diagram CS# 0 SCLK SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 9FH SO MSB CS# Manufacturer ID 5 4 3 2 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI 7 SO Memory Type ID15-ID8 6 5 4 3 2 1 0 MSB Capacity ID7-ID0 6 5 4 3 2 1 7 0 MSB Figure 27a. Read Identification ID Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 6 IOs switch from Input to Output Command 9FH IO0 4 0 12 8 4 0 IO1 5 1 13 9 5 1 IO2 6 2 14 10 6 2 IO3 7 3 15 11 7 3 MID 62 - 40 ID15-8 ID7-0 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.26. Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase Security Registers (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is ongoing. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared form 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure28. Figure 28. Program/Erase Suspend Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 tSUS Command 75H High-Z Accept read command Figure 28a. Program/Erase Suspend Sequence Diagram (QPI) CS# SCLK IO0 0 1 tSUS Command 75H IO1 IO2 IO3 Accept Read 62 - 41 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.27. Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure29. Figure 29. Program/Erase Resume Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 7AH SO Resume Erase/Program Figure 29a. Program/Erase Resume Sequence Diagram (QPI) CS# SCLK IO0 0 1 Command 7AH IO1 IO2 IO3 Resume previously suspended program or Erase 62 - 42 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.28. Erase Security Registers (44H) The GD25LQ128C provides three 512-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command → CS# goes high. The command sequence is shown in Figure30. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address A23-16 A15-12 A11-9 A8-0 Security Register #1 00H 0001 000 Do not care Security Register #2 Security Register #3 00H 00H 0010 0011 000 000 Do not care Do not care Figure 30. Erase Security Registers command Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 44H 29 30 31 24 Bits Address Command SI 9 23 22 MSB 62 - 43 2 1 0 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.29. Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-16 A15-12 A11-9 A8-0 Security Register #1 00H 0001 000 Do not care Security Register #2 00H 0010 000 Do not care Security Register #3 00H 0011 000 Do not care Figure 31. Program Security Registers command Sequence Diagram CS# 5 6 7 8 24-bit address 3 23 22 21 2 Data Byte 1 0 7 1 MSB 6 5 4 3 2 1 2078 42H 2079 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 9 10 2076 4 2077 3 2075 2 1 0 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 2073 1 2074 0 SCLK SCLK SI Data Byte 3 Data Byte 2 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 MSB Data Byte 256 1 0 7 6 5 4 3 2 MSB 62 - 44 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.30. Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. Address A23-16 A15-12 A11-9 A8-0 Security Register #1 Security Register #2 Security Register #3 00H 00H 00H 0001 0010 0011 000 000 000 Do not care Do not care Do not care Figure 32. Read Security Registers command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 28 29 30 31 24-bit address Command SI 9 10 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Byte 7 6 5 4 3 2 1 0 7 6 MSB 62 - 45 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.31. Set Read Parameters (C0H) In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode. P5-P4 Dummy Clocks Maximum Read Freq. P1-P0 Wrap Length 00 4 80MHz 00 8-byte 01 10 11 6 8 8 108MHz 133MHz 133MHz 01 10 11 16-byte 32-byte 64-byte Figure 33. Set Read Parameters command Sequence Diagram CS# SCLK 0 1 Command C0H 2 3 Read Parameters IO0 P4 P0 IO1 P5 P1 IO2 P6 P2 IO3 P7 P3 62 - 46 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.32. Burst Read with Wrap (0CH) The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command. Figure 34. Burst Read with Wrap command Sequence Diagram CS# 0 SCLK 1 2 3 4 6 5 7 8 9 10 11 12 13 14 IOs switch from Input to output Command 0CH IO0 20 16 12 8 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 23 19 15 11 7 3 7 3 7 3 7 IO3 A23-16 A15-8 A7-0 Dummy* Byte1 Byte2 Byte3 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.33. Enable QPI (38H) The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure 35. Enable QPI mode command Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 38H 62 - 47 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.34. Disable QPI (FFH) To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure 36. Disable QPI mode command Sequence Diagram CS# SCLK 0 1 Command FFH IO0 IO1 IO2 IO3 62 - 48 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.35. Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H)”command sequence as follow: CS# goes low → Sending Enable Reset command → CS# goes high → CS# goes low → Sending Reset command → CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST=30µs to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 37. Enable Reset and Reset command Sequence Diagram Figure 38. Enable Reset and Reset command Sequence Diagram 7.34. ReadFigure Serial Flash Discoverable (5AH) Diagram (QPI) 37a. Enable Reset and ResetParameter command Sequence CS# SCLK 0 0 1 Command 66H 1 Command 99H IO0 IO1 IO2 IO3 62 - 49 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.36. Read Serial Flash Discoverable Parameter (5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. Figure 38. Read Serial Flash Discoverable Parameter command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 10 24-bit address Command SI 28 29 30 31 23 22 21 5AH 2 3 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI Dummy Byte 7 5 6 4 3 2 1 0 SO Data Out1 5 4 3 2 7 6 MSB 1 0 Data Out2 7 6 5 MSB Figure 38a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 5 6 7 Command 5AH IO0 A23-16 A15-8 20 16 12 8 A7-0 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 11 8 9 10 11 12 13 IOs switch from Input to output Dummy* 4 0 4 0 4 0 4 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 62 - 50 Byte2 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table 3. Signature and Parameter Identification Data Values Description Comment Add(H) DW Add (Byte) (Bit) Data Data 00H 07:00 53H 53H 01H 02H 15:08 23:16 46H 44H 46H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H Contains 0×FFH and can never be Unused changed 06H 23:16 01H 01H 07H 31:24 FFH FFH 00H: It indicates a JEDEC specified header 08H 07:00 00H 00H Start from 0×00H 09H 15:08 00H 00H Start from 0×01H 0AH 23:16 01H 01H How many DWORDs in the Parameter table 0BH 31:24 09H 09H 0CH 0DH 07:00 15:08 30H 00H 30H 00H 0EH 23:16 00H 00H Contains 0×FFH and can never be changed 0FH 31:24 FFH FFH It is indicates ELM manufacturer ID 10H 07:00 C8H C8H Start from 0×00H 11H 15:08 00H 00H Parameter Table Major Revision Number Start from 0×01H 12H 23:16 01H 01H Parameter Table Length (in double word) How many DWORDs in the Parameter table 13H 31:24 03H 03H 14H 15H 16H 07:00 15:08 23:16 60H 00H 00H 60H 00H 00H 17H 31:24 FFH FFH SFDP Signature ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Fixed: 50444653H First address of JEDEC Flash Parameter Table Pointer (PTP) Parameter table Unused ID Number LSB (ELM Manufacturer ID) Parameter Table Minor Revision Number First address of ELM Flash Parameter Parameter Table Pointer (PTP) table Unused Contains 0×FFH and can never be changed 62 - 51 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table 4. Parameter Table (0): JEDEC Flash Parameter Tables Description Block/Sector Erase Size Comment Add(H) DW Add Data (Byte) (Bit) 00: Reserved; 01: 4KB erase; 10: Reserved; 11: Not support 4KB erase Write Granularity Write Enable Instruction Requested for Writing to Volatile Status Registers 0: 1Byte; 1: 64Byte or larger. 0: Nonvolatile status bit; 1: Volatile status bit (BP status register bit). 0: Use 50H Opcode; 1: Use 06H Opcode. Write Enable Opcode Select Note: for Writing to Volatile Status If target flash status register is Nonvolatile, Registers then bits 3 and 4 must be set to 00b. Unused Contains 111b and can never be changed. 4KB Erase Opcode 30H 31H (1-1-2) Fast Read 0=Not support; 1=Support. Address Bytes Number used 00: 3Byte only; 01: 3 or 4Byte; 10: 4Byte only; 11: Reserved. in addressing flash array Double Transfer Rate (DTR) 0=Not support; 1=Support. clocking (1-2-2) Fast Read 0=Not support; 1=Support. (1-4-4) Fast Read (1-1-4) Fast Read Unused 0=Not support; 1=Support. 0=Not support; 1=Support. Unused Flash Memory Density (1-4-4) Fast Read Number of Wait states (1-4-4) Fast Read Number of Mode Bits (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait states (1-1-4) Fast Read Number of Mode Bits (1-1-4) Fast Read Opcode (1-1-2) Fast Read Number of Wait states (1-1-2) Fast Read Number of Mode Bits (1-1-2) Fast Read Opcode 32H 33H 37H:34H 0 0000b: Wait states (Dummy Clocks) not support. 1b 03 0b 04 0b 07:05 15:08 111b 20H 16 1b 18:17 00b 19 0b 20 1b 21 22 23 1b 1b 1b 31:24 31:00 3BH 3DH 20H F1H 00100b 44H 07:05 010b 15:08 EBH 20:16 01000b 23:21 000b 31:24 6BH 04:00 01000b EBH 08H 3CH 000b: Mode Bits not support. E5H FFH FFH 07FFFFFFH 3AH 000b: Mode Bits not support. 62 - 52 02 38H 39H 0 0000b: Wait states (Dummy Clocks) not support. 01b 04:00 000b: Mode Bits not support. 0 0000b: Wait states (Dummy Clocks) not support. 01:00 Data 6BH 08H 07:05 000b 15:08 3BH 3BH Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com (1-2-2) Fast Read Number of Wait states (1-2-2) Fast Read Number of Mode Bits 0 0000b: Wait states (Dummy Clocks) not support. (2-2-2) Fast Read 3FH 0=not support; 1=support. Unused (4-4-4) Fast Read Unused Unused Unused (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits (4-4-4) Fast Read Opcode Sector Type 1 Size 0=not support; 1=support. Sector/block size=2^N bytes 0×00b: this sector type don’t exist. Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N bytes 0×00b: this sector type don’t exist. Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size=2^N bytes 0×00b: this sector type don’t exist. Sector Type 4 erase Opcode 62 - 53 31:24 BBH 00 0b 03:01 111b 04 07:05 1b 111b 42H BBH FEH 31:08 15:00 0×FFH 0×FFH 0×FFH 0×FFH 20:16 00000b 00H 000b 31:24 15:00 FFH FFH 0×FFH 0×FFH 20:16 00100b 23:21 010b 4BH 31:24 EBH EBH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH 4AH 000b: Mode Bits not support. Sector/block size=2^N bytes 0×00b: this sector type don’t exist. 010b 23:21 47H 49H:48H 0 0000b: Wait states (Dummy Clocks) not support. 23:21 46H 000b: Mode Bits not support. Sector Type 1 erase Opcode Sector Type 2 Size 40H 43H:41H 45H:44H 0 0000b: Wait states (Dummy Clocks) not support. 00010b 3EH 000b: Mode Bits not support. (1-2-2) Fast Read Opcode 20:16 44H (1) Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table 5. Parameter Table (1): ELM Flash Parameter Tables Description Comment Add(H) DW Add Data (Byte) (Bit) Data Vcc Supply Maximum Voltage 2000H=2.000V 2700H=2.700V 3600H=3.600V 61H:60H 15:00 2000H 2000H Vcc Supply Minimum Voltage 1650H=1.650V 2250H=2.250V 2350H=2.350V 2700H=2.700V 63H:62H 31:16 1650H 1650H HW Reset# pin 0=not support; 1=support 00 0b HW Hold# pin Deep Power Down Mode SW Reset 0=not support; 1=support 0=not support; 1=support 0=not support; 1=support 01 02 03 1b 1b 1b 11:04 99H 12 1b Program Suspend/Resume Should be issue Reset Enable(66H) before Reset cmd. 0=not support; 1=support Erase Suspend/Resume 0=not support; 1=support 13 1b Unused 0=not support; 1=support Wrap-Around Read mode Wrap-Around Read mode Opcode 14 15 1b 1b 66H 23:16 77H 77H 67H 31:24 64H 64H 00 0b 01 0b 09:02 FFH 10 0b 11 1b 12 13 0b 1b SW Reset Opcode Wrap-Around Read data length Individual block lock Individual block lock bit (Volatile/Nonvolatile) 08H: support 8B wrap-around read 16H: 8B & 16B 32H: 8B & 16B & 32B 64H: 8B & 16B & 32B & 64B 0=not support; 1=support 65H:64H 0=Volatile; 1=Nonvolatile Individual block lock Opcode Individual block lock Volatile protect bit default protect status Secured OTP 0=protect; 1=unprotect Read Lock Permanent Lock 0=not support; 1=support 0=not support; 1=support 0=not support; 1=support Unused Unused 6BH:68H 15:14 31:16 62 - 54 F99EH EBFCH 11b FFFFH FFFFH Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8. ELECTRICAL CHARACTERISTICS 8.1. Power-On Timing Figure 39. Power-On Timing Sequence Diagram Table 6. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min tVSL VCC(min) To CS# Low 10 tPUW VWI Time Delay From VCC(min) to Write Instruction Write Inhibit Voltage VCC(min) 1 1 Max Unit us 10 1.4 ms V 8.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status Register contains 00H (all Status Register bits are 0). 8.3. Data Retention and Endurance Parameter Minimum Pattern Data Retention Time Erase/Program Endurance Test Condition Min Unit 150°C 10 Years 125°C -40 to 85°C 20 100K Years Cycles 8.4. Latch Up Characteristics Parameter Input Voltage Respect To VSS On I/O Pins VCC Current 62 - 55 Min Max -1.0V VCC+1.0V -100mA 100mA Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8.5. Absolute Maximum Ratings Parameter Value Unit -40 to 85 °C -65 to 150 °C Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.6 to VCC+0.4 V VCC -0.6 to VCC+ 0.4 V Ambient Operating Temperature Storage Temperature Figure 40. Absolute Maximum Ratings Diagram 0.8VCC Input timing reference level 0.7VCC 0.3VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time ara<5ns 8.6. Capacitance Measurement Conditions Symbol CIN COUT CL Parameter Min Typ Max Unit Conditions Input Capacitance 6 pF VIN=0V Output Capacitance Load Capacitance Input Rise And Fall time Input Pause Voltage 8 VOUT=0V 5 pF pF ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC V V 0.5VCC V 30 Input Timing Reference Voltage Output Timing Reference Voltage Figure 41. Input Test Waveform and Measurement Level Maximum Negative Maximum Overshoot Negative Waveform Overshoot Waveform 0V 0V -0.6V -0.6V 20ns Maximum Positive Maximum Overshoot Positive Waveform Overshoot Waveform 20ns 62 - 56 2.35V 2.35V 1.95V 1.95V 20ns 20ns Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8.7. DC Characteristics (T= -40°C~85°C, VCC=1.65~2.0V) Symbol Parameter Test Condition Min. Typ. Max. Unit. ILI Input Leakage Current ±2 μA ILO Output Leakage Current ±2 μA ICC1 Standby Current CS#=VCC, VIN=VCC or VSS 35 50 μA ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS 1 5 μA CLK=0.1VCC/0.9VCC at 133MHz, Q=Open(*1,*2,*4 I/O) 15 20 mA CLK=0.1VCC/0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) 13 18 mA 20 20 mA mA 20 20 0.3VCC mA mA V VCC+0.4 0.2 V V V ICC3 Operating Current (Read) ICC4 ICC5 Operating Current (PP) CS#=VCC Operating Current (WRSR) CS#=VCC ICC6 ICC7 VIL Operating Current (SE) Operating Current (BE) Input Low Voltage VIH VOL VOH Input High Voltage Output Low Voltage Output High Voltage CS#=VCC CS#=VCC -0.5 0.7VCC IOL=100μA IOH=-100μA VCC-0.2 62 - 57 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8.8. AC Characteristics Symbol (T= -40°C~85°C, VCC=1.65~2.0V, CL=30pf) Parameter Min. Typ. Max. Unit. fC Serial Clock Frequency For: all command except for 03H DC. 133 MHz fR DC. 3.5 80 tCLH Serial Clock Frequency For: Read(03H) Serial Clock High Time MHz ns tCLL Serial Clock Low Time 3.5 ns 0.2 0.2 V/ns V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time tSHCH CS# Not Active Setup Time 5 5 ns ns tCHSL CS# Not Active Hold Time tSHSL CS# High Time (Read/Write) 5 20 ns ns tCLCH Serial Clock Rise Time (Slew Rate) tCHCL Serial Clock Fall Time (Slew Rate) tSHQZ Output Disable Time 6 tCLQX Output Hold Time tDVCH Data In Setup Time ns 1.2 2 ns ns tCHDX Data In Hold Time tHLCH Hold# Low Setup Time (Relative to Clock) 2 5 ns ns tHHCH Hold# High Setup Time (Relative to Clock) 5 ns tCHHL Hold# High Hold Time (Relative to Clock) tCHHH Hold# Low Hold Time (Relative to Clock) tHLQZ Hold# Low To High-Z Output 5 5 ns ns ns 6 tHHQX Hold# Low To Low-Z Output tCLQV Clock Low To Output Valid tWHSL Write Protect Setup Time Before CS# Low 6 7 20 tSHWL Write Protect Hold Time After CS# High tDP CS# High To Deep Power-Down Mode 100 20 ns μs 20 20 20 μs μs μs 5 0.7 90 30 2.4 1000 ms ms ms 0.3/0.5 100 1.2/1.5 200 s s tRES1 CS# High To Standby Mode Without Electronic Signature Read tRES2 CS# High To Standby Mode With Electronic Signature Read tSUS CS# High To Next Command After Suspend tW tPP tSE Write Status Register Cycle Time Page Programming Time Sector Erase Time tBE tCE Block Erase Time(32K Bytes/64K Bytes) Chip Erase Time(GD25LQ128C) 62 - 58 ns ns ns Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 42. Serial Input Timing tSHSL CS# tCHSL SCLK tSLCH tDVCH tCHSH MSB SO High-Z tCHCL tCLCH tCHDX SI tSHCH LSB Figure 43. Output Timing CS# tCLH SCLK tCLQV tCLQX tCLQV tSHQZ tCLL tCLQX LSB SO SI Least significant address bit (LIB) in Figure 44. Hold Timing CS# SCLK SO tCHHL tHLCH tCHHH tHLQZ tHHCH tHHQX HOLD# SI do not care during HOLD operation. 62 - 59 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 9. ORDERING INFORMATION GD 25 LQ 128 C x I G x Packing Type Y: Tray R: Tape & Reel Green Code G: Pb Free & Halogen Free Green Package Temperature Range I: Industrial(-40°C to +85°C) Package Type S: SOP8 208mil W: WSON8 (6×5mm) Generation C: C Version Density 128: 128Mb Series LQ: 1.8V, 4KB Uniform Sector Product Family 25: SPI Interface Flash 62 - 60 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 10. PACKAGE INFORMATION 10.1. Package SOP8 208MIL 8 � 5 E1 E L1 L 1 4 C D A2 Dimensions Symbol Unit A1 b e A A A1 A2 b C D E E1 e L L1 θ Min - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0° Nom Max Min 2.16 - 0.15 0.25 0.002 1.80 1.91 0.067 0.41 0.51 0.012 0.21 0.25 0.007 5.23 5.33 0.202 7.90 8.10 0.303 5.28 5.38 0.204 1.27 - 0.67 0.85 0.020 1.31 1.41 0.048 5° 8° 0° Nom 0.006 0.071 0.016 0.008 0.206 0.311 Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 Note: Both package length and width do not include mold flash. 0.208 0.212 0.050 - 0.026 0.033 0.052 0.056 5° 8° mm Inch 62 - 61 Rev.1.0 GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 10.2. Package WSON8 (6×5mm) D A2 y E A Top View L A1 Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit A A1 A2 b D D1 E E1 e y L mm Min Nom 0.70 0.75 - 0.19 0.22 0.35 0.42 5.90 6.00 3.25 3.37 4.90 5.00 3.85 3.97 1.27 BSC 0.00 0.04 0.50 0.60 Inch Max Min Nom 0.80 0.028 0.030 0.05 - 0.25 0.007 0.009 0.48 0.014 0.016 6.10 0.232 0.236 3.50 0.128 0.133 5.10 0.193 0.197 4.10 0.151 0.156 0.05 BSC 0.08 0.000 0.001 0.75 0.020 0.024 Max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030 Note: 1. Both package length and width do not include mold flash. 2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin), so both Floating and connecting GND of exposed pad are also available. 62 - 62 Rev.1.0