PIC16(L)F183XX PIC16(L)F183XX Memory Programming Specification 1.0 OVERVIEW The PIC16(L)F183XX Memory Programming Specification describes the method for programming the 8-bit PIC16(L)F183XX family of microcontrollers. The programming specification describes the programming commands, programming algorithms and electrical specifications which are necessary for programming. Part-specific information can be found in the Appendix sections (Appendix B to Appendix E). Each appendix contains individual part numbers, device identification and checksum values, pinout and packaging information and Configuration Words. Table 1-1 below lists specific part numbers. TABLE 1-1: 1.1 DEVICE APPENDIX LOCATION Device Appendix PIC16(L)F18313 Appendix B PIC16(L)F18323 Appendix B PIC16(L)F18324 Appendix C PIC16(L)F18325 Appendix D PIC16(L)F18326 Appendix E PIC16(L)F18344 Appendix C PIC16(L)F18345 Appendix D PIC16(L)F18346 Appendix E Programming Data Flow Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be programmed into the Program Flash Memory, EEPROM and the Configuration Words. 1.2 Write and/or Erase Selection Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terms are defined in Table 1-2 and are detailed below. TABLE 1-2: PROGRAMMING TERMS Term Definition Programmed Cell A memory cell with a logic ‘0’ Erased Cell A memory cell with a logic ‘1’ Erase Change memory cell from a ‘0’ to a ‘1’ Write Change memory cell from a ‘1’ to a ‘0’ Program Generic Erase and/ or Write 1.2.1 ERASING MEMORY Memory is erased by row or in bulk, where ‘bulk’ includes many subsets of the total memory space. The duration of the erase is always determined internally. All Bulk ICSP Erase commands have minimum VDD requirements, which prevent breach of code protection by ensuring sufficient VDD voltages. 1.2.2 WRITING MEMORY Memory is written one row at a time. Multiple load data for NVM commands are used to fill the row data latches. The duration of the write can be determined either internally or externally. 2014-2016 Microchip Technology Inc. DS40001738D-page 1 PIC16(L)F183XX 1.2.3 MULTI-WORD PROGRAMMING INTERFACE Program Flash memory panels include up to a 32-word (one row) programming interface. The row to be programmed must first be erased either with a Bulk Erase or a Row Erase. 1.3 Hardware Requirements 1.3.1 HIGH-VOLTAGE ICSP PROGRAMMING In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/ VPP pin. 1.3.2 LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the operating range. The MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. 1.3.2.1 Single-Supply ICSP Programming The LVP bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a ‘1’ (enabled) from the factory. The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode, where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. 2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port pin can no longer be used as a general purpose input. 1.4 Pin Utilization Five pins are needed for ICSP programming. The pins are listed in Table 1-3. For pin locations and packaging information please refer to Table B-2 through Table E-2. TABLE 1-3: PIN DESCRIPTIONS DURING PROGRAMMING During Programming Pin Name Function Pin Type ICSPCLK ICSPCLK I ICSPDAT ICSPDAT I/O Pin Description Clock Input – Schmitt Trigger Input Data Input/Output – Schmitt Trigger Input Program/Verify mode P(1) VDD VDD P Power Supply VSS VSS P Ground MCLR/VPP Program Mode Select Legend: I = Input, O = Output, P = Power Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current. DS40001738D-page 2 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 2.0 MEMORY MAP FIGURE 2-1: PROGRAM MEMORY MAPPING PIC16(L)F18313/18323 2K Program Flash Memory PIC16(L)F18324/18344 4K Program Flash Memory PIC16(L)F18325/18345 8K Program Flash Memory PIC16(L)F18326/18346 16K Program Flash Memory PC<14:0> PC<14:0> PC<14:0> PC<14:0> Note 1 Stack (16 levels) Stack (16 levels) Stack (16 levels) Stack (16 levels) 0000h Reset Vector Reset Vector Reset Vector Reset Vector ••• ••• ••• ••• 0004h Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector 0005h • 07FFh Program Flash Memory 0800h • 0FFFh Program Flash Memory 1000h • 2000h • • Not present Roll over to 0000h - 07FFh Program Flash Memory 1FFFh Not present Roll over to 0000h - 0FFFh 3FFFh 4000h Not present Roll over to 0000h - 1FFFh 7FFFh 8000h ••• 8003h 8004h 0004h 0005h • 07FFh 1000h • 1FFFh 0000h ••• Program Flash Memory 0800h • 0FFFh Note 1 2000h • • Not present Roll over to 0000h - 3FFFh 3FFFh 4000h 7FFFh 8000h ••• 8003h User IDs(2) Reserved ICD Halt Entry Instruction 8004h 8005h Revision ID(2,3) 8005h 8006h Device ID(2,3) 8006h 8007h ••• 800Ah Configuration Word 1,2,3,4(2,4) 8007h ••• 800Ah 800Bh ••• 801Dh Unimplemented 801Eh 801Fh 8600h 8601h ••• 87FFh 800Bh ••• 801Dh 801Eh 801Fh Reserved Unimplemented 8600h 8601h ••• 87FFh E000h ••• E003h Calibration Words 1,2,3,4(2,4) E000h ••• E003h E800h ••• E81Fh Unimplemented E800h ••• E81Fh F000h ••• F0FFh User Data EEPROM F000h ••• F0FFh 2014-2016 Microchip Technology Inc. DS40001738D-page 3 PIC16(L)F183XX 2.1 User ID Location A user may store identification information (User ID) in four designated locations. The User ID locations are mapped to 8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location may be read with code protection enabled or disabled. 2.2 Device/Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. REGISTER 2-1: R R DEVICEID: DEVICE ID REGISTER(1) R R R R R R R R R R R R DEV<13:0> bit 13 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 13-0 DEV<13:0>: Device ID bits Refer to Table B-1 through Table E-1 to determine what these bits will read on each device. A value of 3FFFh or 0000h is invalid. Note 1: This location cannot be written. REGISTER 2-2: R R REVISIONID: REVISION ID REGISTER(1) R R R R R R R R R R R R REV<13:0> bit 13 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 13-0 REV<13:0>: Revision ID bits These bits are used to identify the device revision. Note 1: This location cannot be written. DS40001738D-page 4 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 2.3 Configuration Words The devices have several Configuration Words starting at address 8007h. The individual bits within these Configuration Words are critical to the correct operation of the system. Configuration bits enable or disable specific features, placing these controls outside the normal software process, and they establish configured values prior to the execution of any software. In terms of programming, these important Configuration bits should be considered: 1. LVP: Low-Voltage Programming Enable bit • 1 = ON – Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. • 0 = OFF – HV on MCLR/VPP must be used for programming. It is important to note that the LVP bit cannot be written (to 0) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating LVP mode from the configuration state. For more information, see Section 3.1.2 “Low-Voltage Programming (LVP) Mode”. 2. CPD: Data NVM Memory Code Protection bit • 1 = OFF – Data NVM code protection disabled • 0 = ON – Data NVM code protection enabled 3: CP: User NVM Program Memory Code Protection bit • 1 = OFF – User NVM code protection disabled • 0 = ON – User NVM code protection enabled For more information on code protection, see Section 3.3 “Code Protection”. 2.4 Calibration Words The internal calibration values are factory calibrated and stored in the Calibration Word locations. Calibration words are located beginning at address E000h. The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration Words. 2014-2016 Microchip Technology Inc. DS40001738D-page 5 PIC16(L)F183XX 3.0 PROGRAMMING ALGORITHMS 3.1 Program/Verify Mode In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge. In Program/Verify mode, both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/Os are automatically configured as high-impedance inputs and the address is cleared. 3.1.1 HIGH-VOLTAGE PROGRAM/VERIFY MODE ENTRY AND EXIT There are two different modes of entering Program/Verify mode via high voltage: • VPP – First Entry mode • VDD – First Entry mode 3.1.1.1 VPP – First Entry Mode To enter Program/Verify mode via the VPP-first method, the following sequence must be followed: 3. 4. 5. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered. Raise the voltage on MCLR from 0V to VIHH. Raise the voltage on VDD from 0V to the desired operating voltage. The VPP-First entry prevents the device from executing code prior to entering Program/Verify mode. For example, when the Configuration Word has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal oscillator is selected (RSTOSC = HFINTOSC or LFINTOSC), and RA0 and RA1 are driven by the user application, the device will execute code. Since this may prevent entry, VPP-First Entry mode is strongly recommended. See the timing diagram in Figure 3-20. 3.1.1.2 VDD – First Entry Mode To enter Program/Verify mode via the VDD-First Entry mode, the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. Raise the voltage on VDD from 0V to the desired operating voltage. Raise the voltage on MCLR from VDD or below to VIHH. The VDD-First Entry mode is useful when programming the device when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 3-19. 3.1.1.3 Program/Verify Mode Exit To exit Program/Verify mode, take MCLR to VDD or lower (VIL). VDD-First Entry mode should use VDD-Last Exit mode (see Figure 3-19). VPP-First Entry mode should use VPP-Last Exit mode (see Figure 3-20). DS40001738D-page 6 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.1.2 LOW-VOLTAGE PROGRAMMING (LVP) MODE The Low-Voltage Programming mode allows the devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 3 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry mode. Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps: 1. 2. MCLR is brought to VIL; A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 32 clocks are required to match the sequence pattern, and a 33rd clock is required before the pattern detect goes active. The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least Significant bit of the Least Significant nibble must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For low-voltage programming timing, see Figure 3-24 and Figure 3-25. Exiting Program/Verify mode is done by no longer driving MCLR to VIL (see Figure 3-24 and Figure 3-25). Note: 3.1.3 To enter LVP mode, the LSb of the Least Significant nibble must be shifted in first. This differs from entering the key sequence on other parts. PROGRAM/VERIFY COMMANDS These devices implement ten programming commands, each six bits in length. The commands are summarized in Table 3-1. The commands are used to erase and program the device. The commands load and use the Program Counter (PC). Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay, 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. TABLE 3-1: COMMAND MAPPING Mapping Command Data/Note Binary (MSb … LSb) Hex Load Configuration x 0 0 0 0 0 Load Data for NVM J(1) 0 0 0 1 0 02h/22h 0, data (14), 0 Read Data from NVM J(1) 0 0 1 0 0 04h/24h 0, data (14), 0 x 0 0 1 1 0 06h PC = PC + 1 Increment Address 00h 0, data (14), 0 Load PC Address x 1 1 1 0 1 1Dh 0, data (22), 0 Begin Internally Timed Programming x 0 1 0 0 0 08h — Begin Externally Timed Programming x 1 1 0 0 0 18h — End Programming x 0 1 0 1 0 0Ah — Bulk Erase Memory x 0 1 0 0 1 09h Internally Timed Row Erase Memory x 0 0 1 0 1 05h Internally Timed Note 1: When J = 1, the Program Counter is automatically incremented by 1 (PC +1) and does not require an ‘Increment Address’ command to move the PC to the next address. When J = 0, the Program Counter is not incremented, therefore either a ‘Load PC address’ or ‘Increment Address’ command is required to move the PC to the next address. 2014-2016 Microchip Technology Inc. DS40001738D-page 7 PIC16(L)F183XX 3.1.3.1 Load Configuration The Load Configuration command is used to access the configuration memory (User ID Locations, Configuration Words, Calibration Words). The Load Configuration command sets the address to 8000h and loads the data latches with one word of data (see Figure 3-1). After issuing the Load Configuration command, use the Increment Address command until the proper address to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or the Begin Externally Timed Programming command. Note: Externally-timed writes are not supported for Configuration and Calibration bits. Any externally-timed write to the Configuration or Calibration Word will have no effect on the targeted word. FIGURE 3-1: LOAD CONFIGURATION 1 2 3 4 5 6 1 3.1.3.2 15 16 TDLY ICSPCLK ICSPDAT 2 0 0 0 0 0 X 0 LSb MSb 0 Load Data for NVM The Load Data for NVM command is used to load one 14-bit word into the data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is issued (see Figure 3-2). One data word is latched into the Write Data register corresponding to the current Program Counter’s LSbs. Depending on the value of bit 5 of the command, the PC may or may not be incremented (see Table 3-1). The Load Data for NVM command can also be used to load data for data EEPROM. After the 8-bit data word is loaded, the remaining six bits of the 14-bit word will be ‘0’s (see Figure 3-3). FIGURE 3-2: LOAD DATA FOR NVM PROGRAM FLASH MEMORY 1 2 3 4 5 6 ICSPCLK 0 ICSPDAT FIGURE 3-3: 1 2 15 16 TDLY 1 0 0 0 J 0 LSb MSb 0 LOAD DATA FOR NVM EEPROM 1 2 3 4 5 6 ICSPDAT DS40001738D-page 8 1 2 3 9 10 16 TDLY ICSPCLK 0 1 0 0 0 J 0 LSb MSb 0 0 0 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.1.3.3 Read Data from NVM The Read Data from NVM command will transmit data bits out of the current PC address, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program memory is code-protected (CP), the data will be read as zeros (see Figure 3-4 and Figure 3-5). Depending on the value of bit 5 of the command, the PC may or may not be incremented (see Table 3-1). FIGURE 3-4: READ DATA FROM NVM PROGRAM FLASH MEMORY 1 2 3 4 5 6 1 ICSPCLK ICSPDAT (From Programmer) 2 3 9 0 0 1 0 0 16 J ICSPDAT (From device) J LSb MSb Input FIGURE 3-5: 10 TDLY 0 0 Output Input READ DATA FROM NVM EEPROM 1 2 3 4 5 6 ICSPDAT (From Programmer) 0 0 1 0 0 ICSPDAT (From device) 2 15 16 3 J J Input 2014-2016 Microchip Technology Inc. 1 TDLY ICSPCLK LSb MSb Output Input DS40001738D-page 9 PIC16(L)F183XX 3.1.3.4 Increment Address The address is incremented when this command is received. It is not possible to decrement the address. To reset this counter, the user must exit Program/Verify mode and re-enter it. Instead of using multiple Increment Address commands to get to a certain address, the user may choose to use the Load PC Address command. If the address is incremented from address 7FFFh, it will wrap-around to location 0000h. If the address is incremented from FFFFh, it will wrap-around to location 8000h (see Figure 3-6). FIGURE 3-6: INCREMENT ADDRESS 1 2 3 4 5 Next Command 1 2 3 6 TDLY ICSPCLK ICSPDAT 0 1 1 0 0 X X Address 3.1.3.5 X X Address + 1 Load PC Address The PC value is set using the supplied data. The address implies the memory panel (Program Flash Memory or EEPROM) to be accessed. If the memory panel has fewer than 16 address bits, the MSbs are ignored (see Figure 3-7). FIGURE 3-7: LOAD PC ADDRESS 1 2 3 4 5 6 ICSPCLK ICSPDAT DS40001738D-page 10 1 2 3 17 18 24 TDLY 1 0 1 1 1 X 0 LSb ADDRESS MSb 0 0 0 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.1.3.6 Begin Internally Timed Programming A Load Configuration or Load Data for NVM command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. An internal timing mechanism executes the write. The user must allow for the program cycle time, TPINT, in order for the programming to complete. End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used to start the programming. The program memory address that is being programmed is not erased prior to being programmed (see Figure 3-8). FIGURE 3-8: BEGIN INTERNALLY TIMED PROGRAMMING 1 2 3 4 5 Next Command 1 2 3 6 TPINT ICSPCLK ICSPDAT 3.1.3.7 0 0 0 1 0 X X X X Begin Externally Timed Programming A Load Configuration or Load Data for NVM command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. To complete the programming, the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT (see Figure 3-9). Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write to the Configuration or Calibration Word will have no effect on the targeted word. FIGURE 3-9: BEGIN EXTERNALLY TIMED PROGRAMMING End Programming Command Begin Externally Timed Programming Command 1 2 3 4 5 6 1 ICSPCLK ICSPDAT 3.1.3.8 2 3 TPEXT 0 0 0 1 1 X 1 0 0 End Programming This command is required after a Begin Externally Timed Programming command is given. This command must be sent within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent. After sending the End Programming command, an additional delay (TDIS) is required before sending the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 3-10). FIGURE 3-10: END PROGRAMMING 1 2 3 4 5 TDIS ICSPCLK ICSPDAT 2014-2016 Microchip Technology Inc. Next Command 1 2 3 6 0 1 0 1 0 X X X X DS40001738D-page 11 PIC16(L)F183XX 3.1.3.9 Bulk Erase Memory The Bulk Erase Memory command performs different functions dependent on the current state of the address.The Bulk Erase command affects specific portions of the memory depending on the initial value of the Program Counter. Whenever a Bulk Erase command is executed, the device will address the regions listed in Table 3-2 and proceed in the order shown. The specific order shown is designed to ensure the integrity of the device code protection. TABLE 3-2: BULK ERASE Area(s) Erased(1) Address CP = 1 and CPD = 1 (both disabled) CP = 0 or CPD = 0 (either enabled) 0000h-7FFFh Program Memory Configuration Words(2) Program Memory EEPROM Configuration Words(2) 8000h-83FFh Program Memory User ID Locations Configuration Words(2) Program Memory EEPROM User ID Locations Configuration Words(2) 8400h-84FFh(4) Program Memory User ID Locations Program Memory EEPROM User ID Locations 8500h-85FFh(4) Program Memory Program Memory EEPROM E800h-EFFFh Program Memory EEPROM User ID Locations Configuration Words(2) Program Memory EEPROM User ID Locations Configuration Words(2) F000h-FFFFh EEPROM EEPROM Note 1: 2: Based on the address, memory areas will be erased in the shown order. Configuration Word 4 will be erased and the current protection state may be removed; this operation is performed last. After receiving the Bulk Erase Memory command, the erase will not complete until the time interval, TERAB, has expired (see Figure 3-11). FIGURE 3-11: BULK ERASE MEMORY 1 2 3 4 5 TERAB ICSPCLK ICSPDAT DS40001738D-page 12 Next Command 1 2 3 6 1 0 0 1 0 X X X X 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.1.3.10 Row Erase Memory The Row Erase Memory command will erase an individual row. When Program Flash memory write and erase operations are done on a row basis, the row size (number of 14-bit words) for the erase operation is 32, and the row size (number of 14-bit latches) for the write operation is 32. When EEPROM write and erase operations are done on a row basis, the row size (number of 8-bit words) for erase operations is 1, and the row size (number of 8-bit latches) is also 1. If the program memory is code-protected, the Row Erase Program Memory command will be ignored. When the address is 8000h-800Ah, the Row Erase Program Memory command will only erase the User ID locations regardless of the setting of the CP Configuration bit. The Flash memory row defined by the current PC will be erased. The user must wait TPEW for erasing to complete in Program Flash Memory and EEPROM rows, or TPEWCC for Configuration or Calibration data (see Table 3-4). An End Programming command is not required (see Figure 3-12). FIGURE 3-12: ROW ERASE MEMORY 1 2 3 4 5 TPEW ICSPCLK ICSPDAT 2014-2016 Microchip Technology Inc. Next Command 1 2 3 6 1 0 1 0 0 X X X X DS40001738D-page 13 PIC16(L)F183XX 3.2 Programming Algorithms The devices use internal latches to temporarily store the 14-bit words used for programming. The data latches allow the user to write the program words with a single Begin Externally Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally Timed Programming or Begin Internally Timed Programming command is given. The data latches are aligned with the LSbs of the address. The address at the time the Begin Externally Timed Programming or Begin Internally Timed Programming command is given will determine which memory row is written. Writes cannot cross a physical row boundary. For example, attempting to write from address 0002h-0021h in a 32-latch device will result in data being written to 0020h-003Fh. If more than the maximum number of latches are written without a Begin Externally Timed Programming or Begin Internally Timed Programming command, the data in the data latches will be overwritten. Figure 3-13 through Figure 3-18 show the recommended flowcharts for programming. FIGURE 3-13: DEVICE PROGRAM/VERIFY FLOWCHART Start Enter Programming Mode Bulk Erase Device Write Program Memory(1) Write User IDs Verify Program Memory Verify User IDs Write Configuration Words(2) Verify Configuration Words Exit Programming Mode Done Note 1: See Figure 3-14. 2: See Figure 3-17. DS40001738D-page 14 2014-2016 Microchip Technology Inc. PIC16(L)F183XX FIGURE 3-14: PROGRAM MEMORY FLOWCHART Start Bulk Erase Program Memory(1, 2) Program Cycle(3) Load PC Address Command Read Data from NVM No Data Correct? Report Programming Failure Yes Increment Address No Command All Locations Done? Yes Done Note 1: This step is optional if the device has already been erased or has not been previously programmed. 2: If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 3-18. 3: See Figure 3-15 or Figure 3-16. 2014-2016 Microchip Technology Inc. DS40001738D-page 15 PIC16(L)F183XX FIGURE 3-15: ONE-WORD PROGRAM CYCLE Program Cycle Load PC Address Command Load Data for NVM Begin Programming Command (Internally timed) Wait TPINT Begin Programming Command (Externally timed)(1) Wait TPEXT End Programming Command Wait TDIS Note 1: Externally timed writes are not supported for Configuration and Calibration bits. DS40001738D-page 16 2014-2016 Microchip Technology Inc. PIC16(L)F183XX FIGURE 3-16: MULTIPLE-WORD PROGRAM CYCLE Program Cycle Load Data for NVM Latch 1 Increment Address Command(1) Load Data for NVM Latch 2 Load Data for NVM Latch 32 Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS Note 1: This command is only necessary if the ‘Load Data for NVM’ command = 02h; when the ‘Load Data for NVM’ command = 22h, the PC automatically increases by one. See Table 3-2 for more information. 2014-2016 Microchip Technology Inc. DS40001738D-page 17 PIC16(L)F183XX FIGURE 3-17: CONFIGURATION MEMORY PROGRAM FLOWCHART Start Load Configuration Bulk Erase Program Memory(1) One-word Program Cycle(2) (User ID) Read Data From NVM Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 8004h? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle(2) (Config. Word) Read Data From NVM Data Correct? No Report Programming Failure Increment Address Command No Note Address = 800Bh? Yes 1: This step is optional if the device is erased or not previously programmed. 2: See Figure 3-15. DS40001738D-page 18 Done 2014-2016 Microchip Technology Inc. PIC16(L)F183XX FIGURE 3-18: ERASE FLOWCHART Start Load Configuration Bulk Erase Program Memory Done Note: 3.3 This sequence does not erase the Calibration Words. Code Protection Code protection is controlled using the CP bit. When code protection is enabled, all program memory locations (0000h-7FFFh) read as ‘0’. Further programming is disabled for the program memory (0000h-7FFFh). Program memory can still be programmed and read during program execution. The User ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. 3.3.1 PROGRAM MEMORY Code protection is enabled by programming the CP bit to ‘0’. The only way to disable code protection is to use the Bulk Erase Memory command. 3.3.2 DATA EEPROM Data EEPROM protection is enabled by programming the CPD bit to ‘0’. The only way to disable code protection is to use the Bulk Erase Memory command. 2014-2016 Microchip Technology Inc. DS40001738D-page 19 PIC16(L)F183XX 3.4 Hex File Usage In the hex file there are two bytes per program word stored in the Intel® INHX32 hex format. Data is stored LSB first, MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. For example, if the Configuration Word 1 is stored at 8007h, in the hex file this will be referenced as 1000Eh-1000Fh. The PIC16(L)F183XX family allows direct addressing for the data EEPROM, so the EEPROM data will appear at address 0xF000 in the hex file. 3.4.1 CONFIGURATION WORD To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words and User ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Words and User ID information should be included. 3.4.2 DEVICE ID If a device ID is present in the hex file at 1000Ch-1000Dh (8006h on the part), the programmer should verify the device ID against the value read from the part. On a mismatch condition, the programmer should generate a warning message. 3.4.3 CHECKSUM COMPUTATION The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit. 3.4.3.1 Program Code Protection Disabled With the program code protection disabled, the checksum is computed by reading the contents of the program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable location (e.g., 0FFFh). Any Carry bits exceeding 16 bits are ignored. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unimplemented Configuration bits are masked to ‘0’. 3.4.3.2 Program Code Protection Enabled The code protected checksums located in Tables B1 through E1 are calculated with the unprotected checksum located in the User ID memory locations. When using MPLAB® X IDE, the unprotected checksum can be automatically calculated and inserted into the User ID locations by selecting ‘Project Properties’ under the ‘File’ tab. A new window will appear. In the ‘Categories’ section, click on the ‘Building’ selection, then add a check to the ‘Insert unprotected checksum in User ID memory’ check box. The user can also choose to manually write the unprotected checksum into the User ID locations. Each nibble of the unprotected checksum is stored in the Least Significant nibble of each of the four User ID locations. The Most Significant checksum nibble is stored in the User ID at location 8000h, the second Most Significant nibble is stored at location 8001h, and so forth for the remaining nibbles and ID locations. The checksum of a code-protected device is computed in the following manner: the Least Significant nibble of each User ID is used to create a 16-bit value. The Least Significant nibble of User ID location 8000h is the Most Significant nibble of the 16-bit value. The Least Significant nibble of User ID location 8001h is the second Most Significant nibble, and so forth for the remaining User IDs and 16-bit value nibbles. The resulting 16-bit value is summed with the Configuration Words. All unimplemented Configuration bits are masked to ‘0’. DS40001738D-page 20 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.5 Electrical Specifications Refer to device specific data sheet for absolute maximum ratings. TABLE 3-3: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions Production tested at 25°C AC/DC CHARACTERISTICS Sym. Characteristics Min. Typ. Max. Units Conditions/Comments Programming Supply Voltages and Currents VDD Supply Voltage (VDDMIN(2), VDDMAX) PIC16LF183XX 1.80 2.50 — 3.60 3.60 V V FOSC 16 MHz FOSC 16 MHz PIC16F183XX 2.30 2.50 — 5.50 5.50 V V FOSC 16 MHz FOSC 16 MHz VPEW Read/Write and Row Erase operations VDDMIN — VDDMAX V VBE Bulk Erase operations 2.7 — VDDMAX V IDDI Current on VDD, Idle — — 1.0 mA IDDP Current on VDD, Programming — — 3.0 mA VPP IPP Current on MCLR/VPP — — 600 A VIHH High voltage on MCLR/VPP for Program/Verify mode entry 8.0 — 9.0 V TVHHR MCLR rise time (VIL to VIHH) for Program/Verify mode entry — — 1.0 s VIH (ICSPCLK, ICSPDAT, MCLR/VPP) input high level 0.8 VDD — — V VIL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level I/O pins ICSPDAT output high level VOH — — 0.2 VDD V VDD-0.7 VDD-0.7 VDD-0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V — — VSS+0.6 VSS+0.6 VSS+0.6 V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V — 2.70 — V PIC16(L)F183XX — — 2.45 1.90 — — V V PIC16F183XX PIC16LF183XX ICSPDAT output low level VOL Brown-out Reset Voltage: BORV = 0 (high trip) VBOR BORV = 1 (low trip) Programming Mode Entry and Exit TENTS Programing mode entry setup time: ICSPCLK, ICSPDAT setup time before VDD or MCLR 100 — — ns TENTH Programing mode entry hold time: ICSPCLK, ICSPDAT hold time after VDD or MCLR 250 — — s TCKL Clock Low Pulse Width 100 — — ns TCKH Clock High Pulse Width 100 — — ns Serial Program/Verify TDS Data in setup time before clock 100 — — ns TDH Data in hold time after clock 100 — — ns TCO Clock to data out valid (during a Read Data command) 0 — 80 ns Note 1: 2: Externally timed writes are not supported for Configuration and Calibration bits. Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a bulk-erased device, to ensure that the device is not held in Brown-out Reset. 2014-2016 Microchip Technology Inc. DS40001738D-page 21 PIC16(L)F183XX TABLE 3-3: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE (CONTINUED) Standard Operating Conditions Production tested at 25°C AC/DC CHARACTERISTICS Sym. Characteristics Min. Typ. Max. Units Conditions/Comments TLZD Clock to data low-impedance (during a Read Data command) 0 — 80 ns THZD Clock to data high-impedance (during a Read Data command) 0 — 80 ns TDLY Data input not driven to next clock input (delay required between command/data or command/ command) 1.0 — — s TERAB Bulk Erase cycle time — — 5 ms TERAR Row Erase cycle time — — 2.5 ms TPINT Internally timed programming operation time — — — — 2.5 5 ms ms Program memory Configuration Words TPEXT Externally timed programming pulse 1.0 — 2.1 ms Note 1 TDIS Time delay from program to compare (HV discharge time) 300 — — s TEXIT Time delay when exiting Program/Verify mode 1 — — s Note 1: 2: Externally timed writes are not supported for Configuration and Calibration bits. Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a bulk-erased device, to ensure that the device is not held in Brown-out Reset. TABLE 3-4: FLASH MEMORY CHARACTERISTICS Program Flash Memory Characteristics Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ.† Max. Units 10k — — E/W VDD(MIN) — VDD(MAX) V 7.9 — 9.0 V VBORMAX — VDD(MAX) V Conditions Program Flash Memory EP Cell Endurance VDD for Read Voltage on MCLR/VPP during Erase/Program VDD for Bulk Erase Temperature during programming At BOR = 2.45V At VDD = VDD(MIN) VPEW VDD for Write or Row Erase VDD(MIN) — VDD(MAX) V IDDPGM Current on VDD during Erase/ Write — — 5.0 mA TPEW Erase/Write cycle time — — 2.8 ms TPEWCC Erase/Write cycle time, configuration and calibration bits — 2 x TPEW — ms TRETD 40 — — Year Characteristic Retention All except Configuration and Calibration bits Provided no other specifications are violated † Data in ‘Typ.’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001738D-page 22 2014-2016 Microchip Technology Inc. PIC16(L)F183XX 3.5.1 AC TIMING DIAGRAMS FIGURE 3-19: PROGRAMMING ENTRY AND EXIT MODES – VDD FIRST AND LAST PROGRAMMING MODE ENTRY – ENTRY PROGRAMMING MODE ENTRY – EXIT VDD FIRST VDD LAST TENTS TENTH TEXIT VDD VIHH VPP VIL ICSPDAT ICSPCLK FIGURE 3-20: PROGRAMMING ENTRY AND EXIT MODES – VPP FIRST AND LAST PROGRAMMING MODE ENTRY – ENTRY PROGRAMMING MODE ENTRY – EXIT VPP FIRST VPP LAST TENTS TENTH TEXIT VDD VIHH VPP VIL ICSPDAT ICSPCLK 2014-2016 Microchip Technology Inc. DS40001738D-page 23 PIC16(L)F183XX FIGURE 3-21: CLOCK AND DATA TIMING TCKL TCKH ICSPCLK TDS TDH ICSPDAT as input TCO ICSPDAT as output TLZD ICSPDAT from input to output THZD ICSPDAT from output to input FIGURE 3-22: WRITE COMMAND – PAYLOAD TIMING TDLY 1 2 3 4 5 X X X X X 1 6 2 16 15 ICSPCLK 0 LSb X MSb 0 ICSPDAT Command FIGURE 3-23: Next Command Payload READ COMMAND – PAYLOAD TIMING TDLY 1 2 3 4 5 X X X X X 1 6 2 3 15 16 ICSPCLK X ICSPDAT (from Programmer) X ICSPDAT (from device) Command DS40001738D-page 24 LSb MSb Payload 0 Next Command 2014-2016 Microchip Technology Inc. PIC16(L)F183XX FIGURE 3-24: LVP ENTRY (POWERING-UP) VDD MCLR TENTS TENTH 33 clocks TCKH TCKL ICSPCLK TDH TDS ICSPDAT FIGURE 3-25: LSb of Pattern 0 1 2 ... MSb of Pattern 31 LVP ENTRY (POWERED) VDD MCLR TENTH 33 Clocks TCKH TCKL ICSPCLK TDH TDS ICSPDAT Note: LSb of Pattern 0 1 2 ... MSb of Pattern 31 Sequence matching can start with no edge on MCLR first. 2014-2016 Microchip Technology Inc. DS40001738D-page 25 PIC16(L)F183XX APPENDIX A: REVISION HISTORY Revision A (03/2014) Initial release of this document. Revision B (04/2014) Updated Device IDs for the PIC16(L)F18313 and PIC16(L)F18323 devices in Table B-1; Updated Tables C-2 and D-2; Updated Registers B-1 and C-1; Other minor corrections. Revision C (04/2015) Updated Table 1-1 and Table 3-1; Updated Figure 3-1 to Figure 3-12; Added new Appendix B; Other minor corrections. Revision D (01/2016) Updated Figure 2-1, 3.1.3.10 Section, Table 3-4. Updated Appendix B, C and D; Added Appendix E; Other minor corrections. DS40001738D-page 26 2014-2016 Microchip Technology Inc. PIC16(L)F183XX APPENDIX B: TABLE B-1: PIC16(L)F18313 AND PIC16(L)F18323 DEVICE ID, CHECKSUMS AND PINOUT DESCRIPTIONS DEVICE IDs AND CHECKSUMS Config. 1 Config. 2 Config. 3 Config. 4 Checksum Unprotected Device ID Device Word Mask Word Mask Word Mask Unprotected (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) Word (HEX) Code-Protected(1) 00AAh Protected Mask First Word (HEX) Blank and (HEX) (HEX) Last (HEX) Blank (HEX) 00AAh First and Last (HEX) PIC16F18313 3066 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 7C6C FDC2 00D7 822D PIC16LF18313 3068 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 7C6C FDC2 00D7 822D PIC16F18323 3067 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 7C6C FDC2 00D7 822D PIC16LF18323 3069 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 7C6C FDC2 00D7 822D Note 1: The protected checksum values listed assume that the unprotected checksum value has been stored in the User ID memory locations and used in the final calculations (see Section 3.4.3.2 “Program Code Protection Enabled” for details). TABLE B-2: Device PROGRAMMING PIN LOCATIONS BY PACKAGE TYPE Package 8-pin PDIP PIC16(L)F18313 PIC16(L)F18323 Note 1: Package Code Package Drawing Number(1) VDD VSS PIN PIN PIN PORT PIN PORT PIN PORT RA0 MCLR ICSPCLK ICSPDAT (P) C04-018 1 8 4 RA3 6 RA1 7 8-pin SOIC (3.9 mm) (SN) C04-057 1 8 4 RA3 6 RA1 7 RA0 8-pin UDFN (3x3) (RF) C04-254 1 8 4 RA3 6 RA1 7 RA0 14-pin PDIP (P) C04-005 1 14 4 RA3 12 RA1 13 RA0 14-pin SOIC (3.9 mm) (SL) C04-065 1 14 4 RA3 12 RA1 13 RA0 14-pin TSSOP (ST) C04-087 1 14 4 RA3 12 RA1 13 RA0 16-pin UQFN (4x4) (JQ) C04-257 16 13 3 RA3 11 RA1 12 RA0 The most current package drawings can be found in the Microchip Packaging Specification, DS00049, found at http://www.microchip.com/ packaging. The drawing numbers listed above do not include the current revision designator which is added at the end of the number. 2014-2016 Microchip Technology Inc. DS40001738D-page 27 PIC16(L)F183XX REGISTER B-1: ADDRESS 8007h: CONFIGURATION WORD 1 R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC (high, mid or low) or Not Enabled: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 Otherwise: This bit is ignored. bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC<2:0>: Power-Up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 000 = HFINT32 HFINTOSC with 2x PLL (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC (External Clock) above 8 MHz 110 = ECM EC (External Clock) for 100 kHz to 8 MHz 101 = ECL EC (External Clock) below 100 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS (Crystal oscillator) above 8 MHz 001 = XT HT (Crystal oscillator) above 100 kHz, below 8 MHz 000 = LP LP (Crystal oscillator) optimized for 32.768 kHz DS40001738D-page 28 2014-2016 Microchip Technology Inc. PIC16(L)F183XX REGISTER B-2: ADDRESS 8008h: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 DEBUG(2) STVREN PPS1WAY — BORV(1) — BOREN1 BOREN0 LPBOREN(3) — WDTE1 WDTE0 PWRTE MCLRE bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 DEBUG: Debugger Enable bit(2) 1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(1) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit(3) PIC16LF18313/18323 1 = OFF 0 = ON ULPBOR is disabled ULPBOR is enabled PIC16F18313/18323 Reserved - bit must be set to ‘1’. bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE<1:0>: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR 0 = OFF MCLR pin function is port-defined function Note 1: See VBOR parameter for specific trip point voltages. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 3: Low-Power BOR is only available on the PIC16LF18313/18323 devices. 2014-2016 Microchip Technology Inc. DS40001738D-page 29 PIC16(L)F183XX REGISTER B-3: ADDRESS 8009h: CONFIGURATION WORD 3 R/P-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 LVP(1) — — — — — — — — — — — WRT1 WRT0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 07FFh may be modified 01 = HALF 0000h to 03FFh write-protected, 0400h to 07FFh may be modified 00 = ALL 0000h to 07FFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. REGISTER B-4: ADDRESS 800Ah: CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — — CPD CP bit 13 bit 0 Legend: R = Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: Data EEPROM Memory Code Protection bit 1 = OFF - Data EEPROM code protection disabled 0 = ON - Data EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF - Program Memory code protection disabled 0 = ON - Program Memory code protection enabled DS40001738D-page 30 U = Unimplemented bit, read as ‘1’ 2014-2016 Microchip Technology Inc. PIC16(L)F183XX APPENDIX C: TABLE C-1: PIC16(L)F18324 AND PIC16(L)F18344 DEVICE ID, CHECKSUMS AND PINOUT DESCRIPTIONS DEVICE IDs AND CHECKSUMS Config 1 Config 2 Config 3 Config 4 Checksum Unprotected Device ID Device Word Mask Word Mask Word Mask Unprotected (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) Word (HEX) Protected Word (HEX) Mask (HEX) Blank (HEX) 00AAh First and Last (HEX) CodeProtected(1) Blank (HEX) 00AAh First and Last (HEX) PIC16F18324 303A 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 746C F5C2 F8D7 7A2D PIC16LF18324 303C 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 746C F5C2 F8D7 7A2D PIC16F18344 303B 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 746C F5C2 F8D7 7A2D PIC16LF18344 303D 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 746C F5C2 F8D7 7A2D Note 1: The protected checksum values listed assume that the unprotected checksum value has been stored in the User ID memory locations and used in the final calculations (see Section 3.4.3.2 “Program Code Protection Enabled” for details). TABLE C-2: Device Package Type PIC16(L)F18324 PIC16(L)F18344 Note 1: PROGRAMMING PIN LOCATIONS BY PACKAGE TYPE Package Code Package Drawing Number(1) VDD VSS MCLR ICSPCLK ICSPDAT PIN PIN PIN PORT PIN PORT PIN PORT 14-pin PDIP (P) C04-005 1 14 4 RA3 12 RA1 13 RA0 14-pin SOIC (SL) C04-065 1 14 4 RA3 12 RA1 13 RA0 14-pin TSSOP (ST) C04-087 1 14 4 RA3 12 RA1 13 RA0 16-pin UQFN (4x4) (JQ) C04-257 16 13 3 RA3 11 RA1 12 RA0 20-pin PDIP (P) C04-019 1 20 4 RA3 18 RA1 19 RA0 20-pin SOIC (SO) C04-094 1 20 4 RA3 18 RA1 19 RA0 20-pin SSOP (SS) C04-072 1 20 4 RA3 18 RA1 19 RA0 20-pin UQFN (4x4) (GZ) C04-255 18 17 1 RA3 15 RA1 16 RA0 The most current package drawings can be found in the Microchip Packaging Specification, DS00049, found at http://www.microchip.com/packaging. The drawing numbers listed above do not include the current revision designator which is added at the end of the number. 2014-2016 Microchip Technology Inc. DS40001738D-page 31 PIC16(L)F183XX REGISTER C-1: ADDRESS 8007h: CONFIGURATION WORD 1 R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC (high, mid or low) or Not Enabled: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 Otherwise: This bit is ignored. bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC<2:0>: Power-Up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 000 = HFINT32 HFINTOSC with 2x PLL (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC (External Clock) above 8 MHz 110 = ECM EC (External Clock) for 100 kHz to 8 MHz 101 = ECL EC (External Clock) below 100 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS (Crystal oscillator) above 8 MHz 001 = XT HT (Crystal oscillator) above 100 kHz, below 8 MHz 000 = LP LP (Crystal oscillator) optimized for 32.768 kHz DS40001738D-page 32 2014-2016 Microchip Technology Inc. PIC16(L)F183XX REGISTER C-2: R/P-1 R/P-1 DEBUG(2) STVREN ADDRESS 8008h: CONFIGURATION WORD 2 R/P-1 PPS1WAY U-1 R/P-1 — BORV(1) U-1 — R/P-1 BOREN1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 BOREN0 LPBOREN(3) — WDTE1 WDTE0 PWRTE MCLRE bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 DEBUG: Debugger Enable bit(2) 1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(1) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit(3) PIC16LF18324/344 1 = OFF 0 = ON ULPBOR is disabled ULPBOR is enabled PIC16F18324/344 Reserved - bit must be set to ‘1’. bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE<1:0>: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR 0 = OFF MCLR pin function is port-defined function Note 1: See VBOR parameter for specific trip point voltages. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 3: Low-power BOR is only available on the PIC16LF18324/18344 devices. 2014-2016 Microchip Technology Inc. DS40001738D-page 33 PIC16(L)F183XX REGISTER C-3: ADDRESS 8009h: CONFIGURATION WORD 3 R/P-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 LVP(1) — — — — — — — — — — — WRT1 WRT0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>:User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified 01 = HALF 0000h to 07FFh write-protected, 0800h to 0FFFh may be modified 00 = ALL 0000h to 0FFFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. REGISTER C-4: ADDRESS 800Ah: CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — — CPD CP bit 13 bit 0 Legend: R = Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: EEPROM Memory Code Protection bit 1 = OFF - EEPROM code protection disabled 0 = ON - EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF - Program Memory code protection disabled 0 = ON - Program Memory code protection enabled DS40001738D-page 34 U = Unimplemented bit, read as ‘1’ 2014-2016 Microchip Technology Inc. PIC16(L)F183XX APPENDIX D: TABLE D-1: PIC16(L)F18325 AND PIC16(L)F18345 DEVICE ID, CHECKSUMS AND PINOUT DESCRIPTIONS DEVICE IDs AND CHECKSUMS Config 1 Config 2 Config 3 Config 4 Checksum Unprotected Device ID Device Word Mask Word Mask Word Mask Unprotected (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) Word (HEX) Protected Word (HEX) Mask (HEX) CodeProtected(1) Blank (HEX) 00AAh First and Last (HEX) Blank (HEX) 00AAh First and Last (HEX) 6A2D PIC16F18325 303E 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 646C E5C2 E8D7 PIC16LF18325 3040 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 646C E5C2 E8D7 6A2D PIC16F18345 303F 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 646C E5C2 E8D7 6A2D 3041 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 646C E5C2 E8D7 6A2D PIC16LF18345 Note 1: The protected checksum values listed assume that the unprotected checksum value has been stored in the User ID memory locations and used in the final calculations (see Section 3.4.3.2 “Program Code Protection Enabled” for details). TABLE D-2: Device Package Type PIC16(L)F18325 PIC16(L)F18345 Note 1: PROGRAMMING PIN LOCATIONS BY PACKAGE TYPE Package Code Package Drawing Number(1) VDD VSS MCLR ICSPCLK ICSPDAT PIN PIN PIN PORT PIN PORT PIN PORT 14-pin PDIP (P) C04-005 1 14 4 RA3 12 RA1 13 RA0 14-pin SOIC (SL) C04-065 1 14 4 RA3 12 RA1 13 RA0 14-pin TSSOP (ST) C04-087 1 14 4 RA3 12 RA1 13 RA0 16-pin UQFN (4x4) (JQ) C04-257 16 13 3 RA3 11 RA1 12 RA0 20-pin PDIP (P) C04-019 1 20 4 RA3 18 RA1 19 RA0 20-pin SOIC (SO) C04-094 1 20 4 RA3 18 RA1 19 RA0 20-pin SSOP (SS) C04-072 1 20 4 RA3 18 RA1 19 RA0 20-pin UQFN (4x4) (GZ) C04-255 18 17 1 RA3 15 RA1 16 RA0 The most current package drawings can be found in the Microchip Packaging Specification, DS00049, found at http://www.microchip.com/packaging. The drawing numbers listed above do not include the current revision designator which is added at the end of the number. 2014-2016 Microchip Technology Inc. DS40001738D-page 35 PIC16(L)F183XX REGISTER D-1: ADDRESS 8007h: CONFIGURATION WORD 1 R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC (high, mid or low) or Not Enabled: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 Otherwise: This bit is ignored. bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC<2:0>: Power-Up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 000 = HFINT32 HFINTOSC with 2x PLL (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC (External Clock) above 8 MHz 110 = ECM EC (External Clock) for 100 kHz to 8 MHz 101 = ECL EC (External Clock) below 100 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS (Crystal oscillator) above 8 MHz 001 = XT HT (Crystal oscillator) above 100 kHz, below 8 MHz 000 = LP LP (Crystal oscillator) optimized for 32.768 kHz DS40001738D-page 36 2014-2016 Microchip Technology Inc. PIC16(L)F183XX REGISTER D-2: ADDRESS 8008h: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 DEBUG(2) STVREN PPS1WAY — BORV(1) — BOREN1 BOREN0 LPBOREN(3) — WDTE1 WDTE0 PWRTE MCLRE bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 DEBUG: Debugger Enable bit(2) 1 = OFF Background debugger disabled 0 = ON Background debugger enabled bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(1) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit (3) PIC16LF18325/18345 1 = OFF 0 = ON ULPBOR is disabled ULPBOR is enabled PIC16F18325/345 Reserved - bit must be set to ‘1’. bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE<1:0>: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR 0 = OFF MCLR pin function is port-defined function Note 1: See VBOR parameter for specific trip point voltages. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.For normal device operation, this bit should be maintained as a ‘1’. 3: Low-Power BOR is only available on the PIC16LF18325/18345 devices. 2014-2016 Microchip Technology Inc. DS40001738D-page 37 PIC16(L)F183XX REGISTER D-3: R/P-1 (1) LVP ADDRESS 8009h: CONFIGURATION WORD 3 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — WRT1 WRT0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>:User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified 01 = HALF 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified 00 = ALL 0000h to 1FFFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. REGISTER D-4: ADDRESS 800Ah: CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — — CPD CP bit 13 bit 0 Legend: R = Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: EEPROM Memory Code Protection bit 1 = OFF - EEPROM code protection disabled 0 = ON - EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF - Program Memory code protection disabled 0 = ON - Program Memory code protection enabled DS40001738D-page 38 U = Unimplemented bit, read as ‘1’ 2014-2016 Microchip Technology Inc. PIC16(L)F183XX APPENDIX E: TABLE E-1: PIC16(L)F18326 AND PIC16(L)F18346 DEVICE ID, CHECKSUMS AND PINOUT DESCRIPTIONS DEVICE IDs AND CHECKSUMS Config 1 Config 2 Config 3 Config 4 Checksum Unprotected Device ID Device Word Mask Word Mask Word Mask Unprotected (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) Word (HEX) Protected Word (HEX) Mask (HEX) CodeProtected(1) Blank (HEX) 00AAh First and Last (HEX) Blank (HEX) 00AAh First and Last (HEX) 4A2D PIC16F18326 30A4 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 446C C5C2 C8D7 PIC16LF18326 30A6 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 446C C5C2 C8D7 4A2D PIC16F18346 30A5 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 446C C5C2 C8D7 4A2D 30A7 3FFF 2977 3FFF 3AEF 3FFF 2003 3FFF 3FFE 0003 446C C5C2 C8D7 4A2D PIC16LF18346 Note 1: The protected checksum values listed assume that the unprotected checksum value has been stored in the User ID memory locations and used in the final calculations (see Section 3.4.3.2 “Program Code Protection Enabled” for details). TABLE E-2: Device Package Type PIC16(L)F18326 PIC16(L)F18346 Note 1: PROGRAMMING PIN LOCATIONS BY PACKAGE TYPE Package Code Package Drawing Number(1) VDD VSS MCLR ICSPCLK ICSPDAT PIN PIN PIN PORT PIN PORT PIN PORT 14-pin PDIP (P) C04-005 1 14 4 RA3 12 RA1 13 RA0 14-pin SOIC (SL) C04-065 1 14 4 RA3 12 RA1 13 RA0 14-pin TSSOP (ST) C04-087 1 14 4 RA3 12 RA1 13 RA0 16-pin UQFN (4x4) (JQ) C04-257 16 13 3 RA3 11 RA1 12 RA0 20-pin PDIP (P) C04-019 1 20 4 RA3 18 RA1 19 RA0 20-pin SOIC (SO) C04-094 1 20 4 RA3 18 RA1 19 RA0 20-pin SSOP (SS) C04-072 1 20 4 RA3 18 RA1 19 RA0 20-pin UQFN (4x4) (GZ) C04-255 18 17 1 RA3 15 RA1 16 RA0 The most current package drawings can be found in the Microchip Packaging Specification, DS00049, found at http://www.microchip.com/packaging. The drawing numbers listed above do not include the current revision designator which is added at the end of the number. 2014-2016 Microchip Technology Inc. DS40001738D-page 39 PIC16(L)F183XX REGISTER E-1: ADDRESS 8007h: CONFIGURATION WORD 1 R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC (high, mid or low) or Not Enabled: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 Otherwise: This bit is ignored. bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC<2:0>: Power-Up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 000 = HFINT32 HFINTOSC with 2x PLL (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC (External Clock) above 8 MHz 110 = ECM EC (External Clock) for 100 kHz to 8 MHz 101 = ECL EC (External Clock) below 100 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS (Crystal oscillator) above 8 MHz 001 = XT HT (Crystal oscillator) above 100 kHz, below 8 MHz 000 = LP LP (Crystal oscillator) optimized for 32.768 kHz DS40001738D-page 40 2014-2016 Microchip Technology Inc. PIC16(L)F183XX REGISTER E-2: ADDRESS 8008h: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 DEBUG(2) STVREN PPS1WAY — BORV(1) — BOREN1 BOREN0 LPBOREN(3) — WDTE1 WDTE0 PWRTE MCLRE bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 DEBUG: Debugger Enable bit(2) 1 = OFF Background debugger disabled 0 = ON Background debugger enabled bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(1) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit (3) PIC16LF18326/18346 1 = OFF 0 = ON ULPBOR is disabled ULPBOR is enabled PIC16F18326/346 Reserved - bit must be set to ‘1’. bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE<1:0>: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR 0 = OFF MCLR pin function is port-defined function Note 1: See VBOR parameter for specific trip point voltages. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.For normal device operation, this bit should be maintained as a ‘1’. 3: Low-Power BOR is only available on the PIC16LF18326/18346 devices. 2014-2016 Microchip Technology Inc. DS40001738D-page 41 PIC16(L)F183XX REGISTER E-3: R/P-1 (1) LVP ADDRESS 8009h: CONFIGURATION WORD 3 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — WRT1 WRT0 bit 13 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>:User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified 01 = HALF 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified 00 = ALL 0000h to 1FFFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. REGISTER E-4: ADDRESS 800Ah: CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — — CPD CP bit 13 bit 0 Legend: R = Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: EEPROM Memory Code Protection bit 1 = OFF - EEPROM code protection disabled 0 = ON - EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF - Program Memory code protection disabled 0 = ON - Program Memory code protection enabled DS40001738D-page 42 U = Unimplemented bit, read as ‘1’ 2014-2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0167-4 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014-2016 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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