PIC16(L)F183XX Full-Featured, Low Pin Count Microcontrollers with XLP Product Brief Description PIC16(L)F183XX microcontrollers feature Analog, Core Independent Peripherals and communication peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP, PWM and communications) to add flexibility to the application design. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Four 8-Bit Timers • Up to Three 16-Bit Timers • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-out Reset (BOR) with Fast Recovery • Low-Power BOR (LPBOR) Option • Extended Watchdog Timer (WDT) with Dedicated On-Chip Oscillator for Reliable Operation • Programmable Code Protection • Doze mode: Ability to run the CPU core slower than the system clock used by the internal peripherals • Idle mode: Ability to put the CPU core to sleep while internal peripherals continue operating from the system clock • Sleep mode: Lowest Power Consumption • Peripheral Module Disable: Peripheral power disable hardware module to minimize power consumption of unused peripherals Memory • • • • Up to 28 KB Program Flash Memory (PFM) Up to 2 KB Data SRAM Memory 256B of EEPROM Data Flash Memory (DFM) Direct, Indirect and Relative Addressing modes Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF183XX) - 2.3V to 5.5V (PIC16F183XX) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • • • • Sleep mode: 40 nA @ 1.8V, typical Watchdog Timer: 250 nA @ 1.8V, typical Secondary Oscillator: 300 nA @ 32 kHz Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 37 uA/MHz @ 1.8V, typical 2014-2016 Microchip Technology Inc. Digital Peripherals • Configurable Logic Cell (CLC): - Up to four CLCs - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Up to two CWGs - Multiple signal sources • Up to Four Capture/Compare/PWM (CCP) modules • PWM: Two 10-bit Pulse-Width Modulators • Numerically Controlled Oscillator (NCO): - Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock - Input Clock: 0 Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Serial Communications: - SPI, I2C, EUSART - RS-232, RS-485, LIN compatible • Data Signal Modulator (DSM): - Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms DS40001744C-page 1 PIC16(L)F183XX • Peripheral Pin Select (PPS): - I/O pin remapping of digital peripherals • Up to 18 I/O Pins: - Individually programmable pull ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable Clocking Structure • High-Precision Internal Oscillator: - Selectable frequency range up to 32 MHz • x2/x4 PLL with Internal and External Sources • Low-Power Internal 32 kHz Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator (SOCS) • External High-Speed Crystal Oscillators Analog Peripherals • 10-Bit Analog-to-Digital Converter (ADC): - Up to 17 external channels - Conversion available during Sleep • Comparator: - Up to two comparators - Low and High-Speed modes - Fixed Voltage Reference at inverting/ noninverting input(s) - Comparator outputs externally accessible • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels DS40001744C-page 2 2014-2016 Microchip Technology Inc. ICD(2) PPS NCO CLC I2C SPI EUSART CWG CCP/PWM Timers 0/1/2 5-bit DAC Comparators 10-bit ADCs I/Os(1) RAM (B) EEPROM (B) Program Memory (KW) Program Memory (KB) Device Data Sheet Index 2014-2016 Microchip Technology Inc. PIC16(L)F183XX Family Types TABLE 1: PIC16(L)F18313 (A) 3.5 2 256 256 6 5 1 1 1/1/1 2/2 1 1 1 1 2 1 Y I PIC16(L)F18323 (A) 3.5 2 256 256 12 11 2 1 1/1/1 2/2 1 1 1 1 2 1 Y I PIC16(L)F18324 (B) 7 4 256 512 12 11 2 1 1/3/3 4/2 2 1 1 1 4 1 Y I PIC16(L)F18325 (C) 14 8 256 1K 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I PIC16(L)F18326 (D) 28 16 256 2K 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I PIC16(L)F18344 (B) 7 4 256 512 18 17 2 1 1/3/3 4/2 2 1 1 1 4 1 Y I PIC16(L)F18345 (C) 14 8 256 1K 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I PIC16(L)F18346 (D) 28 16 256 2K 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I Note 1: 2: One pin is input-only. Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header. Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001744C-page 3 PIC16(L)F183XX Data Sheet Index: (Unshaded devices are described in this document.) A) DS40001799 PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP B) DS40001800 PIC16(L)F18324/18344 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP C) DS40001795 PIC16(L)F18325/18345 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP D) Future Release PIC16(L)F18326/18346 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP PIC16(L)F183XX TABLE 2: PACKAGES Packages PIC16(L)F18313 PDIP SOIC UDFN X X X TSSOP UQFN SSOP PIC16(L)F18323 X X X X PIC16(L)F18324 X X X X PIC16(L)F18325 X X X X PIC16(L)F18326 X X X X PIC16(L)F18344 X X X X PIC16(L)F18345 X X X X PIC16(L)F18346 X X X X Note: Pin details are subject to change. DS40001744C-page 4 2014-2016 Microchip Technology Inc. PIC16(L)F183XX PIN DIAGRAMS VDD RA5 RA4 VPP/MCLR/RA3 Note: PIC16(L)F18313 Pin Diagram – 8-Pin PDIP, SOIC, UDFN 1 2 3 4 8 7 6 5 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 See Table 3 for location of all peripheral functions. VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 Note: 1 2 3 4 5 6 7 PIC16(L)F18323 PIC16(L)F18324 PIC16(L)F18325 PIC16(L)F18326 Pin Diagram – 14-Pin PDIP, SOIC, TSSOP 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions. NC VSS VDD NC Pin Diagram – 16-Pin UQFN (4x4) 16 15 14 13 RA5 RA4 RA3/MCLR/VPP RC5 1 2 3 4 PIC16(L)F18323 12 RA0/ICSPDAT PIC16(L)F18324 11 RA1/ICSPCLK PIC16(L)F18325 10 RA2 PIC16(L)F18326 9 RC0 RC4 RC3 RC2 RC1 5 6 7 8 Note 1: 2: See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS. 2014-2016 Microchip Technology Inc. DS40001744C-page 5 PIC16(L)F183XX Pin Diagram – 20-Pin PDIP, SOIC, SSOP VDD 1 MCLR/VPP/RA3 4 RC5 5 RC4 6 RC3 7 RC6 8 Note: PIC16(L)F18344 PIC16(L)F18345 PIC16(L)F18346 RA5 2 RA4 3 20 VSS 19 RA0/ICSPDAT 18 RA1/ICSPCLK 17 RA2 16 RC0 15 RC1 14 RC2 RC7 9 13 RB4 12 RB5 RB7 10 11 RB6 See Table 8, Table 9 and Table 10 for location of all peripheral functions. RA4 RA5 VDD Vss RA0/ICSPDAT Pin Diagram – 20-Pin UQFN (4x4) RA3/MCLR/VPP RC5 RC4 RC3 RC6 1 2 3 4 5 PI PI C 1 6( C PI C 1 6( L ) F 16 L ) 1 ( L F 1 83 ) F 83 4 4 18 4 34 5 6 20 19 18 17 16 15 14 13 12 11 RA1/ICSPCLK RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 Note 1: 2: See Table 8, Table 9 and Table 10 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS. DS40001744C-page 6 2014-2016 Microchip Technology Inc. DSM Timers CCP PWM CWG MSSP EUSART C1IN0+ — DAC1OUT MDCIN1(1) — — — — — TX(1) CK(1) RA1 6 ANA1 VREF+ C1IN0- — DAC1REF+ MDMIN(1) — — — — RA2 5 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1(1) SDA(1,3,4) SDO(1) RA3 4 — — — — — — — — — — RA4 3 ANA4 — C1IN1- — — — T1G(1) SOSCO — — RA5 2 ANA5 — — — — MDCIN2(1) T1CKI(1) SOSCIN SOSCI CCP1(1) CCP2(1) — VDD 1 — — — — — — — — — — — — — — VSS 8 — — — — — — — — — — — — — — Note 1: 2: 3: 4: CLCIN3(1) — IOCA0 Y ICDDAT/ ICSPDAT CLCIN2(1) — IOCA1 Y ICDCLK/ ICSPCLK — — — INT(1) IOCA2 Y — SS(1) — CLCIN0(1) — IOCA3 Y MCLR VPP — — — — — IOCA4 Y CLKOUT OSC2 — — — CLCIN1(1) — IOCA5 Y CLKIN OSC1 — — VDD — — VSS — SCK(1) RX(1) SCL(1,3,4) DT(1,3) (3) — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A SDA CK CLC1OUT CLKR — — — — — — — — — — CCP2 PWM6 CWG1B SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — CWG1C SDO TX — — — — — — — — — — — — — — — CWG1D SCK — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ ST as selected by the INLVL register. DS40001744C-page 7 PIC16(L)F183XX OUT (2) Basic DAC — Pull-up NCO ANA0 Interrupt Comparator 7 CLKR Reference RA0 CLC ADC 8-PIN ALLOCATION TABLE (PIC16(L)F18313) 8-Pin PDIP/SOIC/UDFN TABLE 3: I/O(2) 2014-2016 Microchip Technology Inc. PIN ALLOCATION TABLES RA4 3 RA5 2014-2016 Microchip Technology Inc. Basic 3 Pull-up 4 Interrupt RA3 CLKR ANA2 CLC 10 EUSART 11 MSSP RA2 CWG ANA1 VREF+ PWM 11 CCP 12 Timers RA1 DSM ANA0 DAC ADC 12 NCO 16-Pin UQFN 13 Comparator 14/16-Pin PDIP/SOIC/TSSOP RA0 Reference I/O(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) — C1IN0+ — DAC1OUT — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOCA1 Y ICDCLK/ ICSPCLK VREF- — — DAC1REF- — T0CKI(1) — — CWG1(1) — — — — INT(1) IOCA2 Y — — — — — — — — — — — — — — — IOCA3 Y MCLR VPP 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOCA4 Y CLKOUT OSC2 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOCA5 Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — — — — — SCK(1) SCL(1,3,4) — — — IOCC0 Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — — — — SDI(1) SDA(1,3,4) — CLCIN2(1) — IOCC1 Y — RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) — CCP2(1) — — SS(1) — CLCIN0(1) — IOCC3 Y — RC4 6 5 ANC4 — — — — — — — — — — TX(1) CK(1) CLCIN1(1) — IOCC4 Y — RC5 5 4 ANC5 — — — — MDCIN2(1) — CCP1(1) — — — RX(1) DT(1,3) — — IOCC5 Y — VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — VSS Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 8 TABLE 4: Note 1: 2: 3: 4: 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic OUT(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) (CONTINUED) 14/16-Pin PDIP/SOIC/TSSOP I/O(2) 2014-2016 Microchip Technology Inc. TABLE 4: — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A SDA(3) CK CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — — CWG1C SDO TX — — — — — — — — — — — — — — — — CWG1D SCK — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 9 RA4 3 RA5 2014-2016 Microchip Technology Inc. Basic 3 Pull-up 4 Interrupt RA3 CLKR ANA2 CLC 10 EUSART 11 MSSP RA2 CWG ANA1 VREF+ PWM 11 CCP 12 Timers RA1 DSM ANA0 DAC ADC 12 NCO 16-Pin UQFN 13 Comparator 14/16-Pin PDIP/SOIC/TSSOP RA0 Reference I/O(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) — C1IN0+ — DAC1OUT — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOCA1 Y ICDCLK/ ICSPCLK VREF- — — DAC1REF- — T0CKI(1) CCP3(1) — CWG1(1) CWG2(1) — — — — INT(1) IOCA2 Y — — — — — — — — — — — — — — — IOCA3 Y MCLR VPP 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOCA4 Y CLKOUT OSC2 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOCA5 Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK(1) SCL(1,3,4) — — — IOCC0 Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — CCP4(1) — — SDI(1) SDA(1,3,4) — CLCIN2(1) — IOCC1 Y — RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) T5G(1) CCP2(1) — — SS(1) — CLCIN0(1) — IOCC3 Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — — TX(1) CK(1) CLCIN1(1) — IOCC4 Y — RC5 5 4 ANC5 — — — — MDCIN2(1) T3CKI(1) CCP1(1) — — — RX(1) DT(1,3) — — IOCC5 Y — VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — VSS Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 10 TABLE 5: 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) (CONTINUED) 14/16-Pin PDIP/SOIC/TSSOP I/O(2) 2014-2016 Microchip Technology Inc. TABLE 5: — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDA(3) CK CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SDO TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SCK — CLC4OUT — — — — OUT(2) Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 11 14/16-Pin PDIP/SOIC/TSSOP 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 2014-2016 Microchip Technology Inc. I/O(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — SS2(1) — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF + C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — — CWG1(1) CWG2(1) — — — — INT(1) IOCA2 Y — RA3 4 3 — — — — — — — — — — — — — — IOCA3 Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOCA4 Y CLKOUT OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOCA5 Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) SCL1(1,3,4) — — — IOCC0 Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — CCP4(1) — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOCC1 Y — RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) T5G(1) CCP2(1) — — SS1(1) — CLCIN0(1) — IOCC3 Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1) SCL2(1,3,4) TX(1) CK(1) CLCIN1(1) — IOCC4 Y — RC5 5 4 ANC5 — — — — — — SDI2(1) SDA2(1,3,4) RX(1) DT(1,3 — — IOCC5 Y — T0CKI(1) CCP3(1) MDCIN2(1) T3CKI(1) CCP1(1) ) VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — VSS Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 12 TABLE 6: 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) (CONTINUED) 14/16-Pin PDIP/SOIC/TSSOP I/O(2) 2014-2016 Microchip Technology Inc. TABLE 6: — — — — C1OUT DDS — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDA1(3) SDA2(3) CK CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCL1(3) SCL2(3) DT(3) CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SDO1 SDO2 TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SCK1 SCK2 — CLC4OUT — — — — OUT(2) Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 13 14/16-Pin PDIP/SOIC/TSSOP 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 2014-2016 Microchip Technology Inc. I/O(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — SS2(1) — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF + C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — — CWG1(1) CWG2(1) — — — — INT(1) IOCA2 Y — RA3 4 3 — — — — — — — — — — — — — — IOCA3 Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOCA4 Y CLKOUT OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOCA5 Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) SCL1(1,3,4) — — — IOCC0 Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — CCP4(1) — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOCC1 Y — RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) T5G(1) CCP2(1) — — SS1(1) — CLCIN0(1) — IOCC3 Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1) SCL2(1,3,4) TX(1) CK(1) CLCIN1(1) — IOCC4 Y — RC5 5 4 ANC5 — — — — — — SDI2(1) SDA2(1,3,4) RX(1) DT(1,3 — — IOCC5 Y — T0CKI(1) CCP3(1) MDCIN2(1) T3CKI(1) CCP1(1) ) VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — VSS Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 14 TABLE 7: 16-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) (CONTINUED) 14/16-Pin PDIP/SOIC/TSSOP I/O(2) 2014-2016 Microchip Technology Inc. TABLE 7: — — — — C1OUT DDS — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDA1(3) SDA2(3) CK CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCL1(3) SCL2(3) DT(3) CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SDO1 SDO2 TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SCK1 SCK2 — CLC4OUT — — — — OUT(2) Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 15 20-Pin PDIP/SOIC/SSOP 20-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 2014-2016 Microchip Technology Inc. I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F18344) RA0 19 16 ANA0 — C1IN0+ — DAC1OUT — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 18 15 ANA1 VREF + C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 17 14 ANA2 VREF- — — DAC1REF- — — CWG1(1) CWG2(1) — — CLCIN0(1) — INT(1) IOCA2 Y — RA3 4 1 — — — — — — — — — — — — — — IOCA3 Y MCLR VPP RA4 3 20 ANA4 — — — — — T1G(1) T3G(1) T5G(1) SOSCO CCP4(1) — — — — — — IOCA4 Y CLKOUT OSC2 RA5 2 19 ANA5 — — — — — T1CKI(1) T3CKI(1) T5CKI(1) SOSCIN SOSCI — — — — — — — IOCA5 Y CLKIN OSC1 RB4 13 10 ANB4 — — — — — — — — — SDI(1) SDA(1,3,4) — CLCIN2(1) — IOCB4 Y — RB5 12 9 ANB5 — — — — — — — — — — RX(1) DT(1) CLCIN3(1) — IOCB5 Y — RB6 11 8 ANB6 — — — — — — — — — SCK(1) SCL(1,3,4) — — — IOCB6 Y — RB7 10 7 ANB7 — — — — — — — — — — TX(1) CK(1) — — IOCB7 Y — RC0 16 13 ANC0 — C2IN0+ — — — — — — — — — — — IOCC0 Y — RC1 15 12 ANC1 — C1IN1C2IN1- — — — — — — — — — — — IOCC1 Y — RC2 14 11 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — Note 1: 2: 3: 4: T0CKI(1) CCP3(1) Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 16 TABLE 8: RC4 6 3 ANC4 — — — RC5 5 2 ANC5 — — — RC6 8 5 ANC6 — — — — — — — RC7 9 6 ANC7 — — — — — — — VDD 1 18 — — — — — — — — VSS 20 17 — — — — — — — — — — — — — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDO DT(3) — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCK CK — — — — — — — — — CCP3 — CWG1C CWG2C SCL(3) — — — — — — — — — CCP4 — CWG1D CWG2D SDA(3) — — — CCP1(1) — — — — — — — — — — — — — SS(1) — — — — — — — — — — — — (2) OUT Note CLCIN1(1) — IOCC3 Y — — — IOCC4 Y — — — IOCC5 Y — — IOCC6 Y — — IOCC7 Y — — — — VDD — — — — VSS CLC1OUT CLKR — — — CLC2OUT — — — — TX CLC3OUT — — — — — CLC4OUT — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. DS40001744C-page 17 PIC16(L)F183XX 1: 2: 3: 4: Basic MDCIN2(1) — Pull-up — — CCP2(1) Interrupt — — CLKR MDMIN(1) CLC — EUSART — MSSP C1IN3C2IN3- CWG NCO — PWM Comparator ANC3 CCP Reference 4 Timers ADC 7 DSM 20-Pin UQFN RC3 DAC 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F18344) (CONTINUED) I/O(2) 2014-2016 Microchip Technology Inc. TABLE 8: 20-Pin PDIP/SOIC/SSOP 20-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 2014-2016 Microchip Technology Inc. I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F18345) RA0 19 16 ANA0 — C1IN0+ — DAC1OUT — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 18 15 ANA1 VREF + C1IN0C2IN0- — DAC1REF+ — — — — — SS2(1) — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 17 14 ANA2 VREF- — — DAC1REF- — — CWG1(1) CWG2(1) — — CLCIN0(1) — INT(1) IOCA2 Y — RA3 4 1 — — — — — — — — — — — — — — IOCA3 Y MCLR VPP RA4 3 20 ANA4 — — — — — T1G(1) T3G(1) T5G(1) SOSCO CCP4(1) — — — — — — IOCA4 Y CLKOUT OSC2 RA5 2 19 ANA5 — — — — — T1CKI(1) T3CKI(1) T5CKI(1) SOSCIN SOSCI — — — — — — — IOCA5 Y CLKIN OSC1 RB4 13 10 ANB4 — — — — — — — — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOCB4 Y — RB5 12 9 ANB5 — — — — — — — — — SDI2(1) SDA2(1,3,4) RX(1) DT(1) CLCIN3(1) — IOCB5 Y — RB6 11 8 ANB6 — — — — — — — — — SCK1(1) SCL1(1,3,4) — — — IOCB6 Y — RB7 10 7 ANB7 — — — — — — — — — SCK2(1) SCL2(1,3,4) TX(1) CK(1) — — IOCB7 Y — RC0 16 13 ANC0 — C2IN0+ — — — — — — — — — — — IOCC0 Y — RC1 15 12 ANC1 — C1IN1C2IN1- — — — — — — — — — — — IOCC1 Y — RC2 14 11 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — RC3 7 4 ANC3 — C1IN3C2IN3- — — MDMIN(1) — CCP2(1) — — — — CLCIN1(1) — IOCC3 Y — Note 1: 2: 3: 4: T0CKI(1) CCP3(1) Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 18 TABLE 9: Reference Comparator DSM Timers CCP PWM CWG MSSP EUSART CLKR Interrupt Pull-up Basic 3 ANC4 — — — — — — — — — — — — — IOCC4 Y — 5 2 ANC5 — — — — MDCIN2(1) — CCP1(1) — — — — — — IOCC5 Y — RC6 8 5 ANC6 — — — — — — — — — SS(1) — — — IOCC6 Y — RC7 9 6 ANC7 — — — — — — — — — — — — — IOCC7 Y — VDD 1 18 — — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — — VSS — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDO1 SDO2 DT(3) CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCK1 SCK2 CK CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SCL1(3) SCL2(3) TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SDA1(3) SDA2(3) — CLC4OUT — — — — OUT(2) Note 1: 2: 3: 4: CLC ADC 6 RC5 DAC 20-Pin UQFN RC4 NCO 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F18345) (CONTINUED) I/O(2) 2014-2016 Microchip Technology Inc. TABLE 9: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 19 20-Pin PDIP/SOIC/SSOP 20-Pin UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic 2014-2016 Microchip Technology Inc. I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F18346) RA0 19 16 ANA0 — C1IN0+ — DAC1OUT — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 18 15 ANA1 VREF + C1IN0C2IN0- — DAC1REF+ — — — — — SS2(1) — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 17 14 ANA2 VREF- — — DAC1REF- — — CWG1(1) CWG2(1) — — CLCIN0(1) — INT(1) IOCA2 Y — RA3 4 1 — — — — — — — — — — — — — — IOCA3 Y MCLR VPP RA4 3 20 ANA4 — — — — — T1G(1) T3G(1) T5G(1) SOSCO CCP4(1) — — — — — — IOCA4 Y CLKOUT OSC2 RA5 2 19 ANA5 — — — — — T1CKI(1) T3CKI(1) T5CKI(1) SOSCIN SOSCI — — — — — — — IOCA5 Y CLKIN OSC1 RB4 13 10 ANB4 — — — — — — — — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOCB4 Y — RB5 12 9 ANB5 — — — — — — — — — SDI2(1) SDA2(1,3,4) RX(1) DT(1) CLCIN3(1) — IOCB5 Y — RB6 11 8 ANB6 — — — — — — — — — SCK1(1) SCL1(1,3,4) — — — IOCB6 Y — RB7 10 7 ANB7 — — — — — — — — — SCK2(1) SCL2(1,3,4) TX(1) CK(1) — — IOCB7 Y — RC0 16 13 ANC0 — C2IN0+ — — — — — — — — — — — IOCC0 Y — RC1 15 12 ANC1 — C1IN1C2IN1- — — — — — — — — — — — IOCC1 Y — RC2 14 11 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y — Note 1: 2: 3: 4: T0CKI(1) CCP3(1) Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F183XX DS40001744C-page 20 TABLE 10: — RC6 8 5 ANC6 — — — — — — — RC7 9 6 ANC7 — — — — — — — VDD 1 18 — — — — — — — — VSS 20 17 — — — — — — — — — — — — — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDO1 SDO2 DT(3) — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCK1 SCK2 CK — — — — — — — — — CCP3 — CWG1C CWG2C SCL1(3) SCL2(3) — — — — — — — — — CCP4 — CWG1D CWG2D SDA1(3) SDA2(3) OUT Note Basic — — Pull-up — — Interrupt — ANC5 CLKR ANC4 2 CLC 3 5 EUSART 6 RC5 MSSP RC4 CWG C1IN3C2IN3- PWM — CCP Comparator ANC3 Timers Reference 4 DSM ADC 7 DAC 20-Pin UQFN RC3 NCO 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED) I/O(2) 2014-2016 Microchip Technology Inc. TABLE 10: — — MDMIN(1) — CCP2(1) — — — — CLCIN1(1) — IOCC3 Y — — — — MDCIN2(1) — IOCC4 Y — — IOCC5 Y — — IOCC6 Y — — IOCC7 Y — — — — VDD — — — — VSS CLC1OUT CLKR — — — CLC2OUT — — — — TX CLC3OUT — — — — — CLC4OUT — — — — — — — — — — CCP1(1) — — — — — — SS(1) — — — — — — — — — — — — (2) Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. DS40001744C-page 21 PIC16(L)F183XX 1: 2: 3: 4: — — — Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0183-4 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS40001744C-page 22 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2014-2016 Microchip Technology Inc. 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DS40001744C-page 23