C8051F912-GDI Tested Single/Dual Battery, 0.9–3.6 V, 16 kB Flash, SmaRTClock, 12/10-Bit ADC MCU Die in Wafer Form Ultra-Low Power - 160 µA/MHz in active mode (24.5 MHz clock) - 2 µs wake-up time (two-cell mode) - 10 nA sleep mode with memory retention - 50 nA sleep mode with brownout detector - 300 nA sleep mode with LFO - 600 nA sleep mode with external crystal Supply Voltage 0.9 to 3.6 V - One-cell mode supports 0.9 to 3.6 V operation - Two-cell mode supports 1.8 to 3.6 V operation - Built-in dc-dc converter with 1.8 to 3.3 V output for use 12 or 10-Bit Analog-to-Digital Converter - ±1 LSB INL no missing codes (10-bit mode) - Programmable throughput up to 300 ksps - - programmable drive strength Hardware SMBusTM (I2CTM Compatible), 2 x SPITM, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer Clock Sources - Internal oscillators: 24.5 MHz, 2% accuracy supports (10-bit mode) 12-bit extended resolution mode provides ±1.5 LSB INL at up to 75 ksps throughput 15 external inputs On-chip voltage reference On-chip PGA allows measuring voltages up to twice the reference voltage 16-bit auto-averaging accumulator with burst mode provides increased ADC resolution Data dependent windowed interrupt generator Built-in temperature sensor - UART operation; 20 MHz low power oscillator requires very little bias current External oscillator: Crystal, RC, C, or CMOS Clock SmaRTClock oscillator: 32 kHz crystal or internal LFO Can switch between clock sources on-the-fly; useful in implementing various power saving modes On-Chip Debug - On-chip debug circuitry facilitates full-speed, non-intrusive in-system debug (no emulator required) Two Comparators - Programmable hysteresis and response time - Configurable as wake-up or reset source 6-Bit Programmable Current Reference - Up to ± 500 A. Can be used as a bias or for generat- instructions in 1 or 2 system clocks - 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 768 bytes RAM - 16 kB Flash; In-system programmable Digital Peripherals - 16 port I/O; All 5 V tolerant with high sink current and - Provides 4 breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit Temperature range: –40 to +85o C Full Technical Data Sheet - C8051F91x-C8051F90x ing a custom reference voltage PWM Enhanced Mode provides additional resolution ANALOG PERIPHERALS A M U X 12/10-bit 75/300 ksps ADC TEMP SENSOR VREF VREG IREF + + – – VOLTAGE COMPARATORS DIGITAL I/O UART SMBus 2 x SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR - in one-cell mode Built-in LDO regulator allows a high analog supply voltage and low digital core voltage 2 built-in supply monitors (brownout detectors) High-Speed 8051 C Core - Pipelined instruction architecture; executes 70% of Port 1 Port 2 24.5 MHz PRECISION INTERNAL OSCILLATOR 20 MHz LOW POWER INTERNAL OSCILLATOR External Oscillator HARDWARE smaRTClock HIGH-SPEED CONTROLLER CORE 16 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.2 12/13 8051 CPU (25 MIPS) DEBUG CIRCUITRY 768 B SRAM POR WDT Copyright © 2013 by Silicon Laboratories C8051F912-GDI SmaRTClock Real Time Clock SMBus/I2C UART Enhanced SPI Timers (16-bit) Programmable Counter Array Digital Port I/Os Analog Comparators Lead-free (RoHS Compliant) C8051F912-D-G1DI 25 16 768 1 1 2 4 16 2 28.54 mil / 725 µm (no backgrind) C8051F912-D-GDI 768 1 1 2 4 16 2 12 mil (backgrind) 2 25 16 *Note: 1024 bytes reserved for factory use Rev. 1.2 Wafer Thickness C8051F9xx Plus Features Temperature Sensor Internal Voltage Reference Programmable Current Reference 10-bit 300ksps ADC Flash Memory (kB)* MIPS (Peak) RAM (Bytes) Ordering Part Number C8051F912-GDI 1. Ordering Information Table 1.1. Product Selection Guide C8051F912-GDI 2. Pin Definitions Table 2.1. Pin Definitions for C8051F912-GDI Name Physical Pad Number Type Description VBAT 6 P In Battery Supply Voltage. C8051F912 devices: Must be 0.9 to 3.6 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell battery mode. VDD / 4 DC+ DC– / 2 GND P In Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is not required in low power sleep mode. This voltage must always be > VBAT. P Out Positive output of the dc-dc converter. In single-cell battery mode, a 1uF ceramic capacitor is required between DC+ and DC–. This pin can supply power to external devices when operating in single-cell battery mode. P In DC-DC converter return current path. In single-cell battery mode, this pin is typically not connected to ground. G In dual-cell battery mode, this pin must be connected directly to ground. Required Ground. GND 3 G DCEN 5 P In G RST/ 7 C2CK P2.7/ 8 C2D In dual-cell battery mode, this pin must be connected directly to ground. D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 k to 5 k pullup to VDD is recommended. D I/O Clock signal for the C2 Debug Interface. D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O Section of C8051F91x-C8051F90x data sheet for a complete description. D I/O Bi-directional data signal for the C2 Debug Interface. SmaRTClock Oscillator Crystal Input. XTAL3 10 A In XTAL4 9 A Out P0.0 32 VREF DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to VBAT through a 0.68 µH inductor. SmaRTClock Oscillator Crystal Output. D I/O or A Port 0.0. In External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recomA In mended. A Out Rev. 1.2 3 C8051F912-GDI Table 2.1. Pin Definitions for C8051F912-GDI (Continued) Name Physical Pad Number P0.1 31 AGND P0.2 Type D I/O or A Port 0.1. In G 30 XTAL1 Description Optional Analog Ground. D I/O or A Port 0.2. See Port I/O Section of the C8051F91x-C8051F90x data sheet In for a complete description. A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. Buffered SmaRTClock oscillator output. P0.3 29 D I/O or A Port 0.3. In External Clock Output. This pin is the excitation driver for an external crysA Out tal or resonator. External Clock Input. This pin is the external clock input in external CMOS D In clock mode. External Clock Input. This pin is the external clock input in capacitor or RC A In oscillator configurations. 28 D I/O or A Port 0.4. In XTAL2 P0.4 TX P0.5 D Out 26 RX P0.6 CNVSTR P0.7 24 UART RX Pin. D I/O or A Port 0.6. In D In IREF0 4 D I/O or A Port 0.5. In D In 25 UART TX Pin. External Convert Start Input for ADC0. D I/O or A Port 0.7. In A Out IREF0 Output. See IREF Section of the C8051F91x-C8051F90x data sheet for complete description. P1.0 19 D I/O or A In Port 1.0. May also be used as SCK for SPI1. P1.1 18 D I/O or A In Port 1.1. May also be used as MISO for SPI1. P1.2 17 D I/O or A In Port 1.2. May also be used as MOSI for SPI1. Rev. 1.2 C8051F912-GDI Table 2.1. Pin Definitions for C8051F912-GDI (Continued) Name Physical Pad Number P1.3 16 D I/O or A In Port 1.3. May also be used as NSS for SPI1. P1.4 13 D I/O or A In Port 1.4. P1.5 12 D I/O or A In Port 1.5. P1.6 11 D I/O or A In Port 1.6. Type Description Rev. 1.2 5 C8051F912-GDI 3. Bonding Instructions Table 3.1. Bond Pad Coordinates Physical Pad Number Example Package Pin Number (QFN-24) Package Pin Name 1 Reserved* 2 X (µm) Y (µm) — –836 600 1 DC–/GND –836 480 3 2 GND –836 233 4 3 VDD/DC+ –836 78 5 4 DCEN –836 –105 6 5 VBAT –836 –329 7 6 RST/C2CK –836 –688 8 7 P2.7/C2D –633 –891 9 8 XTAL4 –348 –891 10 9 XTAL3 –126 –891 11 10 P1.6 134 –891 12 11 P1.5 290 –891 13 12 P1.4 433 –891 14 Reserved* — 577 –891 15 Reserved* — 667 –891 16 13 P1.3 836 –688 17 14 P1.2 836 –545 18 15 P1.1 836 –389 19 16 P1.0 836 –226 20 Reserved* — 836 –103 21 Reserved* — 836 –13 22 Reserved* — 836 77 23 Reserved* — 836 167 24 17 P0.7/IREF0 836 369 *Note: Pins marked “Reserved” should not be connected. 6 Pad Coordinates Relative to Center Rev. 1.2 C8051F912-GDI Table 3.1. Bond Pad Coordinates (Continued) Physical Pad Number Example Package Pin Number (QFN-24) Package Pin Name 25 18 26 Pad Coordinates Relative to Center X (µm) Y (µm) P0.6/CNVSTR 836 525 19 P0.5/RX 836 688 27 Reserved* — 745 883 28 20 P0.4/TX 641 891 29 21 P0.3/XTAL2 484 891 30 22 P0.2/XTAL1 342 891 31 23 P0.1/AGND –490 891 32 24 P0.0/VREF –633 891 *Note: Pins marked “Reserved” should not be connected. Rev. 1.2 7 C8051F912-GDI C8051F911D Figure 3.1. Die Bonding (QFN-24) 8 Rev. 1.2 C8051F912-GDI Table 3.2. Wafer and Die Information Wafer ID C8051F911D Wafer Dimensions 8 in. Die Dimensions 1.9256 mm x 2.0366 mm Wafer Thickness (No backgrind) Wafer Thickness (With backgrind) 28.54 mil ±1 mil (725 µm) 12 mil ±1 mil Wafer Identification Notch Scribe Line Width 80 µm Die per Wafer* Contact Sales for info Passivation Standard Wafer Packaging Detail Wafer Jar Bond Pad Dimensions 60 µm x 60 µm Maximum Processing Temperature 250 °C Electronic Die Map Format .txt Bond Pad Pitch Minimum 142 µm *Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer). Rev. 1.2 9 C8051F912-GDI 4. Wafer Storage Guidelines It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination. Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs. must be stored at a temperature of 18–24 °C. Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%. Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air). Wafers 10 Rev. 1.2 C8051F912-GDI 5. Failure Analysis (FA) Guidelines Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in wafer form. In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories must be provided with die assembled in an industry standard package that is pin compatible with existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that meet this requirements will follow the standard FA guidelines for packaged parts. If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape. Initial response time for FA requests that meet this requirements will be 3 weeks. Rev. 1.2 11 C8051F912-GDI DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Changed Wafer Packaging Detail to “Wafer Jar” in Table 3.2 on page 9. Revision 1.1 to Revision 1.2 12 Replaced “C8051F912-GDI” with “C8051F912-D-GDI” (except in title). Updated Table 1.1, “Product Selection Guide,” on page 2. Added C8051F912-D-G1DI row to Table 1.1. Changed “Package” column heading to “Wafer Thickness” in Table 1.1. Updated label in Figure 3.1 on page 8 to read “C8051F911D”. Updated Table 3.2 on page 11 with new Wafer Thickness (no backgrind) row. Added “5. Failure Analysis (FA) Guidelines” on page 11. Rev. 1.2 Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! 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