S i 5 2 1 4 4 - E VB Si52144 E VALUATION B OARD U SER ’ S G UIDE Description EVB Features The Si52144 is a four port PCIe clock generator compliant with the PCIe Gen1, Gen2 and Gen3 standards. The Si52144 is a 24-pin QFN device that operates on a 3.3 V power supply and can be controlled using SMBus signals along with hardware control input pins. The differential outputs support spread spectrum and can be controlled through SSON input pin. The Si52144 needs a crystal or clock input of 25 MHz. The connections are described in this document. This document is intended to be used in conjunction with the Si52144 device and data sheet for the following tests: GND PCIe Gen1, Gen2, Gen3 compliancy Power consumption test Jitter performance Testing out I2C code for signal tuning In-system validation where SMA connectors are present VDD = 3.3 V power supply Power connectors External Clock Input DIFF3 Output Enable SDATA SRC3 connection for application GND SCLK Si52144 DIFF1 Output Enable SRC2 connection for application Spread Selection DIFF2 Output Enable DIFF0 Output Enable SRC0 connection for application Rev. 0.1 12/11 Copyright © 2011 by Silicon Labs SRC1 connection for application Si52144-EVB Si52144-EVB 1. Front Panel External Clock Input for Si52144-EVB only I2C Connect for I2C Read and Write. In sequence SData, GND, SCLK from left to right. 3.3 V Power Supply Connector OE_DIFF3 Hardware Input Control for DIFF3 Output GND Connector VDD Connectors DIFF3 Differential Output OE1 Hardware Input Control for DIFF1 Output SSON Spread Select Input OE2 Hardware Input Control for DIFF2 Output DIFF2 Differential Output OE0 Hardware Input Control for DIFF0 Output DIFF1 Differential Output Si52144 Device Mount DIFF0 Differential Output Figure 1. Evaluation Module Front Panel Table 1. Input Jumper Settings 2 Jumper Label Type Description OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output. 1 = DIFF0 enabled, 0 = DIFF0 disabled. OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output. 1 = DIFF1 enabled, 0 = DIFF1 disabled. OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output. 1 = DIFF2 enabled, 0 = DIFF2 disabled. OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output. 1 = DIFF3 enabled, 0 = DIFF3 disabled. SSON I SSON Input, 3.3 V-Tolerant Active Input for Spread Selection. Internal 100 k pulldown. Refer to Table 2. SDATA I/O SCLK I SMBus-Compatible SDATA. SMBus-Compatible SCLOCK. Rev. 0.1 Si52144-EVB Table 2. Spread Selection SSON Frequency (MHz) Spread (%) 0 100.00 OFF 1 100.00 –0.5 Note Default Value for SSON=0 1.1. Generating DIFF Outputs from the Si52144 If the input pins are left floating upon power-on of the device, by default all DIFF outputs DIFF[0:3] are ON with 100 MHz and with spread spectrum disabled. The input pin headers have clear indication of jumper settings for setting logic LOW (0) and HIGH (1) as shown below. The jumper placed on the middle and left pin will set input OE0 to LOW; the jumper placed on the middle and right pin will set input OE0 to HIGH. The output enable pins can be changed on the fly to observe outputs stopped cleanly. To enable the spread spectrum, the SSON input needs to change from a logic level low to high. Input functionality is explained in detail below. 1.1.1. SSON Input Apply the appropriate logic level to SSON input to achieve clock frequency selection. When the SSON is HIGH, –0.5% down spread is enabled on all differential outputs with a saw-tooth spread profile. When the SSON is LOW, spread profile is disabled. 1.1.2. OE [0:3] Input The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high) results in corresponding output that was stopped are to resume normal operation in a glitch-free manner. Each of the hardware OE [0:3] pins are mapped via I2C to control bit in Control register. The hardware pin and the Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF outputs and their corresponding I2C control bits and hardware pins are listed in Table 3. Table 3. Output Enable Control I2C Control Bit Output Hardware Control Input Byte1 [bit 2] DIFF0 OE0 Byte1 [bit 0] DIFF1 OE1 Byte2 [bit 7] DIFF2 OE2 Byte2 [bit 6] DIFF3 OE3 Rev. 0.1 3 Si52144-EVB 2. Schematics R1 U2 5 OE2 For Si52144,R10 open For Si53154,R11 open 7 OE0 18 OE3 VDD1 R10 R11 10K 2 OE1 NI 3 SSON NI OE2 XOUT/DIFFIN OE0 R2 0 OE3 OE1 SSON XIN/DIFFIN# XOUT_DIFFIN 22 YC1 20pF Y1 25MHz 23 YC2 20pF Si52144 19 SCLK 20 SDATA VDD1 VDD6 VDD12 VDD17 VDD21 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF 4 24 25 DUTGND DUTGND R3 0 SCLK R4 SDA NI 1 6 12 17 21 XTL P/N: ECS-250-20-5PXDU-F-TR Use SMD footprint VDD1 VDD6 VDD12 VDD17 VDD21 DIFF0 DIFF0# DIFF1 DIFF1# DIFF2 DIFF2# VSS4 VSS24 EPAD DIFF3 DIFF3# 8 9 10 11 14 13 16 15 XIN_DIFFIN# DIFF0 DIFF0# DIFF1 DIFF1# DIFF2 DIFF2# DIFF3 DIFF3# DUTGND Figure 2. QFN-24 Device Connection VDD_3.3V + C6 10uF L1 DUTGND VDD_3V31 VDD_3.3V C7 0.1uF HEADER 1x1 DUTGND 1 HEADER 1x1 JP1 JP2 JP3 JP4 JP5 JUMPER JUMPER JUMPER JUMPER JUMPER L2 L3 L4 L5 L6 TP1 TP2 TP3 TP4 TP5 GND GND GND GND GND DUTGND + C8 10uF R5 0 + C9 C13 1uF DUTGND 10uF R6 0 + C10 C17 1uF DUTGND 10uF R7 0 + C11 C14 1uF DUTGND 10uF R8 0 + C12 C15 1uF DUTGND 10uF R9 0 C16 1uF DUTGND VDD1 VDD21 VDD6 VDD12 VDD17 Figure 3. Device Power Supply 4 Rev. 0.1 GND1 1 Si52144-EVB SCLK/SDATA OE2 VDD_3.3V OE2 VDD_3.3V XIN_DIFFIN#1 HEADER 1x3 VDD 3 2 1 GND P2 XIN_DIFFIN# R16 3 2 1 DUTGND SMA R15 10K HEADER 1x3 10K SCLK DUTGND VDD_3.3V P1 XOUT_DIFFIN1 DUTGND XOUT_DIFFIN SMA R17 10K OE0 DUTGND SDATA VDD_3.3V OE0 VDD HEADER 1x3 3 2 1 R20 GND P3 10K DUTGND OE3 OE3 VDD_3.3V VDD HEADER 1x3 3 2 1 R23 GND P4 10K DUTGND VDD_3.3V OE1 HEADER 1x3 VDD 3 2 1 P5 GND R24 10K DUTGND OE1 SSON SSON VDD_3.3V HEADER 1x3 VDD 3 2 1 P6 GND DUTGND Figure 4. Clock and Control Signals DUTGND DIFF0_1 DIFF2_1 SMA DIFF0 C27 2.0pF DIFF0# C29 2.0pF SMA DIFF2 C28 2.0pF DIFF2# C30 2.0pF DUTGND L1 SHOULD BE SHORT AS POSSIBLE DUTGND L1 SHOULD BE SHORT AS POSSIBLE DIFF0#_1 SMA DIFF2#_1 SMA DUTGND DUTGND DUTGND DUTGND DUTGND DIFF1_1 SMA SMA C32 2.0pF DIFF1 C31 2.0pF DIFF3 DUTGND DUTGND DIFF1# L1 SHOULD BE SHORT AS POSSIBLE C34 2.0pF DIFF3_1 DIFF3# L1 SHOULD BE SHORT AS POSSIBLE DIFF1#_1 SMA DUTGND C33 2.0pF DIFF3#_1 SMA DUTGND DUTGND Figure 5. Differential Clock Signals Rev. 0.1 5 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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