SiM3U1xx-SiM3C1xx Reference Manual

SiM3U1xx/SiM3C1xx
SiM3U1 XX /SiM3C1 XX R EFERENCE M ANUAL
This reference manual accompanies several documents to provide the complete description of SiM3U1xx/
SiM3C1xx devices, part of the Silicon Laboratories 32-bit ARM Cortex-M3 family of microcontrollers.
This document provides the detailed description for all peripherals available on all SiM3U1xx/SiM3C1xx devices.
The peripheral mix varies across different members of the device families. Refer to the device data sheet for details
on the specific peripherals available for each member of the device family. In the event that the device data sheet
and this document contain conflicting information, the device data sheet should be considered the authoritative
source.
Analog
Core
ARM Cortex M3
Power On Reset /
PMU
APB
Debug /
Programming
Hardware
AHB
Watchdog
Timer
(WDTIMER0)
SARADC0
SARADC1
IDAC0
IDAC1
Comparator 0 Comparator 1
Memory
Voltage Supply
Monitor (VMON0)
32/64/128/256 kB Flash
IVC0
Capacitive Sensing 0
4/12/28 kB RAM
I/O
Power
4 kB retention RAM
USB0
EMIF
DMA
2 kB Buffer
Crossbars
External Regulator (EXTVREG0)
16-Channel Controller
5 Bidirectional
Endpoints
Standard I/O pins
Power Management Unit (PMU)
Peripheral Crossbar
Internal Oscillator
5 V tolerant pins
Low Dropout Regulator (LDO0)
Voltage Regulator (VREG0)
High Drive pins
Clocking
Digital
Real-Time Clock (RTC0OSC)
USART0
USART1
UART0
UART1
Low Frequency Oscillator (LFOSC0)
SPI0
SPI1
SPI2
Low Power Oscillator (LPOSC0)
Clock Control
USB Oscillator (USB0OSC)
I2C0
I2C1
I2S0
External Oscillator Control (EXTOSC0)
EPCA0
PCA0
PCA1
Phase-Locked Loop (PLL0OSC)
AES0
Peripheral Clock Control (CLKCTRL)
CRC0
Timer 0
Timer 1
Low Power Timer (LPTIMER0)
DMA access available for these peripherals
Rev. 1.0 11/12
Copyright © 2012 by Silicon Laboratories
SiM3U1xx/SiM3C1xx
SiM3U1xx/SiM3C1xx
Ta ble of Contents
1. Related Documents and Conventions ............................................................................. 11
1.1. Related Documents...................................................................................................... 11
1.2. Conventions ................................................................................................................. 11
2. Memory Organization ........................................................................................................12
2.1. Flash Region ................................................................................................................ 13
2.2. RAM Region ................................................................................................................. 14
2.3. Peripheral Region......................................................................................................... 15
2.4. External Memory .......................................................................................................... 16
2.5. Cortex-M3 Internal Peripherals .................................................................................... 16
3. SiM3U1xx/SiM3C1xx Register Memory Map.................................................................... 17
4. Interrupts ............................................................................................................................ 34
4.1. System Exceptions....................................................................................................... 34
4.2. Interrupt Vector Table................................................................................................... 35
4.3. Priorities ....................................................................................................................... 40
5. Clock Control (CLKCTRL0) ............................................................................................... 43
5.1. Clock Control Features.................................................................................................43
5.2. CLKCTRL0 Registers................................................................................................... 45
5.3. CLKCTRL0 Register Memory Map............................................................................... 53
6. Reset Sources (RSTSRC0)................................................................................................ 55
6.1. Reset Sources Features............................................................................................... 55
6.2. RSTSRC0 Registers .................................................................................................... 59
6.3. RSTSRC0 Register Memory Map ................................................................................ 64
7. Register Security (LOCK0)................................................................................................ 65
7.1. Security Features ......................................................................................................... 65
7.2. LOCK0 Registers ......................................................................................................... 66
7.3. LOCK0 Register Memory Map ..................................................................................... 72
8. Port I/O Configuration ....................................................................................................... 73
8.1. Port Bank Description................................................................................................... 73
8.2. Crossbars ..................................................................................................................... 74
8.3. Port Bank Standard (PBSTD) Features ....................................................................... 85
8.4. Standard Modes of Operation ...................................................................................... 86
8.5. Assigning Standard Port Bank Pins to Analog and Digital Functions........................... 86
8.6. Standard Port Match and Capacitive Sensing (CAPSENSE0) Activity Monitoring ...... 87
8.7. Standard Port Bank Pulse Generator........................................................................... 87
8.8. High Drive (PBHD) Features ........................................................................................ 88
8.9. High Drive Modes of Operation .................................................................................... 89
8.10.High Drive Configuration Procedure ............................................................................90
8.11.High Drive Function Selection...................................................................................... 90
8.12.Port Bank Security ....................................................................................................... 92
8.13.Ports and Power Mode 9 ............................................................................................. 92
8.14.Debugging Interfaces................................................................................................... 93
8.15.External Memory Interface (EMIF)............................................................................... 94
8.16.External Interrupts........................................................................................................97
8.17.PBCFG0 Registers ...................................................................................................... 99
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8.18.PBCFG0 Register Memory Map ................................................................................ 112
8.19.PBSTD0, PBSTD1, PBSTD2, and PBSTD3 Registers..............................................114
8.20.PBSTDn Register Memory Map.................................................................................125
8.21.PBHD4 Registers....................................................................................................... 128
8.22.PBHD4 Register Memory Map................................................................................... 140
9. Power ................................................................................................................................ 142
9.1. Power Modes .............................................................................................................142
9.2. Power Management Unit (PMU0) .............................................................................. 144
9.3. PMU0 Registers ......................................................................................................... 147
9.4. PMU0 Register Memory Map ..................................................................................... 156
10. Core Voltage Regulator (LDO0) ...................................................................................... 158
10.1.Core Voltage Regulator Features .............................................................................. 158
10.2.Functional Description ...............................................................................................159
10.3.LDO0 Registers ......................................................................................................... 160
10.4.LDO0 Register Memory Map ..................................................................................... 161
11. Device Identification (DEVICEID0) and Universally Unique Identifier......................... 162
11.1.Device ID Features .................................................................................................... 162
11.2.Universally Unique Identifier (UUID) ..........................................................................162
11.3.DEVICEID0 Registers................................................................................................ 163
11.4.DEVICEID0 Register Memory Map............................................................................ 167
12. Advanced Encryption Standard (AES0)......................................................................... 169
12.1.AES Features.............................................................................................................169
12.2.Overview ....................................................................................................................170
12.3.Interrupts....................................................................................................................170
12.4.Debug Mode .............................................................................................................. 170
12.5.DMA Configuration and Usage .................................................................................. 171
12.6.Using the AES0 Module for Electronic Codebook (ECB)........................................... 173
12.7.Using the AES0 Module for Cipher Block Chaining (CBC) ........................................ 176
12.8.Using the AES0 Module for Counter (CTR) ............................................................... 183
12.9.Performing “In-Place” Ciphers ................................................................................... 186
12.10.Using the AES0 Module in Software Mode.............................................................. 187
12.11.AES0 Registers........................................................................................................ 188
12.12.AES0 Register Memory Map ................................................................................... 208
13. Capacitive Sensing (CAPSENSE0).................................................................................212
13.1.Capacitive Sensing Features ..................................................................................... 212
13.2.Overview ....................................................................................................................213
13.3.Measurement Overview ............................................................................................. 214
13.4.Conversion and Input Modes ..................................................................................... 216
13.5.Conversion Rate ........................................................................................................ 217
13.6.Accumulation Modes.................................................................................................. 217
13.7.Measuring Multiple Channels in a Single Measurement............................................ 217
13.8.Pin Monitoring ............................................................................................................217
13.9.Compare Threshold ................................................................................................... 218
13.10.Interrupts.................................................................................................................. 218
13.11.Additional Options.................................................................................................... 218
13.12.Taking a Measurement ............................................................................................ 219
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3
SiM3U1xx/SiM3C1xx
13.13.CAPSENSE0 Registers ........................................................................................... 220
13.14.CAPSENSE0 Register Memory Map ....................................................................... 230
14. Comparator (CMP0 and CMP1)....................................................................................... 232
14.1.Comparator Features................................................................................................. 232
14.2.Overview ....................................................................................................................233
14.3.Inputs ......................................................................................................................... 233
14.4.Outputs ...................................................................................................................... 239
14.5.Response Time.......................................................................................................... 240
14.6.Hysteresis .................................................................................................................. 240
14.7.Interrupts and Flags ................................................................................................... 240
14.8.CMP0 and CMP1 Registers....................................................................................... 241
14.9.CMPn Register Memory Map..................................................................................... 246
15. Cyclic Redundancy Check (CRC0).................................................................................247
15.1.CRC Features ............................................................................................................ 247
15.2.Overview ....................................................................................................................248
15.3.Interrupts....................................................................................................................248
15.4.DMA Configuration and Usage .................................................................................. 248
15.5.Byte-Level Bit Reversal and Byte Reordering............................................................249
15.6.CRC0 Registers ......................................................................................................... 252
15.7.CRC0 Register Memory Map..................................................................................... 256
16. DMA Controller (DMACTRL0) ......................................................................................... 257
16.1.DMA Controller Features ........................................................................................... 257
16.2.Overview ....................................................................................................................259
16.3.Interrupts....................................................................................................................259
16.4.Configuring a DMA Channel ...................................................................................... 259
16.5.DMA Channel Transfer Structures............................................................................. 260
16.6.Transfer Types........................................................................................................... 265
16.7.Data Requests ........................................................................................................... 272
16.8.Masking Channels ..................................................................................................... 273
16.9.Errors ......................................................................................................................... 273
16.10.Arbitration................................................................................................................. 274
16.11.DMACTRL0 Registers ............................................................................................. 275
16.12.DMACTRL0 Register Memory Map ......................................................................... 309
17. DMA Crossbar (DMAXBAR0) .......................................................................................... 314
17.1.DMA Crossbar Features ............................................................................................ 314
17.2.Channel Priority ......................................................................................................... 315
17.3.DMAXBAR0 Registers ...............................................................................................316
17.4.DMAXBAR0 Register Memory Map........................................................................... 323
18. External Memory Interface (EMIF0) ................................................................................ 324
18.1.EMIF Features ........................................................................................................... 324
18.2.Overview ....................................................................................................................325
18.3.Signal Descriptions .................................................................................................... 326
18.4.Memory Interface ....................................................................................................... 328
18.5.Non-Multiplexed Output Mode ................................................................................... 330
18.6.Multiplexed Output Mode ........................................................................................... 330
18.7.Mixing Configurations ................................................................................................ 331
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SiM3U1xx/SiM3C1xx
18.8.Transaction Timing .................................................................................................... 332
18.9.Idle and Off States ..................................................................................................... 334
18.10.Additional Features .................................................................................................. 334
18.11.Configuring the External Memory Interface ............................................................. 334
18.12.EMIF0 Registers ......................................................................................................335
18.13.EMIF0 Register Memory Map .................................................................................. 337
18.14.EMIF0_IFx Registers ...............................................................................................338
18.15.EMIFn_IFx Register Memory Map ........................................................................... 348
19. External Oscillator (EXTOSC0) ....................................................................................... 350
19.1.External Oscillator Features....................................................................................... 350
19.2.Introduction ................................................................................................................ 351
19.3.External Crystal Oscillator.......................................................................................... 351
19.4.External CMOS Oscillator .......................................................................................... 352
19.5.External RC Oscillator................................................................................................ 353
19.6.External C Oscillator .................................................................................................. 355
19.7.EXTOSC0 Registers .................................................................................................. 357
19.8.EXTOSC0 Register Memory Map.............................................................................. 359
20. External Regulator (EXTVREG0) .................................................................................... 360
20.1.External Regulator Features ...................................................................................... 360
20.2.Overview ....................................................................................................................361
20.3.Operating Modes ....................................................................................................... 361
20.4.Current Sensing ......................................................................................................... 363
20.5.Current Limiting..........................................................................................................365
20.6.Foldback Limiting ....................................................................................................... 366
20.7.Regulator Stability......................................................................................................367
20.8.Configuring the External Regulator............................................................................ 368
20.9.EXTVREG0 Registers................................................................................................ 369
20.10.EXTVREG0 Register Memory Map ......................................................................... 376
21. Flash Controller (FLASHCTRL0) .................................................................................... 378
21.1.Flash Controller Features .......................................................................................... 378
21.2.Overview ....................................................................................................................379
21.3.Flash Read Control .................................................................................................... 379
21.4.Flash Write and Erase Control................................................................................... 380
21.5.FLASHCTRL0 Registers............................................................................................ 383
21.6.FLASHCTRL0 Register Memory Map........................................................................ 389
22. Inter-Integrated Circuit Bus (I2C0 and I2C1) ................................................................. 391
22.1.I2C Features ..............................................................................................................391
22.2.I2C Protocol ............................................................................................................... 392
22.3.Clocking ..................................................................................................................... 396
22.4.Operational Modes..................................................................................................... 396
22.5.Error Handling............................................................................................................407
22.6.Additional Features .................................................................................................... 408
22.7.Debug Mode .............................................................................................................. 409
22.8.DMA Configuration and Usage .................................................................................. 410
22.9.I2C0 and I2C1 Registers............................................................................................ 415
22.10.I2Cn Register Memory Map ..................................................................................... 431
Rev. 1.0
5
SiM3U1xx/SiM3C1xx
23. Integrated Interchip Sound (I2S0) .................................................................................. 433
23.1.I2S Features ..............................................................................................................433
23.2.Signal Descriptions and Protocol Overview ............................................................... 434
23.3.Clocking ..................................................................................................................... 434
23.4.Clock (SCK) Signal Formatting .................................................................................. 435
23.5.Word Select or Frame Sync (WS) Signal Formatting ................................................ 435
23.6.Basic Data (SD) Signal Formatting ............................................................................ 436
23.7.Left-Justified and Longer-Delay Formats...................................................................436
23.8.Time-Division Multiplexing (TDM) .............................................................................. 437
23.9.Transmitter and Receiver........................................................................................... 438
23.10.Interrupts and Flags ................................................................................................. 439
23.11.Debug Mode ............................................................................................................ 439
23.12.Module Reset........................................................................................................... 439
23.13.DMA Usage and Configuration ................................................................................ 440
23.14.I2S0 Registers ......................................................................................................... 441
23.15.I2S0 Register Memory Map ..................................................................................... 460
24. Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1) .................................. 463
24.1.IDAC Features ........................................................................................................... 463
24.2.IDAC Setup ................................................................................................................464
24.3.Using the IDAC in On-Demand Mode........................................................................ 468
24.4.Using the IDAC in Periodic FIFO-Only Mode............................................................. 468
24.5.Using the IDAC in Periodic FIFO Wrap Mode............................................................468
24.6.Using the IDAC in Periodic DMA Mode (on select IDAC peripherals only)................ 469
24.7.Adjusting the IDAC Output Current............................................................................ 469
24.8.Debug Mode .............................................................................................................. 469
24.9.IDAC0 and IDAC1 Registers...................................................................................... 470
24.10.IDACn Register Memory Map .................................................................................. 479
25. Current-to-Voltage Converter (IVC0).............................................................................. 481
25.1.IVC Features..............................................................................................................481
25.2.Functional Description ...............................................................................................482
25.3.Configuration.............................................................................................................. 482
25.4.IVC0 Registers........................................................................................................... 483
25.5.IVC0 Register Memory Map....................................................................................... 485
26. Low Power Oscillator (LPOSC0)..................................................................................... 486
26.1.Low Power Oscillator Features .................................................................................. 486
26.2.Operation ................................................................................................................... 487
26.3.LPOSC0 Registers..................................................................................................... 488
26.4.LPOSC0 Register Memory Map ................................................................................ 489
27. Low Power Timer (LPTIMER0) ........................................................................................490
27.1.Low Power Timer Features........................................................................................490
27.2.Clocking ..................................................................................................................... 491
27.3.Configuring the Timer ................................................................................................ 492
27.4.Interrupts....................................................................................................................492
27.5.Output ........................................................................................................................ 493
27.6.Automatic Reset......................................................................................................... 493
27.7.Debug Mode .............................................................................................................. 493
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SiM3U1xx/SiM3C1xx
27.8.LPTIMER0 Registers ................................................................................................. 494
27.9.LPTIMER0 Register Memory Map ............................................................................. 499
28. Enhanced Programmable Counter Array (EPCA0) ....................................................... 500
28.1.Enhanced Programmable Counter Array Features.................................................... 500
28.2.Module Overview ....................................................................................................... 502
28.3.Clocking ..................................................................................................................... 503
28.4.Interrupts....................................................................................................................504
28.5.Outputs ...................................................................................................................... 504
28.6.Triggers...................................................................................................................... 507
28.7.Operational Modes..................................................................................................... 508
28.8.DMA Configuration and Usage .................................................................................. 519
28.9.EPCA0 Registers ....................................................................................................... 521
28.10.EPCA0 Register Memory Map.................................................................................534
28.11.EPCA0_CH0-5 Registers......................................................................................... 536
28.12.EPCAn_CHx Register Memory Map........................................................................ 542
29. Programmable Counter Array (PCA0 and PCA1).......................................................... 544
29.1.Programmable Counter Array Features..................................................................... 544
29.2.Module Overview ....................................................................................................... 545
29.3.Clocking ..................................................................................................................... 546
29.4.Interrupts....................................................................................................................547
29.5.Outputs ...................................................................................................................... 547
29.6.Operational Modes..................................................................................................... 548
29.7.PCA0 and PCA1 Registers ........................................................................................559
29.8.PCAn Register Memory Map ..................................................................................... 565
29.9.PCA0_CH0-1 and PCA1_CH0-1 Registers ............................................................... 566
29.10.PCAn_CHx Register Memory Map ..........................................................................572
30. Phase-Locked Loop (PLL0)............................................................................................. 574
30.1.PLL Features .............................................................................................................574
30.2.Overview ....................................................................................................................575
30.3.Interrupts....................................................................................................................575
30.4.Output Modes ............................................................................................................ 575
30.5.Additional Features .................................................................................................... 580
30.6.Advanced Setup Examples........................................................................................582
30.7.PLL0 Registers .......................................................................................................... 583
30.8.PLL0 Register Memory Map ...................................................................................... 592
31. Real Time Clock and Low Frequency Oscillator (RTC0) ..............................................593
31.1.RTC Features ............................................................................................................ 593
31.2.Overview ....................................................................................................................594
31.3.Clocking ..................................................................................................................... 594
31.4.Accessing the Timer .................................................................................................. 600
31.5.Alarms........................................................................................................................ 600
31.6.Interrupts....................................................................................................................602
31.7.Usage Models ............................................................................................................ 602
31.8.RTC0 Registers ......................................................................................................... 603
31.9.RTC0 Register Memory Map ..................................................................................... 613
32. SAR Analog-to-Digital Converter (SARADC0 and SARADC1)..................................... 615
32.1.SARADC Features..................................................................................................... 615
Rev. 1.0
7
SiM3U1xx/SiM3C1xx
32.2.Tracking and Conversion Time .................................................................................. 617
32.3.Burst Mode................................................................................................................. 621
32.4.Channel Sequencer ................................................................................................... 622
32.5.Sample Sync Generator............................................................................................. 626
32.6.Voltage Reference Configuration............................................................................... 627
32.7.Power Configuration .................................................................................................. 628
32.8. Data Output.............................................................................................................629
32.9.Interrupts....................................................................................................................632
32.10.DMA Configuration and Usage ................................................................................ 634
32.11.SARADC0 and SARADC1 Registers....................................................................... 635
32.12.SARADCn Register Memory Map............................................................................ 656
33. Serial Peripheral Interface (SPI0, SPI1 and SPI2) ......................................................... 659
33.1.SPI Features ..............................................................................................................659
33.2.Signal Descriptions .................................................................................................... 660
33.3.Clocking ..................................................................................................................... 661
33.4.Signal Format.............................................................................................................661
33.5.Master Mode Configurations and Data Transfer........................................................ 664
33.6.Slave Mode Configurations and Data Transfer.......................................................... 666
33.7.Interrupts....................................................................................................................668
33.8.Debug Mode .............................................................................................................. 668
33.9.Module Reset.............................................................................................................668
33.10.DMA Configuration and Usage ................................................................................ 669
33.11.SPI0, SPI1 and SPI2 Registers ............................................................................... 670
33.12.SPIn Register Memory Map..................................................................................... 679
34. Sample Sync Generator (SSG0) ..................................................................................... 680
34.1.SSG Features ............................................................................................................ 680
34.2.Phase Generator........................................................................................................ 681
34.3.Pulse Generator......................................................................................................... 681
34.4.SSG0 Registers ......................................................................................................... 685
34.5.SSG0 Register Memory Map ..................................................................................... 689
35. Timers (TIMER0 and TIMER1) ......................................................................................... 690
35.1.Timer Features........................................................................................................... 690
35.2.Clocking ..................................................................................................................... 691
35.3.Configuring Timer Interrupts ...................................................................................... 692
35.4.Timer Synchronization ...............................................................................................693
35.5.Timer Modes .............................................................................................................. 694
35.6.TIMER0 and TIMER1 Registers ................................................................................ 704
35.7.TIMERn Register Memory Map .................................................................................711
36. Universal Synchronous/Asynchronous Receiver/Transmitter
(USART0 and USART1) ................................................................................................... 712
36.1.USART Features........................................................................................................ 712
36.2.Basic Data Format ..................................................................................................... 714
36.3.Baud Rate .................................................................................................................. 714
36.4.Interrupts....................................................................................................................715
36.5.Flow Control............................................................................................................... 716
36.6.Debug Mode .............................................................................................................. 716
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Rev. 1.0
SiM3U1xx/SiM3C1xx
36.7.Sending Data .............................................................................................................717
36.8.Receiving Data........................................................................................................... 719
36.9.Synchronous Communications .................................................................................. 720
36.10.Additional Communication Support..........................................................................722
36.11.DMA Configuration and Usage ................................................................................ 726
36.12.USART0 and USART1 Registers ............................................................................ 727
36.13.USARTn Register Memory Map .............................................................................. 745
37. Universal Asynchronous Receiver/Transmitter (UART0 and UART1) ........................ 747
37.1.UART Features .......................................................................................................... 747
37.2.Basic Data Format ..................................................................................................... 749
37.3.Baud Rate .................................................................................................................. 749
37.4.Interrupts....................................................................................................................750
37.5.Flow Control............................................................................................................... 751
37.6.Debug Mode .............................................................................................................. 751
37.7.Sending Data .............................................................................................................752
37.8.Receiving Data........................................................................................................... 754
37.9.Additional Communication Support............................................................................ 755
37.10.UART0 and UART1 Registers .................................................................................759
37.11.UARTn Register Memory Map.................................................................................775
38. Universal Serial Bus Controller (USB0) ......................................................................... 777
38.1.USB Features ............................................................................................................ 777
38.2.Overview ....................................................................................................................778
38.3.Clocking ..................................................................................................................... 778
38.4.Endpoints ................................................................................................................... 779
38.5.USB Transceiver........................................................................................................ 779
38.6.FIFO Management..................................................................................................... 779
38.7.Function Addressing .................................................................................................. 780
38.8.Function Configuration and Control ........................................................................... 781
38.9.Interrupts....................................................................................................................782
38.10.The Serial Interface Engine ..................................................................................... 782
38.11.Endpoint 0................................................................................................................ 782
38.12.Configuring Endpoints 1-4 ....................................................................................... 783
38.13.Controlling Endpoints 1-4 IN .................................................................................... 784
38.14.Controlling Endpoints 1-4 OUT ................................................................................ 785
38.15.DMA Configuration and Usage ................................................................................ 787
38.16.USB0 Registers ....................................................................................................... 791
38.17.USB0 Register Memory Map ................................................................................... 818
38.18.USB0_EP1-4 Registers ........................................................................................... 822
38.19.USBn_EPx Register Memory Map........................................................................... 830
39. Voltage Supply Monitor (VMON0)................................................................................... 832
39.1.Voltage Supply Monitor Features............................................................................... 832
39.2.VDD Supply Monitoring.............................................................................................. 833
39.3.VREGIN Pin Monitoring ............................................................................................. 834
39.4.VMON0 Registers ......................................................................................................835
39.5.VMON0 Register Memory Map.................................................................................. 837
40. Voltage Reference and Temperature Sensor (VREF0) ................................................. 838
Rev. 1.0
9
SiM3U1xx/SiM3C1xx
40.1.Voltage Reference Features ...................................................................................... 838
40.2.Functional Description ...............................................................................................839
40.3.VREF0 and Temperature Sensor Registers .............................................................. 840
40.4.VREF0 Register Memory Map ................................................................................... 841
41. Voltage Regulator (VREG0)............................................................................................. 842
41.1.Voltage Regulator Features ....................................................................................... 842
41.2.Operational Modes..................................................................................................... 843
41.3.Interrupts and Flags ................................................................................................... 844
41.4.VREG0 Registers....................................................................................................... 845
41.5.VREG0 Register Memory Map .................................................................................. 847
42. Watchdog Timer (WDTIMER0) ........................................................................................848
42.1.Watchdog Timer Features ......................................................................................... 848
42.2.Overview ....................................................................................................................849
42.3.Lock and Key Interface .............................................................................................. 849
42.4.Setting the Early Warning and Reset Thresholds ...................................................... 850
42.5.Interrupts and Flags ................................................................................................... 851
42.6.Debug Mode .............................................................................................................. 851
42.7.WDTIMER0 Registers................................................................................................ 852
42.8.WDTIMER0 Register Memory Map ........................................................................... 857
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Rev. 1.0
1. Related Documents and Conventions
1.1. Related Documents
1.1.1. SiM3U1xx and SiM3C1xx Data Sheets
The Silicon Laboratories SiM3U1xx and SiM3C1xx Data Sheets provide specific information for each device family,
including electrical characteristics, mechanical characteristics, and ordering information.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides functions to modify and read each bit in the
SiM3U1xx and SiM3C1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found online at the following link:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Internal Module
Other Internal
Peripheral Block
External Memory
Block
DMA Block
Memory Block
Input_Pin
External to MCU
Block
Output_Pin
Functional Block
Internal_Input_Signal
Internal_Output_Signal
REGn_NAME / BIT_NAME
Figure 1.1. Block Diagram Conventions
Rev. 1.0
11
Related Documents and Conventions
SiM3U1xx/SiM3C1xx
Memory Organization
SiM3U1xx/SiM3C1xx
2. Memory Organization
The memory organization of the SiM3U1xx/SiM3C1xx devices follows the standard ARM Cortex-M3 structure,
shown in Figure 2.1. There is one 32-bit memory space shared amongst the flash, RAM, SiM3U1xx/SiM3C1xx
Peripherals, External Memory, and M3 Peripherals. The unused memory addresses are reserved and should not
be accessed.
0xFFFFFFFF
0xE0110000
0xE010FFFF
Reserved
Cortex-M3 Internal Peripherals
0xE0000000
0xDFFFFFFF
0xA0000000
0x9FFFFFFF
Reserved
External RAM (EMIF)
0x60000000
0x5FFFFFFF
0x44000000
0x43FFFFFF
Reserved
Peripheral Bit-Band Alias
Peripheral
Region
0x42000000
0x41FFFFFF
0x40046000
0x40045FFF
Reserved
SiM3U1xx Peripherals
0x40000000
0x3FFFFFFF
0x24000000
0x23FFFFFF
Reserved
RAM Bit-Band Alias
0x22000000
0x21FFFFFF
RAM
Region
0x20010800
0x200107FF
0x20010000
0x2000FFFF
0x20008000
0x20007FFF
Reserved
USB Buffer/FIFO
Reserved
Standard RAM
0x20001000
0x20000FFF
0x20000000
0x1FFFFFF
0x00040000
0x0003FFFF
Flash
Region
Retention RAM
Reserved
Flash
0x00000000
Figure 2.1. SiM3U1xx/SiM3C1xx Memory Map
12
Rev. 1.0
2.1. Flash Region
The SiM3U1xx/SiM3C1xx devices implement 256, 128, 64, or 32 kB of flash which is accessible starting at
0x00000000. The flash can be read using standard ARM instructions. The FLASHCTRL0 module should be used
to write and erase flash from firmware.
The flash block can be locked by writing to the lock word located at 0x0003FFFC. A value of 0xFFFFFFFF or
0x00000000 at this location will unlock the flash. Any other value written to this location will lock the entire flash
from external (debugger) or firmware writes or reads until:
An
erase operation is initiated from firmware.
An erase operation is initiated through the debug port (SWD/JTAG).
Firmware writes 0x00000000 to the lock word.
The DMA can access all of flash.
0x1FFF_FFFF
0x0004_0000
0x0003_FFFF
Reserved
Lock Word
0x0003_FFFC
Flash
0x0000_0000
Figure 2.2. SiM3U16x Flash Memory Map (256 kB)
0x1FFF_FFFF
0x0004_0000
0x0003_FFFF
Reserved
Lock Word
0x0003_FFFC
Reserved
0x0001_FFFF
Flash
0X0000_0000
Figure 2.3. SiM3U15x Flash Memory Map (128 kB)
Rev. 1.0
13
Memory Organization
SiM3U1xx/SiM3C1xx
Memory Organization
SiM3U1xx/SiM3C1xx
0x1FFF_FFFF
0x0004_0000
0x0003_FFFF
Reserved
Lock Word
0x0003_FFFC
Reserved
0x0000_FFFF
Flash
0x0000_0000
Figure 2.4. SiM3U14x Flash Memory Map (64 kB)
0x1FFF_FFFF
0x0004_0000
0x0003_FFFF
Reserved
Lock Word
0x0003_FFFC
Reserved
0x0000_7FFF
0x0000_0000
Flash
Figure 2.5. SiM3U13x Flash Memory Map (32 kB)
2.2. RAM Region
The RAM Region of SiM3U1xx/SiM3C1xx devices has the following areas: Standard RAM, Retention RAM, USB
Buffer/FIFO RAM, and the RAM Bit-Banded Alias.
The Standard RAM region implements 28 kB (SiM3U16x and SiM3U15x), 12 kB (SiM3U14x), or 4 kB (SiM3U13x)
of RAM and starts at location 0x20001000.
The SiM3U1xx/SiM3C1xx devices implement 4 kB of Retention RAM located at address 0x20000000. This RAM
will retain it’s value in Power Mode 9 as long as the VDD Monitor has not caused a reset.
The USB Buffer/FIFO RAM should be used by the USB0 Module and not accessed directly. If the USB0 Module is
not in use, the clocks to this memory can be disabled to save power.
The RAM Bit-Band Alias region can be used to perform sets or clears of individual bits in the RAM. Each bit in the
RAM region is represented by the least-significant bit at the word-aligned bit-band alias address.
14
Rev. 1.0
2.3. Peripheral Region
The SiM3U1xx/SiM3C1xx peripheral registers are located starting at address 0x4000_0000. Registers for a
specific module are typically located together in the peripheral region of memory to facilitate structure access from
firmware. Each register may have up to four access methods, implemented as four separate locations in memory.
The four possible access methods are named ALL, SET, CLR, and MSK.
The register’s ALL access address is the primary access point for any register. Individual bits may be Read/Write
(RW), Read-Only (RO), or Write-Only (WO). The ALL access address is implemented for all registers, and where
absolute memory addresses are given in the documentation, they refer to the ALL address. For registers with write
access, the ALL address will directly write all bits of the register. A read of the ALL address will read the current
value in the register.
The SET and CLR addresses provide bit-wise, atomic write access to set and clear bits in the register without
colliding with hardware. Writing a 1 to a bit in the SET address will set the corresponding bit, and writing a 1 to a bit
in the CLR address will clear the corresponding bit. A write of 0 to either SET or CLR will have no effect on the
corresponding bit. For registers implementing SET and CLR access methods, the SET address is at offset 0x4,
and the CLR address is at offset 0x8 from the register’s ALL access address. SET and CLR access are not
implemented on every register.
The MSK address allows a write to a specific range of bits in the register. The upper 16 bits act as a mask for
writing a value in the lower 16 bits of the register. For example, a write of 0x0F000400 to the MASK address would
write a value of 4 to bits [11:8] of the register, while none of the rest of the bits are modified. For registers
implementing the MSK access method, the MSK address is at offset 0xC from the registers ALL access address.
MSK access is implemented for only a small set of registers which may require atomic, simultaneous writes of both
1s and 0s (such as port output registers).
Many control and status registers are supported by the SET and CLR access methods. The Peripheral Bit-Band
Alias region can also be used to perform sets or clears of individual bits in the peripheral registers, which results in
a read-modify-write operation on the bus. Each bit in the registers region is represented by the least-significant bit
at the word-aligned bit-band alias address. When supported, it is recommended to use the SET and CLR registers
instead of the Bit-Band Alias region to change individual bits in a register.
Each peripheral is discussed in detail in the corresponding chapter. The register map for the SiM3U1xx/SiM3C1xx
devices can be found in “3. SiM3U1xx/SiM3C1xx Register Memory Map” . Detailed descriptions of each register
and the bit fields within can be found in the specific peripheral section for that register.
Rev. 1.0
15
Memory Organization
SiM3U1xx/SiM3C1xx
Memory Organization
SiM3U1xx/SiM3C1xx
2.4. External Memory
The EMIF Module accesses the External Memory Region. The EMIF module on the SiM3U1xx/SiM3C1xx devices
supports two interfaces accessed at addresses 0x60000000 and 0x68000000, as shown in Figure 2.6.
SiM3U1xx
External RAM
EMIFn_IF1 Interface
Interface
Configuration
Interface State
Control
Interface Timing
Interface State
Control
0x68000000
EMIFn_IF0 Interface
0x60000000
Interface
Configuration
Interface State
Control
Interface Timing
Interface State
Control
Figure 2.6. SiM3U1xx/SiM3C1xx External Memory Map
More information on the timing and configuration of this module can be found in the EMIF Module documentation.
2.5. Cortex-M3 Internal Peripherals
The Cortex-M3 Internal Peripherals space includes standard M3 functions, such as the NVIC and ETM. For more
information on these functions of the ARM core, consult the ARM Cortex-M3 Reference Manual.
16
Rev. 1.0
3. SiM3U1xx/SiM3C1xx Register Memory Map
This section details the register memory map for the SiM3U1xx/SiM3C1xx devices. Registers are listed in address
order, beginning with 0x4000_0000
CLR(+0x8)
USART0_CONFIG
Module Configuration
0x4000_0000
Y
Y
USART0_MODE
Module Mode Select
0x4000_0010
Y
Y
USART0_FLOWCN
Flow Control
0x4000_0020
Y
Y
USART0_CONTROL
Module Control
0x4000_0030
Y
Y
USART0_IPDELAY
Inter-Packet Delay
0x4000_0040
USART0_BAUDRATE
Transmit and Receive Baud Rate
0x4000_0050
USART0_FIFOCN
FIFO Control
0x4000_0060
Y
Y
USART0_DATA
FIFO Input/Output Data
0x4000_0070
USART1_CONFIG
Module Configuration
0x4000_1000
Y
Y
USART1_MODE
Module Mode Select
0x4000_1010
Y
Y
USART1_FLOWCN
Flow Control
0x4000_1020
Y
Y
USART1_CONTROL
Module Control
0x4000_1030
Y
Y
USART1_IPDELAY
Inter-Packet Delay
0x4000_1040
USART1_BAUDRATE
Transmit and Receive Baud Rate
0x4000_1050
USART1_FIFOCN
FIFO Control
0x4000_1060
Y
Y
USART1_DATA
FIFO Input/Output Data
0x4000_1070
UART0_CONFIG
Module Configuration
0x4000_2000
Y
Y
UART0_MODE
Module Mode Select
0x4000_2010
Y
Y
UART0_FLOWCN
Flow Control
0x4000_2020
Y
Y
UART0_CONTROL
Module Control
0x4000_2030
Y
Y
UART0_IPDELAY
Inter-Packet Delay
0x4000_2040
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
USART0 Registers
USART1 Registers
UART0 Registers
Rev. 1.0
17
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Y
Y
0x4000_3000
Y
Y
Module Mode Select
0x4000_3010
Y
Y
UART1_FLOWCN
Flow Control
0x4000_3020
Y
Y
UART1_CONTROL
Module Control
0x4000_3030
Y
Y
UART1_IPDELAY
Inter-Packet Delay
0x4000_3040
UART1_BAUDRATE
Transmit and Receive Baud Rate
0x4000_3050
UART1_FIFOCN
FIFO Control
0x4000_3060
Y
Y
UART1_DATA
FIFO Input/Output Data
0x4000_3070
SPI0_DATA
Input/Output Data
0x4000_4000
SPI0_CONTROL
Module Control
0x4000_4010
Y
Y
SPI0_CONFIG
Module Configuration
0x4000_4020
Y
Y
SPI0_CLKRATE
Module Clock Rate Control
0x4000_4030
SPI0_FSTATUS
FIFO Status
0x4000_4040
SPI1_DATA
Input/Output Data
0x4000_5000
SPI1_CONTROL
Module Control
0x4000_5010
Y
Y
SPI1_CONFIG
Module Configuration
0x4000_5020
Y
Y
SPI1_CLKRATE
Module Clock Rate Control
0x4000_5030
SPI1_FSTATUS
FIFO Status
0x4000_5040
Register Name
Title
Address
(ALL Access)
UART0_BAUDRATE
Transmit and Receive Baud Rate
0x4000_2050
UART0_FIFOCN
FIFO Control
0x4000_2060
UART0_DATA
FIFO Input/Output Data
0x4000_2070
UART1_CONFIG
Module Configuration
UART1_MODE
UART1 Registers
SPI0 Registers
SPI1 Registers
18
Rev. 1.0
MSK (+0xC)
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
CLR(+0x8)
SPI2_DATA
Input/Output Data
0x4000_6000
SPI2_CONTROL
Module Control
0x4000_6010
Y
Y
SPI2_CONFIG
Module Configuration
0x4000_6020
Y
Y
SPI2_CLKRATE
Module Clock Rate Control
0x4000_6030
SPI2_FSTATUS
FIFO Status
0x4000_6040
I2C0_CONTROL
Module Control
0x4000_9000
Y
Y
I2C0_CONFIG
Module Configuration
0x4000_9010
Y
Y
I2C0_SADDRESS
Slave Address
0x4000_9020
I2C0_SMASK
Slave Address Mask
0x4000_9030
I2C0_DATA
Data Buffer Access
0x4000_9040
I2C0_TIMER
Timer Data
0x4000_9050
I2C0_TIMERRL
Timer Reload Values
0x4000_9060
I2C0_SCONFIG
SCL Signal Configuration
0x4000_9070
I2C0_I2CDMA
DMA Configuration
0x4000_9080
I2C1_CONTROL
Module Control
0x4000_A000
Y
Y
I2C1_CONFIG
Module Configuration
0x4000_A010
Y
Y
I2C1_SADDRESS
Slave Address
0x4000_A020
I2C1_SMASK
Slave Address Mask
0x4000_A030
I2C1_DATA
Data Buffer Access
0x4000_A040
I2C1_TIMER
Timer Data
0x4000_A050
I2C1_TIMERRL
Timer Reload Values
0x4000_A060
I2C1_SCONFIG
SCL Signal Configuration
0x4000_A070
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
SPI2 Registers
I2C0 Registers
I2C1 Registers
Rev. 1.0
19
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Title
Address
(ALL Access)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EPCA0 Registers
EPCA0_CH0_MODE
Channel Capture/Compare Mode
0x4000_E000
EPCA0_CH0_CONTROL
Channel Capture/Compare Control
0x4000_E010
EPCA0_CH0_CCAPV
Channel Compare Value
0x4000_E020
EPCA0_CH0_CCAPVUPD
Channel Compare Update Value
0x4000_E030
EPCA0_CH1_MODE
Channel Capture/Compare Mode
0x4000_E040
EPCA0_CH1_CONTROL
Channel Capture/Compare Control
0x4000_E050
EPCA0_CH1_CCAPV
Channel Compare Value
0x4000_E060
EPCA0_CH1_CCAPVUPD
Channel Compare Update Value
0x4000_E070
EPCA0_CH2_MODE
Channel Capture/Compare Mode
0x4000_E080
EPCA0_CH2_CONTROL
Channel Capture/Compare Control
0x4000_E090
EPCA0_CH2_CCAPV
Channel Compare Value
0x4000_E0A0
EPCA0_CH2_CCAPVUPD
Channel Compare Update Value
0x4000_E0B0
EPCA0_CH3_MODE
Channel Capture/Compare Mode
0x4000_E0C0
EPCA0_CH3_CONTROL
Channel Capture/Compare Control
0x4000_E0D0
EPCA0_CH3_CCAPV
Channel Compare Value
0x4000_E0E0
EPCA0_CH3_CCAPVUPD
Channel Compare Update Value
0x4000_E0F0
EPCA0_CH4_MODE
Channel Capture/Compare Mode
0x4000_E100
EPCA0_CH4_CONTROL
Channel Capture/Compare Control
0x4000_E110
EPCA0_CH4_CCAPV
Channel Compare Value
0x4000_E120
EPCA0_CH4_CCAPVUPD
Channel Compare Update Value
0x4000_E130
EPCA0_CH5_MODE
Channel Capture/Compare Mode
0x4000_E140
EPCA0_CH5_CONTROL
Channel Capture/Compare Control
0x4000_E150
EPCA0_CH5_CCAPV
Channel Compare Value
0x4000_E160
EPCA0_CH5_CCAPVUPD
Channel Compare Update Value
0x4000_E170
EPCA0_MODE
Module Operating Mode
0x4000_E180
EPCA0_CONTROL
Module Control
0x4000_E190
20
Rev. 1.0
MSK (+0xC)
Register Name
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Address
(ALL Access)
Y
Y
Y
Y
Y
Y
EPCA0_STATUS
Module Status
0x4000_E1A0
EPCA0_COUNTER
Module Counter/Timer
0x4000_E1B0
EPCA0_LIMIT
Module Upper Limit
0x4000_E1C0
EPCA0_LIMITUPD
Module Upper Limit Update Value
0x4000_E1D0
EPCA0_DTIME
Phase Delay Time
0x4000_E1E0
EPCA0_DTARGET
DMA Transfer Target
0x4000_E200
PCA0_CH0_MODE
Channel Capture/Compare Mode
0x4000_F000
PCA0_CH0_CONTROL
Channel Capture/Compare Control
0x4000_F010
PCA0_CH0_CCAPV
Channel Compare Value
0x4000_F020
PCA0_CH0_CCAPVUPD
Channel Compare Update Value
0x4000_F030
PCA0_CH1_MODE
Channel Capture/Compare Mode
0x4000_F040
PCA0_CH1_CONTROL
Channel Capture/Compare Control
0x4000_F050
PCA0_CH1_CCAPV
Channel Compare Value
0x4000_F060
PCA0_CH1_CCAPVUPD
Channel Compare Update Value
0x4000_F070
PCA0_MODE
Module Operating Mode
0x4000_F180
PCA0_CONTROL
Module Control
0x4000_F190
Y
Y
PCA0_STATUS
Module Status
0x4000_F1A0
Y
Y
PCA0_COUNTER
Module Counter/Timer
0x4000_F1B0
PCA0_LIMIT
Module Counter/Timer Upper Limit
0x4000_F1C0
PCA1_CH0_MODE
Channel Capture/Compare Mode
0x4001_0000
PCA1_CH0_CONTROL
Channel Capture/Compare Control
0x4001_0010
Y
Y
PCA1_CH0_CCAPV
Channel Compare Value
0x4001_0020
PCA1_CH0_CCAPVUPD
Channel Compare Update Value
0x4001_0030
PCA1_CH1_MODE
Channel Capture/Compare Mode
0x4001_0040
PCA1_CH1_CONTROL
Channel Capture/Compare Control
0x4001_0050
Y
Y
MSK (+0xC)
Title
CLR(+0x8)
Register Name
SET (+0x4)
Table 3.1. Register Memory Map
PCA0 Registers
PCA1 Registers
Rev. 1.0
21
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Address
(ALL Access)
PCA1_CH1_CCAPV
Channel Compare Value
0x4001_0060
PCA1_CH1_CCAPVUPD
Channel Compare Update Value
0x4001_0070
PCA1_MODE
Module Operating Mode
0x4001_0180
PCA1_CONTROL
Module Control
0x4001_0190
Y
Y
PCA1_STATUS
Module Status
0x4001_01A0
Y
Y
PCA1_COUNTER
Module Counter/Timer
0x4001_01B0
PCA1_LIMIT
Module Counter/Timer Upper Limit
0x4001_01C0
TIMER0_CONFIG
High and Low Timer Configuration
0x4001_4000
Y
Y
TIMER0_CLKDIV
Module Clock Divider Control
0x4001_4010
TIMER0_COUNT
Timer Value
0x4001_4020
TIMER0_CAPTURE
Timer Capture/Reload Value
0x4001_4030
TIMER1_CONFIG
High and Low Timer Configuration
0x4001_5000
Y
Y
TIMER1_CLKDIV
Module Clock Divider Control
0x4001_5010
TIMER1_COUNT
Timer Value
0x4001_5020
TIMER1_CAPTURE
Timer Capture/Reload Value
0x4001_5030
USB0_FADDR
Function Address
0x4001_8000
USB0_POWER
Power Control
0x4001_8010
USB0_IOINT
IN/OUT Endpoint Interrupt Flags
0x4001_8020
Y
USB0_CMINT
Common Interrupt Flags
0x4001_8030
Y
USB0_IOINTE
IN/OUT Endpoint Interrupt Control
0x4001_8040
USB0_CMINTEPE
Common Interrupt and Endpoint Control
0x4001_8050
USB0_CRCONTROL
Clock Recovery Control
0x4001_8060
USB0_FRAME
Frame Number
0x4001_8070
USB0_TCONTROL
Transceiver Control
0x4001_8200
Register Name
TIMER0 Registers
TIMER1 Registers
USB0 Registers
22
Rev. 1.0
MSK (+0xC)
Title
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
CLR(+0x8)
USB0_CLKSEL
Module Clock Select
0x4001_8300
USB0_OSCCONTROL
Oscillator Control
0x4001_8310
Y
Y
USB0_AFADJUST
Oscillator Additional Frequency Adjust
0x4001_8320
Y
Y
USB0_FADJUST
Oscillator Frequency Adjust
0x4001_8330
USB0_DMAFIFO
DMA Data FIFO Access
0x4001_8400
USB0_DMACONTROL
DMA Control
0x4001_8410
USB0_EP0CONTROL
Endpoint 0 Control
0x4001_8810
USB0_EP0COUNT
Endpoint 0 Data Count
0x4001_8820
USB0_EP0FIFO
Endpoint 0 Data FIFO Access
0x4001_8830
USB0_EP1_EPMPSIZE
Endpoint Maximum Packet Size
0x4001_8880
USB0_EP1_EPCONTROL
Endpoint Control
0x4001_8890
USB0_EP1_EPCOUNT
Endpoint Data Count
0x4001_88A0
USB0_EP1_EPFIFO
Endpoint Data FIFO Access
0x4001_88B0
USB0_EP2_EPMPSIZE
Endpoint Maximum Packet Size
0x4001_8900
USB0_EP2_EPCONTROL
Endpoint Control
0x4001_8910
USB0_EP2_EPCOUNT
Endpoint Data Count
0x4001_8920
USB0_EP2_EPFIFO
Endpoint Data FIFO Access
0x4001_8930
USB0_EP3_EPMPSIZE
Endpoint Maximum Packet Size
0x4001_8980
USB0_EP3_EPCONTROL
Endpoint Control
0x4001_8990
USB0_EP3_EPCOUNT
Endpoint Data Count
0x4001_89A0
USB0_EP3_EPFIFO
Endpoint Data FIFO Access
0x4001_89B0
USB0_EP4_EPMPSIZE
Endpoint Maximum Packet Size
0x4001_8A00
USB0_EP4_EPCONTROL
Endpoint Control
0x4001_8A10
USB0_EP4_EPCOUNT
Endpoint Data Count
0x4001_8A20
USB0_EP4_EPFIFO
Endpoint Data FIFO Access
0x4001_8A30
Register Name
Title
Rev. 1.0
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
23
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
SARADC0_CONFIG
Module Configuration
0x4001_A000
Y
Y
SARADC0_CONTROL
Measurement Control
0x4001_A010
Y
Y
SARADC0_SQ7654
Channel Sequencer Time Slots 4-7 Setup
0x4001_A020
SARADC0_SQ3210
Channel Sequencer Time Slots 0-3 Setup
0x4001_A030
SARADC0_CHAR32
Conversion Characteristic 2 and 3 Setup
0x4001_A040
Y
Y
SARADC0_CHAR10
Conversion Characteristic 0 and 1 Setup
0x4001_A050
Y
Y
SARADC0_DATA
Output Data Word
0x4001_A060
SARADC0_WCLIMITS
Window Comparator Limits
0x4001_A070
SARADC0_ACC
Accumulator Initial Value
0x4001_A080
SARADC0_STATUS
Module Status
0x4001_A090
Y
Y
SARADC0_FIFOSTATUS
FIFO Status
0x4001_A0A0
SARADC1_CONFIG
Module Configuration
0x4001_B000
Y
Y
SARADC1_CONTROL
Measurement Control
0x4001_B010
Y
Y
SARADC1_SQ7654
Channel Sequencer Time Slots 4-7 Setup
0x4001_B020
SARADC1_SQ3210
Channel Sequencer Time Slots 0-3 Setup
0x4001_B030
SARADC1_CHAR32
Conversion Characteristic 2 and 3 Setup
0x4001_B040
Y
Y
SARADC1_CHAR10
Conversion Characteristic 0 and 1 Setup
0x4001_B050
Y
Y
SARADC1_DATA
Output Data Word
0x4001_B060
SARADC1_WCLIMITS
Window Comparator Limits
0x4001_B070
SARADC1_ACC
Accumulator Initial Value
0x4001_B080
SARADC1_STATUS
Module Status
0x4001_B090
Y
Y
SARADC1_FIFOSTATUS
FIFO Status
0x4001_B0A0
SSG0_CONFIG
Module Configuration
0x4001_E000
SSG0_CONTROL
Module Control
0x4001_E010
Y
Y
Register Name
Title
Address
(ALL Access)
SARADC0 Registers
SARADC1 Registers
SSG0 Registers
24
Rev. 1.0
MSK (+0xC)
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
CLR(+0x8)
CMP0_CONTROL
Module Control
0x4001_F000
Y
Y
CMP0_MODE
Input and Module Mode
0x4001_F010
Y
Y
CMP1_CONTROL
Module Control
0x4002_0000
Y
Y
CMP1_MODE
Input and Module Mode
0x4002_0010
Y
Y
CAPSENSE0_CONTROL
Module Control
0x4002_3000
Y
Y
CAPSENSE0_MODE
Measurement Mode
0x4002_3010
Y
Y
CAPSENSE0_DATA
Measurement Data
0x4002_3020
CAPSENSE0_SCAN
Channel Scan Enable
0x4002_3030
CAPSENSE0_CSTH
Compare Threshold
0x4002_3040
CAPSENSE0_MUX
Mux Channel Select
0x4002_3050
EMIF0_CONTROL
Module Control
0x4002_6000
Y
Y
EMIF0_STATUS
Module Status
0x4002_6020
EMIF0_IF0_CONFIG
Interface Configuration
0x4002_6080
Y
Y
EMIF0_IF0_IFRT
Interface Read Timing
0x4002_6090
EMIF0_IF0_IFWT
Interface Write Timing
0x4002_60A0
EMIF0_IF0_IFRCST
Interface Read Control States
0x4002_60B0
EMIF0_IF0_IFWCST
Interface Write Control States
0x4002_60C0
EMIF0_IF1_CONFIG
Interface Configuration
0x4002_6100
Y
Y
EMIF0_IF1_IFRT
Interface Read Timing
0x4002_6110
EMIF0_IF1_IFWT
Interface Write Timing
0x4002_6120
EMIF0_IF1_IFRCST
Interface Read Control States
0x4002_6130
EMIF0_IF1_IFWCST
Interface Write Control States
0x4002_6140
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
CMP0 Registers
CMP1 Registers
CAPSENSE0 Registers
EMIF0 Registers
Rev. 1.0
25
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Title
Address
(ALL Access)
Y
Y
AES0 Registers
AES0_CONTROL
Module Control
0x4002_7000
AES0_XFRSIZE
Number of Blocks
0x4002_7010
AES0_DATAFIFO
Input/Output Data FIFO Access
0x4002_7020
AES0_XORFIFO
XOR Data FIFO Access
0x4002_7030
AES0_HWKEY0
Hardware Key Word 0
0x4002_7040
AES0_HWKEY1
Hardware Key Word 1
0x4002_7050
AES0_HWKEY2
Hardware Key Word 2
0x4002_7060
AES0_HWKEY3
Hardware Key Word 3
0x4002_7070
AES0_HWKEY4
Hardware Key Word 4
0x4002_7080
AES0_HWKEY5
Hardware Key Word 5
0x4002_7090
AES0_HWKEY6
Hardware Key Word 6
0x4002_70A0
AES0_HWKEY7
Hardware Key Word 7
0x4002_70B0
AES0_HWCTR0
Hardware Counter Word 0
0x4002_70C0
AES0_HWCTR1
Hardware Counter Word 1
0x4002_70D0
AES0_HWCTR2
Hardware Counter Word 2
0x4002_70E0
AES0_HWCTR3
Hardware Counter Word 3
0x4002_70F0
AES0_STATUS
Module Status
0x4002_7100
Y
Y
CRC0_CONTROL
Module Control
0x4002_8000
Y
Y
CRC0_DATA
Input/Result Data
0x4002_8010
CRC0_RDATA
Bit-Reversed Output Data
0x4002_8020
CRC0 Registers
26
Rev. 1.0
MSK (+0xC)
Register Name
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
CLR(+0x8)
RTC0_CONFIG
RTC Configuration
0x4002_9000
Y
Y
RTC0_CONTROL
RTC Control
0x4002_9010
Y
Y
RTC0_ALARM0
RTC Alarm 0
0x4002_9020
RTC0_ALARM1
RTC Alarm 1
0x4002_9030
RTC0_ALARM2
RTC Alarm 2
0x4002_9040
RTC0_SETCAP
RTC Timer Set/Capture Value
0x4002_9050
RTC0_LFOCONTROL
LFOSC Control
0x4002_9060
PBCFG0_CONTROL0
Global Port Control 0
0x4002_A000
Y
Y
PBCFG0_CONTROL1
Global Port Control 1
0x4002_A010
Y
Y
PBCFG0_XBAR0L
Crossbar 0 Control (Low)
0x4002_A020
Y
Y
PBCFG0_XBAR0H
Crossbar 0 Control (High)
0x4002_A030
Y
Y
PBCFG0_XBAR1
Crossbar 1 Control
0x4002_A040
Y
Y
PBCFG0_PBKEY
Global Port Key
0x4002_A050
PBSTD0_PB
Output Latch
0x4002_A0A0
Y
Y
PBSTD0_PBPIN
Pin Value
0x4002_A0B0
PBSTD0_PBMDSEL
Mode Select
0x4002_A0C0
Y
Y
PBSTD0_PBSKIPEN
Crossbar Pin Skip Enable
0x4002_A0D0
Y
Y
PBSTD0_PBOUTMD
Output Mode
0x4002_A0E0
Y
Y
PBSTD0_PBDRV
Drive Strength
0x4002_A0F0
Y
Y
PBSTD0_PM
Port Match Value
0x4002_A100
Y
Y
PBSTD0_PMEN
Port Match Enable
0x4002_A110
Y
Y
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
RTC0 Registers
PBCFG0 Registers
PBSTD0 Registers
Rev. 1.0
Y
27
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Title
Address
(ALL Access)
MSK (+0xC)
Register Name
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Y
Y
Y
PBSTD1 Registers
PBSTD1_PB
Output Latch
0x4002_A140
PBSTD1_PBPIN
Pin Value
0x4002_A150
PBSTD1_PBMDSEL
Mode Select
0x4002_A160
Y
Y
PBSTD1_PBSKIPEN
Crossbar Pin Skip Enable
0x4002_A170
Y
Y
PBSTD1_PBOUTMD
Output Mode
0x4002_A180
Y
Y
PBSTD1_PBDRV
Drive Strength
0x4002_A190
Y
Y
PBSTD1_PM
Port Match Value
0x4002_A1A0
Y
Y
PBSTD1_PMEN
Port Match Enable
0x4002_A1B0
Y
Y
PBSTD2_PB
Output Latch
0x4002_A1E0
Y
Y
PBSTD2_PBPIN
Pin Value
0x4002_A1F0
PBSTD2_PBMDSEL
Mode Select
0x4002_A200
Y
Y
PBSTD2_PBSKIPEN
Crossbar Pin Skip Enable
0x4002_A210
Y
Y
PBSTD2_PBOUTMD
Output Mode
0x4002_A220
Y
Y
PBSTD2_PBDRV
Drive Strength
0x4002_A230
Y
Y
PBSTD2_PM
Port Match Value
0x4002_A240
Y
Y
PBSTD2_PMEN
Port Match Enable
0x4002_A250
Y
Y
PBSTD2_PBLOCK
Lock Control
0x4002_A260
PBSTD2_PBPGEN
Pulse Generator Pin Enable
0x4002_A270
PBSTD2_PBPGPHASE
Pulse Generator Phase
0x4002_A280
PBSTD3_PB
Output Latch
0x4002_A320
Y
Y
PBSTD3_PBPIN
Pin Value
0x4002_A330
PBSTD3_PBMDSEL
Mode Select
0x4002_A340
Y
Y
PBSTD3_PBSKIPEN
Crossbar Pin Skip Enable
0x4002_A350
Y
Y
PBSTD3_PBOUTMD
Output Mode
0x4002_A360
Y
Y
PBSTD2 Registers
Y
PBSTD3 Registers
28
Rev. 1.0
Y
CLR(+0x8)
PBSTD3_PBDRV
Drive Strength
0x4002_A370
Y
Y
PBSTD3_PM
Port Match Value
0x4002_A380
Y
Y
PBSTD3_PMEN
Port Match Enable
0x4002_A390
Y
Y
PBSTD3_PBLOCK
Lock Control
0x4002_A3A0
PBHD4_PB
Output Latch
0x4002_A3C0
Y
Y
PBHD4_PBPIN
Pin Value
0x4002_A3D0
PBHD4_PBMDSEL
Mode Select
0x4002_A3E0
Y
Y
PBHD4_PBDEN
Driver Enable
0x4002_A3F0
Y
Y
PBHD4_PBDRV
Drive Strength
0x4002_A400
Y
Y
PBHD4_PBILIMIT
Current Limit
0x4002_A410
Y
Y
PBHD4_PBFSEL
Function Select
0x4002_A430
PBHD4_PBSS
Safe State Control
0x4002_A440
Y
Y
PBHD4_PBLOCK
Lock Control
0x4002_A450
CLKCTRL0_CONTROL
Module Control
0x4002_D000
CLKCTRL0_AHBCLKG
AHB Clock Gate
0x4002_D010
Y
Y
CLKCTRL0_APBCLKG0
APB Clock Gate 0
0x4002_D020
Y
Y
CLKCTRL0_APBCLKG1
APB Clock Gate 1
0x4002_D030
Y
Y
CLKCTRL0_PM3CN
Power Mode 3 Clock Control
0x4002_D040
RSTSRC0_RESETEN
System Reset Source Enable
0x4002_D060
Y
Y
RSTSRC0_RESETFLAG
System Reset Flags
0x4002_D070
RSTSRC0_CONFIG
Configuration Options
0x4002_D080
Y
Y
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
PBHD4 Registers
Y
CLKCTRL0 Registers
RSTSRC0 Registers
Rev. 1.0
29
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Address
(ALL Access)
FLASHCTRL0_CONFIG
Controller Configuration
0x4002_E000
Y
Y
FLASHCTRL0_WRADDR
Flash Write Address
0x4002_E0A0
FLASHCTRL0_WRDATA
Flash Write Data
0x4002_E0B0
FLASHCTRL0_KEY
Flash Modification Key
0x4002_E0C0
FLASHCTRL0_TCONTROL
Flash Timing Control
0x4002_E0D0
Module Control
0x4002_F000
Y
Y
WDTIMER0_CONTROL
Module Control
0x4003_0000
Y
Y
WDTIMER0_STATUS
Module Status
0x4003_0010
Y
Y
WDTIMER0_THRESHOLD
Threshold Values
0x4003_0020
WDTIMER0_WDTKEY
Module Key
0x4003_0030
IDAC0_CONTROL
Module Control
0x4003_1000
Y
Y
IDAC0_DATA
Output Data
0x4003_1010
IDAC0_BUFSTATUS
FIFO Buffer Status
0x4003_1020
Y
Y
IDAC0_BUFFER10
FIFO Buffer Entries 0 and 1
0x4003_1030
IDAC0_BUFFER32
FIFO Buffer Entries 2 and 3
0x4003_1040
IDAC0_GAINADJ
Output Current Gain Adjust
0x4003_1050
IDAC1_CONTROL
Module Control
0x4003_2000
Y
Y
IDAC1_DATA
Output Data
0x4003_2010
IDAC1_BUFSTATUS
FIFO Buffer Status
0x4003_2020
Y
Y
IDAC1_BUFFER10
FIFO Buffer Entries 0 and 1
0x4003_2030
IDAC1_BUFFER32
FIFO Buffer Entries 2 and 3
0x4003_2040
IDAC1_GAINADJ
Output Current Gain Adjust
0x4003_2050
Register Name
FLASHCTRL0 Registers
VMON0 Registers
VMON0_CONTROL
WDTIMER0 Registers
IDAC0 Registers
IDAC1 Registers
30
Rev. 1.0
MSK (+0xC)
Title
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
CLR(+0x8)
DMACTRL0_STATUS
Controller Status
0x4003_6000
DMACTRL0_CONFIG
Controller Configuration
0x4003_6004
DMACTRL0_BASEPTR
Base Pointer
0x4003_6008
DMACTRL0_ABASEPTR
Alternate Base Pointer
0x4003_600C
DMACTRL0_CHSTATUS
Channel Status
0x4003_6010
DMACTRL0_CHSWRCN
Channel Software Request Control
0x4003_6014
DMACTRL0_CHREQMSET
Channel Request Mask Set
0x4003_6020
DMACTRL0_CHREQMCLR
Channel Request Mask Clear
0x4003_6024
DMACTRL0_CHENSET
Channel Enable Set
0x4003_6028
DMACTRL0_CHENCLR
Channel Enable Clear
0x4003_602C
DMACTRL0_CHALTSET
Channel Alternate Select Set
0x4003_6030
DMACTRL0_CHALTCLR
Channel Alternate Select Clear
0x4003_6034
DMACTRL0_CHHPSET
Channel High Priority Set
0x4003_6038
DMACTRL0_CHHPCLR
Channel High Priority Clear
0x4003_603C
DMACTRL0_BERRCLR
Bus Error Clear
0x4003_604C
DMAXBAR0_DMAXBAR0
Channel 0-7 Trigger Select
0x4003_7000
Y
Y
DMAXBAR0_DMAXBAR1
Channel 8-15 Trigger Select
0x4003_7010
Y
Y
LPTIMER0_CONTROL
Module Control
0x4003_8000
Y
Y
LPTIMER0_DATA
Timer and Comparator Data
0x4003_8010
LPTIMER0_STATUS
Module Status
0x4003_8020
Y
Y
Control
0x4003_9000
Y
Y
Voltage Reference Control
0x4003_9010
Y
Y
Register Name
Title
Address
(ALL Access)
MSK (+0xC)
SET (+0x4)
Table 3.1. Register Memory Map
DMACTRL0 Registers
DMAXBAR0 Registers
LPTIMER0 Registers
LDO0 Registers
LDO0_CONTROL
VREF0 Registers
VREF0_CONTROL
Rev. 1.0
31
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
I2S0_TXCONTROL
Transmit Control
0x4003_A000
Y
Y
I2S0_TXMODE
Transmit Mode
0x4003_A010
Y
Y
I2S0_FSDUTY
Frame Sync Duty Cycle
0x4003_A020
I2S0_RXCONTROL
Receive Control
0x4003_A030
Y
Y
I2S0_RXMODE
Receive Mode
0x4003_A040
Y
Y
I2S0_CLKCONTROL
Clock Control
0x4003_A050
Y
Y
I2S0_TXFIFO
Transmit Data FIFO
0x4003_A060
I2S0_RXFIFO
Receive Data FIFO
0x4003_A070
I2S0_FIFOSTATUS
FIFO Status
0x4003_A080
I2S0_FIFOCONTROL
FIFO Control
0x4003_A090
Y
Y
I2S0_INTCONTROL
Interrupt Control
0x4003_A0A0
Y
Y
I2S0_STATUS
Module Status
0x4003_A0B0
Y
Y
I2S0_DMACONTROL
DMA Control
0x4003_A0C0
Y
Y
I2S0_DBGCONTROL
Debug Control
0x4003_A0D0
Y
Y
PLL0_DIVIDER
Reference Divider Setting
0x4003_B000
PLL0_CONTROL
Module Control
0x4003_B010
Y
Y
PLL0_SSPR
Spectrum Spreading Control
0x4003_B020
PLL0_CALCONFIG
Calibration Configuration
0x4003_B030
Oscillator Control
0x4003_C000
Y
Y
Module Control
0x4004_0000
Y
Y
Low Power Oscillator Output Value
0x4004_1000
Y
Y
Register Name
Title
Address
(ALL Access)
I2S0 Registers
PLL0 Registers
EXTOSC0 Registers
EXTOSC0_CONTROL
VREG0 Registers
VREG0_CONTROL
LPOSC0 Registers
LPOSC0_OSCVAL
32
Rev. 1.0
MSK (+0xC)
CLR(+0x8)
Table 3.1. Register Memory Map
SET (+0x4)
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Address
(ALL Access)
Y
Y
Y
Y
MSK (+0xC)
Title
CLR(+0x8)
Register Name
SET (+0x4)
Table 3.1. Register Memory Map
EXTVREG0 Registers
EXTVREG0_CONTROL
Module Control
0x4004_2000
EXTVREG0_CONFIG
Module Configuration
0x4004_2010
EXTVREG0_STATUS
Module Status
0x4004_2020
EXTVREG0_CSCONTROL
Current Sense Control
0x4004_2040
EXTVREG0_CSCONFIG
Current Sense Configuration
0x4004_2050
Module Control
0x4004_4000
Y
Y
PMU0_CONTROL
Module Control
0x4004_8000
Y
Y
PMU0_CONFIG
Module Configuration
0x4004_8010
Y
Y
PMU0_STATUS
Module Status
0x4004_8020
Y
Y
PMU0_WAKEEN
Wake Source Enable
0x4004_8030
Y
Y
PMU0_WAKESTATUS
Wake Source Status
0x4004_8040
PMU0_PWEN
Pin Wake Pin Enable
0x4004_8050
Y
Y
PMU0_PWPOL
Pin Wake Pin Polarity Select
0x4004_8060
Y
Y
LOCK0_KEY
Security Key
0x4004_9000
LOCK0_PERIPHLOCK0
Peripheral Lock Control 0
0x4004_9020
Y
Y
LOCK0_PERIPHLOCK1
Peripheral Lock Control 1
0x4004_9040
Y
Y
System Configuration
0x4004_90B0
Y
Y
DEVICEID0_DEVICEID0
Device ID Word 0
0x4004_90C0
DEVICEID0_DEVICEID1
Device ID Word 1
0x4004_90D0
DEVICEID0_DEVICEID2
Device ID Word 2
0x4004_90E0
DEVICEID0_DEVICEID3
Device ID Word 3
0x4004_90F0
IVC0 Registers
IVC0_CONTROL
PMU0 Registers
LOCK0 Registers
SCONFIG0 Registers
SCONFIG0_CONFIG
DEVICEID0 Registers
Rev. 1.0
33
SiM3U1xx/SiM3C1xx Register Memory Map
SiM3U1xx/SiM3C1xx
Interrupts
SiM3U1xx/SiM3C1xx
4. Interrupts
SiM3U1xx/SiM3C1xx devices implement the standard nested-vectored interrupt controller (NVIC) available in the
ARM Cortex-M3 core. The specific system exceptions, interrupt vectors, and priority implementation are described
in the following sections.
4.1. System Exceptions
The system-level exceptions on SiM3U1xx/SiM3C1xx devices are shown in Table 4.1.
Table 4.1. System Exceptions
34
Exception
Number
Type
Priority
Description
1
Reset
–3
System Reset.
2
NMI
–2
External NMI Input.
3
Hard Fault
–1
All fault conditions if the corresponding fault handler is disabled.
4
MemManage
Fault
5
Bus Fault
6
Usage Fault
7
Reserved
8
Reserved
9
Reserved
10
Reserved
11
SVcall
Programmable System Service Call using SWI or SVC instruction.
12
Debug Monitor
Programmable Breakpoint, Watchpoint, or external debug request.
13
Reserved
14
PendSV
15
SYSTICK
Programmable MMU/MPU fault (not supported).
Programmable AHB error received from slave (either prefetch abort or data
abort).
Programmable Exception due to program error.
Programmable Pendable reset for system device.
Programmable System tick timer.
Rev. 1.0
4.2. Interrupt Vector Table
The interrupt vector table for SiM3U1xx/SiM3C1xx is shown in Table 4.2.
Table 4.2. Interrupt Vector Table
Position Default
Priority
Name/
Description
–3
Reset
–2
NMI
–1
Hard Fault
0
MemManage
1
Bus Fault
2
Usage Fault
3
4
Sources
Default
Address
System Reset
0x00000004
NMI
0x00000008
All fault conditions if the corresponding fault handler is
disabled
0x0000000C
MMU/MPU fault (not supported)
0x00000010
AHB error received from slave (either prefetch abort or
data abort)
0x00000014
Exception due to program error
0x00000018
Reserved
0x0000001C
Reserved
0x00000020
Reserved
0x00000024
Reserved
0x00000028
SVcall
System Service Call using SWI or SVC instruction
Debug Monitor Breakpoint
Watchpoint
External debug request
Reserved
5
PendSV
6
SYSTICK
0
7
WDTIMER0
1
8
2
0x0000002C
0x00000030
0x00000034
Pendable reset for system device
0x00000038
System tick timer
0x0000003C
First threshold crossed
0x00000040
PBEXT0
External pin (INT0.x) rising edge
External pin (INT0.x) falling edge
0x00000044
9
PBEXT1
External pin (INT1.x) rising edge
External pin (INT1.x) falling edge
0x00000048
3
10
RTC0ALRM
Alarm 0
Alarm 1
Alarm 2
0x0000004C
4
11
DMACH0
DMA Channel 0 done
0x00000050
5
12
DMACH1
DMA Channel 1 done
0x00000054
6
13
DMACH2
DMA Channel 2 done
0x00000058
7
14
DMACH3
DMA Channel 3 done
0x0000005C
8
15
DMACH4
DMA Channel 4 done
0x00000060
Rev. 1.0
35
Interrupts
SiM3U1xx/SiM3C1xx
Interrupts
SiM3U1xx/SiM3C1xx
Table 4.2. Interrupt Vector Table (Continued)
Position Default
Priority
36
Name/
Description
Sources
Default
Address
9
16
DMACH5
DMA Channel 5 done
0x00000064
10
17
DMACH6
DMA Channel 6 done
0x00000068
11
18
DMACH7
DMA Channel 7 done
0x0000006C
12
19
DMACH8
DMA Channel 8 done
0x00000070
13
20
DMACH9
DMA Channel 9 done
0x00000074
14
21
DMACH10
DMA Channel 10 done
0x00000078
15
22
DMACH11
DMA Channel 11 done
0x0000007C
16
23
DMACH12
DMA Channel 12 done
0x00000080
17
24
DMACH13
DMA Channel 13 done
0x00000084
18
25
DMACH14
DMA Channel 14 done
0x00000088
19
26
DMACH15
DMA Channel 15 done
0x0000008C
20
27
TIMER0L
TIMER0 Low overflow
0x00000090
21
28
TIMER0H
TIMER0 High overflow
0x00000094
22
29
TIMER1L
TIMER1 Low overflow
0x00000098
23
30
TIMER1H
TIMER1 High overflow
0x0000009C
24
31
EPCA0
Counter overflow
Halt external signal is high
Channel compare or match
Channel intermediate overflow
0x000000A0
25
32
PCA0
Counter overflow
Channel compare or match
Channel intermediate overflow
0x000000A4
26
33
PCA1
Counter overflow
Channel compare or match
Channel intermediate overflow
0x000000A8
27
34
USART0
Receive frame error
Receive parity error
Receive overrun
Receive data request
Transmit SmartCard parity error
Transmit underrun
Transmit data request
Transmit complete
0x000000AC
Rev. 1.0
Table 4.2. Interrupt Vector Table (Continued)
Position Default
Priority
Name/
Description
Sources
Default
Address
Receive frame error
Receive parity error
Receive overrun
Receive data request
Transmit SmartCard parity error
Transmit underrun
Transmit data request
Transmit complete
0x000000B0
SPI0
Shift Register empty
FIFO underrun
Mode fault
Slave Select pin
Illegal receive FIFO access
Receive FIFO Overrun
Receive FIFO read request
Illegal transmit FIFO access
Transmit FIFO overrun
Transmit FIFO write request
0x000000B4
37
SPI1
Shift Register empty
FIFO underrun
Mode fault
Slave Select pin
Illegal receive FIFO access
Receive FIFO Overrun
Receive FIFO read request
Illegal transmit FIFO access
Transmit FIFO overrun
Transmit FIFO write request
0x000000B8
38
SPI2
Shift Register empty
FIFO underrun
Mode fault
Slave Select pin
Illegal receive FIFO access
Receive FIFO Overrun
Receive FIFO read request
Illegal transmit FIFO access
Transmit FIFO overrun
Transmit FIFO write request
0x000000BC
28
35
USART1
29
36
30
31
Rev. 1.0
37
Interrupts
SiM3U1xx/SiM3C1xx
Interrupts
SiM3U1xx/SiM3C1xx
Table 4.2. Interrupt Vector Table (Continued)
Position Default
Priority
38
Name/
Description
Sources
Default
Address
32
39
I2C0
Start
Transmit complete
Receive complete
Acknowledge
Stop
Timer byte 0 overflow
Timer byte 1 overflow
Timer byte 2 overflow
Timer byte 3 overflow
Arbitration lost
0x000000C0
33
40
I2C1
Start
Transmit complete
Receive complete
Acknowledge
Stop
Timer byte 0 overflow
Timer byte 1 overflow
Timer byte 2 overflow
Timer byte 3 overflow
Arbitration lost
0x000000C4
34
41
USB0
Endpoint 0 data
Endpoint 1-4 IN or OUT data
Suspend
Resume
Start-of-Frame (SOF)
USB Reset
0x000000C8
35
42
SARADC0
Conversion complete
Scan complete
FIFO underrun
FIFO overrun
Window comparator threshold crossed
0x000000CC
36
43
SARADC1
Conversion complete
Scan complete
FIFO underrun
FIFO overrun
Window comparator threshold crossed
0x000000D0
37
44
CMP0
Rising edge occurred
Falling edge occurred
0x000000D4
38
45
CMP1
Rising edge occurred
Falling edge occurred
0x000000D8
39
46
CAPSENSE0
Conversion complete
Compare threshold crossed
End-of-Scan
0x000000DC
Rev. 1.0
Table 4.2. Interrupt Vector Table (Continued)
Position Default
Priority
Name/
Description
Sources
Default
Address
40
47
I2S0RX
Receive FIFO overflow
Receive FIFO high watermark crossed
0x000000E0
41
48
I2S0TX
Transmit FIFO underflow
Transmit FIFO low watermark crossed
0x000000E4
42
49
AES0
Operation complete
Error occurred
0x000000E8
43
50
VDDLOW
VDD falls below the early warning threshold
0x000000EC
44
51
RTC0FAIL
RTC0 Oscillator failed
0x000000F0
45
52
PMATCH0
Port Match event
0x000000F4
46
53
UART0
Receive frame error
Receive parity error
Receive overrun
Receive data request
Transmit SmartCard parity error
Transmit underrun
Transmit data request
Transmit complete
0x000000F8
47
54
UART1
Receive frame error
Receive parity error
Receive overrun
Receive data request
Transmit SmartCard parity error
Transmit underrun
Transmit data request
Transmit complete
0x000000FC
48
55
IDAC0
Data buffer overrun
Data buffer underrun
Data buffer went empty
0x00000100
49
56
IDAC1
Data buffer overrun
Data buffer underrun
Data buffer went empty
0x00000104
50
57
LPTIMER0
Timer overflow
Compare threshold crossed
0x00000108
51
58
PLL0
Lock saturation high or low
Oscillator lock
0x0000010C
52
59
VBUS Invalid
The VBUS input is below the valid threshold
0x00000110
53
60
VREGLOW
VREGIN / 4 falls below the early warning threshold
0x00000114
Rev. 1.0
39
Interrupts
SiM3U1xx/SiM3C1xx
Interrupts
SiM3U1xx/SiM3C1xx
4.3. Priorities
The SiM3U1xx/SiM3C1xx devices implement 4 bits of interrupt priority, as shown in Figure 4.1.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Programmable Interrupt Priority Level
Bit 1
Bit 0
Reserved
Figure 4.1. SiM3U1xx/SiM3C1xx Interrupt Priorities
In addition to the different priority levels, the NVIC allows for different priority groups, as shown in Table 4.3. These
groups determine the number of bits used to determine the Preempt Priority and Subpriority settings for each
interrupt. A higher priority interrupt can preempt or interrupt a lower priority interrupt. If two interrupts of the same
priority occur at the same time, the interrupts cannot preempt each other and the interrupt with the higher
Subpriority (lowest value) will be taken first. The Reset, NMI, and Hard Fault exceptions have fixed negative
priorities to always take precedence over other interrupts in the system.
Table 4.3. Priority Groups
40
Priority Group
Preempt
Priority Field
Size
Subpriority
Field Size
0–3
[7:4]
None
4
[7:5]
[4]
5
[7:6]
[5:4]
6
[7]
[6:4]
7
None
[7:4]
Rev. 1.0
Bit 7
Bit 6
Bit 5
Bit 4
Preempt Priority Level
Bit 3
Bit 2
Subpriority
Bit 1
Bit 0
Reserved
Figure 4.2. Priority Group 4 Fields
Table 4.4. Priority Levels with Priority Group 4
Preempt Priority
Subpriority
Priority Value
1 (Highest)
1 (Highest)
0x00
1
2
0x10
2
1
0x20
2
2
0x30
3
1
0x40
3
2
0x50
4
1
0x60
4
2
0x70
5
1
0x80
5
2
0x90
6
1
0xA0
6
2
0xB0
7
1
0xC0
7
2
0xD0
8
1
0xE0
8 (Lowest)
2 (Lowest)
0xF0
Rev. 1.0
41
Interrupts
SiM3U1xx/SiM3C1xx
Interrupts
SiM3U1xx/SiM3C1xx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Subpriority Level
Bit 1
Reserved
Figure 4.3. Priority Group 7 Fields
Table 4.5. Priority Levels with Priority Group 7 (Interrupts Cannot Preempt)
Preempt Priority
Subpriority
Priority Value
1 (Highest)
0x00
2
0x10
3
0x20
4
0x30
5
0x40
6
0x50
7
0x60
8
0x70
9
0x80
10
0x90
11
0xA0
12
0xB0
13
0xC0
14
0xD0
15
0xE0
16 (Lowest)
0xF0
The Priority Group and Interrupt Priority settings are in the NVIC.
42
Rev. 1.0
Bit 0
5. Clock Control (CLKCTRL0)
This section describes the Clock Control (CLKCTRL) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
Note that features related to the USB peripheral are only available on the SiM3U1xx device family.
5.1. Clock Control Features
Clock Control includes the following features:
Support
for multiple oscillator sources for system clock with smooth and glitch-less transition.
clock gating controls for most peripherals and modules.
Multiple options for AHB clock settings and a divider for the APB clock.
Synchronization between AHB and APB clocks.
Individual
Clock Control
RAM
RTC0
Oscillator
DMA
LFOSC0
AHB clock
LPOSC0
Flash
EMIF
AHB Clock
Divider
USB Buffer
PLL0 Registers
External
Oscillator
PLL0
Oscillator
PBCFG and
PB0/1/2/3/4
APB Clock
Divider
APB clock
USART0
USART1
USB0
Oscillator
UART0
Figure 5.1. Clock Control Block Diagram
Clock Control generates the two system clocks: AHB and APB. The AHB clock services memory peripherals and
can be derived from one of seven sources: the RTC0 Oscillator, the Low Frequency Oscillator, the Low Power
Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the USB0 Oscillator.
In addition, a divider for the AHB clock provides flexible clock options for the device. The APB clock services data
peripherals and is synchronized with the AHB clock. The APB clock can be equal to the AHB clock (if AHB is less
than or equal to 50 MHz) or set to the AHB clock divided by two.
Rev. 1.0
43
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Clock Control allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any
registers in a peripheral with disabled clocks will be unable to be accessed (read or write) until the clocks are
enabled. Most peripherals have clocks off by default after a power-on reset.
44
Rev. 1.0
5.2. CLKCTRL0 Registers
This section contains the detailed register descriptions for CLKCTRL0 registers.
31
29
28
Name
Reserved
Type
R
R
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
APBDIV
Bit
EXTESEL
30
OBUSYF
Register 5.1. CLKCTRL0_CONTROL: Module Control
RW
R
RW
Reset
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
AHBDIV
Reserved
AHBSEL
Type
R
RW
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CLKCTRL0_CONTROL = 0x4002_D000
Table 5.1. CLKCTRL0_CONTROL Register Bit Descriptions
Bit
Name
Function
31:30
Reserved
Must write reset value.
29
OBUSYF
Oscillators Busy Flag.
When set, this status bit indicates that a requested clock switch-over is in progress.
Firmware should wait until the flag is clear to reconfigure the AHBSEL, AHBDIV,
and APBDIV fields.
28
EXTESEL
External Clock Edge Select.
Select the edge mode used by the external clock for the TIMER, PCA, and EPCA
modules. This external clock is synchronized with the APB clock.
0: External clock generated by both rising and falling edges of the external oscillator.
1: External clock generated by only rising edges of the external oscillator.
27:17
Reserved
16
APBDIV
Must write reset value.
APB Clock Divider.
Divides the APB clock from the AHB clock. This field should not be modified when
OBUSYF is set.
0: APB clock is the same as the AHB clock (divided by 1).
1: APB clock is the AHB clock divided by 2.
15:11
Reserved
Must write reset value.
Rev. 1.0
45
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Table 5.1. CLKCTRL0_CONTROL Register Bit Descriptions
Bit
Name
10:8
AHBDIV
Function
AHB Clock Divider.
Divides the AHB clock. This field should not be modified when OBUSYF is set.
000: AHB clock divided by 1.
001: AHB clock divided by 2.
010: AHB clock divided by 4.
011: AHB clock divided by 8.
100: AHB clock divided by 16.
101: AHB clock divided by 32.
110: AHB clock divided by 64.
111: AHB clock divided by 128.
7:3
Reserved
Must write reset value.
2:0
AHBSEL
AHB Clock Source Select.
This field should not be modified when OBUSYF is set.
000: AHB clock source is the Low-Power Oscillator.
001: AHB clock source is the Low-Frequency Oscillator.
010: AHB clock source is the RTC Oscillator.
011: AHB clock source is the External Oscillator.
100: AHB clock source is the USB Oscillator.
101: AHB clock source is the PLL.
110: AHB clock source is a divided version of the Low-Power Oscillator.
111: Reserved.
46
Rev. 1.0
Register 5.2. CLKCTRL0_AHBCLKG: AHB Clock Gate
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
RAMCEN
0
DMACEN
0
FLASHCEN
0
EMIF0CEN
0
USB0BCEN
Reset
Type
R
RW
RW
RW
RW
RW
0
0
1
0
1
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CLKCTRL0_AHBCLKG = 0x4002_D010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 5.2. CLKCTRL0_AHBCLKG Register Bit Descriptions
Bit
Name
31:5
Reserved
4
USB0BCEN
Function
Must write reset value.
USB0 Buffer Clock Enable.
0: Disable the AHB clock to the USB0 Buffer (default).
1: Enable the AHB clock to the USB0 Buffer.
3
EMIF0CEN
EMIF Clock Enable.
0: Disable the AHB clock to the External Memory Interface (EMIF) (default).
1: Enable the AHB clock to the External Memory Interface (EMIF).
2
FLASHCEN
Flash Clock Enable.
0: Disable the AHB clock to the Flash.
1: Enable the AHB clock to the Flash (default).
1
DMACEN
DMA Controller Clock Enable.
0: Disable the AHB clock to the DMA Controller (default).
1: Enable the AHB clock to the DMA Controller.
0
RAMCEN
RAM Clock Enable.
0: Disable the AHB clock to the RAM.
1: Enable the AHB clock to the RAM (default).
Rev. 1.0
47
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
ADC0CEN
TIMER1CEN
17
16
Type
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PLL0CEN
ADC1CEN
18
PB0CEN
CMP0CEN
19
USART0CEN
CMP1CEN
20
USART1CEN
CS0CEN
21
UART0CEN
AES0CEN
22
UART1CEN
CRC0CEN
23
SPI0CEN
IDAC0CEN
24
SPI1CEN
IDAC1CEN
25
SPI2CEN
LPT0CEN
26
I2C0CEN
I2S0CEN
27
I2C1CEN
USB0CEN
28
EPCA0CEN
EVREGCEN
29
PCA0CEN
Name
FLCTRLCEN
30
PCA1CEN
31
SSG0CEN
Bit
Reserved
Register 5.3. CLKCTRL0_APBCLKG0: APB Clock Gate 0
TIMER0CEN
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CLKCTRL0_APBCLKG0 = 0x4002_D020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 5.3. CLKCTRL0_APBCLKG0 Register Bit Descriptions
Bit
Name
31
Reserved
30
FLCTRLCEN
Function
Must write reset value.
Flash Controller Clock Enable.
0: Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default).
1: Enable the APB clock to the Flash Controller Module (FLASHCTRL0).
29
EVREGCEN
External Regulator Clock Enable.
0: Disable the APB clock to the External Regulator Module (EXTVREG0) (default).
1: Enable the APB clock to the External Regulator Module (EXTVREG0).
28
USB0CEN
USB0 Module Clock Enable.
0: Disable the APB clock to the USB0 Module (default).
1: Enable the APB clock to the USB0 Module.
27
I2S0CEN
I2S0 Module Clock Enable.
0: Disable the APB clock to the I2S0 Module (default).
1: Enable the APB clock to the I2S0 Module.
26
LPT0CEN
Low Power Timer (LPTIMER0) Module Clock Enable.
0: Disable the APB clock to the LPTIMER0 Module (default).
1: Enable the APB clock to the LPTIMER0 Module.
48
Rev. 1.0
Table 5.3. CLKCTRL0_APBCLKG0 Register Bit Descriptions
Bit
Name
25
IDAC1CEN
Function
IDAC1 Module Clock Enable.
0: Disable the APB clock to the IDAC1 Module (default).
1: Enable the APB clock to the IDAC1 Module.
24
IDAC0CEN
IDAC0 Module Clock Enable.
0: Disable the APB clock to the IDAC0 Module (default).
1: Enable the APB clock to the IDAC0 Module.
23
CRC0CEN
CRC0 Module Clock Enable.
0: Disable the APB clock to the CRC0 Module (default).
1: Enable the APB clock to the CRC0 Module.
22
AES0CEN
AES0 Module Clock Enable.
0: Disable the APB clock to the AES0 Module (default).
1: Enable the APB clock to the AES0 Module.
21
CS0CEN
Capacitive Sensing (CAPSENSE0) Module Clock Enable.
0: Disable the APB clock to the CAPSENSE0 Module (default).
1: Enable the APB clock to the CAPSENSE0 Module.
20
CMP1CEN
Comparator 1 Module Clock Enable.
0: Disable the APB clock to the Comparator 1 Module (default).
1: Enable the APB clock to the Comparator 1 Module.
19
CMP0CEN
Comparator 0 Module Clock Enable.
0: Disable the APB clock to the Comparator 0 Module (default).
1: Enable the APB clock to the Comparator 0 Module.
18
ADC1CEN
SARADC1 Module Clock Enable.
0: Disable the APB clock to the SARADC1 Module (default).
1: Enable the APB clock to the SARADC1 Module.
17
ADC0CEN
SARADC0 Module Clock Enable.
0: Disable the APB clock to the SARADC0 Module (default).
1: Enable the APB clock to the SARADC0 Module.
16
TIMER1CEN
TIMER1 Module Clock Enable.
0: Disable the APB clock to the TIMER1 Module (default).
1: Enable the APB clock to the TIMER1 Module.
15
TIMER0CEN
TIMER0 Module Clock Enable.
0: Disable the APB clock to the TIMER0 Module (default).
1: Enable the APB clock to the TIMER0 Module.
14
SSG0CEN
SSG0 Module Clock Enable.
0: Disable the APB clock to the SSG0 Module (default).
1: Enable the APB clock to the SSG0 Module.
13
PCA1CEN
PCA1 Module Clock Enable.
0: Disable the APB clock to the PCA1 Module (default).
1: Enable the APB clock to the PCA1 Module.
Rev. 1.0
49
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Table 5.3. CLKCTRL0_APBCLKG0 Register Bit Descriptions
Bit
Name
12
PCA0CEN
Function
PCA0 Module Clock Enable.
0: Disable the APB clock to the PCA0 Module (default).
1: Enable the APB clock to the PCA0 Module.
11
EPCA0CEN
EPCA0 Module Clock Enable.
0: Disable the APB clock to the EPCA0 Module (default).
1: Enable the APB clock to the EPCA0 Module.
10
I2C1CEN
I2C1 Module Clock Enable.
0: Disable the APB clock to the I2C1 Module (default).
1: Enable the APB clock to the I2C1 Module.
9
I2C0CEN
I2C0 Module Clock Enable.
0: Disable the APB clock to the I2C0 Module (default).
1: Enable the APB clock to the I2C0 Module.
8
SPI2CEN
SPI2 Module Clock Enable.
0: Disable the APB clock to the SPI2 Module (default).
1: Enable the APB clock to the SPI2 Module.
7
SPI1CEN
SPI1 Module Clock Enable.
0: Disable the APB clock to the SPI1 Module (default).
1: Enable the APB clock to the SPI1 Module.
6
SPI0CEN
SPI0 Module Clock Enable.
0: Disable the APB clock to the SPI0 Module (default).
1: Enable the APB clock to the SPI0 Module.
5
UART1CEN
UART1 Module Clock Enable.
0: Disable the APB clock to the UART1 Module (default).
1: Enable the APB clock to the UART1 Module.
4
UART0CEN
UART0 Module Clock Enable.
0: Disable the APB clock to the UART0 Module (default).
1: Enable the APB clock to the UART0 Module.
3
USART1CEN
USART1 Module Clock Enable.
0: Disable the APB clock to the USART1 Module (default).
1: Enable the APB clock to the USART1 Module.
2
USART0CEN
USART0 Module Clock Enable.
0: Disable the APB clock to the USART0 Module (default).
1: Enable the APB clock to the USART0 Module.
1
PB0CEN
Port Bank Module Clock Enable.
0: Disable the APB clock to the Port Bank Modules (default).
1: Enable the APB clock to the Port Bank Modules.
0
PLL0CEN
PLL Module Clock Enable.
0: Disable the APB clock to the PLL0 registers (default).
1: Enable the APB clock to the PLL0 registers.
50
Rev. 1.0
Register 5.4. CLKCTRL0_APBCLKG1: APB Clock Gate 1
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
MISC0CEN
0
MISC1CEN
0
MISC2CEN
Reset
Type
R
RW
RW
RW
0
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CLKCTRL0_APBCLKG1 = 0x4002_D030
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 5.4. CLKCTRL0_APBCLKG1 Register Bit Descriptions
Bit
Name
31:3
Reserved
2
MISC2CEN
Function
Must write reset value.
Miscellaneous 2 Clock Enable.
0: Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default).
1: Enable the APB clock to the OSCVLDF flag in the EXTOSC module.
1
MISC1CEN
Miscellaneous 1 Clock Enable.
0: Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA
Crossbar (DMAXBAR0) modules.
1: Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA
Crossbar (DMAXBAR0) modules (default).
0
MISC0CEN
Miscellaneous 0 Clock Enable.
0: Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0,
VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default).
1: Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0,
VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules.
Rev. 1.0
51
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Register 5.5. CLKCTRL0_PM3CN: Power Mode 3 Clock Control
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
PM3CEN
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PM3CSEL
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CLKCTRL0_PM3CN = 0x4002_D040
Table 5.5. CLKCTRL0_PM3CN Register Bit Descriptions
Bit
Name
Function
31:17
Reserved
Must write reset value.
16
PM3CEN
Power Mode 3 Fast-Wake Clock Enable.
When set to 1, the core will automatically switch to the clock source defined by
PM3CSEL during Power Mode 3, which speeds up the wakeup time.
0: Disable the core clock when in Power Mode 3.
1: The core clock is enabled and runs off the clock selected by PM3CSEL in Power
Mode 3.
15:3
Reserved
Must write reset value.
2:0
PM3CSEL
Power Mode 3 Fast-Wake Clock Source.
If PM3CEN is set to 1, this clock selection should be the LFOSC0 or RTC0OSC
clock to save power while in Power Mode 3. Additionally, the AHB and APB source
must be set to the Low-Power Oscillator or divided version of the Low-Power Oscillator.
000: Power Mode 3 clock source is the Low-Power Oscillator.
001: Power Mode 3 clock source is the Low-Frequency Oscillator.
010: Power Mode 3 clock source is the RTC Oscillator.
011: Power Mode 3 clock source is the External Oscillator.
100: Power Mode 3 clock source is the USB Oscillator.
101: Power Mode 3 clock source is the PLL.
110: Power Mode 3 clock source is a divided version of the Low-Power Oscillator.
111: Reserved.
52
Rev. 1.0
CLKCTRL0_APBCLKG0 CLKCTRL0_AHBCLKG CLKCTRL0_CONTROL Register Name
ALL Address
0x4002_D010
0x4002_D020
0x4002_D000
Access Methods
ALL | SET | CLR
ALL | SET | CLR
ALL
Reserved
Bit 31
Reserved
FLCTRLCEN
Bit 30
OBUSYF
EVREGCEN
Bit 29
EXTESEL
USB0CEN
Bit 28
I2S0CEN
Bit 27
LPT0CEN
Bit 26
IDAC1CEN
Bit 25
IDAC0CEN
Bit 24
CRC0CEN
Bit 23
Reserved
AES0CEN
Bit 22
CS0CEN
Bit 21
CMP1CEN
Bit 20
CMP0CEN
Bit 19
Reserved
ADC1CEN
Bit 18
ADC0CEN
Bit 17
APBDIV
TIMER1CEN
Bit 16
TIMER0CEN
Bit 15
SSG0CEN
Bit 14
Reserved
PCA1CEN
Bit 13
PCA0CEN
Bit 12
EPCA0CEN
Bit 11
I2C1CEN
Bit 10
AHBDIV
I2C0CEN
Bit 9
SPI2CEN
Bit 8
SPI1CEN
Bit 7
SPI0CEN
Bit 6
Reserved
UART1CEN
Bit 5
USB0BCEN
UART0CEN
Bit 4
EMIF0CEN
USART1CEN
Bit 3
FLASHCEN
USART0CEN
Bit 2
AHBSEL
DMACEN
PB0CEN
Bit 1
RAMCEN
PLL0CEN
Bit 0
5.3. CLKCTRL0 Register Memory Map
Table 5.6. CLKCTRL0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
53
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Table 5.6. CLKCTRL0 Memory Map
CLKCTRL0_PM3CN CLKCTRL0_APBCLKG1 Register Name
0x4002_D030
ALL Address
0x4002_D040
ALL | SET | CLR
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Reserved
Bit 17
PM3CEN
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Reserved
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MISC2CEN
Bit 2
PM3CSEL
MISC1CEN
Bit 1
MISC0CEN
Bit 0
Clock Control (CLKCTRL0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
54
Rev. 1.0
6. Reset Sources (RSTSRC0)
This section describes the Reset Sources (RSTSRC) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
Note that features related to the USB peripheral are only available on the SiM3U1xx device family.
6.1. Reset Sources Features
The Reset Source block includes the following features:
Separate
Separate
enable mask bits for each reset source other than the RESET pin.
flags for each reset source indicating the cause of the last reset.
Reset Sources
RESET
VDD Supply
Monitor
Missing Clock
Detector
Watchdog Timer
Software Reset
system reset
Comparator 0
Comparator 1
USB0
RTC0 Alarm
PMU / Wakeup
Core Reset
Figure 6.1. Reset Sources Block Diagram
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
The
core halts program execution.
registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
Clocks to all AHB peripherals other than the USB0 buffers are enabled.
Clocks to all APB peripherals other than Watchdog Timer, EMIF0, and DMAXBAR are disabled.
Module
Rev. 1.0
55
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VDD Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal lowpower oscillator. The Watchdog Timer is enabled with the low frequency oscillator as its clock source. Program
execution begins at location 0x00000000.
6.1.1. Power-On Reset
During power-up, the device is held in a reset state and the RESET pin voltage tracks VDD (through a weak pullup) until the device is released from reset. After VDD settles above VPOR, a delay occurs before the device is
released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast
VDD ramps from 0 V to VPOR). Figure 6.2 plots the power-on and VDD monitor reset timing. For valid ramp times,
the power-on reset delay (tPOR) is given in the electrical specifications chapter of the device data sheet.
Note: VDD ramp times slower than the maximum may cause the device to be released from reset before VDD reaches the
VPOR level.
On exit from a power-on reset, the PORRF flag is set by hardware. When PORRF or VMONRF is set, all of the
other reset flags in the RESETFLAG Register are indeterminate. Since all resets cause program execution to begin
at the same location, firmware can read the PORF flag in the PMU STATUS register to determine if a power-up was
the cause of reset. The contents of internal data memory, including retention RAM should be assumed to be
undefined after a power-on reset.
volts
~0.8
VDD
VPOR
D
0.6
VD
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
~0.5
t
Logic HIGH
RESET
TPORDelay
Logic LOW
Power-On
Reset
Figure 6.2. Power-On Reset Timing Diagram
56
Rev. 1.0
6.1.2. VDD Monitor Power-Fail Reset
SiM3U1xx/SiM3C1xx devices have a VDD Supply Monitor that is enabled and selected as a reset source after
each power-on. When enabled and selected as a reset source, any power down transition or power irregularity that
causes VDD to drop below VRST will cause the RESET pin to be driven low and the core will be held in a reset
state. When VDD returns to a level above VRST, the core will be released from the reset state.
After a power-fail reset, the VDDMRF flag reads 1, all of the other reset flags in the RESETFLAG Register are
indeterminate, the contents of RAM are invalid, and the VDD Monitor is enabled and selected as a reset source.
The enable state of the VDD Monitor and its selection as a reset source is only altered by power-on and power-fail
resets. For example, if the VDD supply monitor is de-selected as a reset source and disabled by firmware, then a
software reset is performed, the VDD Monitor will remain disabled and de-selected after the reset.
To allow firmware early notification that a power failure is about to occur, the VDDHI bit is cleared when the VDD
supply falls below the VDD High threshold. The VDDHI bit can be configured to generate an interrupt.
Note: To protect the integrity of flash contents, the VDD Monitor must be enabled and selected as a reset source if firmware
contains routines which erase or write flash memory. If the VDD Monitor is not enabled, any erase or write performed on
flash memory will be ignored.
Important Notes:
The
Power-on Reset (POR) delay is not incurred after a VDD supply monitor reset.
should take care not to inadvertently disable the VDD Monitor as a reset source when writing to
RESETEN to enable other reset sources or to trigger a software reset. All writes to RESETEN should
explicitly set VDDMREN to 1 to keep the VDD Monitor enabled as a reset source.
The VDD Monitor must be enabled before selecting it as a reset source. Selecting the VDD Monitor as a
reset source before it has stabilized may generate a system reset. In systems where this reset would be
undesirable, a delay should be introduced between enabling the VDD Monitor and selecting it as a reset
source. The procedure for enabling the VDD Monitor and selecting it as a reset source from a disabled
state is:
1. Enable the VDD Monitor.
Firmware
2. Wait for the VDD Monitor to stabilize (optional).
3. Select the VDD Monitor as a reset source (VDDMREN bit).
6.1.3. External Reset
The external RESET pin provides a means for external circuitry to force the device into a reset state. Asserting an
active-low signal on the RESET pin generates a reset; an external pull-up and/or decoupling of the RESET pin may
be necessary to avoid erroneous noise-induced resets. The external reset remains functional even when the
device is in the low power modes. The PINRF flag is set on exit from an external reset.
6.1.4. Missing Clock Detector Reset
The missing clock detector (MCD) is a one-shot circuit that is triggered by the APB clock. The APB clock is derived
from the AHB clock, so monitoring the APB clock will detect a failure in either clock tree. If the APB clock remains
high or low for longer than the Missing Clock Detector Timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRF flag will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0.
Writing a 1 to the MCDREN bit enables the Missing Clock Detector; writing a 0 disables it. The missing clock
detector reset is automatically disabled when the device is in the low power modes. Upon exit from either low
power state, the enabled/disabled state of this reset source is restored to its previous value. The state of the
RESET pin is unaffected by this reset. Missing clock detector timeout values are given in the device data sheet
electrical specifications tables.
6.1.5. Comparator Reset
Comparator 0 (CMP0) or Comparator 1 (CMP1) can be configured as a reset source by writing a 1 to the
CMP0REN or CMP1REN bit. The Comparator should be enabled and allowed to settle prior to writing to the enable
bits to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator reset is
active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device
Rev. 1.0
57
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
is put into the reset state. After a Comparator reset, the CMP0RF or CMP1RF flag will read 1 signifying
Comparator 0 or Comparator 1 as the reset source; otherwise, these bits read 0. The Comparator reset source
remains functional even when the device is in the low power modes as long as Comparator is also enabled as a
wake-up source. The state of the RESET pin is unaffected by this reset.
6.1.6. Watchdog Timer Reset
The Watchdog Timer (WDTIMER0) can be used to recover from certain types of system malfunctions. If a system
malfunction prevents user firmware from updating the Watchdog Timer, a reset is generated and the WDTRF bit is
set to 1. The Watchdog Timer can be enabled or disabled as a reset source using the WDTREN bit. Note that
WDTREN will always read back 1 if the Watchdog Timer is ever disabled. The Watchdog Timer is automatically
disabled as a reset source when the device is in the low power modes. Upon exit from either low power state, the
enabled/disabled state of this reset source is restored to its previous value.The state of the RESET pin is
unaffected by this reset.
6.1.7. RTC Reset
The RTC0 Module can generate a system reset on two events: RTC0 Oscillator Fail or RTC0 Alarm 0. The RTC0
Oscillator Fail event occurs when the RTC0 Missing Clock Detector is enabled and the RTC0 clock is below the
Missing Clock Detector Trigger Frequency. An RTC0 Alarm event occurs when the RTC0 Alarm 0 is enabled and
the RTC0 timer value matches the Alarm 0 threshold value. The RTC0 can be configured as a reset source by
writing a 1 to the RTC0REN bit. The RTC0 reset remains functional even when the device is in a low power mode.
The state of the RESET pin is unaffected by this reset.
6.1.8. Software Reset
Firmware may force a reset by writing a 1 to the SWREN bit. The SWRF bit will read 1 following a firmware forced
reset. The state of the RESET pin is unaffected by this reset.
6.1.9. Core Reset
The Core Reset is a firmware reset generated in the NVIC by setting the SYSRESETREQ bit.
6.1.10. USB Reset
Writing 1 to the USB0REN bit selects USB0 as a reset source. With USB0 selected as a reset source, a system
reset will be generated when either of the following occur:
1. Reset signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for
Reset signaling to be detected.
2. A rising or falling edge on the VBUS pin.
The USB0RF bit will read 1 following a USB0 reset. The state of the RESET pin is unaffected by this reset.
6.1.11. PMU or Wake Reset
The PMU will issue a system reset whenever one of the wakeup events occurs. In power mode PM9, this is the
only way to wake the system from this mode other than a RESET pin reset. The WAKERF flag indicates when a
PMU Wake reset occurs.
All RSTSRC0 registers may be locked against writes by setting the CLKRSTL bit in the LOCK0_PERIPHLOCK0
register to 1.
58
Rev. 1.0
6.2. RSTSRC0 Registers
This section contains the detailed register descriptions for RSTSRC0 registers.
Register 6.1. RSTSRC0_RESETEN: System Reset Source Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
VMONREN
0
Reserved
0
MCDREN
0
WDTREN
0
SWREN
0
CMP0REN
0
CMP1REN
0
USB0REN
0
RTC0REN
0
WAKEREN
Reset
Reserved
Type
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
0
0
1
0
1
1
Reset
0
0
0
0
1
1
Register ALL Access Address
RSTSRC0_RESETEN = 0x4002_D060
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 6.1. RSTSRC0_RESETEN Register Bit Descriptions
Bit
Name
31:12
Reserved
11
WAKEREN
Function
Must write reset value.
PMU Wakeup Reset Enable.
This bit always reads back as 1.
0: Reserved.
1: Enable the PMU Wakeup event as a reset source.
10
RTC0REN
RTC0 Reset Enable.
0: Disable the RTC0 event as a reset source.
1: Enable the RTC0 event as a reset source.
9
USB0REN
USB0 Reset Enable.
0: Disable the USB0 reset event as a reset source.
1: Enable the USB0 reset event as a reset source.
8
CMP1REN
Comparator 1 Reset Enable.
0: Disable the Comparator 1 event as a reset source.
1: Enable the Comparator 1 event as a reset source.
7
CMP0REN
Comparator 0 Reset Enable.
0: Disable the Comparator 0 event as a reset source.
1: Enable the Comparator 0 event as a reset source.
Rev. 1.0
59
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Table 6.1. RSTSRC0_RESETEN Register Bit Descriptions
Bit
Name
6
SWREN
Function
Software Reset.
Writing a 1 to this bit generates a Software Reset.
5
WDTREN
Watchdog Timer Reset Enable.
0: Disable the Watchdog Timer event as a reset source.
1: Enable the Watchdog Timer event as a reset source.
4
MCDREN
Missing Clock Detector Reset Enable.
0: Disable the Missing Clock Detector event as a reset source.
1: Enable the Missing Clock Detector event as a reset source.
3
Reserved
2
VMONREN
Must write reset value.
Voltage Supply Monitor VDD Reset Enable.
0: Disable the Voltage Supply Monitor VDD event as a reset source.
1: Enable the Voltage Supply Monitor VDD event as a reset source.
1:0
60
Reserved
Must write reset value.
Rev. 1.0
Register 6.2. RSTSRC0_RESETFLAG: System Reset Flags
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PINRF
0
PORRF
0
VMONRF
0
CORERF
0
MCDRF
0
WDTRF
0
SWRF
0
CMP0RF
0
CMP1RF
0
USB0RF
0
RTC0RF
0
WAKERF
Reset
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
X
X
X
X
Reset
0
0
0
0
Register ALL Access Address
RSTSRC0_RESETFLAG = 0x4002_D070
Table 6.2. RSTSRC0_RESETFLAG Register Bit Descriptions
Bit
Name
Function
31:12
Reserved
Must write reset value.
11
WAKERF
PMU Wakeup Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A PMU Wakeup event did not cause the last system reset.
1: A PMU Wakeup event caused the last system reset.
10
RTC0RF
RTC0 Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: An RTC0 event did not cause the last system reset.
1: An RTC0 event caused the last system reset.
9
USB0RF
USB0 Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A USB0 Reset event did not cause the last system reset.
1: A USB0 Reset event caused the last system reset.
8
CMP1RF
Comparator 1 Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Comparator 1 event did not cause the last system reset.
1: A Comparator 1 event caused the last system reset.
7
CMP0RF
Comparator 0 Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Comparator 0 event did not cause the last system reset.
1: A Comparator 0 event caused the last system reset.
Rev. 1.0
61
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Table 6.2. RSTSRC0_RESETFLAG Register Bit Descriptions
Bit
Name
6
SWRF
Function
Software Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Software Reset event did not cause the last system reset.
1: A Software Reset event caused the last system reset.
5
WDTRF
Watchdog Timer Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Watchdog Timer event did not cause the last system reset.
1: A Watchdog Timer event caused the last system reset.
4
MCDRF
Missing Clock Detector Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Missing Clock Detector event did not cause the last system reset.
1: A Missing Clock Detector event caused the last system reset.
3
CORERF
Core Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A Core Reset event did not cause the last system reset.
1: A Core Reset event caused the last system reset.
2
VMONRF
Voltage Supply Monitor VDD Reset Flag.
After checking PORRF, firmware should then check VMONRF for the last reset
source, as all other flags are indeterminate if VMONRF is set. This flag is an indeterminate value when PORRF is set.
0: A Voltage Supply Monitor VDD Reset event did not cause the last system reset.
1: A Voltage Supply Monitor VDD Reset event caused the last system reset.
1
PORRF
Power-On Reset Flag.
This flag should be checked first by firmware as all other flags are indeterminate if
PORRF is set. This flag is an indeterminate value when VMONRF is set. Firmware
can check the PORF bit in the PMU STATUS register to determine if the last reset
was caused by a power-on reset.
0: A Power-On Reset event did not cause the last system reset.
1: A Power-On Reset event caused the last system reset.
0
PINRF
Pin Reset Flag.
This flag is an indeterminate value when VMONRF or PORRF is set.
0: A RESET pin event did not cause the last system reset.
1: A RESET pin event caused the last system reset.
62
Rev. 1.0
Register 6.3. RSTSRC0_CONFIG: Configuration Options
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PMSEL
Reset
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RSTSRC0_CONFIG = 0x4002_D080
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 6.3. RSTSRC0_CONFIG Register Bit Descriptions
Bit
Name
31:1
Reserved
0
PMSEL
Function
Must write reset value.
Power Mode Select.
This bit is used to enable the reset circuitry to wake the device from power mode 9
(PM9). It should be set to 1 before entering PM9. This bit should be cleared to 0 for
all other low power modes.
Rev. 1.0
63
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
6.3. RSTSRC0 Register Memory Map
Table 6.4. RSTSRC0 Memory Map
RSTSRC0_CONFIG RSTSRC0_RESETFLAG RSTSRC0_RESETEN Register Name
ALL Address
0x4002_D070
0x4002_D080
0x4002_D060
Access Methods
ALL
ALL | SET | CLR
ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Reserved
Reserved
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
WAKERF
WAKEREN
Bit 11
RTC0RF
RTC0REN
Bit 10
USB0RF
USB0REN
Bit 9
CMP1RF
CMP1REN
Bit 8
CMP0RF
CMP0REN
Bit 7
SWRF
SWREN
Bit 6
WDTRF
WDTREN
Bit 5
MCDRF
MCDREN
Bit 4
Reserved
CORERF
Bit 3
VMONREN
VMONRF
Bit 2
PORRF
Bit 1
Reserved
PMSEL
PINRF
Bit 0
Reset Sources (RSTSRC0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
64
Rev. 1.0
7. Register Security (LOCK0)
This section describes the Register Security (LOCK) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
Note that features related to the USB peripheral are only available on the SiM3U1xx device family.
7.1. Security Features
The Security module includes the following features:
Centralized
global key protection implementation with mask bits for each peripheral group.
Peripheral Lock and Key
USART0/1,
UART0/1
SPI0/1/2
I2C0/1
PERIPHLOCK0
EPCA0, PCA0/1
KEY
PERIPHLOCK1
TIMER0/1
USB0
SARADC0/1
Figure 7.1. Security Block Diagram
The peripherals on the SiM3U1xx/SiM3C1xx devices have a register lock and key mechanism that prevents any
undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of
peripherals. A key sequence must be written in order to the KEY register to modify any of the bits in
PERIPHLOCK0 or PERIPOHLOCK1. Any subsequent write to KEY will then inhibit any accesses of the
PERIPHLOCK registers until they are unlocked again through KEY. Reading the KEY register indicates the current
status of the PERIPHLOCK registers lock state.
If a peripheral’s registers are locked, all writes will be ignored. The registers can always be read, regardless of the
peripheral’s lock state.
Rev. 1.0
65
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
7.2. LOCK0 Registers
This section contains the detailed register descriptions for LOCK0 registers.
Register 7.1. LOCK0_KEY: Security Key
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
Reserved
KEY
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LOCK0_KEY = 0x4004_9000
Table 7.1. LOCK0_KEY Register Bit Descriptions
Bit
Name
31:8
Reserved
7:0
KEY
Function
Must write reset value.
Peripheral Lock Mask Key.
This field prevents accidental writes to the PERIPHLOCK0 and PERIPHLOCK1 registers. Writing 0xA5 and 0xF1 will unlock the PERIPHLOCK registers. Any value
written to KEY while the PERIPHLOCK registers are unlocked will lock the register.
Reading this register returns the current lock state (0 = Registers locked and no
keys written, 1 = Registers locked and first key written, 2 = Registers unlocked)
66
Rev. 1.0
Register 7.2. LOCK0_PERIPHLOCK0: Peripheral Lock Control 0
19
18
17
16
Name
Reserved
IDACL
20
DMACTRLL
21
DMAXBARL
22
LPTL
23
VREFL
24
I2SL
25
PLLL
26
EXTOSCL
27
VREGL
28
LPOSCL
29
EVREGL
30
Reserved
31
IVCL
Bit
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
USARTL
0
SPIL
0
I2CL
0
PCAL
0
TIMERL
0
USBL
0
SARADCL
0
SSGL
0
CMPL
0
CSL
0
EMIFL
0
AESL
0
CRCL
0
RTCL
0
CLKRSTL
0
VMONL
Reset
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LOCK0_PERIPHLOCK0 = 0x4004_9020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 7.2. LOCK0_PERIPHLOCK0 Register Bit Descriptions
Bit
Name
31:29
Reserved
28
IVCL
Function
Must write reset value.
IVC Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the IVC0 Module registers.
1: Lock the IVC0 Module registers (bits can still be read).
27
Reserved
Must write reset value.
26
EVREGL
External Regulator Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the External Regulator (EXTVREG0) Module registers.
1: Lock the External Regulator (EXTVREG0) Module registers (bits can still be
read).
25
LPOSCL
Low Power Oscillator Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Low Power Oscillator (LPOSC0) Module registers.
1: Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read).
Rev. 1.0
67
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Table 7.2. LOCK0_PERIPHLOCK0 Register Bit Descriptions
Bit
Name
24
VREGL
Function
Voltage Regulator Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Voltage Regulator (VREG0) Module registers.
1: Lock the Voltage Regulator (VREG0) Module registers (bits can still be read).
23
EXTOSCL
External Oscillator Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the External Oscillator (EXTOSC0) Module registers.
1: Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read).
22
PLLL
PLL Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the PLL0 Module registers.
1: Lock the PLL0 Module registers (bits can still be read).
21
I2SL
I2S Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the I2S0 Module registers.
1: Lock the I2S0 Module registers (bits can still be read).
20
VREFL
Voltage Reference Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Voltage Reference (VREF0) Module registers.
1: Lock the Voltage Reference (VREF0) Module registers (bits can still be read).
19
LPTL
Low Power Timer Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Low Power Timer (LPTIMER0) Module registers.
1: Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read).
18
DMAXBARL
DMA Crossbar Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the DMA Crossbar (DMAXBAR0) Module registers.
1: Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read).
17
DMACTRLL
DMA Controller Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the DMA Controller (DMACTRL0) Module registers.
1: Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read).
16
IDACL
IDAC Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the IDAC0 and IDAC1 Module registers.
1: Lock the IDAC0 and IDAC1 Module registers (bits can still be read).
15
VMONL
Voltage Supply Monitor Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Voltage Supply Monitor (VMON0) Module registers.
1: Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be
read).
68
Rev. 1.0
Table 7.2. LOCK0_PERIPHLOCK0 Register Bit Descriptions
Bit
Name
14
CLKRSTL
Function
Clock Control and Reset Sources Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers.
1: Lock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers (bits can still be read).
13
RTCL
RTC Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the RTC0 Module registers.
1: Lock the RTC0 Module registers (bits can still be read).
12
CRCL
CRC Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the CRC0 Module registers.
1: Lock the CRC0 Module registers (bits can still be read).
11
AESL
AES Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the AES0 Module registers.
1: Lock the AES0 Module registers (bits can still be read).
10
EMIFL
EMIF Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the External Memory Interface (EMIF0) Module registers.
1: Lock the External Memory Interface (EMIF0) Module registers (bits can still be
read).
9
CSL
Capacitive Sensing Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Capacitive Sensing (CAPSENSE0) Module registers.
1: Lock the Capacitive Sensing (CAPSENSE0) Module registers (bits can still be
read).
8
CMPL
Comparator Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the Comparator 0 and Comparator 1 Module registers.
1: Lock the Comparator 0 and Comparator 1 Module registers (bits can still be
read).
7
SSGL
SSG Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the SSG0 Module registers.
1: Lock the SSG0 Module registers (bits can still be read).
6
SARADCL
SARADC Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the SARADC0 and SARADC1 Module registers.
1: Lock the SARADC0 and SARADC1 Module registers (bits can still be read).
Rev. 1.0
69
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Table 7.2. LOCK0_PERIPHLOCK0 Register Bit Descriptions
Bit
Name
5
USBL
Function
USB Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the USB0 Module registers.
1: Lock the USB0 Module registers (bits can still be read).
4
TIMERL
Timer Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the TIMER0 and TIMER1 Module registers.
1: Lock the TIMER0 and TIMER1 Module registers (bits can still be read).
3
PCAL
PCA Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the EPCA0, PCA0, and PCA1 Module registers.
1: Lock the EPCA0, PCA0, and PCA1 Module registers (bits can still be read).
2
I2CL
I2C Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the I2C0 and I2C1 Module registers.
1: Lock the I2C0 and I2C1 Module registers (bits can still be read).
1
SPIL
SPI Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the SPI0, SPI1, and SPI2 Module registers.
1: Lock the SPI0, SPI1, and SPI2 Module registers (bits can still be read).
0
USARTL
USART/UART Module Lock Enable.
This bit cannot be written until the PERIPHLOCK0 register is unlocked using KEY.
0: Unlock the USART0, USART1, UART0, and UART1 Module registers.
1: Lock the USART0, USART1, UART0, and UART1 Module registers (bits can still
be read).
70
Rev. 1.0
Register 7.3. LOCK0_PERIPHLOCK1: Peripheral Lock Control 1
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PMUL
Reset
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LOCK0_PERIPHLOCK1 = 0x4004_9040
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 7.3. LOCK0_PERIPHLOCK1 Register Bit Descriptions
Bit
Name
31:1
Reserved
0
PMUL
Function
Must write reset value.
PMU Module Lock Enable.
This bit cannot be written until the PERIPHLOCK1 register is unlocked using KEY.
0: Unlock the PMU Module registers.
1: Lock the PMU Module registers (bits can still be read).
Rev. 1.0
71
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
7.3. LOCK0 Register Memory Map
Table 7.4. LOCK0 Memory Map
LOCK0_PERIPHLOCK1 LOCK0_PERIPHLOCK0 LOCK0_KEY Register Name
0x4004_9020
0x4004_9040
0x4004_9000 ALL Address
ALL | SET | CLR
Access Methods
ALL | SET | CLR
ALL
Bit 31
Reserved
Bit 30
Bit 29
IVCL
Bit 28
Reserved
Bit 27
EVREGL
Bit 26
LPOSCL
Bit 25
VREGL
Bit 24
EXTOSCL
Bit 23
PLLL
Bit 22
I2SL
Bit 21
VREFL
Bit 20
Reserved
LPTL
Bit 19
DMAXBARL
Bit 18
DMACTRLL
Bit 17
Reserved
IDACL
Bit 16
VMONL
Bit 15
CLKRSTL
Bit 14
RTCL
Bit 13
CRCL
Bit 12
AESL
Bit 11
EMIFL
Bit 10
CSL
Bit 9
CMPL
Bit 8
SSGL
Bit 7
SARADCL
Bit 6
USBL
Bit 5
TIMERL
Bit 4
KEY
PCAL
Bit 3
I2CL
Bit 2
SPIL
Bit 1
PMUL
USARTL
Bit 0
Register Security (LOCK0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
72
Rev. 1.0
8. Port I/O Configuration
This section describes the Port I/O Crossbars and general Port Bank configuration and is applicable to all products
in the following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
8.1. Port Bank Description
The features of the SiM3U1xx/SiM3C1xx port banks are shown in Table 8.1.
Table 8.1. Port Bank Features
Port Bank
Type
Crossbar 0
Crossbar 1
Pulse
Generator
Port Mapped
Level Shifter
PB0
Standard
(PBSTD)

PB1
Standard
(PBSTD)

PB2
Standard
(PBSTD)


(PB2.0-5 only)
PB3
Standard
(PBSTD)

PB4
High Drive
(PBHD)
5 V Tolerant


Note: I/O pins in Port Banks 0, 1, and 2 operate between 0 V and VIO. Port Bank 3 I/O pins can operate at voltages up to VIO +
2 V when configured as digital inputs (or as open-drain digital outputs with an external pull-up resistor), which allows
them to interface to 5 V signals when VIO = 3.3 V. Port Bank 4 I/O pins operate between 0 V and VIOHD, which allows
them to function as digital inputs or as open-drain or push-pull digital outputs up to the maximum value for VIOHD.
Rev. 1.0
73
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.2. Crossbars
8.2.1. Crossbar Features
There are two port I/O crossbars included on the SiM3U1xx/SiM3C1xx, with the following features:
Flexible
assignment of many digital peripherals to port pins.
Pin skip capabilities to reserve specific I/O for other purposes (analog signals, GPIO, layout
considerations)
The port I/O crossbars on the SiM3U1xx/SiM3C1xx are used to route many of the digital peripherals to the devices
I/O pins. They allow the user to select the specific mix of peripherals that are needed for the application, and route
them out of the device, leaving the unused pins available for general-purpose I/O. Crossbar 0 controls peripherals
to PB0 and PB1, while Crossbar 1 controls peripherals to PB2 and PB3.
Table 8.2. Crossbar Peripheral Availability
Peripheral Name
Functional
Group
Available on Crossbar 0
(PB0 and PB1)
Available on Crossbar 1
(PB2 and PB3)

AHB Clock / 16
Synchronous
Output

Asynchronous
Output

Synchronous
Output

Asynchronous
Output


Comparator 0

Comparator 1
EPCA0

I2C0



I2C1
Transmitter


I2S0

Receiver

LPTIMER0
PB0

High Drive Kill
PCA0

PCA1


RTC0
74
Rev. 1.0
Table 8.2. Crossbar Peripheral Availability (Continued)
Peripheral Name
Functional
Group
Available on Crossbar 0
(PB0 and PB1)
Available on Crossbar 1
(PB2 and PB3)
Clock/Data

SPI0
Slave Select
Clock/Data
SPI1




Slave Select
Clock/Data
SPI2
Slave Select

SSG0
Timer 0
Timer 1
Count

External
Output

Count

External
Output

Data
UART0




Flow Control
Data
UART1
Flow Control
Data
USART0
Flow Control

Clock Out
Data
USART1
Flow Control


Clock Out
Rev. 1.0
75
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.2.2. Crossbar Configuration
The peripherals which are routed through each crossbar have a specific priority order in which they are assigned to
pins and a specific range of pins where they can be routed. The crossbar assigns peripherals in priority order,
starting with the highest-priority peripherals and the lowest-order port pins available to the peripherals. When a
peripheral is enabled, all of the pins associated with that peripheral are routed in sequence. Some peripherals are
split into multiple functional groups, to route only the necessary pins. Additionally, pin skip registers can be used to
prevent the crossbar from assigning peripherals to those pins.
When configuring the crossbar, all settings should be made to the crossbar and Port Bank registers before
enabling the crossbar. This ensures that peripherals will not shift around while each one is being enabled and Port
I/O pins will remain stable. The settings in PBOUTMD, PBMDSEL, or PBSKIPEN will not take effect until the
crossbars are enabled.
If any pins are used for special functions not associated with the crossbars, these pins should be skipped using the
corresponding Port Bank PBSKIPEN register. This applies to External Interrupts, SARADC0/1 inputs, Capacitive
Sensing inputs, Comparator inputs, IDAC0/1 outputs, PB2 pins used with the pulse generator, and other analog
and non-crossbar signals. The only EMIF pins that must be skipped by the crossbar are CS0 and CS1, but the
EMIF will take precedence over the crossbar function during any read or write operation.
Registers XBAR0H, XBAR0L, and XBAR1 are used to enable peripherals on the different crossbars. Some
peripherals use multiple signals that are all enabled when the corresponding bit is set to 1. For example, enabling
I2C0 on the crossbar enables both data and clock signals (SDA and SCL). Several peripherals have individual
groups of pins that can be enabled or disabled as well. In the crossbar priority tables (Table 8.3 and Table 8.4),
such pins are listed with the same numerical priority and a letter (A, B, or C) indicating the priority of the functional
group. In all cases, the primary functional group (A) must be enabled on the crossbar for the other groups (B or C)
to be routed out. For example, on crossbar 0, the USART0 Data group (priority 1A) must be enabled in order to use
either the USART0 Flow Control group (priority 1B) or the Clock Output group (priority 1C).
When a peripheral is selected in more than one place (crossbars or high-drive I/O), the output pins will map to all
places where that peripheral is enabled. For input pins, only one of the selections will be valid. Priority is given first
to the high-drive I/O, then to crossbar 1, and finally to crossbar 0.
76
Rev. 1.0
8.2.2.1. Crossbar 0
Crossbar 0
Highest
Priority
RX/TX
USART0
Flow Control
Clock
SCK/MISO/MOSI
PB0.0
SPI0
NSS
16
RX/TX
USART1
Port
I/O
Cells
Digital
Crossbar 0
Flow Control
PB0.15
Clock
PB1.0
EPCA0
“N” Channels
PCA0
“N” Channels
PCA1
“N” Channels
EPCA0
ECI
PCA0
ECI
PCA1
ECI
I2S0
TX
XBAR0L
I2C0
SDA/SCL
PBSKIP
16
Port
I/O
Cells
PB1.15
Not all Port I/O pins are
available on all packages.
Priority
Decoder
XBAR0H
CMP0S
CMP0
CMP0A
CMP1S
Port Match
CMP1A
PM
CMP1
PMMSK
T0CT
TIMER0
T0EX
T1CT
TIMER1
T1EX
RX/TX
UART0
Flow Control
UART1
RX/TX
SCK/MISO/MOSI
SPI1
NSS
SCK/MISO/MOSI
SPI2
NSS
Lowest
Priority
AHB
Clock
Output (
16)
Figure 8.1. Crossbar 0 Block Diagram
Rev. 1.0
77
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.3. Crossbar 0 Peripherals and Priority
Peripheral Name
USART0
Functional
Group
Priority
Enable Bits
Data
1-A
USART0EN
USART0_TX
USART0_RX
Flow Control
1-B
USART0FCEN
USART0_RTS
USART0_CTS
Clock Out
1-C
USART0CEN
USART0_UCLK
Clock/Data
2-A
SPI0EN
SPI0_SCK
SPI0_MISO
SPI0_MOSI
SPI0
USART1
Signal Names
(in order)
First
Available
Port Pin
Last
Available
Port Pin
PB0.0
PB1.15
PB0.0
PB1.15
PB0.0
PB1.15
Slave Select
2-B
SPI0NSSEN
SPI0_NSS
Data
3-A
USART1EN
USART1_TX
USART1_RX
Flow Control
3-B
USART1FCEN
USART1_RTS
USART1_CTS
Clock Out
3-C
USART1CEN
USART1_UCLK
PB0.0
PB1.15
EPCA0
4
EPCA0EN[2:0]
EPCA0_STD_CEX0
EPCA0_STD_CEX1
EPCA0_STD_CEX2
EPCA0_STD_CEX3
EPCA0_STD_CEX4
EPCA0_STD_CEX5
PCA0
5
PCA0EN[1:0]
PCA0_CEX0
PCA0_CEX1
PB0.0
PB1.15
PCA1
6
PCA1EN[1:0]
PCA1_CEX0
PCA1_CEX1
PB0.0
PB1.15
EECI0
7
EECI0EN
EPCA0_ECI
PB0.0
PB1.15
ECI0
8
ECI0EN
PCA0_ECI
PB0.0
PB1.15
ECI1
9
ECI1EN
PCA1_ECI
PB0.0
PB1.15
I2S0 Transmitter
10
I2S0TXEN
I2S0_TX_WS
I2S0_TX_SCK
I2S0_TX_SD
PB0.0
PB1.15
I2C0
11
I2C0EN
I2C0_SDA
I2C0_SCL
PB0.0
PB1.15
78
Rev. 1.0
Table 8.3. Crossbar 0 Peripherals and Priority (Continued)
Peripheral Name
Functional
Group
Synchronous
Output
Priority
Enable Bits
Signal Names
(in order)
12
CMP0SEN
CMP0_S
Comparator 0
Asynchronous
Output
13
CMP0AEN
CMP0_A
Synchronous
Output
14
CMP1SEN
CMP1_S
Comparator 1
Timer 0
Timer 1
PB0.0
PB1.15
PB0.0
PB1.15
15
CMP1AEN
CMP1_A
Count
16
TMR0CTEN
TIMER0_CT
PB0.0
PB1.15
Input /
Output
17
TMR0EXEN
TIMER0_EX
PB0.0
PB1.15
Count
18
TMR1CTEN
TIMER1_CT
PB0.0
PB1.15
Input /
Output
19
TMR1EXEN
TIMER1_EX
PB0.0
PB1.15
Data
20-A
UART0EN
UART0_TX
UART0_RX
PB0.0
PB1.15
PB0.0
PB1.15
PB0.0
PB1.15
PB0.0
PB1.15
PB0.0
PB1.15
Flow Control
20-B
UART0FCEN
UART0_RTS
UART0_CTS
Data
21-A
UART1EN
UART1_TX
UART1_RX
Clock/Data
22-A
SPI1EN
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1
Slave Select
22-B
SPI1NSSEN
SPI1_NSS
Clock/Data
23-A
SPI2EN
SPI2_SCK
SPI2_MISO
SPI2_MOSI
SPI2
Slave Select
AHB Clock / 16
Last
Available
Port Pin
Asynchronous
Output
UART0
UART1
First
Available
Port Pin
23-B
SPI2NSSEN
SPI2_NSS
24
AHBEN
AHB_OUT
Rev. 1.0
79
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.2.2.2. Crossbar 1
Crossbar 1
Highest
Priority
SSG0
“N” Channels
CMP0
CMP0S
PB2.0
15
CMP1
Port
I/O
Cells
CMP1S
Digital
Crossbar 1
SCK/MISO/MOSI
PB2.14
SPI1
NSS
PB3.0
RTC0
Output
12
Port
I/O
Cells
SCK/MISO/MOSI
SPI2
PB3.11
NSS
Not all Port I/O pins are
available on all packages.
RX/TX
USART1
Flow Control
Priority
Decoder
Clock
RX/TX
XBR1
UART0
Flow Control
I2S0
TX
I2C0
SDA/SCL
UART1
RX/TX
I2S0
RX
PBSKIP
Port Match
PM
PMMSK
Input
LPTIMER0
Output
Lowest
Priority
I2C1
SDA/SCL
PB
High Drive Kill
Figure 8.2. Crossbar 1 Block Diagram
80
Rev. 1.0
Table 8.4. Crossbar 1 Peripherals and Priority
Peripheral Name
Functional
Group
SSG0
Priority
Enable Bits
Signal Names
(in order)
First
Available
Port Pin
Last
Available
Port Pin
PB2.0
PB3.11
PB2.0
PB3.11
PB2.0
PB3.11
PB2.2
PB3.11
1
SSG0EN[1:0]
SSG0_EX0
SSG0_EX1
SSG0_EX2
SSG0_EX3
Comparator 0
Synchronous
Output
2
CMP0SEN
CMP0_S
Comparator 1
Synchronous
Output
3
CMP1SEN
CMP1_S
SPI1EN
SPI1_SCK
SPI1_MISO
SPI1_MOSI
Clock/Data
4-A
SPI1
Slave Select
RTC0
Clock / Data
4-B
SPI1NSSEN
SPI1_NSS
5
RTC0EN
RTC0_OUT
PB2.5
PB3.11
6-A
SPI2EN
SPI2_SCK
SPI2_MISO
SPI2_MOSI
PB2.6
PB3.11
PB2.6
PB3.11
PB2.11
PB3.11
PB2.11
PB3.11
SPI2
USART1
Slave Select
6-B
SPI2NSSEN
SPI2_NSS
Data
7-A
USART1EN
USART1_TX
USART1_RX
Flow Control
7-B
USART1FCEN
USART1_RTS
USART1_CTS
Clock Out
7-C
USART1CEN
USART1_UCLK
Data
8-A
UART0EN
UART0_TX
UART0_RX
UART0FCEN
UART0_RTS
UART0_CTS
I2S0TXEN
I2S0_TX_WS
I2S0_TX_SCK
I2S0_TX_SD
UART0
Flow Control
I2S0 Transmitter
8-B
9
Rev. 1.0
81
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.4. Crossbar 1 Peripherals and Priority (Continued)
Peripheral Name
Functional
Group
Priority
Enable Bits
First
Available
Port Pin
Last
Available
Port Pin
10
I2C0EN
I2C0_SDA
I2C0_SCL
PB3.0
PB3.11
11
UART1EN
UART1_TX
UART1_RX
PB3.3
PB3.11
I2S0 Receiver
12
I2S0RXEN
I2S0_RX_WS
I2S0_RX_SCK
I2S0_RX_SD
PB3.0
PB3.11
LPTIMER0
13
LPT0OEN
LPTIMER0_OUT
PB3.1
PB3.11
I2C1
14
I2C1EN
I2C1_SDA
I2C1_SCL
PB3.2
PB3.11
15
KILLHDEN
PB_HDKill
PB3.3
PB3.11
I2C0
UART1
PB
82
Data
High Drive Kill
Rev. 1.0
Signal Names
(in order)
8.2.2.3. Crossbar Configuration Examples
Configuring Crossbar 0 to enable the SPI0 SCK, MISO, and MOSI pins, all EPCA0 channels, UART0 data, and
UART1 data would look like:
P0
Peripheral
Signal Name
USART0
USART0_TX
P1
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USART0_RX
USART0_RTS
USART0_CTS
USART0_UCLK
SPI0
SPI0_SCK
SPI0_MISO
SPI0_MOSI
SPI0_NSS
USART1
USART1_TX
USART1_RX
USART1_RTS
USART1_CTS
USART1_UCLK
EPCA0
EPCA0_CEX0
EPCA0_CEX1
EPCA0_CEX2
EPCA0_CEX3
EPCA0_CEX4
EPCA0_CEX5
PCA0
PCA0_CEX0
PCA0_CEX1
PCA1
PCA1_CEX0
PCA1_CEX1
EPCA0 ECI
EPCA0_ECI
PCA0 ECI
PCA0_ECI
PCA1 ECI
PCA1_ECI
I2S0 TX
I2S0_TX_WS
I2S0_TX_SCK
I2S0_TX_SD
I2C0
I2C0_SDA
I2C0_SCL
CMP0
CMP0S
CMP0A
CMP1
CMP1S
CMP1A
TIMER0
TIMER0_CT
TIMER0_EX
TIMER1
TIMER1_CT
TIMER1_EX
UART0
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
UART1
UART1_TX
UART1_RX
SPI1
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1_NSS
SPI2
SPI2_SCK
SPI2_MISO
SPI2_MOSI
SPI2_NSS
AHB Clock / 16
AHB_OUT
PBSKIPEN
0
Figure 8.3. Crossbar 0 Example Configuration
Rev. 1.0
83
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
In this particular example, PB0.0-PB0.7, PB0.13, and PB0.14 are skipped. As a result, the SPI0 pins are placed on
PB0.8-PB0.10, since this is the highest priority peripheral. The EPCA0 signals are next, and they’re placed on
PB0.11-PB1.2, since PB0.13 and PB0.14 are skipped. The UART0 RX and TX pins are then allocated to PB1.3
and PB1.4, since this is the next peripheral in the priority list. Finally, the UART1 pins are placed on PB1.5 and
PB1.6.
Similarly, configuring Crossbar 1 to enable all four channels of SSG0, USART1 data and flow control, UART0 data,
and the LPTIMER0 output would look like:
P2
Peripheral
Signal Name
SSG0
SSG0_EX0
P3
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
0
1
2
3
4
5
6
7
8
9
10 11
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSG0_EX1
SSG0_EX2
SSG0_EX3
CMP0
CMP0S
CMP1
CMP1S
SPI1
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1_NSS
RTC0
SPI2
RTC0_OUT
SPI2_SCK
SPI2_MISO
SPI2_MOSI
SPI2_NSS
USART1
USART1_TX
USART1_RX
USART1_RTS
USART1_CTS
USART1_UCLK
UART0
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
I2S0 TX
I2S0_TX_WS
I2S0_TX_SCK
I2S0_TX_SD
I2C0
I2C0_SDA
UART1
UART1_TX
I2S0 RX
I2S0_RX_WS
I2C0_SCL
UART1_RX
I2S0_RX_SCK
I2S0_RX_SD
LPTIMER0 Output
LPTIMER0_OUT
I2C1
I2C1_SDA
PB
PB_HDKill
I2C1_SCL
PBSKIPEN
0
0
0
0
Figure 8.4. Crossbar 1 Example Configuration
Because the SSG0 peripheral has the highest priority on Crossbar 1, this peripheral is allocated first. The first pin
this peripheral can appear on is PB2.0, so the SSG0 channels appear on PB2.0-PB2.3.
The USART1 peripheral has the next highest priority. The first pin this peripheral can appear on is PB2.6, but both
PB2.6 and PB2.7 are skipped in this particular crossbar configuration. The USART1 data signals then appear on
PB2.8 and PB2.9, and the flow control signals appear on PB2.10 and PB2.11.
The next peripheral in the priority list is UART0. In this instance, only the data lines of UART0 are enabled, so the
flow control signals do not appear on the port pins. The first pin this peripheral can appear on is PB2.11, so this
peripheral is shifted to PB2.12 and PB2.13 because of the higher-priority USART1 peripheral already allocated to
PB2.11.
84
Rev. 1.0
The final peripheral enabled is the LPTIMER0 output. This peripheral has the lowest priority of those enabled, so it
is allocated last. The first pin this signal can appear on is PB3.1, so this pin is allocated to the LPTIMER0 output.
This leaves PB2.14 and PB3.0 unallocated.
8.3. Port Bank Standard (PBSTD) Features
The Port Bank Standard module includes the following features:
Push-pull
or open-drain output modes and analog or digital input modes.
for high or low output drive strength.
Port Match allows any pin or combination of pins to generate an interrupt.
Internal pull-up resistors are enabled or disabled on a port-by-port basis.
Pulse generator logic which can produce fast pulses on one or more output pins (PB2 only).
PB2.0-PB2.5 can also serve as inputs to the Port Mapped Level Shifters available on PB4.0-PB4.5.
Option
PBSTDn Module
Pin Latch
PBCFGn Module
Port Bank Match
and Enable
Mode Select
Crossbar(s)
Output Mode
Pulse Generator
Timer
Port Bank Pulse
Generator Enable
Drive Mode
Pull-Ups Enable
Security
(lock and key)
PBn.0
Pin
Control
PBn.1
Pin
Control
PBn.2
Pin
Control
PBn.3
Pin
Control
PBn.15
Port Bank Lock
Control
Crossbar Skip
External Interrupt
Control
Pin
Control
Pulse Generator
Phase 0 and 1
VIO
Figure 8.5. PBSTD Block Diagram
Rev. 1.0
85
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.4. Standard Modes of Operation
Each Port Bank pin can be configured by firmware for analog I/O or digital I/O using the PBMDSEL register. On
reset, all Port Bank cells default to a digital high impedance state with weak pull-ups enabled.
8.4.1. Port Bank Pins Configured for Analog I/O
Any pins used as a Comparator, SARADC, IVC, CAPSENSE, EXTOSC0, IDAC, or VREF input or output should be
configured for analog I/O (PBMDSEL.x = 0). When a pin is configured for analog I/O, its weak pullup and digital
receiver are disabled. In most cases, firmware should also disable the digital output drivers. Firmware will always
read back a value of 0 from the PBPIN register for port pins configured for analog I/O regardless of the actual
voltage on the pin.
Configuring pins as analog I/O saves power and isolates the port pin from digital interference. Port pins configured
as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result
in measurement errors.
8.4.2. Port Pins Configured For Digital I/O
Any pins used by digital peripherals (USART, SPI, I2C, etc.), external digital event capture functions, or as GPIO
should be configured as digital I/O (PBMDSEL.x = 1). For digital I/O pins, one of two output modes (push-pull or
open-drain) must be selected using the PBOUTMD register.
Push-pull outputs (PBOUTMD.x = 1) drive the port pad to the VIO or VSS supply rails based on the output logic
value of the port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the port pad
to VSS when the output logic value is 0 and become high impedance (both high and low drivers turned off) when
the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the VIO
supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is
driven to VSS to minimize power consumption and may be disabled on a port-by-port basis by clearing PBPUEN to
0. The user should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to
prevent extra supply current caused by intermediate values. From the PB register, port pins configured for digital I/
O always read back the logic state last written to the latch, regardless of the output logic value of the port pin. The
output logic value of the pins (high or low) can be read using the PBPIN register.
8.4.3. Increasing Port I/O Drive Strength
Port Bank output drivers support a high and low drive strength; the default is low drive strength. The drive strength
of a pin is configurable using the PBDRV register. See the electrical specifications chapter for the difference in
output drive strength between the two modes.
8.4.4. Interfacing Port I/O to 5 V Logic
Port Bank PB3 pins configured for digital, open-drain operation are capable of interfacing to digital logic operating
above the supply pin. To provide logic high “output” to external systems above the rail, a pullup resistor is required.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at
least 150 A to flow into the port pin when the pin voltage is between VIO + 0.4 V and VIO + 1.0 V. When the pin
voltage increases beyond this range, the current flowing into the port pin is minimal.
8.5. Assigning Standard Port Bank Pins to Analog and Digital Functions
Port Bank pins can be assigned to various analog, digital, and external interrupt functions. The port pins assigned
to analog functions should be configured for analog I/O and port pins assigned to digital or external interrupt
functions should be configured for digital I/O.
8.5.1. Assigning Port Bank Pins to Analog Functions
Port pins selected for analog functions should have their digital drivers disabled (PBOUTMD.x = 0 and PB.x = 1)
and their corresponding bit in PBSKIPEN set to 1. This reserves the pin for use by the analog function and does
not allow it to be claimed by the crossbars.
86
Rev. 1.0
8.5.2. Assigning Port Bank Pins to Digital Functions
Any Port Bank pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the crossbars for pin assignment; however, some digital functions bypass the crossbars.
Port pins used by these digital functions and any port pins selected for use as GPIO should have their
corresponding bit in PBSKIPEN set to 1.
8.5.3. Assigning Port Bank Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low power
mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require dedicated pins
and will function on both GPIO pins (PBSKIPEN.x = 1) and pins in use by the Crossbars (PBSKIPEN.x = 0).
External digital event capture functions cannot be used on pins configured for analog I/O.
8.6. Standard Port Match and Capacitive Sensing (CAPSENSE0) Activity Monitoring
When MATMD is 0 in the CONTROL1 register, Port Match functionality allows system events to be triggered by a
logic value change on PB0-PB3. A port match event occurs if the logic levels of any of the selected input pins
match the firmware controlled value in the PM register. This allows firmware to be notified if a certain change
occurs on PB0-PB3 input pins regardless of the crossbar settings.
The PMEN registers can be used to individually select which Port Bank pins should be compared against the PM
registers.
A port match event may be used to generate an interrupt. If multiple pins are used to generate a port match event,
the individual pins can be checked inside the Port Match ISR to determine the cause of the current interrupt. In this
case, the event that causes the interrupt must be present long enough to enter the ISR and check the current state
of the pins.
When MATMD is 1 or 2, the PM and PMEN registers are used for CAPSENSE activity monitoring. The PMEN
register sets which bits can cause retries from the Capacitive Sensing (CAPSENSE0) module. In this mode, the
PM register is read-only and indicates the current state of the pin (high or low). More information on activity
monitoring can be found in the SiM3xxxx reference manual.
8.7. Standard Port Bank Pulse Generator
PB2 on SiM3U1xx/SiM3C1xx devices has an additional Pulse Generator feature. This Pulse Generator provides
the capability to toggle the PB2 port from a single 32-bit word write with a preset 5-bit delay between the setting
and clearing of the port. This 5-bit delay is implemented as a timer in the PGTIMER field where the actual count
time is PGTIMER + 1. This timer is clocked from the APB clock, and the PGDONEF bit asserts when the timer
expires.
Writing to the PBPGPHASE register will update the PB2 value with the phase 0 (PBPGPH0) value, start the
counter, and clear the PGDONEF bit. When the timer expires, the PB2 register updates with the phase 1
(PBPGPH1) value, and PGDONEF is set. The PBPGEN register selects which pins are controlled by the pulse
generator.
For example:
1. Set PB2’s mask register PBPGEN to 0x000000FF.
2. Write the 5-bit pulse generator timer value, PGTIMER, to 0x0F for a 16 cycle delay.
3. Write the PBPGPHASE register with 0x000500FF to set PBPGPH0 and PBPGPH1 at the same time.
4. Poll for PGDONEF.
In this example, the Pulse Generator writes PB2[7:0] to 0xFF, waits 16 cycles, and then updates PB2[7:0] to 0x05.
PB2[14:8] are unaffected by this operation since the PBPGEN register only enables bits [7:0] for a pulse generation
update.
While PGDONEF is zero, the PB2 and PBPGPHASE bits that have been enabled for pulse generation with the
PBPGEN register cannot be updated with a register write. In the previous example, any writes to PB2 during the 16
cycles will take according to the restrictions imposed by the PBPGEN register. For example, if PB2[14:8] was
written to 0x5A, this write will take effect since PBPGEN[14:8] was set to 0x00. Conversely, if PB2[7:0] was written
during this period, it will not take effect since PBPGEN[7:0] was set to 0xFF.
The P2 bits can be locked even if they are used with the Pulse Generator.
Rev. 1.0
87
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.8. High Drive (PBHD) Features
The High Drive Port Bank module includes the following features:
Push-pull
or open-drain output modes and analog or digital input modes.
Option for high or low output drive strength.
Internal pull-up resistors are enabled or disabled for the port.
Programmable safe state: high, low, or high impedance.
Programmable drive strength and slew rates.
Programmable current limiting.
Powered from a separate supply (VIOHD, which can be up to 6 V) capable of delivering higher voltage and
current.
Internal VIOHD divider to provide other circuits with VIOHD/4.
Supports various functions, including GPIO, UART1 pins, EPCA0 pins, or Port Mapped Level Shifting.
PBHDn Module
PB_HDKill
Safe State
Pin Latch
N-Driver Enable
Mode Select
Pin
Control
PBn.0
Pin
Control
PBn.1
Pin
Control
PBn.2
Pin
Control
PBn.3
Pin
Control
PBn.5
P-Driver Enable
PBCFGn Module
Output Mode
Slew Rate
Security
(lock and key)
Current Limiting
Port Bank Lock
Control
Drive Mode
Pull-Ups Enable
Function Select
Divide
by 4
VIOHD
Figure 8.6. PBHD Block Diagram
88
Rev. 1.0
VIOHD/4
8.9. High Drive Modes of Operation
In addition to the analog, digital, and drive strength modes described in Section 8.4, the high drive pins have
individual N-channel (low) and P-channel (high) drivers that can be enabled. The different output modes are shown
in Table 8.5.
Table 8.5. High Drive Output Modes
Output Mode
PBPDEN.x
PBNDEN.x
Tristate
0
0
NMOS Open-Drain
0
1
PMOS Open-Drain
1
0
Push-Pull
1
1
The pins are in tristate output mode after a reset.
The high drive pins also have slew rate control on a port basis using the PBSLEW field.
8.9.1. Safe States
All PBHD pins have a "safe state" which overrides the output of the pin and can be triggered by firmware or
hardware. The safe state of the high drive pins can be specified in the PBSS register. Each pin can be low, high,
high impedance, or unchanged when entering safe state. Firmware can place the pins in the safe state by setting
the SSMDEN bit to 1. If the PB_HDKill signal is routed to pins using Crossbar 1, this input signal sets SSMDEN to
1 when asserted (active low). The PBSSSMD bit allows this PB_HDKill signal to take immediate effect or be
deglitched and require two APB clocks to be recognized.
Once set by firmware or the PB_HDKill signal, the SSMDEN bit can only be cleared by writing 0 from firmware or
when a device reset occurs. Entering the safe state does not modify the settings in the PB4 registers.
8.9.2. Current Limiting
All PBHD pins have current limiting circuitry built in. This can be useful to prevent short circuits from damaging
external components or causing undesired system operation. Separate current limits can be set for the high and
low-side drivers to limit the source and sink current respectively, to one of 16 different levels. These limits are
configured using the PILIMIT and NILIMIT fields in the PBILIMIT register, and apply to all of the PBHD pins. Each
pin can then have current limiting enabled or disabled individually, using the PBILEN field.
Rev. 1.0
89
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.10. High Drive Configuration Procedure
The High Drive Port Bank pins are locked by default. Before configuring the High Drive Port Bank pins, all High
Drive Port Bank pins must be unlocked using the following procedure:
1. Unlock the High Drive Port Bank pins by writing 0xA5 followed by 0xF1 to the PBCFG.KEY bitfield
2. Unlock all bits in the High Drive Port Bank by writing 0x00 to PBHD4.PBLOCK bitfield. Unless all bits in the
High Drive Port Bank are unlocked, the bank-wide configuration bits (e.g., PBBIASEN, PBDRVEN,
PBLVMD) cannot be modified.
After unlocking the High Drive Port Bank pins, firmware should use the following procedure to configure the high
drive pins:
1. Set the safe state for each pin using PBSS.
2. Set PBBIASEN in PBDRV to 1 to enable current biasing.
3. In a separate write to PBDRV, set the PBLVMD bit according to the supply level. Low power mode
(PBLVMD = 1) must be used if VIOHD is less than 2.7 V and is recommended if VIOHD is less than 3.0 V.
PBLVMD must be cleared to 0 if VIOHD is greater than 3.6 V.
4. In a third write to PBDRV, set PBDRVEN to 1 to release the pins.
5. In another separate write, configure the appropriate drive strength for each pin and the global port controls
for pull-ups (PBPUEN), slew rate (PBSLEW), and VIOHD tracking (PBVTRKEN) in the PBDRV register.
6. Enable current limiting per pin as needed by setting (PBILEN.x), setting the drive strength to low drive
(PBDRV = 0), and setting the N-channel (NILIMIT) and P-channel (PILIMIT) modes. These N-channel and
P-channel modes are global to all pins that have current limiting enabled.
7. Configure the remaining control registers PBDEN, PBMDSEL, and PBFSEL.
8.11. High Drive Function Selection
The port crossbars do not route to the high drive port bank pins, but certain hardware peripherals can be mapped
directly to these pins. The pin mode select (PBMDSEL), output driver enable (PBDEN), drive (PBDRV), current
limiting (PBILIMIT), and safe state (PBSS) settings can be used to modify the pin behavior in all of these modes.
The auxiliary functions are as follows:
Table 8.6. High Drive Function Selections
Pin
(PB4.x)
90
PBxSEL Value in PBFSEL
0
1
2
PB4.0
GPIO
PB2.0 PMLS
EPCA0_HD_CEX0
PB4.1
GPIO
PB2.1 PMLS
EPCA0_HD_CEX1
PB4.2
GPIO
PB2.2 PMLS
EPCA0_HD_CEX2
UART1_TX
PB4.3
GPIO
PB2.3 PMLS
EPCA0_HD_CEX3
UART1_RX
PB4.4
GPIO
PB2.4 PMLS
EPCA0_HD_CEX4
UART1_RTS
PB4.5
GPIO
PB2.5 PMLS
EPCA0_HD_CEX5
UART1_CTS
Rev. 1.0
3
4
LPTIMER0_OUT
8.11.1. GPIO
In this mode, a high drive pin behaves as a standard GPIO using the VIOHD and VSSHD logic levels.
In digital mode, the pin will assume the state of the port latch value in the PB register. If the N-Channel drivers are
enabled, low values will be driven. If the P-Channel drivers are enabled for the pin, high values will be driven. The
current logic level of the pin can be read using the PBPIN register. The analog or digital mode of the pin can be
controlled using PBMDSEL. The drive modes and current limiting can be controlled using PBDRV and PBILIMIT.
The safe state of the pin is set using PBSS.
8.11.2. Port Mapped Level Shift (PMLS)
Each PB4 high drive pin can serve as a buffered or level-shifted version of the corresponding PB2 pins. In this
mode, the logic level seen on the PB2.x pin will be driven out on the corresponding PB4.x pin.
The primary purpose of the PMLS feature is to route an input on a PB2 pin as an output to the corresponding PB4
pin. It's also possible to use crossbar 1 to output a signal on a PB2 pin and use the PMLS feature to map it to a
PB4 pin. This crossbar mapping feature is only available with crossbar outputs.
8.11.3. EPCA
When set to an EPCA0 output, the high drive pin is controlled by the EPCA0 module. The EPCA0 channel that
controls the EPCA0_HD_CEXx output is set in the EPCA0 module with the HDOSEL field.
8.11.4. UART1
The high drive pins in UART1 mode serve as inputs or outputs for the UART1 module. The flow control signals
RTS and CTS must be also be enabled in the UART1 module if they are selected as PBHD functions.
8.11.5. Low Power Timer
When set to the Low Power Timer output, the pin will toggle as defined in the LPTIMER0 register settings.
8.11.6. VIOHD Divider
The PBVTRKEN bit in the PBDRV register enables a divide-by-4 circuit on the VIOHD power supply. The VIOHD/4
signal can be used as an input to the SARDADCs or Comparator blocks for easy measurement of the VIOHD
supply.
Rev. 1.0
91
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.12. Port Bank Security
PB2, PB3, PB4, and the control registers have one shared lock which is unlocked by a series of writes to the KEY
register. The Port Bank lock mechanism is split into two types: control registers (controlled by the LOCK bit) and
Port Bank data registers (controlled by the PBLOCK register for that port bank). Both the control registers and Port
Bank data registers for PB2 and PB3 are unlocked after a reset. The Port Bank data registers for PB4 and the lock
state machine itself is in a locked state after a reset.
If any Port Bank pins or control registers are locked (LOCK or any bit in PBLOCK set to 1), the sequence of 0xA5
followed by 0xF1 must be written to the KEY register. Once unlocked, writing to a lockable register or writing an
invalid value to KEY will relock the registers. All of the registers can be read at any time, regardless of the lock
state. Additionally, writes to non-lockable registers (like CONTROL0) do not affect the state of the lock. The KEY
register can be read at any time to return the status of the lock.
8.12.1. Control Registers
Control and Configuration registers are locked if the LOCK bit is set and the lock is in a locked state. This lock
ensures the fields that control the peripheral output mapping cannot change inadvertently. Setting LOCK will lock
CONTROL1, XBAR0L, XBAR0H, XBAR1, and all PBSKIPEN registers.
8.12.2. Port Bank Data Registers
PB2, PB3, and PB4 have lock mask registers that allow individual pins to be locked. Each bit in the PBLOCK
register controls whether the respective pin fields in the other pin configuration registers (PBMDSEL, PBOUTMD,
etc.) are locked for write access. Common control fields that apply to the entire port bank, like weak pull-ups for
PB2 and PB3 and slew and weak pull-ups for PB4, are locked if any single lock mask bit is set for that bank.
The lock mask registers require the state machine to be unlocked for write access. After a reset, firmware must first
unlock the Port Bank lock by writing the correct sequence to KEY before writing to the PBLOCK registers.
8.13. Ports and Power Mode 9
When entering PM9, the High Drive pins must be put into a low power mode. To do this:
1. Clear PBBIASEN to 0.
2. Clear PBILEN to 0.
PBLVMD should remain set if VIOHD is less than 2.7 V and is also recommended to remain set if VIOHD is less
than 3.0 V. PBLVMD must be cleared to 0 if VIOHD will be greater than 3.6 V while the device is in Power Mode 9.
When the device enters PM9, the pins retain their state but are no longer powered. In addition, the settings are
removed from the port control registers. Firmware must reconfigure the port registers (including safe states) after
exiting PM9 prior to re-enabling the ports by writing a 0 to PINLPEN in the PMU.
92
Rev. 1.0
8.14. Debugging Interfaces
After a reset, SiM3U1xx/SiM3C1xx devices are configured with JTAG enabled to allow external JTAG modules to
connect. Firmware must disable this if not needed, freeing the JTAG pins for use with other functions. If the core is
configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer is enabled to come out of the
TDO pin and the TRST and TDI pins are available for other Crossbar or GPIO functions. The Serial Wire Viewer
(SWV) provides a single pin to send out TPIU messages.
Enabling the JTAG or ETM interfaces overrides all other Crossbar and GPIO functionality, so these pins should be
skipped in the PBSKIPEN registers, and all writes to these bits in PB will be ignored. ETM must also be enabled in
the core.
Table 8.7. Debug Interface Pin Information
Debug
Interface
JTAG
ETM
Serial Wire
Debug
Serial Wire
Viewer
Debug Signal
Name
Conditions
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
TRST
PB1.2
TCK
SWCLK/TCK
SWCLK/TCK
PB1.3
PB0.14
TDI
PB1.4
PB0.15
TMS
SWDIO/TMS
SWDIO/TMS
ETM0
PB1.5
ETM1
PB1.6
TDO
ETM2
JTAGEN = 1
ETMEN = 1
PB1.7
ETM3
PB1.8
TRACECLK
PB1.9
SWCLK
SWDIO
SWV
Clock sequence on
SWCLK
JTAGEN = 1, ARM
debugger in SW mode
Rev. 1.0
SWCLK/TCK
SWCLK
SWCLK
SWDIO/TMS
SWDIO
SWDIO
PB1.3
PB0.14
93
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.15. External Memory Interface (EMIF)
8.15.1. EMIF Features
The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD
controllers, to appear as part of the system memory map. The EMIF0 module includes the following features:
Provides
a memory mapped view of multiple external devices.
Support for byte, half-word and word accesses regardless of external device data-width.
Error indicator for certain invalid transfers.
Minimum external timing allows for 3 clocks per write or 4 clocks per read.
Output bus can be shared between non-muxed and muxed devices.
Available extended address output allows for up to 24-bit address with 8-bit parallel devices.
Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals.
Support for internally muxed devices with dynamic address shifting.
Fully programmable control signal waveforms.
The bits controlling the additional EMIF0 pins, including an extra chip select (CS1) and byte enable (BE0), and the
EMIF enable are located in the Port Bank CONTROL1 register. All other settings for the EMIF are configured with
the EMIF peripheral registers discussed in the SiM3xxxx reference manual.
When the additional EMIF bits are selected, the resulting number of pins in a muxed configuration is EMIFWIDTH
+ 8. The EMIFWIDTH field should not be used in non-muxed mode.
Table 8.8. EMIF Muxed Configuration Pin Information
EMIF Signal
Description
AD0m
Address/Data Bit 0
PB3.2
PB3.2
AD1m
Address/Data Bit 1
PB3.1
PB3.1
AD2m
Address/Data Bit 2
PB3.0
PB3.0
AD3m
Address/Data Bit 3
PB2.14
PB2.3
AD4m
Address/Data Bit 4
PB2.13
PB2.2
AD5m
Address/Data Bit 5
PB2.12
PB2.1
AD6m
Address/Data Bit 6
PB2.11
PB2.0
AD7m
Address/Data Bit 7
PB2.10
PB1.15
AD8m
Address/Data Bit 8
EMIFWIDTH = 1
PB2.9
PB1.14
AD9m
Address/Data Bit 9
EMIFWIDTH = 2
PB2.8
PB1.13
AD10m
Address/Data Bit 10
EMIFWIDTH = 3
PB2.7
PB1.12
AD11m
Address/Data Bit 11
EMIFWIDTH = 4
PB2.6
PB1.11
AD12m
Address/Data Bit 12
EMIFWIDTH = 5
PB2.5
PB1.10
AD13m
Address/Data Bit 13
EMIFWIDTH = 6
PB2.4
PB1.9
AD14m
Address/Data Bit 14
EMIFWIDTH = 7
PB2.3
PB1.8
AD15m
Address/Data Bit 15
EMIFWIDTH = 8
PB2.2
PB1.7
A16m
Address Bit 16
EMIFWIDTH = 9
PB2.1
A17m
Address Bit 17
EMIFWIDTH = 10
PB2.0
94
Conditions
Rev. 1.0
SiM3U1x7/C1x7 SiM3U1x6/C1x6
Pin Name
Pin Name
Table 8.8. EMIF Muxed Configuration Pin Information (Continued)
EMIF Signal
Description
Conditions
A18m
Address Bit 18
EMIFWIDTH = 11
PB1.15
A19m
Address Bit 19
EMIFWIDTH = 12
PB1.14
A20m
Address Bit 20
EMIFWIDTH = 13
PB1.13
A21m
Address Bit 21
EMIFWIDTH = 14
PB1.12
A22m
Address Bit 22
EMIFWIDTH = 15
PB1.11
A23m
Address Bit 23
EMIFWIDTH = 16
PB1.10
WR
Active-Low Write
PB3.3
PB3.3
OE
Active-Low Output Enable
PB3.4
PB3.4
ALEm
Address Latch Enable
PB3.5
PB3.5
CS0
Chip Select 0
PB3.6
PB3.6
BE1
Active-Low Byte Enable 1
PB3.7
PB3.7
CS1
Chip Select 1
EMIFCS1EN = 1
PB3.8
PB3.8
BE0
Active-Low Byte Enable 0
EMIFBE0BEN = 1
PB3.9
PB3.9
Rev. 1.0
SiM3U1x7/C1x7 SiM3U1x6/C1x6
Pin Name
Pin Name
95
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.9. EMIF Non-Muxed Configuration Pin Information
EMIF Signal
Description
Conditions
A0
Address Bit 0
EMIFWIDTH = 1
PB2.9
PB1.14
A1
Address Bit 1
EMIFWIDTH = 2
PB2.8
PB1.13
A2
Address Bit 2
EMIFWIDTH = 3
PB2.7
PB1.12
A3
Address Bit 3
EMIFWIDTH = 4
PB2.6
PB1.11
A4
Address Bit 4
EMIFWIDTH = 5
PB2.5
PB1.10
A5
Address Bit 5
EMIFWIDTH = 6
PB2.4
PB1.9
A6
Address Bit 6
EMIFWIDTH = 7
PB2.3
PB1.8
A7
Address Bit 7
EMIFWIDTH = 8
PB2.2
PB1.7
A8
Address Bit 8
EMIFWIDTH = 9
PB2.1
A9
Address Bit 9
EMIFWIDTH = 10
PB2.0
A10
Address Bit 10
EMIFWIDTH = 11
PB1.15
A11
Address Bit 11
EMIFWIDTH = 12
PB1.14
A12
Address Bit 12
EMIFWIDTH = 13
PB1.13
A13
Address Bit 13
EMIFWIDTH = 14
PB1.12
A14
Address Bit 14
EMIFWIDTH = 15
PB1.11
A15
Address Bit 15
EMIFWIDTH = 16
PB1.10
D0
Data Bit 0
PB3.2
PB3.2
D1
Data Bit 1
PB3.1
PB3.1
D2
Data Bit 2
PB3.0
PB3.0
D3
Data Bit 3
PB2.14
PB2.3
D4
Data Bit 4
PB2.13
PB2.2
D5
Data Bit 5
PB2.12
PB2.1
D6
Data Bit 6
PB2.11
PB2.0
D7
Data Bit 7
PB2.10
PB1.15
WR
Active-Low Write
PB3.3
PB3.3
OE
Active-Low Output Enable
PB3.4
PB3.4
unused by EMIF
PB3.5
PB3.5
CS0
Chip Select 0
PB3.6
PB3.6
BE1
Active-Low Byte Enable 1
PB3.7
PB3.7
CS1
Chip Select 1
EMIFCS1EN = 1
PB3.8
PB3.8
BE0
Active-Low Byte Enable 0
EMIFBE0BEN = 1
PB3.9
PB3.9
96
Rev. 1.0
SiM3U1x7/C1x7 SiM3U1x6/C1x6
Pin Name
Pin Name
The EMIF is not supported on SiM3U1x4 devices.
The EMIF pins should be skipped in the corresponding PBSKIPEN register and set to push-pull or open-drain
using the PBOUTMD registers, as appropriate. Any pins not used by the EMIF as a result of the EMIFWIDTH,
EMIFCS1EN, and EMIFBE0BEN bit settings can be used for crossbar or GPIO functions. When the EMIF is not
actively transferring data, the EMIF pin state is controlled by the PB registers, providing a mechanism to place the
pins at a stable or desired value when the EMIF is idle.
8.16. External Interrupts
8.16.1. External Interrupt Features
The External Interrupts (INT0/INT1) on the SiM3U1xx/SiM3C1xx devices have the following features:
Level
(high or low) or edge (rising or falling) detection.
Can select one of up to 16 inputs to monitor.
Separate from the crossbars so can be used in conjunction with other peripherals on the same pins.
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The
INT0POL (INT0 Polarity) and INT1POL (INT1 Polarity) bits in the CONTROL0 register select active high or active
low; the INT0MD and INT1MD bits in the same register select level or edge sensitive. The table below lists the
possible configurations.
Table 8.10. External Interrupt Configuration
INTnMD
INTnPOL
INTn Configuration
1
0
Active low, edge sensitive (falling)
1
1
Active high, edge sensitive (rising)
0
0
Active low, level sensitive (low level)
0
1
Active high, level sensitive (high level)
INT0 and INT1 are assigned to Port Bank pins as defined in the CONTROL0 register. These pin assignments are
independent of any crossbar assignments. The External Interrupts will monitor their assigned Port Bank pins
without disturbing the peripheral that was assigned to the pin via the crossbars. To assign a Port Bank pin only to
INT0 or INT1, configure the crossbar to skip the selected pins by setting the associated bit in PBSKIPEN register.
The pins available for use as external interrupt sources vary by package, and are defined in Table 8.11.
Table 8.11. External Interrupt Triggers
INT0 and INT1
Trigger
INT0 and INT1 Trigger
Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
INT0.0 / INT1.0
External Interrupt Trigger
PB2.0
PB2.0
PB3.0
INT0.1 / INT1.1
External Interrupt Trigger
PB2.1
PB2.1
PB3.1
INT0.2 / INT1.2
External Interrupt Trigger
PB2.2
PB2.2
PB3.2
INT0.3 / INT1.3
External Interrupt Trigger
PB2.3
PB2.3
PB3.3
INT0.4 / INT1.4
External Interrupt Trigger
PB2.4
PB3.3
Reserved
Rev. 1.0
97
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.11. External Interrupt Triggers
INT0 and INT1
Trigger
INT0 and INT1 Trigger
Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
INT0.5 / INT1.5
External Interrupt Trigger
PB2.5
PB3.4
Reserved
INT0.6 / INT1.6
External Interrupt Trigger
PB2.6
PB3.5
Reserved
INT0.7 / INT1.7
External Interrupt Trigger
PB2.7
PB3.6
Reserved
INT0.8 / INT1.8
External Interrupt Trigger
PB3.3
PB3.7
Reserved
INT0.9 / INT1.9
External Interrupt Trigger
PB3.4
PB3.8
Reserved
INT0.10 / INT1.10
External Interrupt Trigger
PB3.5
PB3.9
Reserved
INT0.11 / INT1.11
External Interrupt Trigger
PB3.6
Reserved
Reserved
INT0.12 / INT1.12
External Interrupt Trigger
PB3.7
Reserved
Reserved
INT0.13 / INT1.13
External Interrupt Trigger
PB3.8
Reserved
Reserved
INT0.14 / INT1.14
External Interrupt Trigger
PB3.9
Reserved
Reserved
INT0.15 / INT1.15
External Interrupt Trigger
PB3.10
Reserved
Reserved
If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is set
once per edge. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is
active as defined by the corresponding polarity bit (INT0POL or INT1POL); the flag remains cleared while the input
is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
98
Rev. 1.0
8.17. PBCFG0 Registers
This section contains the detailed register descriptions for PBCFG0 registers.
Bit
31
30
Name
PGDONEF
Reserved
PGTIMER
Reserved
Type
R
R
RW
R
Reset
1
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Name
INT1EN
INT1MD
INT1POL
INT1SEL
INT0EN
INT0MD
INT0POL
Register 8.1. PBCFG0_CONTROL0: Global Port Control 0
29
INT0SEL
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
28
0
27
0
26
0
25
24
0
0
23
22
0
21
0
0
20
0
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
Register ALL Access Address
PBCFG0_CONTROL0 = 0x4002_A000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.12. PBCFG0_CONTROL0 Register Bit Descriptions
Bit
Name
31
PGDONEF
Function
Pulse Generator Timer Done Flag.
This bit is cleared by hardware when firmware writes to the PBPGPHASE register.
This bit is set when the Pulse Generator timer expires. While PGDONEF is 0, the
PB and PBPGPHASE bits that have been enabled for pulse generation with the
PBPGMSK cannot be updated with a register write.
30:29
Reserved
Must write reset value.
28:24
PGTIMER
Pulse Generator Timer.
Count down timer value for supported toggle ports.
23:16
Reserved
15
INT1EN
Must write reset value.
External Interrupt 1 Enable.
0: Disable external interrupt 1.
1: Enable external interrupt 1.
14:13
INT1MD
External Interrupt 1 Mode.
00: Interrupt based on level sensitivity.
01: Interrupt based on edge sensitivity.
10-11: Reserved.
Rev. 1.0
99
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.12. PBCFG0_CONTROL0 Register Bit Descriptions
Bit
Name
12
INT1POL
Function
External Interrupt 1 Polarity.
0: A low value or falling edge on the selected pin will cause interrupt.
1: A high value or rising edge on the selected pin will cause interrupt.
11:8
INT1SEL
External Interrupt 1 Pin Selection.
Selects the external pin to use as external interrupt 1. (INT1SEL = 0 selects INT1.0).
7
INT0EN
External Interrupt 0 Enable.
0: Disable external interrupt 0.
1: Enable external interrupt 0.
6:5
INT0MD
External Interrupt 0 Mode.
00: Interrupt based on level sensitivity.
01: Interrupt based on edge sensitivity.
10-11: Reserved.
4
INT0POL
External Interrupt 0 Polarity.
0: A low value or falling edge on the selected pin will cause interrupt.
1: A high value or rising edge on the selected pin will cause interrupt.
3:0
INT0SEL
External Interrupt 0 Pin Selection.
Selects the external pin to use as external interrupt 0 (INT0SEL = 0 selects INT0.0).
100
Rev. 1.0
Register 8.2. PBCFG0_CONTROL1: Global Port Control 1
28
27
Name
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
23
22
RW
RW
RW
R
0
0
0
0
0
0
0
17
16
RW
RW
0
18
R
Type
0
19
RW
EMIFWIDTH
0
20
MATMD
Name
Reset
21
Reserved
EMIFBE0BEN
R
24
EMIFCS1EN
RW
25
EMIFEN
Reserved
26
Reserved
RW
0
0
0
0
JTAGEN
29
ETMEN
30
EVREGRMD
31
LOCK
Bit
RW
RW
0
1
Register ALL Access Address
PBCFG0_CONTROL1 = 0x4002_A010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.13. PBCFG0_CONTROL1 Register Bit Descriptions
Bit
Name
31
LOCK
Function
Port Bank Configuration Lock.
This bit controls the lock for the port bank configuration and control registers.
0: Port Bank Configuration and Control registers are unlocked.
1: The following registers are locked from write access: CONTROL1, XBAR0L,
XBAR0H, XBAR1, and all PBSKIP registers.
30:24
Reserved
23
EVREGRMD
Must write reset value.
External Regulator Reset Mode.
0: The pins used by the external regulator will default to digital inputs with weak pullup enabled on any reset.
1: The pins used by the external regulator will default to digital inputs with weak pullup enabled only on Power-On Reset. Their configured mode will be preserved
through all other resets.
22:18
Reserved
Must write reset value.
Rev. 1.0
101
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.13. PBCFG0_CONTROL1 Register Bit Descriptions
Bit
Name
17:16
MATMD
Function
Match Mode.
Determines how the port match registers are used.
00: Port Match registers used to provide interrupt / wake sources.
01: Port Match registers used to monitor output pin activity for Capacitive Sensing
measurements.
10: Port Match registers used to monitor input pin activity for Capacitive Sensing
measurements.
11: Reserved.
15:10
EMIFWIDTH
EMIF Width.
This field is the number of additional pins allocated to EMIF address. The number of
total address lines will be 8 + EMIFWIDTH.
9
EMIFEN
EMIF Enable.
0: Disable the EMIF pins.
1: EMIF is enabled and pinned out.
8
EMIFCS1EN
EMIF CS1 Pin Enable.
0: Disable the EMIF CS1 pin.
1: Enable the CS1 pin if EMIFEN is also set to 1.
7
EMIFBE0BEN
EMIF BE0 Pin Enable.
0: Disable the EMIF BE0 pin.
1: Enable the BE0 pin if EMIFEN is also set to 1.
6:2
Reserved
1
ETMEN
Must write reset value.
ETM Enable.
0: ETM not pinned out.
1: ETM is enabled and pinned out.
0
JTAGEN
JTAG Enable.
0: JTAG functionality is not pinned out.
1: JTAG functionality is pinned out.
102
Rev. 1.0
24
23
22
21
20
19
18
17
Name
TMR1EXEN
TMR1CTEN
TMR0EXEN
TMR0CTEN
CMP1AEN
CMP1SEN
CMP0AEN
CMP0SEN
I2C0EN
I2S0TXEN
ECI1EN
ECI0EN
EECI0EN
16
PCA1EN
Type
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PCA0EN
Reserved
EPCA0EN
USART0EN
25
USART0FCEN
26
USART0CEN
27
SPI0EN
28
SPI0NSSEN
29
USART1EN
30
USART1FCEN
31
USART1CEN
Bit
Reserved
Register 8.3. PBCFG0_XBAR0L: Crossbar 0 Control (Low)
Type
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Register ALL Access Address
PBCFG0_XBAR0L = 0x4002_A020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.14. PBCFG0_XBAR0L Register Bit Descriptions
Bit
Name
Function
31
Reserved
Must write reset value.
30
TMR1EXEN
TIMER1 T1EX Enable.
0: Disable TIMER1 EX on Crossbar 0.
1: Enable TIMER1 EX on Crossbar 0.
29
TMR1CTEN
TIMER1 T1CT Enable.
0: Disable TIMER1 CT on Crossbar 0.
1: Enable TIMER1 CT on Crossbar 0.
28
TMR0EXEN
TIMER0 T0EX Enable.
0: Disable TIMER0 EX on Crossbar 0.
1: Enable TIMER0 EX on Crossbar 0.
27
TMR0CTEN
TIMER0 T0CT Enable.
0: Disable TIMER0 CT on Crossbar 0.
1: Enable TIMER0 CT on Crossbar 0.
26
CMP1AEN
Comparator 1 Asynchronous Output (CMP1A) Enable.
0: Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
1: Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
Rev. 1.0
103
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.14. PBCFG0_XBAR0L Register Bit Descriptions
Bit
Name
25
CMP1SEN
Function
Comparator 1 Synchronous Output (CMP1S) Enable.
0: Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
1: Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
24
CMP0AEN
Comparator 0 Asynchronous Output (CMP0A) Enable.
0: Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
1: Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
23
CMP0SEN
Comparator 0 Synchronous Output (CMP0S) Enable.
0: Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
1: Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
22
I2C0EN
I2C0 Enable.
0: Disable I2C0 SDA and SCL on Crossbar 0.
1: Enable I2C0 SDA and SCL on Crossbar 0.
21
I2S0TXEN
I2S0 TX Enable.
0: Disable I2S0 TX on Crossbar 0.
1: Enable I2S0 TX on Crossbar 0.
20
ECI1EN
PCA1 ECI Enable.
0: Disable PCA1 ECI on Crossbar 0.
1: Enable PCA1 ECI on Crossbar 0.
19
ECI0EN
PCA0 ECI Enable.
0: Disable PCA0 ECI on Crossbar 0.
1: Enable PCA0 ECI on Crossbar 0.
18
EECI0EN
EPCA0 ECI Enable.
0: Disable EPCA0 ECI on Crossbar 0.
1: Enable EPCA0 ECI on Crossbar 0.
17:16
PCA1EN
PCA1 Channel Enable.
00: Disable all PCA1 channels on Crossbar 0.
01: Enable PCA1 CEX0 on Crossbar 0.
10: Reserved.
11: Enable PCA1 CEX0 and CEX1 on Crossbar 0.
15:14
PCA0EN
PCA0 Channel Enable.
00: Disable all PCA0 channels on Crossbar 0.
01: Enable PCA0 CEX0 on Crossbar 0.
10: Reserved.
11: Enable PCA0 CEX0 and CEX1 on Crossbar 0.
13:11
104
Reserved
Must write reset value.
Rev. 1.0
Table 8.14. PBCFG0_XBAR0L Register Bit Descriptions
Bit
Name
10:8
EPCA0EN
Function
EPCA0 Channel Enable.
000: Disable all EPCA0 channels on Crossbar 0.
001: Enable EPCA0 STD_CEX0 on Crossbar 0.
010: Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0.
011: Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0.
100: Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on
Crossbar 0.
101: Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and
STD_CEX4 on Crossbar 0.
110: Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3,
STD_CEX4, and STD_CEX5 on Crossbar 0.
111: Reserved.
7
USART1CEN
USART1 Clock Signal Enable.
0: Disable USART1 clock on Crossbar 0.
1: Enable USART1 clock on Crossbar 0.
6
USART1FCEN
USART1 Flow Control Enable.
0: Disable USART1 flow control on Crossbar 0.
1: Enable USART1 flow control on Crossbar 0.
5
USART1EN
USART1 Enable.
0: Disable USART1 RX and TX on Crossbar 0.
1: Enable USART1 RX and TX on Crossbar 0.
4
SPI0NSSEN
SPI0 NSS Pin Enable.
0: Disable SPI0 NSS on Crossbar 0.
1: Enable SPI0 NSS on Crossbar 0.
3
SPI0EN
SPI0 Enable.
0: Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.
1: Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.
2
USART0CEN
USART0 Clock Signal Enable.
0: Disable USART0 clock on Crossbar 0.
1: Enable USART0 clock on Crossbar 0.
1
USART0FCEN
USART0 Flow Control Enable.
0: Disable USART0 flow control on Crossbar 0.
1: Enable USART0 flow control on Crossbar 0.
0
USART0EN
USART0 Enable.
0: Disable USART0 RX and TX on Crossbar 0.
1: Enable USART0 RX and TX on Crossbar 0.
Rev. 1.0
105
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.4. PBCFG0_XBAR0H: Crossbar 0 Control (High)
24
23
22
21
20
19
18
17
16
Name
Reserved
Type
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
UART0EN
25
UART0FCEN
26
UART1EN
27
SPI1EN
28
SPI1NSSEN
29
SPI2EN
30
SPI2NSSEN
31
AHBEN
Bit
XBAR0EN
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Register ALL Access Address
PBCFG0_XBAR0H = 0x4002_A030
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.15. PBCFG0_XBAR0H Register Bit Descriptions
Bit
Name
31
XBAR0EN
Function
Crossbar 0 Enable.
0: Disable Crossbar 0.
1: Enable Crossbar 0.
30:8
Reserved
7
AHBEN
Must write reset value.
AHB Clock Output Enable.
0: Disable the AHB Clock / 16 output on Crossbar 0.
1: Enable the AHB Clock / 16 output on Crossbar 0.
6
SPI2NSSEN
SPI2 NSS Pin Enable.
0: Disable SPI2 NSS on Crossbar 0.
1: Enable SPI2 NSS on Crossbar 0.
5
SPI2EN
SPI2 Enable.
0: Disable SPI2 SCK, MISO, and MOSI on Crossbar 0.
1: Enable SPI2 SCK, MISO, and MOSI on Crossbar 0.
4
SPI1NSSEN
SPI1 NSS Pin Enable.
0: Disable SPI1 NSS on Crossbar 0.
1: Enable SPI1 NSS on Crossbar 0.
106
Rev. 1.0
Table 8.15. PBCFG0_XBAR0H Register Bit Descriptions
Bit
Name
3
SPI1EN
Function
SPI1 Enable.
0: Disable SPI1 SCK, MISO, and MOSI on Crossbar 0.
1: Enable SPI1 SCK, MISO, and MOSI on Crossbar 0.
2
UART1EN
UART1 Enable.
0: Disable UART1 RX and TX on Crossbar 0.
1: Enable UART1 RX and TX on Crossbar 0.
1
UART0FCEN
UART0 Flow Control Enable.
0: Disable UART0 flow control on Crossbar 0.
1: Enable UART0 flow control on Crossbar 0.
0
UART0EN
UART0 Enable.
0: Disable UART0 RX and TX on Crossbar 0.
1: Enable UART0 RX and TX on Crossbar 0.
Rev. 1.0
107
Port I/O Configuration
SiM3U1xx/SiM3C1xx
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
SSG0EN
RW
RW
RW
RW
RW
RW
RW
RW
Table 8.16. PBCFG0_XBAR1 Register Bit Descriptions
Bit
Name
31
XBAR1EN
Function
Crossbar 1 Enable.
0: Disable Crossbar 1.
1: Enable Crossbar 1.
30:22
Reserved
21
KILLHDEN
Must write reset value.
High Drive Kill Pin Enable.
0: Disable the PB High Drive Kill Pin on Crossbar 1.
1: Enable the PB High Drive Kill Pin on Crossbar 1.
I2C1EN
I2C1 Enable.
0: Disable I2C1 SDA and SCL on Crossbar 1.
1: Enable I2C1 SDA and SCL on Crossbar 1.
LPT0OEN
LPTIMER0 Output Enable.
0: Disable LPTIMER0 Output on Crossbar 1.
1: Enable LPTIMER0 Output on Crossbar 1.
18
108
16
RW
PBCFG0_XBAR1 = 0x4002_A040
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
19
17
Reserved
Register ALL Access Address
20
18
UART1EN
19
I2S0RXEN
20
Reserved
21
CMP0SEN
22
LPT0OEN
23
CMP1SEN
24
I2C1EN
25
SPI1EN
0
USART1EN
26
KILLHDEN
0
USART1FCEN
27
SPI1NSSEN
Reset
USART1CEN
28
RTC0EN
Type
UART0EN
29
SPI2EN
Name
UART0FCEN
30
SPI2NSSEN
31
XBAR1EN
Bit
I2S0TXEN
Register 8.5. PBCFG0_XBAR1: Crossbar 1 Control
I2C0EN
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Reserved
Must write reset value.
Rev. 1.0
0
0
Table 8.16. PBCFG0_XBAR1 Register Bit Descriptions
Bit
Name
17
I2S0RXEN
Function
I2S0 RX Enable.
0: Disable I2S0 RX on Crossbar 1.
1: Enable I2S0 RX on Crossbar 1.
16
UART1EN
UART1 Enable.
0: Disable UART1 RX and TX on Crossbar 1.
1: Enable UART1 RX and TX on Crossbar 1.
15
I2C0EN
I2C0 Enable.
0: Disable I2C0 SDA and SCL on Crossbar 1.
1: Enable I2C0 SDA and SCL on Crossbar 1.
14
I2S0TXEN
I2S0 TX Enable.
0: Disable I2S0 TX on Crossbar 1.
1: Enable I2S0 TX on Crossbar 1.
13
UART0FCEN
UART0 Flow Control Enable.
0: Disable UART0 flow control on Crossbar 1.
1: Enable UART0 flow control on Crossbar1.
12
UART0EN
UART0 Enable.
0: Disable UART0 RX and TX on Crossbar 1.
1: Enable UART0 RX and TX on Crossbar 1.
11
USART1CEN
USART1 Clock Signal Enable.
0: Disable USART1 clock on Crossbar 1.
1: Enable USART1 clock on Crossbar 1.
10
USART1FCEN
USART1 Flow Control Enable.
0: Disable USART1 flow control on Crossbar 1.
1: Enable USART1 flow control on Crossbar 1.
9
USART1EN
USART1 Enable.
0: Disable USART1 RX and TX on Crossbar 1.
1: Enable USART1 RX and TX on Crossbar 1.
8
SPI2NSSEN
SPI2 NSS Pin Enable.
0: Disable SPI2 NSS on Crossbar 1.
1: Enable SPI2 NSS on Crossbar 1.
7
SPI2EN
SPI2 Enable.
0: Disable SPI2 SCK, MISO, and MOSI on Crossbar 1.
1: Enable SPI2 SCK, MISO, and MOSI on Crossbar 1.
6
RTC0EN
RTC0 Output Enable.
0: Disable RTC0 Output on Crossbar 1.
1: Enable RTC0 Output on Crossbar 1.
5
SPI1NSSEN
SPI1 NSS Pin Enable.
0: Disable SPI1 NSS on Crossbar 1.
1: Enable SPI1 NSS on Crossbar 1.
Rev. 1.0
109
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.16. PBCFG0_XBAR1 Register Bit Descriptions
Bit
Name
4
SPI1EN
Function
SPI1 Enable.
0: Disable SPI1 SCK, MISO, and MOSI on Crossbar 1.
1: Enable SPI1 SCK, MISO, and MOSI on Crossbar 1.
3
CMP1SEN
Comparator 1 Synchronous Output (CMP1S) Enable.
0: Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.
1: Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.
2
CMP0SEN
Comparator 0 Synchronous Output (CMP0S) Enable.
0: Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.
1: Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.
1:0
SSG0EN
SSG0 Enable.
00: Disable all SSG0 channels on Crossbar 1.
01: Enable SSG0 EX0 on Crossbar 1.
10: Enable SSG0 EX0 and EX1 on Crossbar 1.
11: Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1.
110
Rev. 1.0
Register 8.6. PBCFG0_PBKEY: Global Port Key
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
Reserved
KEY
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBCFG0_PBKEY = 0x4002_A050
Table 8.17. PBCFG0_PBKEY Register Bit Descriptions
Bit
Name
31:8
Reserved
7:0
KEY
Function
Must write reset value.
Port Bank 2, 3, and 4 Key.
When a port pin on bank 2, 3, or 4 is locked for access, firmware must write the
value 0xA5 followed by a write of 0xF1 to this field to unlock the pin. Reading this
register returns the current status of lock (0 = Locked with no keys written, 1 =
Locked with first key written, 2 = Unlocked). Once unlocked, any write to a port bank
2, 3, or 4 register or writing the incorrect key sequence value will re-lock the interface. Locked bits are determined by the PBLOCK settings for the specific port bank.
Rev. 1.0
111
Port I/O Configuration
SiM3U1xx/SiM3C1xx
PBCFG0_XBAR0H PBCFG0_XBAR0L PBCFG0_CONTROL1 PBCFG0_CONTROL0 Register Name
0x4002_A010
0x4002_A020
ALL Address
0x4002_A030
0x4002_A000
ALL | SET | CLR
ALL | SET | CLR
Access Methods
ALL | SET | CLR
ALL | SET | CLR
LOCK
Reserved
Bit 31
XBAR0EN
PGDONEF
TMR1EXEN
Bit 30
Reserved
TMR1CTEN
Bit 29
TMR0EXEN
Bit 28
Reserved
TMR0CTEN
Bit 27
PGTIMER
CMP1AEN
Bit 26
CMP1SEN
Bit 25
CMP0AEN
Bit 24
EVREGRMD
CMP0SEN
Bit 23
I2C0EN
Bit 22
I2S0TXEN
Bit 21
Reserved
ECI1EN
Bit 20
Reserved
Reserved
ECI0EN
Bit 19
EECI0EN
Bit 18
Bit 17
MATMD
PCA1EN
Bit 16
INT1EN
Bit 15
PCA0EN
Bit 14
INT1MD
Bit 13
EMIFWIDTH
Reserved
INT1POL
Bit 12
Bit 11
Bit 10
INT1SEL
EPCA0EN
EMIFEN
Bit 9
EMIFCS1EN
Bit 8
USART1CEN
AHBEN
EMIFBE0BEN
INT0EN
Bit 7
USART1FCEN
SPI2NSSEN
Bit 6
INT0MD
USART1EN
SPI2EN
Bit 5
Reserved
SPI0NSSEN
SPI1NSSEN
INT0POL
Bit 4
SPI0EN
SPI1EN
Bit 3
USART0CEN
UART1EN
Bit 2
INT0SEL
ETMEN
USART0FCEN
UART0FCEN
Bit 1
JTAGEN
USART0EN
UART0EN
Bit 0
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.18. PBCFG0 Register Memory Map
Table 8.18. PBCFG0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
112
Rev. 1.0
PBCFG0_PBKEY PBCFG0_XBAR1 Register Name
0x4002_A040
ALL Address
0x4002_A050
ALL | SET | CLR Access Methods
ALL
XBAR1EN
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Reserved
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
KILLHDEN
Bit 21
I2C1EN
Bit 20
Reserved
LPT0OEN
Bit 19
Reserved
Bit 18
I2S0RXEN
Bit 17
UART1EN
Bit 16
I2C0EN
Bit 15
I2S0TXEN
Bit 14
UART0FCEN
Bit 13
UART0EN
Bit 12
USART1CEN
Bit 11
USART1FCEN
Bit 10
USART1EN
Bit 9
SPI2NSSEN
Bit 8
SPI2EN
Bit 7
RTC0EN
Bit 6
SPI1NSSEN
Bit 5
SPI1EN
Bit 4
KEY
CMP1SEN
Bit 3
CMP0SEN
Bit 2
Bit 1
SSG0EN
Bit 0
Table 8.18. PBCFG0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
113
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.19. PBSTD0, PBSTD1, PBSTD2, and PBSTD3 Registers
This section contains the detailed register descriptions for PBSTD0, PBSTD1, PBSTD2 and PBSTD3 registers.
Register 8.7. PBSTDn_PB: Output Latch
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
Name
PB
Type
RW
Reset
1
1
1
1
1
1
1
1
Register ALL Access Addresses
PBSTD0_PB = 0x4002_A0A0
PBSTD1_PB = 0x4002_A140
PBSTD2_PB = 0x4002_A1E0
PBSTD3_PB = 0x4002_A320
This register also supports SET access at (ALL+0x4), CLR access at (ALL+0x8) and MSK access at (ALL+0xC)
Table 8.19. PBSTDn_PB Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PB
Function
Must write reset value.
Output Latch.
These bits define the logic level of the port bank output latch. Each bit in this field
controls the output latch value for the corresponding port bank pin (bit x controls the
latch for pin PBn.x). Digital input pins should be written to 1 and configured for open
drain mode. When using this register via the MSK address, the upper 16 bits can be
used to mask writes of the lower 16 bits to the corresponding port bank latches.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
114
Rev. 1.0
Register 8.8. PBSTDn_PBPIN: Pin Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
PBPIN
Type
R
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Addresses
PBSTD0_PBPIN = 0x4002_A0B0
PBSTD1_PBPIN = 0x4002_A150
PBSTD2_PBPIN = 0x4002_A1F0
PBSTD3_PBPIN = 0x4002_A330
Table 8.20. PBSTDn_PBPIN Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PBPIN
Function
Must write reset value.
Pin Value.
These bits read the digital logic level present at the corresponding port bank pin (bit
x reads the logic level of pin PBn.x). Pins configured for analog mode will always
read back 0.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
Rev. 1.0
115
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.9. PBSTDn_PBMDSEL: Mode Select
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
PBMDSEL
Type
RW
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Addresses
PBSTD0_PBMDSEL = 0x4002_A0C0
PBSTD1_PBMDSEL = 0x4002_A160
PBSTD2_PBMDSEL = 0x4002_A200
PBSTD3_PBMDSEL = 0x4002_A340
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.21. PBSTDn_PBMDSEL Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
PBMDSEL
Mode Select.
These bits configure the mode of the corresponding port bank pin (bit x controls the
mode of pin PBn.x). Setting a bit to 1 configures the pin for digital mode, while clearing a bit to 0 configures the pin for analog mode. Pins configured in analog mode
have their digital input paths and weak pullup disconnected.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
116
Rev. 1.0
Register 8.10. PBSTDn_PBSKIPEN: Crossbar Pin Skip Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PBSKIPEN
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD0_PBSKIPEN = 0x4002_A0D0
PBSTD1_PBSKIPEN = 0x4002_A170
PBSTD2_PBSKIPEN = 0x4002_A210
PBSTD3_PBSKIPEN = 0x4002_A350
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.22. PBSTDn_PBSKIPEN Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PBSKIPEN
Function
Must write reset value.
Crossbar Pin Skip Enable.
These bits configure the crossbar to skip over the corresponding port bank pin (bit x
skips over pin PBn.x). Setting a bit to 1 prevents the crossbar from assigning a
peripheral to the pin.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
Rev. 1.0
117
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.11. PBSTDn_PBOUTMD: Output Mode
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PBOUTMD
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD0_PBOUTMD = 0x4002_A0E0
PBSTD1_PBOUTMD = 0x4002_A180
PBSTD2_PBOUTMD = 0x4002_A220
PBSTD3_PBOUTMD = 0x4002_A360
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.23. PBSTDn_PBOUTMD Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PBOUTMD
Function
Must write reset value.
Output Mode.
These bits configure the digital output mode of the corresponding port bank pin (bit
x configures the output mode of pin PBn.x). Setting a bit to 1 configures the pin for
push-pull operation. Clearing a bit to 0 configures the pin for open-drain operation.
Digital inputs should be configured for open drain mode, with a 1 written to the corresponding output latch.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
118
Rev. 1.0
Register 8.12. PBSTDn_PBDRV: Drive Strength
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
PBPUEN
Bit
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PBDRV
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD0_PBDRV = 0x4002_A0F0
PBSTD1_PBDRV = 0x4002_A190
PBSTD2_PBDRV = 0x4002_A230
PBSTD3_PBDRV = 0x4002_A370
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.24. PBSTDn_PBDRV Register Bit Descriptions
Bit
Name
Function
31:17
Reserved
Must write reset value.
16
PBPUEN
Port Bank Weak Pull-up Enable.
Globally enables the weak pull-up for all pins on this port bank. Pins in analog mode
will have their individual weak pullups automatically disabled.
15:0
PBDRV
Drive Strength.
These bits configure the output drive strength of the corresponding port bank pin (bit
x configures the drive strength of pin PBn.x). Setting a bit to 1 enables high drive
output on the pin. Clearing a bit to 0 selects low drive output for the pin.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
Rev. 1.0
119
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.13. PBSTDn_PM: Port Match Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Name
PM
Type
RW
Reset
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD0_PM = 0x4002_A100
PBSTD1_PM = 0x4002_A1A0
PBSTD2_PM = 0x4002_A240
PBSTD3_PM = 0x4002_A380
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.25. PBSTDn_PM Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PM
Function
Must write reset value.
Port Match Value.
These bits serve a dual purpose as either a Port Match function, or an Activity Monitor function.
When used in Port Match mode (MATMD is 00b), the bits in this register determine
the match value for individual pins (bit x configures the match value for pin PBn.x). If
the corresponding bit in PMEN is set to 1, a port match event will be triggered when
the value in PM matches the logic level at the pin.
If Activity Monitoring is enabled (MATMD is 01b or 10b), the Port Match registers
are used for Activity Monitoring. In this mode, PM is read-only and reports the Activity Monitoring status on a pin, PMEN selects the pins for Activity Monitoring, and
Port Match is unavailable.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
120
Rev. 1.0
Register 8.14. PBSTDn_PMEN: Port Match Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PMEN
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD0_PMEN = 0x4002_A110
PBSTD1_PMEN = 0x4002_A1B0
PBSTD2_PMEN = 0x4002_A250
PBSTD3_PMEN = 0x4002_A390
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.26. PBSTDn_PMEN Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
PMEN
Function
Must write reset value.
Port Match Enable.
These bits enable Port Match or Activity Monitoring on the corresponding port bank
pin (bit x enables these functions for pin PBn.x). Setting a bit to 1 enables the pin to
be used for Port Match or Activity Monitoring. Clearing the bit to 0 disables these
functions for the pin.
Notes:
1. On SiM3x1x7 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of 15 pins (PB2.0-PB2.14), and PB3
consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB0 and PB1 are full ports (PBx.0-PBx.15), PB2 consists of
4 pins (PB2.0-PB2.3), and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB0 is a full port (PB0.0PB0.15), PB1 consists of 4 pins (PB1.0-PB1.3), PB2 is not implemented, and PB3 consists of 4 pins (PB3.0-PB3.3).
Any bits in this register controlling unimplemented pins are reserved.
Rev. 1.0
121
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.15. PBSTDn_PBLOCK: Lock Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PBLOCK
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD2_PBLOCK = 0x4002_A260
PBSTD3_PBLOCK = 0x4002_A3A0
Table 8.27. PBSTDn_PBLOCK Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
PBLOCK
Port Bank Lock.
These bits lock the corresponding port bank pins (bit x locks functions for pin
PBn.x). Setting a bit to 1 prevents modification of that bit in all of the port bank control registers unless the port bank security interface is unlocked.
Notes:
1. Only standard ports PB2 and PB3 implement this register. On SiM3x1x7 devices, PB2 consists of 15 pins (PB2.0PB2.14) and PB3 consists of 12 pins (PB3.0-PB3.11). On SiM3x1x6 devices, PB2 consists of 4 pins (PB2.0-PB2.3)
and PB3 consists of 10 pins (PB3.0-PB3.9). On SiM3x1x4 devices, PB2 is not implemented and PB3 consists of 4 pins
(PB3.0-PB3.3). Any bits in this register controlling unimplemented pins are reserved.
122
Rev. 1.0
Register 8.16. PBSTDn_PBPGEN: Pulse Generator Pin Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
PBPGEN
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PBSTD2_PBPGEN = 0x4002_A270
Table 8.28. PBSTDn_PBPGEN Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
PBPGEN
Pulse Generator Pin Enable.
These bits enable the pulse generator function on the corresponding port bank pin
(bit x enables the pulse generator for pin PBn.x). Setting a bit to 1 enables pulse
generation for the pin and clearing a bit to 0 disables pulse generation for the pin.
Notes:
1. Only standard port PB2 implements this register. On SiM3x1x7 devices, PB2 consists of 15 pins (PB2.0-PB2.14). On
SiM3x1x6 devices, PB2 consists of 4 pins (PB2.0-PB2.3). On SiM3x1x4 devices, PB2 is not implemented. Any bits in
this register controlling unimplemented pins are reserved.
Rev. 1.0
123
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.17. PBSTDn_PBPGPHASE: Pulse Generator Phase
Bit
31
30
29
28
27
26
25
24
23
Name
PBPGPH1
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
PBPGPH0
Type
RW
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Addresses
PBSTD2_PBPGPHASE = 0x4002_A280
Table 8.29. PBSTDn_PBPGPHASE Register Bit Descriptions
Bit
Name
31:16
PBPGPH1
Function
Pulse Generator Phase 1.
These bits set the logic level for phase 1 of the pulse generator on the corresponding port bank pin (bit x defines phase 1 for pin PBn.x). If pulse generation is enabled
on the pin, writing to this register will trigger the beginning of the pulse. The value in
PBPGPH0 will be applied to the enabled pins immediately, and when the pulse generator counter times out, the enabled pins will be set to the value in PBPGPH1.
15:0
PBPGPH0
Pulse Generator Phase 0.
These bits set the logic level for phase 0 of the pulse generator on the corresponding port bank pin (bit x defines phase 0 for pin PBn.x). If pulse generation is enabled
on the pin, writing to this register will trigger the beginning of the pulse. The value in
PBPGPH0 will be applied to the enabled pins immediately, and when the pulse generator counter times out, the enabled pins will be set to the value in PBPGPH1.
Notes:
1. Only standard port PB2 implements this register. On SiM3x1x7 devices, PB2 consists of 15 pins (PB2.0-PB2.14). On
SiM3x1x6 devices, PB2 consists of 4 pins (PB2.0-PB2.3). On SiM3x1x4 devices, PB2 is not implemented. Any bits in
this register controlling unimplemented pins are reserved.
124
Rev. 1.0
8.20. PBSTDn Register Memory Map
PBSTDn_PBMDSEL PBSTDn_PBPIN
Register Name
PBSTDn_PB
0x20
0x10
ALL Offset
0x0
ALL | SET | CLR
ALL
ALL | SET | CLR | MASK Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PBMDSEL
PBPIN
PB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 8.30. PBSTDn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PBSTD0 = 0x4002_A0A0, PBSTD1 = 0x4002_A140, PBSTD2 =
0x4002_A1E0, PBSTD3 = 0x4002_A320
Rev. 1.0
125
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.30. PBSTDn Memory Map
PBSTDn_PM PBSTDn_PBDRV PBSTDn_PBOUTMD PBSTDn_PBSKIPEN Register Name
0x50
0x40
0x30
ALL Offset
0x60
ALL | SET | CLR
ALL | SET | CLR
Access Methods
ALL | SET | CLR ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
Bit 24
Reserved
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
PBPUEN
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PM
PBOUTMD
PBSKIPEN
PBDRV
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PBSTD0 = 0x4002_A0A0, PBSTD1 = 0x4002_A140, PBSTD2 =
0x4002_A1E0, PBSTD3 = 0x4002_A320
126
Rev. 1.0
PBSTDn_PBPGPHASE PBSTDn_PBPGEN PBSTDn_PBLOCK PBSTDn_PMEN Register Name
0xA0
0x90
0x80
0x70
ALL Offset
ALL
ALL
ALL
ALL | SET | CLR Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Reserved
PBPGPH1
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PBPGEN
PBLOCK
PMEN
PBPGPH0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 8.30. PBSTDn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PBSTD0 = 0x4002_A0A0, PBSTD1 = 0x4002_A140, PBSTD2 =
0x4002_A1E0, PBSTD3 = 0x4002_A320
Rev. 1.0
127
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.21. PBHD4 Registers
This section contains the detailed register descriptions for PBHD4 registers.
Register 8.18. PBHD4_PB: Output Latch
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
Name
Reserved
PB
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
1
1
1
Register ALL Access Address
PBHD4_PB = 0x4002_A3C0
This register also supports SET access at (ALL+0x4), CLR access at (ALL+0x8) and MSK access at (ALL+0xC)
Table 8.31. PBHD4_PB Register Bit Descriptions
Bit
Name
31:6
Reserved
5:0
PB
Function
Must write reset value.
Output Latch.
These bits define the logic level of the port bank output latch. Each bit in this field
controls the output latch value for the corresponding port bank pin (bit x controls the
latch for pin PBn.x). Digital input pins should be written to 1 and configured for open
drain mode. When using this register via the MSK address, the upper 16 bits can be
used to mask writes of the lower 16 bits to the corresponding port bank latches.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
128
Rev. 1.0
Register 8.19. PBHD4_PBPIN: Pin Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
Name
Reserved
PBPIN
Type
R
R
Reset
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Register ALL Access Address
PBHD4_PBPIN = 0x4002_A3D0
Table 8.32. PBHD4_PBPIN Register Bit Descriptions
Bit
Name
31:6
Reserved
5:0
PBPIN
Function
Must write reset value.
Pin Value.
These bits read the digital logic level present at the corresponding port bank pin (bit
x reads the logic level of pin PBn.x). Pins configured for analog mode will always
read back 0.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
129
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.20. PBHD4_PBMDSEL: Mode Select
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
Name
Reserved
PBMDSEL
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Register ALL Access Address
PBHD4_PBMDSEL = 0x4002_A3E0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.33. PBHD4_PBMDSEL Register Bit Descriptions
Bit
Name
Function
31:6
Reserved
Must write reset value.
5:0
PBMDSEL
Mode Select.
These bits configure the mode of the corresponding port bank pin (bit x controls the
mode of pin PBn.x). Setting a bit to 1 configures the pin for digital mode, while clearing a bit to 0 configures the pin for analog mode. Pins configured in analog mode
have their digital input paths and weak pullup disconnected.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
130
Rev. 1.0
Register 8.21. PBHD4_PBDEN: Driver Enable
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Name
Reserved
PBPDEN
Type
R
RW
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Name
Reserved
PBNDEN
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBHD4_PBDEN = 0x4002_A3F0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.34. PBHD4_PBDEN Register Bit Descriptions
Bit
Name
Function
31:22
Reserved
Must write reset value.
21:16
PBPDEN
Port Bank P-Channel Driver Enable.
These bits enable the P-channel (high-side) driver for the corresponding port bank
pin (bit x enables the P-channel driver for pin PBn.x). When a bit is set to 1, the Pchannel driver is enabled.
15:6
Reserved
Must write reset value.
5:0
PBNDEN
Port Bank N-Channel Driver Enable.
These bits enable the N-channel (low-side) driver for the corresponding port bank
pin (bit x enables the N-channel driver for pin PBn.x). When a bit is set to 1, the Nchannel driver is enabled.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
131
Port I/O Configuration
SiM3U1xx/SiM3C1xx
28
27
26
25
24
23
22
21
20
19
PBPUEN
29
18
RW
RW
Name
Reserved
Reserved
30
PBBIASEN
31
PBDRVEN
Bit
PBLVMD
Register 8.22. PBHD4_PBDRV: Drive Strength
PBVTRKEN
Port I/O Configuration
SiM3U1xx/SiM3C1xx
PBSLEW
Type
R
RW
RW
RW
RW
RW
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Name
Reserved
PBDRV
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBHD4_PBDRV = 0x4002_A400
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.35. PBHD4_PBDRV Register Bit Descriptions
Bit
Name
31:24
Reserved
23
PBVTRKEN
Function
Must write reset value.
Port Voltage Supply Tracking Enable.
When set to 1, this bit enables an internal 1/4 voltage divider on the VIOHD supply.
The output of this divider can be used by the Comparator and SARADC modules.
0: Disable VIOHD tracking.
1: Enable VIOHD tracking.
22
PBDRVEN
Port Drive Enable.
0: Disable the port drivers.
1: Enable the port drivers.
21
PBBIASEN
Port Bias Enable.
When set to 1, this bit enables the bias generator for high drive capability on this
port. When enabling High Drive Port Bank pins, firmware must set these bits in the
following sequence with separate register writes:
1) PBBIASEN
2) PBLVMD (optional)
3) PBDRVEN
20
Reserved
Must write reset value.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
132
Rev. 1.0
Table 8.35. PBHD4_PBDRV Register Bit Descriptions
Bit
Name
19:18
PBSLEW
Function
Port Slew Control.
Selects the slew rate for this port bank. Four slew rates are available, from 0 (fastest) to 3 (slowest).
17
PBLVMD
Port Low Voltage Mode.
Low power mode (PBLVMD = 1) must be used if VIOHD is less than 2.7 V and is
recommended if VIOHD is less than 3.0 V. PBLVMD must be cleared to 0 if VIOHD
is greater than 3.6 V.
0: Port configured for normal mode.
1: Port configured for low power mode.
16
PBPUEN
Port Bank Weak Pull-up Enable.
Globally enables the weak pull-up for all pins on this port bank. Pins in analog mode
will have their individual weak pullups automatically disabled.
15:6
Reserved
5:0
PBDRV
Must write reset value.
Drive Strength.
These bits configure the output drive strength of the corresponding port bank pin (bit
x configures the drive strength of pin PBn.x). Setting a bit to 1 enables high drive
output on the pin. Clearing a bit to 0 selects low drive output for the pin. PBDRV
must be cleared to 0 to use the current-limiting feature.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
133
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Register 8.23. PBHD4_PBILIMIT: Current Limit
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
PILIMIT
NILIMIT
Type
R
RW
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Name
Reserved
PBILEN
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBHD4_PBILIMIT = 0x4002_A410
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.36. PBHD4_PBILIMIT Register Bit Descriptions
Bit
Name
31:24
Reserved
23:20
PILIMIT
Function
Must write reset value.
P-Channel Current Limit.
Current limit value for P-channel devices for all pins in this port bank. Each pin can
individually have current limiting enabled or disabled. There are 16 current limit levels, from 0 (lowest) to 15 (highest).
19:16
NILIMIT
N-Channel Current Limit.
This field is the current limit value for N-channel devices for all pins in this port bank.
Each pin can individually have current limiting enabled or disabled. There are 16
current limit levels, from 0 (lowest) to 15 (highest).
15:6
Reserved
Must write reset value.
5:0
PBILEN
Current Limit Enable.
These bits enable the current-limiting circuitry of the corresponding port bank pin
(bit x enables the current limiter for pin PBn.x). Setting a bit to 1 enables the current
limiting circuitry for that pin. The drive strength must be set to low (PBDRV=0) to
use current-limiting.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
134
Rev. 1.0
Register 8.24. PBHD4_PBFSEL: Function Select
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PB5SEL
PB4SEL
PB3SEL
PB2SEL
PB1SEL
PB0SEL
Type
R
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBHD4_PBFSEL = 0x4002_A430
Table 8.37. PBHD4_PBFSEL Register Bit Descriptions
Bit
Name
Function
31:13
Reserved
Must write reset value.
12:10
PB5SEL
Port Bank n.5 Function Select.
Digital functional selection for pin PBn.5.
000: Pin configured for GPIO.
001: Pin configured for Port Mapped Level Shift.
010: Pin configured for EPCA0 output.
011: Pin configured for UART1 CTS.
100: Pin configured for LPTIMER0 toggle output.
101-111: Reserved.
9:8
PB4SEL
Port Bank n.4 Function Select.
Digital functional selection for pin PBn.4.
00: Pin configured for GPIO.
01: Pin configured for Port Mapped Level Shift.
10: Pin configured for EPCA0 output.
11: Pin configured for UART1 RTS.
7:6
PB3SEL
Port Bank n.3 Function Select.
Digital functional selection for pin PBn.3.
00: Pin configured for GPIO.
01: Pin configured for Port Mapped Level Shift.
10: Pin configured for EPCA0 output.
11: Pin configured for UART1 RX.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
135
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.37. PBHD4_PBFSEL Register Bit Descriptions
Bit
Name
5:4
PB2SEL
Function
Port Bank n.2 Function Select.
Digital functional selection for pin PBn.2.
00: Pin configured for GPIO.
01: Pin configured for Port Mapped Level Shift.
10: Pin configured for EPCA0 output.
11: Pin configured for UART1 TX.
3:2
PB1SEL
Port Bank n.1 Function Select.
Digital functional selection for pin PBn.1.
00: Pin configured for GPIO.
01: Pin configured for Port Mapped Level Shift.
10: Pin configured for EPCA0 output.
11: Reserved.
1:0
PB0SEL
Port Bank n.0 Function Select.
Digital functional selection for pin PBn.0.
00: Pin configured for GPIO.
01: Pin configured for Port Mapped Level Shift.
10: Pin configured for EPCA0 output.
11: Reserved.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
136
Rev. 1.0
Register 8.25. PBHD4_PBSS: Safe State Control
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
SSMDEN
31
PBSSSMD
Bit
Type
R
RW
RW
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PB0SSSEL
0
PB1SSSEL
0
PB2SSSEL
0
PB3SSSEL
0
PB4SSSEL
0
PB5SSSEL
Reset
Type
R
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PBHD4_PBSS = 0x4002_A440
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 8.38. PBHD4_PBSS Register Bit Descriptions
Bit
Name
31:18
Reserved
17
PBSSSMD
Function
Must write reset value.
Safe State Signal Mode.
When PBSSSMD is cleared to 0, the kill signal from from a Crossbar must be
asserted for two APB clocks before the pins will switch to their designated safe
state. When PBSSSMD is set to 1, the kill signal will bypass this deglitching logic
and immediately take effect.
16
SSMDEN
Enter Safe State Mode.
Set by firmware or the PB_HDKill signal to place the high drive port in the Safe State
specified by the PBxSSSEL fields. Once set, this bit must be cleared by firmware or
a device reset.
0: Disable Safe State.
1: Enter Safe State. Each PBn.x pin will enter the states defined by PBxSSSEL.
15:12
Reserved
Must write reset value.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
137
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Table 8.38. PBHD4_PBSS Register Bit Descriptions
Bit
Name
11:10
PB5SSSEL
Function
Port Bank n.5 Safe State Select.
Safe state for pin PBn.5.
00: Place PBn.5 in a High Impedance state.
01: Drive PBn.5 High.
10: Drive PBn.5 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
9:8
PB4SSSEL
Port Bank n.4 Safe State Select.
Safe state for pin PBn.4.
00: Place PBn.4 in a High Impedance state.
01: Drive PBn.4 High.
10: Drive PBn.4 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
7:6
PB3SSSEL
Port Bank n.3 Safe State Select.
Safe state for pin PBn.3.
00: Place PBn.3 in a High Impedance state.
01: Drive PBn.3 High.
10: Drive PBn.3 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
5:4
PB2SSSEL
Port Bank n.2 Safe State Select.
Safe state for pin PBn.2.
00: Place PBn.2 in a High Impedance state.
01: Drive PBn.2 High.
10: Drive PBn.2 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
3:2
PB1SSSEL
Port Bank n.1 Safe State Select.
Safe state for pin PBn.1.
00: Place PBn.1 in a High Impedance state.
01: Drive PBn.1 High.
10: Drive PBn.1 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
1:0
PB0SSSEL
Port Bank n.0 Safe State Select.
Safe state for pin PBn.0.
00: Place PBn.0 in a High Impedance state.
01: Drive PBn.0 High.
10: Drive PBn.0 Low.
11: Ignore the safe state signal (weak pull-ups disabled).
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
138
Rev. 1.0
Register 8.26. PBHD4_PBLOCK: Lock Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
Name
Reserved
PBLOCK
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Register ALL Access Address
PBHD4_PBLOCK = 0x4002_A450
Table 8.39. PBHD4_PBLOCK Register Bit Descriptions
Bit
Name
Function
31:6
Reserved
Must write reset value.
5:0
PBLOCK
Port Bank Lock.
These bits lock the corresponding port bank pins (bit x locks functions for pin
PBn.x). Setting a bit to 1 prevents modification of that bit in all of the port bank control registers unless the port bank security interface is unlocked.
Notes:
1. On SiM3x1x7 devices, PB4 is a full high drive port (PB4.0-PB4.5). On SiM3x1x6 devices, PB4 consists of 4 pins
(PB4.0-PB4.3). On SiM3x1x4 devices, PB4 consists of 4 pins (PB4.0-PB4.3). Any bits in this register controlling
unimplemented pins are reserved.
Rev. 1.0
139
Port I/O Configuration
SiM3U1xx/SiM3C1xx
8.22. PBHD4 Register Memory Map
Table 8.40. PBHD4 Memory Map
PBHD4_PBDEN PBHD4_PBMDSEL PBHD4_PBPIN
Register Name
PBHD4_PB
0x4002_A3F0
0x4002_A3E0
0x4002_A3D0
ALL Address
0x4002_A3C0
ALL | SET | CLR ALL | SET | CLR
ALL
ALL | SET | CLR | MASK Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Reserved
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Reserved
Reserved
Reserved
PBPDEN
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Reserved
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PBMDSEL
PBPIN
PB
PBNDEN
Bit 2
Bit 1
Bit 0
Port I/O Configuration
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
140
Rev. 1.0
PBHD4_PBLOCK PBHD4_PBSS PBHD4_PBFSEL PBHD4_PBILIMIT PBHD4_PBDRV Register Name
0x4002_A430
0x4002_A410
0x4002_A400
ALL Address
0x4002_A440
0x4002_A450
ALL
ALL | SET | CLR ALL | SET | CLR Access Methods
ALL | SET | CLR
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Reserved
Reserved
Bit 27
Bit 26
Bit 25
Reserved
Bit 24
PBVTRKEN
Bit 23
Reserved
PBDRVEN
Bit 22
PILIMIT
PBBIASEN
Bit 21
Reserved
Bit 20
Bit 19
Reserved
PBSLEW
Bit 18
NILIMIT
PBSSSMD
PBLVMD
Bit 17
SSMDEN
PBPUEN
Bit 16
Bit 15
Bit 14
Reserved
Bit 13
Bit 12
PB5SEL
Bit 11
Reserved
Reserved
PB5SSSEL
Bit 10
Bit 9
PB4SEL
PB4SSSEL
Bit 8
Bit 7
PB3SEL
PB3SSSEL
Bit 6
Bit 5
PB2SEL
PB2SSSEL
Bit 4
Bit 3
PBLOCK
PBILEN
PBDRV
PB1SEL
PB1SSSEL
Bit 2
Bit 1
PB0SEL
PB0SSSEL
Bit 0
Table 8.40. PBHD4 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
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Power
SiM3U1xx/SiM3C1xx
9. Power
This section describes the power modes and Power Management Unit of SiM3U1xx/SiM3C1xx devices.
9.1. Power Modes
The SiM3U1xx/SiM3C1xx devices have the power modes defined in Table 9.1.
Table 9.1. SiM3U1xx/SiM3C1xx Power Modes
Mode
Normal
Power Mode 1
(PM1)
Description
Mode Entrance
Mode Exit
Core operating at full speed
 Code executing from flash
—
—
—
—
WFI or WFE instruction
NVIC or WIC wakeup




Power Mode 2
(PM2)

Core operating at full speed
Code executing from RAM
Core halted
AHB and APB clocks on
selectively to support
peripherals

Power Mode 3
(PM3)
Core halted
 DMACTRL0 AHB clock
disabled
 All AHB and APB clocks off
 All APB clocks disabled
 PMSEL bit in
RSTSRC0_CONTROL
must be cleared to 0
 WFI or WFE instruction
Reset event, or
RTC0ALRM, RTC0FAIL,
LPTIMER0, VDDLOW or
VREGLOW interrupt

Power Mode 9
(PM9)
Low power shutdown
SLEEPDEEP set in the
ARM System Control
Register
 PMSEL bit in
RSTSRC0_CONTROL
must be set to 1
 WFI or WFE instruction
Requires a reset defined by
the PMU as a wake up
source
In addition to the power modes described in Table 9.1, all peripherals can have their clocks disconnected in the
Clock Control module (CLKCTRL) to reduce power consumption whenever a peripheral is not being used.
9.1.1. Normal Mode (Power Mode 0)
Normal Mode is the default mode of the device. The core and peripherals are fully operational, and instructions are
executed from flash memory.
9.1.2. Power Mode 1
In Power Mode 1 the core and peripherals are fully operational, with instructions executing from RAM. Compared
with Normal Mode, the active power consumption of the device in PM1 is reduced. Additionally, at higher speeds in
PM1, the core throughput can also be increased because RAM does not require additional wait states that reduce
the instruction fetch speed.
142
Rev. 1.0
9.1.3. Power Mode 2
In Power Mode 2 the core halts and any enabled peripherals continue to run at the selected clock speed. The
power consumption in PM2 corresponds to the AHB and APB clocks left enabled, thus the power can be tuned to
the optimal level for the needs of the application. To place the device in PM2, the core should execute a wait-forinterrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine,
the interrupt that wakes the device from PM2 must be of a sufficient priority to be recognized by the core. It is
recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization
Barrier) operation prior to the WFI to ensure all bus accesses complete. When operating from the LFOSC0 with the
DMACTRL0 AHB clock disabled, PM2 can achieve similar power consumption to PM3, but with the ability to wake
on APB-clocked interrupts. For example, enabling only the APB clock to the Ports will allow the firmware to wake
on a PMATCH0, PBEXT0 or PBEXT1 interrupt with minimal impact on the supply current.
9.1.4. Power Mode 3
In Power Mode 3, the AHB and APB clocks are halted. The device may only wake from enabled interrupt sources
which do not require the APB clock (RTC0ALRM, RTC0FAIL, LPTIMER0, VDDLOW and VREGLOW). A special
fast wake option allows the device to operate at a very low level from the RTC0TCLK or LFOSC0 oscillator while in
PM3, but quickly switch to the faster LPOSC0 when the wake event occurs. Because the current consumption of
these blocks is minimal, it is recommended to use the fast wake option.
Before entering PM3, the desired wake source interrupt(s) should be configured, and the AHB clock to the DMA
controller and all APB clocks should be disabled. The PMSEL bit in the RSTSRC0_CONFIG register must be
cleared to indicate that PM3 is the desired power mode. For fast wake, the core clocks (AHB and APB) should be
configured to run from the LPOSC, and the PM3 Fast wake option and PM3 clock source should be selected in the
PM3CN register.
The device will enter PM3 on a WFI or WFE instruction. Because all AHB master clocks are disabled, the LPOSC
will automatically halt and go into a low-power suspended state. If the WFI instruction is called from an interrupt
service routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the
core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete.
9.1.5. Power Mode 9
In Power Mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are
set to a lower power mode. In addition, standard RAM contents are not preserved, though retention RAM contents
are still available after exiting the power mode. This mode provides the lowest power consumption for the device,
but requires an appropriate reset to exit. The available reset sources to wake from PM9 are controlled by the
Power Management Unit (PMU).
Before entering PM9, the desired reset source(s) should be configured in the PMU. The SLEEPDEEP bit in the
ARM System Control Register should be set, and the PMSEL bit in the RSTSRC0_CONFIG register must be set to
indicate that PM9 is the desired power mode.
The device will enter PM9 on a WFI or WFE instruction, and remain in PM9 until a reset configured by the PMU
occurs. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete. More information on the
wake up sources and wake up procedure can be found in Section 9.2.
Rev. 1.0
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Power
SiM3U1xx/SiM3C1xx
9.2. Power Management Unit (PMU0)
This section describes the Power Management Unit (PMU) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the PMU block, which is used by all device families covered in this document.
The PMU module includes the following features:
Up
to 16 pin wake inputs can wake the PMU from Power Mode 9.
Low Power Timer, RTC0 (alarms and oscillator fail), Comparator 0, and the RESET pin can also serve
as wake sources for Power Mode 9.
All PM9 wake sources (except for the RESET pin) can also reset the Low Power Timer or RTC0 modules.
Disables the level shifters to pins and peripherals to further reduce power usage in PM9. These level
shifters must be re-enabled by firmware after exiting PM9.
Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM9.
The
PMU Module
WAKE.0
WAKE.1
WAKE.2
WAKE.3
Pin Wake Mask
and Level Select
Power Mode 9
Disable/Enable
Pins and
Peripherals
Pin Wake
WAKE.15
RTC0
Module Reset
LPTIMER0
Low Power Timer
Comparator 0
RTC0 Alarm 0
Power Mode 9
Wake
to core
RTC0 Alarm 1
RTC0 Alarm 2
RTC0 Fail
Power Mode 9
Status
PMU_Asleep
Reset Pin (RESET)
Figure 9.1. PMU Block Diagram
The PMU manages the power-up sequence on power on and the wake up sources from PM9. On power-up, the
PMU ensures the core voltages are of a proper value before core instruction execution begins.
144
Rev. 1.0
9.2.1. Waking from Power Mode 9
The reset wake for PM9 can be sourced from pins (Pin Wake), the Low Power Timer, Comparator 0, RTC0 Alarms
(0, 1, or 2), RTC0 Fail, or the Reset Pin (RESET). In most cases, the corresponding interrupt enable must be set in
the module in order for an event to be a wakeup source. The Comparator module is the exception and the wakeup
event will occur even if the interrupt is disabled. These wakeup sources (except for the reset pin) can also be
optionally used to reset RTC0 or the Low Power Timer while the device remains in PM9.
Firmware can check the PM9EF bit during the initialization sequence to determine if the device reset because of a
wake from Power Mode 9. If the device did reset because of a wake from PM9, firmware must clear the bits
keeping the peripheral and pin interfaces in a lower power state (PERILPEN and PINLPEN), and the
WAKESTATUS register provides status flags to indicate the wakeup source. The WAKESTATUS register can be
cleared by writing 0 to the WAKECLR bit.
9.2.2. Pin Wake
Up to 16 pins are available as Pin Wake sources (WAKE.0-WAKE.15). any one of these signals can be used to
wake the device from low power sleep modes. The pin wake function can be enabled for a pin by setting the
corresponding bit in the PWEN register. The desired polarity of the pin to wake the device should be programmed
into the corresponding bit in the PWPOL register. Note that if multiple pins are selected as wake sources using
PWEN, the polarity of all of the selected pins must match PWPOL in order to wake the device. To serve as a wake
source, the pins must remain active in the matching state long enough for the PMU to detect the wake up signal
(50ns). The pin wake trigger sources vary by package and are shown in Table 9.2.
Table 9.2. Pin Wake Sources
Pin Wake
Source
Trigger Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
WAKE.0
Low Power Wake Pin
PB1.13
PB1.6
PB0.12
WAKE.1
Low Power Wake Pin
PB1.14
PB1.7
PB0.13
WAKE.2
Low Power Wake Pin
PB1.15
PB1.8
PB0.14
WAKE.3
Low Power Wake Pin
PB2.0
PB1.9
PB0.15
WAKE.4
Low Power Wake Pin
PB2.1
PB1.10
PB1.0
WAKE.5
Low Power Wake Pin
PB2.2
PB1.11
PB1.1
WAKE.6
Low Power Wake Pin
PB2.3
PB1.12
Reserved
WAKE.7
Low Power Wake Pin
PB2.4
Reserved
Reserved
WAKE.8
Low Power Wake Pin
PB3.4
PB3.2
Reserved
WAKE.9
Low Power Wake Pin
PB3.5
PB3.3
Reserved
WAKE.10
Low Power Wake Pin
PB3.6
PB3.4
Reserved
WAKE.11
Low Power Wake Pin
PB3.7
PB3.5
Reserved
WAKE.12
Low Power Wake Pin
PB3.8
PB3.6
PB3.0
Rev. 1.0
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SiM3U1xx/SiM3C1xx
Table 9.2. Pin Wake Sources
Pin Wake
Source
Trigger Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
WAKE.13
Low Power Wake Pin
PB3.9
PB3.7
PB3.1
WAKE.14
Low Power Wake Pin
PB3.10
PB3.8
PB3.2
WAKE.15
Low Power Wake Pin
PB3.11
PB3.9
PB3.3
9.2.3. Low Power Timer
The Low Power Timer wake up source is caused by a Low Power Timer overflow.
9.2.4. Comparator 0
A Comparator 0 (CMP0) event can serve as a wake up or reset source in the PMU. This event can occur from a
rising, falling, or either edge on the Comparator 0 output, depending on the settings in the Comparator module.
9.2.5. RTC0
The RTC0 Alarms (0, 1, and 2) and Fail events are wake up sources from PM9 or can automatically reset the
LPTIMER0 and RTC0 modules. The Alarms occur from a match between the RTC0 timer and the corresponding
Alarm compare value. The Fail event occurs when the RTC0 missing clock detector indicates the RTC0 clock is no
longer running.
146
Rev. 1.0
9.3. PMU0 Registers
This section contains the detailed register descriptions for PMU0 registers.
Register 9.1. PMU0_CONTROL: Module Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
WAKECLR
0
PERILPEN
0
PINLPEN
0
PWAKEEN
0
PMUASLPEN
Reset
Type
R
RW
RW
RW
RW
W
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PMU0_CONTROL = 0x4004_8000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.3. PMU0_CONTROL Register Bit Descriptions
Bit
Name
31:5
Reserved
4
PMUASLPEN
Function
Must write reset value.
PMU Asleep Pin Enable.
When set to 1, the PMU Asleep signal will be sent to the appropriate pin. This pin
should be skipped by the Crossbar if firmware enables the PMU Asleep signal.
3
PWAKEEN
Pin Wake Match Enable.
0: Disable Pin Wake.
1: Enable Pin Wake.
2
PINLPEN
Pin Low Power Enable.
When this bit is set, the PMU will place the pin interfaces in a low power state before
entering Power Mode 9. After exiting PM9, firmware must clear this bit to resume
normal operation of the pins.
1
PERILPEN
Peripheral Low Power Enable.
When this bit is set, the PMU will place the peripheral interfaces in a low power state
before entering Power Mode 9. After exiting PM9, firmware must clear this bit to
resume normal operation of the peripherals.
0
WAKECLR
Wakeup Source Clear.
Writing a 0 to this bit clears all wakeup sources.
0: Clear all wakeup sources.
1: Reserved.
Rev. 1.0
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SiM3U1xx/SiM3C1xx
Register 9.2. PMU0_CONFIG: Module Configuration
Bit
31
30
29
28
27
26
25
24
23
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
RTC0FREN
R
19
RTC0AREN
Type
20
CMP0REN
Reserved
21
PWAKEREN
Name
22
LPT0REN
Power
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
1
0
0
0
0
0
Reserved
R
0
0
RW
0
0
0
0
Register ALL Access Address
PMU0_CONFIG = 0x4004_8010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.4. PMU0_CONFIG Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
LPT0REN
Low Power Timer RTC0/LPTIMER0 Reset Enable.
When set to 1, an LPTIMER0 event will cause the RTC0 and LPTIMER0 modules to
reset.
14
PWAKEREN
Pin Wake RTC0/LPTIMER0 Reset Enable.
When set to 1, a Pin Wake event will cause the RTC0 and LPTIMER0 modules to
reset.
13
CMP0REN
Comparator 0 RTC0/LPTIMER0 Reset Enable.
When set to 1, a Comparator 0 event will cause the RTC0 and LPTIMER0 modules
to reset.
12:10
Reserved
9
RTC0AREN
Must write reset value.
RTC0 Alarm RTC0/LPTIMER0 Reset Enable.
When set to 1, an RTC0 alarm event will cause the RTC0 and LPTIMER0 modules
to reset. This alarm event can occur from any of the three RTC0 alarms.
8
RTC0FREN
RTC0 Fail RTC0/LPTIMER0 Reset Enable.
When set to 1, an RTC0 fail event will cause the RTC0 and LPTIMER0 modules to
reset.
7:0
148
Reserved
Must write reset value.
Rev. 1.0
Register 9.3. PMU0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
PM9EF
0
PWAKEF
0
PORF
Reset
Type
R
RW
R
RW
1
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PMU0_STATUS = 0x4004_8020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.5. PMU0_STATUS Register Bit Descriptions
Bit
Name
Function
31:3
Reserved
Must write reset value.
2
PORF
Power-On Reset Flag.
Hardware sets this bit to 1 to indicate that a power-on reset event occurred. This bit
must be cleared by firmware.
1
PWAKEF
Pin Wake Status Flag.
When cleared to 0, this flag indicates that a pin wake event has occured.
0
PM9EF
Power Mode 9 Exited Flag.
When set to 1, this flag indicates that the device exited Power Mode 9. Firmware
must clear this flag.
Rev. 1.0
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SiM3U1xx/SiM3C1xx
Register 9.4. PMU0_WAKEEN: Wake Source Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
RW
RW
RW
1
0
0
0
Reset
0
0
0
0
0
0
0
RTC0FWEN
Type
Reserved
RTC0AWEN
Reserved
CMP0WEN
Name
PWAKEWEN
0
LPT0WEN
Reset
RSTWEN
Power
SiM3U1xx/SiM3C1xx
RW
RW
RW
RW
0
0
0
0
0
Register ALL Access Address
PMU0_WAKEEN = 0x4004_8030
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.6. PMU0_WAKEEN Register Bit Descriptions
Bit
Name
Function
31:9
Reserved
Must write reset value.
8
RSTWEN
Reset Pin Wake Enable.
When set to 1, a RESET Pin event will wake the device from Power Mode 9.
7
LPT0WEN
Low Power Timer Wake Enable.
When set to 1, an LPTIMER0 event will wake the device from Power Mode 9.
6
PWAKEWEN
Pin Wake Wake Enable.
When set to 1, a Pin Wake event will wake the device from Power Mode 9.
5
CMP0WEN
Comparator 0 Wake Enable.
When set to 1, a Comparator 0 event will wake the device from Power Mode 9.
4:2
Reserved
1
RTC0AWEN
Must write reset value.
RTC0 Alarm Wake Enable.
When set to 1, an RTC0 alarm event will wake the device from Power Mode 9. This
alarm event can occur from any of the three RTC0 alarms.
0
RTC0FWEN
RTC0 Fail Wake Enable.
When set to 1, an RTC0 fail event will wake the device from Power Mode 9.
150
Rev. 1.0
Register 9.5. PMU0_WAKESTATUS: Wake Source Status
Bit
31
30
29
28
27
26
25
24
23
Type
R
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
X
X
Name
Reserved
CMP0WF
0
PWAKEWF
0
LPT0WF
0
RSTWF
Reset
RTC0FWF
Reserved
21
RTC0AWF
Name
22
Reserved
Type
R
R
R
R
R
R
X
X
X
0
Reset
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PMU0_WAKESTATUS = 0x4004_8040
Table 9.7. PMU0_WAKESTATUS Register Bit Descriptions
Bit
Name
Function
31:9
Reserved
Must write reset value.
8
RSTWF
Reset Pin Wake Flag.
When set to 1, this flag indicates that the RESET pin woke the device. Firmware
must clear this flag.
7
LPT0WF
Low Power Timer Wake Flag.
When set to 1, this flag indicates that a LPTIMER0 event woke the device. Firmware
must clear this flag.
6
PWAKEWF
Pin Wake Wake Flag.
When set to 1, this flag indicates that a Pin Wake event woke the device. Firmware
must clear this flag.
5
CMP0WF
Comparator 0 Wake Flag.
When set to 1, this flag indicates that a Comparator 0 event woke the device. Firmware must clear this flag.
4:2
Reserved
Must write reset value.
1
RTC0AWF
RTC0 Alarm Wake Flag.
When set to 1, this flag indicates that an RTC0 alarm event woke the device. This
alarm event can occur from any of the three RTC0 alarms. Firmware must clear this
flag.
0
RTC0FWF
RTC0 Fail Wake Flag.
When set to 1, this flag indicates that an RTC0 fail event woke the device. Firmware
must clear this flag.
Rev. 1.0
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SiM3U1xx/SiM3C1xx
Register 9.6. PMU0_PWEN: Pin Wake Pin Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PW0EN
0
PW1EN
0
PW2EN
0
PW3EN
0
PW4EN
0
PW5EN
0
PW6EN
0
PW7EN
0
PW8EN
0
PW9EN
0
PW10EN
0
PW11EN
0
PW12EN
0
PW13EN
0
PW14EN
Reset
PW15EN
Power
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PMU0_PWEN = 0x4004_8050
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.8. PMU0_PWEN Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
PW15EN
WAKE.15 Enable.
When set to 1, this bit enables the WAKE.15 signal to wake the device.
14
PW14EN
WAKE.14 Enable.
When set to 1, this bit enables the WAKE.14 signal to wake the device.
13
PW13EN
WAKE.13 Enable.
When set to 1, this bit enables the WAKE.13 signal to wake the device.
12
PW12EN
WAKE.12 Enable.
When set to 1, this bit enables the WAKE.12 signal to wake the device.
11
PW11EN
WAKE.11 Enable.
When set to 1, this bit enables the WAKE.11 signal to wake the device.
10
PW10EN
WAKE.10 Enable.
When set to 1, this bit enables the WAKE.10 signal to wake the device.
9
PW9EN
WAKE.9 Enable.
When set to 1, this bit enables the WAKE.9 signal to wake the device.
8
PW8EN
WAKE.8 Enable.
When set to 1, this bit enables the WAKE.8 signal to wake the device.
7
PW7EN
WAKE.7 Enable.
When set to 1, this bit enables the WAKE.7 signal to wake the device.
152
Rev. 1.0
Table 9.8. PMU0_PWEN Register Bit Descriptions
Bit
Name
6
PW6EN
Function
WAKE.6 Enable.
When set to 1, this bit enables the WAKE.6 signal to wake the device.
5
PW5EN
WAKE.5 Enable.
When set to 1, this bit enables the WAKE.5 signal to wake the device.
4
PW4EN
WAKE.4 Enable.
When set to 1, this bit enables the WAKE.4 signal to wake the device.
3
PW3EN
WAKE.3 Enable.
When set to 1, this bit enables the WAKE.3 signal to wake the device.
2
PW2EN
WAKE.2 Enable.
When set to 1, this bit enables the WAKE.2 signal to wake the device.
1
PW1EN
WAKE.1 Enable.
When set to 1, this bit enables the WAKE.1 signal to wake the device.
0
PW0EN
WAKE.0 Enable.
When set to 1, this bit enables the WAKE.0 signal to wake the device.
Rev. 1.0
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SiM3U1xx/SiM3C1xx
Register 9.7. PMU0_PWPOL: Pin Wake Pin Polarity Select
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PW0POL
0
PW1POL
0
PW2POL
0
PW3POL
0
PW4POL
0
PW5POL
0
PW6POL
0
PW7POL
0
PW8POL
0
PW9POL
0
PW10POL
0
PW11POL
0
PW12POL
0
PW13POL
0
PW14POL
Reset
PW15POL
Power
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PMU0_PWPOL = 0x4004_8060
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 9.9. PMU0_PWPOL Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
PW15POL
WAKE.15 Polarity Select.
If PW15EN is set, this bit selects the logic level of WAKE.15 that will be used in the
wake comparison.
14
PW14POL
WAKE.14 Polarity Select.
If PW14EN is set, this bit selects the logic level of WAKE.14 that will be used in the
wake comparison.
13
PW13POL
WAKE.13 Polarity Select.
If PW13EN is set, this bit selects the logic level of WAKE.13 that will be used in the
wake comparison.
12
PW12POL
WAKE.12 Polarity Select.
If PW12EN is set, this bit selects the logic level of WAKE.12 that will be used in the
wake comparison.
11
PW11POL
WAKE.11 Polarity Select.
If PW11EN is set, this bit selects the logic level of WAKE.11 that will be used in the
wake comparison.
10
PW10POL
WAKE.10 Polarity Select.
If PW10EN is set, this bit selects the logic level of WAKE.10 that will be used in the
wake comparison.
154
Rev. 1.0
Table 9.9. PMU0_PWPOL Register Bit Descriptions
Bit
Name
9
PW9POL
Function
WAKE.9 Polarity Select.
If PW9EN is set, this bit selects the logic level of WAKE.9 that will be used in the
wake comparison.
8
PW8POL
WAKE.8 Polarity Select.
If PW8EN is set, this bit selects the logic level of WAKE.8 that will be used in the
wake comparison.
7
PW7POL
WAKE.7 Polarity Select.
If PW7EN is set, this bit selects the logic level of WAKE.7 that will be used in the
wake comparison.
6
PW6POL
WAKE.6 Polarity Select.
If PW6EN is set, this bit selects the logic level of WAKE.6 that will be used in the
wake comparison.
5
PW5POL
WAKE.5 Polarity Select.
If PW5EN is set, this bit selects the logic level of WAKE.5 that will be used in the
wake comparison.
4
PW4POL
WAKE.4 Polarity Select.
If PW4EN is set, this bit selects the logic level of WAKE.4 that will be used in the
wake comparison.
3
PW3POL
WAKE.3 Polarity Select.
If PW3EN is set, this bit selects the logic level of WAKE.3 that will be used in the
wake comparison.
2
PW2POL
WAKE.2 Polarity Select.
If PW2EN is set, this bit selects the logic level of WAKE.2 that will be used in the
wake comparison.
1
PW1POL
WAKE.1 Polarity Select.
If PW1EN is set, this bit selects the logic level of WAKE.1 that will be used in the
wake comparison.
0
PW0POL
WAKE.0 Polarity Select.
If PW0EN is set, this bit selects the logic level of WAKE.0 that will be used in the
wake comparison.
Rev. 1.0
155
Power
SiM3U1xx/SiM3C1xx
PMU0_WAKEEN PMU0_STATUS PMU0_CONFIG PMU0_CONTROL Register Name
0x4004_8020
ALL Address
0x4004_8030
0x4004_8010
0x4004_8000
ALL | SET | CLR ALL | SET | CLR ALL | SET | CLR ALL | SET | CLR Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Bit 23
Bit 22
Bit 21
Reserved
Bit 20
Bit 19
Reserved
Bit 18
Reserved
Bit 17
Bit 16
LPT0REN
Bit 15
PWAKEREN
Bit 14
CMP0REN
Bit 13
Bit 12
Reserved
Bit 11
Bit 10
RTC0AREN
Bit 9
RSTWEN
RTC0FREN
Bit 8
LPT0WEN
Bit 7
PWAKEWEN
Bit 6
CMP0WEN
Bit 5
PMUASLPEN
Bit 4
Reserved
Reserved
PWAKEEN
Bit 3
PORF
PINLPEN
Bit 2
RTC0AWEN
PWAKEF
PERILPEN
Bit 1
RTC0FWEN
PM9EF
WAKECLR
Bit 0
Power
SiM3U1xx/SiM3C1xx
9.4. PMU0 Register Memory Map
Table 9.10. PMU0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
156
Rev. 1.0
PMU0_PWEN PMU0_WAKESTATUS Register Name
PMU0_PWPOL
0x4004_8050
0x4004_8040
ALL Address
0x4004_8060
ALL
Access Methods
ALL | SET | CLR ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Reserved
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
PW15POL
PW15EN
Bit 15
PW14POL
PW14EN
Bit 14
PW13POL
PW13EN
Bit 13
PW12POL
PW12EN
Bit 12
PW11POL
PW11EN
Bit 11
PW10POL
PW10EN
Bit 10
PW9POL
PW9EN
Bit 9
RSTWF
PW8POL
PW8EN
Bit 8
LPT0WF
PW7POL
PW7EN
Bit 7
PWAKEWF
PW6POL
PW6EN
Bit 6
CMP0WF
PW5POL
PW5EN
Bit 5
PW4POL
PW4EN
Bit 4
Reserved
PW3POL
PW3EN
Bit 3
PW2POL
PW2EN
Bit 2
RTC0AWF
PW1POL
PW1EN
Bit 1
RTC0FWF
PW0POL
PW0EN
Bit 0
Table 9.10. PMU0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
157
Power
SiM3U1xx/SiM3C1xx
Core Voltage Regulator (LDO0)
SiM3U1xx/SiM3C1xx
10. Core Voltage Regulator (LDO0)
This section describes the core voltage regulator (LDO) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
10.1. Core Voltage Regulator Features
The core voltage regulator includes the following features:
Regulates
internal supply for core, memory and peripherals.
Two bias settings for power savings during low-frequency operation (AHB Clock < 2.5 MHz).
LDO Module
VDD
Bias Power
Selection
LDO Regulator
To Core,
Memory and
Peripherals
VSS
Figure 10.1. Core Regulator Block Diagram
158
Rev. 1.0
10.2. Functional Description
The core voltage regulator consists of an LDO regulator with a programmable bias current setting. It is powered
from the device VDD and VSS supply pins. By default, the core voltage regulator starts up in the high bias setting,
allowing the device to quickly come out of reset and begin executing firmware. If the frequency of the AHB clock
used in the application is less than or equal to 2.5 MHz, the LDOIBIAS bit in the CONTROL register can be set to 1
for additional power savings. LDOIBIAS should always be cleared to 0 when operating the AHB clock above
2.5 MHz.
Rev. 1.0
159
Core Voltage Regulator (LDO0)
SiM3U1xx/SiM3C1xx
10.3. LDO0 Registers
This section contains the detailed register descriptions for LDO0 registers.
Register 10.1. LDO0_CONTROL: Control
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
Type
RW
R
Reset
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
31
LDOIBIAS
Bit
LDOAEN
Core Voltage Regulator (LDO0)
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LDO0_CONTROL = 0x4003_9000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 10.1. LDO0_CONTROL Register Bit Descriptions
Bit
Name
31
LDOAEN
Function
LDO Analog Enable.
This bit enables/disables an output from the LDO to the VREF0, LPOSC0,
USBOSC and PLLOSC0 blocks. It must be set to 1 when any of these functions is
enabled. Clearing this bit to 0 when not using the affected circuits will reduce the
current consumption of the device by approximately 15 A.
0: LDO0 analog output disabled.
1: LDO0 analog output enabled.
30:2
Reserved
Must write reset value.
1
LDOIBIAS
LDO Bias Current Selection.
Selects between two bias levels for the internal LDO regulator.
0: Select high bias.
1: Select low bias (AHB frequency < 2.5 MHz).
0
160
Reserved
Must write reset value.
Rev. 1.0
10.4. LDO0 Register Memory Map
LDO0_CONTROL Register Name
ALL Address
0x4003_9000
ALL | SET | CLR Access Methods
Bit 31
LDOAEN
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LDOIBIAS
Bit 1
Reserved
Bit 0
Table 10.2. LDO0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
161
Core Voltage Regulator (LDO0)
SiM3U1xx/SiM3C1xx
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
11. Device Identification (DEVICEID0) and Universally Unique Identifier
This section describes the Device Identification (DEVICEID) registers and the pre-programmed Unique Identifier,
and is applicable to all products in the following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
11.1. Device ID Features
In full production devices, the Device ID module consists of four static registers which include the following device
identification information:
Silicon
Laboratories part number
Package identification
Silicon revision
Custom device ID
Note: For pre-production and early engineering devices, the registers associated with the DEVICEID module
contained a 124-bit unique number, as well as the 4-bit REVID field to indicate the silicon revision. The full 128-bit
unique identifier is still available in all versions of silicon. See “11.2. Universally Unique Identifier (UUID)” for more
details.
11.1.1. Device Identification Encoding
The device identification information is encoded into the DEVICEID0-DEVICEID3 registers. DEVICEID0 contains
revision and packaging information. DEVICEID2 and DEVICEID1 contain the part number string, excluding the
revision, packaging and “Si” prefix information. DEVICEID3 is set to all zeros for standard-catalog products, and a
unique product number for custom-numbered products. FIGURE details the DEVICEID register encoding for an
example product (SiM3U167-B-GQ).
DEVICEID3
0x00
0x00
0x00
DEVICEID2
0x00
Custom product number.
Standard catalog product is
number 0x00000000.
0x00
0x00
0x4D
(M)
DEVICEID1
0x33
(3)
0x55
(U)
0x31
(1)
DEVICEID0
0x36
(6)
0x37
(7)
Right-justified, ASCII-encoded part number. Unused
characters are 0x00.
0x51
(Q)
0x00
0x00
0x01
Revision identification.
A = 0, B = 1, etc.
Left-justified, ASCII-encoded package
characters. Unused characters are 0x00.
Example: SiM3U167-B-GQ
Figure 11.1. Example DEVICEID encoding for part number SiM3U167-B-GQ
11.2. Universally Unique Identifier (UUID)
A128-bit universally unique identifier (UUID) is pre-programmed into all devices. The UUID resides in an area of
flash memory which cannot be erased or written in the end application. The UUID can be read by firmware or
through the debug port at addresses 0x00040380 through 0x00040383.
162
Rev. 1.0
11.3. DEVICEID0 Registers
This section contains the detailed register descriptions for DEVICEID0 registers.
Register 11.1. DEVICEID0_DEVICEID0: Device ID Word 0
Bit
31
30
29
28
27
26
25
24
23
Name
PACKID[23:8]
Type
RW
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PACKID[7:0]
Reserved
REVID
Type
RW
RW
RW
Reset
X
X
X
X
X
X
X
X
0
0
0
0
X
X
X
X
Register ALL Access Address
DEVICEID0_DEVICEID0 = 0x4004_90C0
Table 11.1. DEVICEID0_DEVICEID0 Register Bit Descriptions
Bit
Name
31:8
PACKID
Function
Package ID.
This field describes the device package. For standard catalog products, the most
significant byte contains the package type letter encoded in ASCII. The unused
bytes are encoded as 0x00.
7:4
Reserved
3:0
REVID
Must write reset value.
Revision ID.
This field provides the revision information for the device.
0000: Revision A.
0001: Revision B.
0010-1111: Reserved.
Rev. 1.0
163
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Register 11.2. DEVICEID0_DEVICEID1: Device ID Word 1
Bit
31
30
29
28
27
26
25
24
23
22
Name
DEVICEID1[31:16]
Type
RW
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
DEVICEID1[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
DEVICEID0_DEVICEID1 = 0x4004_90D0
Table 11.2. DEVICEID0_DEVICEID1 Register Bit Descriptions
Bit
Name
31:0
DEVICEID1
Function
Device ID 1.
The DEVICEID1 and DEVICEID2 registers contain the ASCII-encoded part number
for the silicon, excluding the prefix "Si". The part number is right-justified within the
two registers, and any unused characters are set to 0x00.
164
Rev. 1.0
Register 11.3. DEVICEID0_DEVICEID2: Device ID Word 2
Bit
31
30
29
28
27
26
25
24
23
22
Name
DEVICEID2[31:16]
Type
RW
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
DEVICEID2[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
DEVICEID0_DEVICEID2 = 0x4004_90E0
Table 11.3. DEVICEID0_DEVICEID2 Register Bit Descriptions
Bit
Name
31:0
DEVICEID2
Function
Device ID 2.
The DEVICEID1 and DEVICEID2 registers contain the ASCII-encoded part number
for the silicon, excluding the prefix "Si". The part number is right-justified within the
two registers, and any unused characters are set to 0x00.
Rev. 1.0
165
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Register 11.4. DEVICEID0_DEVICEID3: Device ID Word 3
Bit
31
30
29
28
27
26
25
24
23
22
Name
DEVICEID3[31:16]
Type
RW
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
DEVICEID3[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
DEVICEID0_DEVICEID3 = 0x4004_90F0
Table 11.4. DEVICEID0_DEVICEID3 Register Bit Descriptions
Bit
Name
31:0
DEVICEID3
Function
Device ID 3.
For standard products the DEVICEID3 register will read back all 0's. For customprogrammed MCUs, this register may contain the number assigned to the custom
product.
166
Rev. 1.0
11.4. DEVICEID0 Register Memory Map
DEVICEID0_DEVICEID1 DEVICEID0_DEVICEID0 Register Name
0x4004_90D0
ALL Address
0x4004_90C0
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
PACKID
Bit 19
Bit 18
Bit 17
Bit 16
DEVICEID1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
REVID
Bit 1
Bit 0
Table 11.5. DEVICEID0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
167
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Table 11.5. DEVICEID0 Memory Map
DEVICEID0_DEVICEID3 DEVICEID0_DEVICEID2 Register Name
0x4004_90F0
0x4004_90E0
ALL Address
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
DEVICEID3
DEVICEID2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device Identification (DEVICEID0) and Universally Unique Identifier
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
168
Rev. 1.0
12. Advanced Encryption Standard (AES0)
This section describes the Advanced Encryption Standard (AES) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the AES block, which is used by all device families covered in this document.
12.1. AES Features
The AES module includes the following features:
Operates
on 4-word (16-byte) blocks.
key sizes of 128, 192, and 256 bits for both encryption and decryption.
Generates the round key for decryption operations.
All cipher operations can be performed without any firmware intervention for a set of 4-word blocks (up to
32 kB).
Support for various chained and stream-ciphering configurations with XOR paths on both the input and
output.
Internal 4-word FIFOs to facilitate DMA operations.
Integrated key storage.
Hardware acceleration for Cipher-Block Chaining (CBC) and Counter (CTR) algorithms utilizing integrated
counter-block generation and previous-block caching.
Supports
AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
XORFIFO
Keystore
Figure 12.1. AES0 Block Diagram
Rev. 1.0
169
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
12.2. Overview
The AES block cipher is a symmetric key encryption algorithm. Symmetric key encryption relies on secret keys that
are known by both the sender and receiver. The decryption key may be obtained using a simple transformation of
the encryption key. AES is not a public key encryption algorithm.
The AES block cipher uses a fixed 4-word (16-byte) block size. Data segments less than 4 words in length must be
padded with zeros to fill the entire block.
Since symmetric key encryption relies on secret keys, the security of the data can only be protected if the key
remains secret. If the encryption key is stored in flash memory, then the entire flash should be locked to ensure the
encryption key cannot be discovered.
The hardware counter in the AES0 module can be programmed with an initial value using the HWCTR register.
Similarly, the hardware keystore can be programmed with an initial value using the HWKEY register.
The basic AES block cipher is implemented in hardware. The integrated hardware acceleration for cipher block
chaining (CBC) and counter (CTR) algorithms results in identical performance, memory bandwidth, and memory
footprint between the most basic electronic codebook (ECB) algorithm and these more complex algorithms. This
hardware accelerator provides performance that is much faster than a software implementation, which translates to
more bandwidth available for other functions or a power savings for low-power applications.
12.2.1. Enabling the AES0 Module
Immediately following any device reset, the RESET bit is set to 1 to save power. All register bits except RESET are
reset using the combined device reset and the RESET bit. To use the AES0 module, firmware must first clear the
RESET bit before initializing the registers.
12.3. Interrupts
The AES0 interrupt flags are located in the STATUS register. The associated interrupt enable bits are located in the
CONTROL register. An AES0 completion interrupt can be generated if OCIEN is set to 1 whenever an encryption
or decryption operation is complete. An AES0 error interrupt can be generated whenever an input/output data FIFO
overrun (DORF = 1) or underrun (DURF = 1) error occurs, or when an XOR data FIFO overrun (XORF = 1) occurs.
The completion interrupt should only be used in conjunction with software mode (SWMDEN bit is set to 1) and not
with DMA operations, where the DMA completion interrupt should be used. The error interrupt should always be
enabled (ERRIEN = 1), even when using the DMA with the AES module.
12.4. Debug Mode
Firmware can clear the DBGMD bit to force the AES0 module to halt on a debug breakpoint. Setting the DBGMD
bit forces the module to continue operating while the core halts in debug mode.
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12.5. DMA Configuration and Usage
A DMA channel may be used to transfer data for the input/output data FIFO or the XOR data FIFO. The AES
module FIFOs only support word reads and writes. Each DMA transfer must consist of 4 words (16 bytes). To write
to the input/output data FIFO, the DMA must move data from the source location in memory to the internal
DATAFIFO register in non-incrementing mode. To read from the input/output data FIFO, the DMA must move data
from the internal DATAFIFO register in non-incrementing mode to the destination location in memory. For the XOR
data FIFO, the DMA must move data from the source location in memory to the internal XORFIFO register in nonincrementing mode. Firmware should only directly access the DATAFIFO and XORFIFO registers in software mode
(SWMDEN bit is set to 1). AES0 FIFOs targeted by the DMA module should not be directly written to or read from.
SiM3xxxx
Address Space
DMA Module
AESn Output Data
AESn Module
Data FIFO
DMA Channel
DATAFIFO
XOR
AESn Input Data
DMA Channel
Hardware Counter
CBC Block Cache
AESn XOR Data
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
DMA Channel
XORFIFO
Keystore
Figure 12.2. AES DMA Configuration
12.5.1. DMA and Interrupts
If a DMA channel is enabled for one of the FIFOs, the AES operation complete and error interrupts will not be
suppressed. In software mode (SWMDEN = 1) the AES operation complete interrupt should be used, and in DMA
mode (SWMDEN = 0) the DMA complete interrupt should be used. The error interrupt should be used in both
software and DMA modes to notify the firmware of error conditions.
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12.5.2. General DMA Transfer Setup
For the AES module, the DMA channels have these common settings:
Source
size (SRCSIZE) and destination size (DSTSIZE) are 2 for a word transfer.
of transfers is (4 x N) – 1, where N is the number of 4-byte words.
RPOWER = 2 (4 data transfers per transaction).
The size of all memory buffers (input, output, and XOR) modulo 16 bytes must equal 0, so an even number
of 4-word transfers must occur.
The input DMA channel should be programmed as follows:
Number
Destination
end pointer set to the DATAFIFO register.
Source end pointer set to the plain or cipher text input buffer address location + 16 x N – 4, where N is the
number of blocks.
The DSTAIMD field should be set to 011b for no increment.
The SRCAIMD field should be set to 010b for word increments.
The output DMA channel should be programmed as follows:
Destination
end pointer set to the plain or cipher text output buffer address location + 16 x N – 4, where N
is the number of blocks.
Source end pointer set to the DATAFIFO register.
The DSTAIMD field should be set to 010b for word increments.
The SRCAIMD field should be set to 011b for no increment.
The XOR DMA channel should be programmed as follows:
Destination
Source
end pointer set to the XORFIFO register.
end pointer set to the In XOR buffer address location + 16 x N – 4, where N is the number of
blocks.
The DSTAIMD field should be set to 011b for no increment.
The SRCAIMD field should be set to 010b for word increments.
To start a DMA operation with the AES module out of any device reset:
1. Set up the DMA channels for the input/output and XOR FIFOs depending on the desired cipher algorithm.
2. Clear the soft reset bit (RESET) to 0.
3. Configure the AES peripheral operation in the CONTROL, XFRSIZE, HWKEYx, and HWCTRx registers.
4. Start the AES operation by writing a 1 to XFRSTA.
5. Wait for the DMA completion interrupt.
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12.6. Using the AES0 Module for Electronic Codebook (ECB)
The electronic codebook (ECB) cipher algorithm is the most basic block cipher mode since each cipher text output
is only a function of its corresponding plain text input and the encryption key. This algorithm is shown in
Figure 12.3.
Plain Text
Encryption
Key
Encryption
Module
Encrypted (Cipher)
Text
Encrypted (Cipher)
Text
Decryption
Key
Encryption
Module
Plain Text
Figure 12.3. Electronic Codebook (ECB) Algorithm Diagram
The block diagram of the AES module performing this algorithm (encryption and decryption) is shown in
Figure 12.4. The active data paths in this mode are shown in red.
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AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
XORFIFO
Keystore
Figure 12.4. Electronic Codebook (ECB) AES Module Block Diagram—Encryption and Decryption
12.6.1. Configuring the DMA for ECB Encryption
To use the DMA with ECB encryption, the DMA and AES modules should be configured as follows:
DMA Input Channel:
1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the plain text input buffer address location + 16 x N – 4, where N is the number of
blocks.
DMA Output Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. EDMD set to 1 for encryption.
d. KEYCPEN set to 1 to enable key capture at the end of the transaction.
e. The HCBCEN, HCTREN, XOREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
When the encryption process finishes, the decryption key will be available in the HWKEYx registers.
12.6.2. Configuring the DMA for ECB Decryption
To use the DMA with ECB decryption, the DMA and AES modules should be configured as follows:
DMA Input Channel:
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1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the cipher text input buffer address location + 16 x N – 4, where N is the number
of blocks.
DMA Output Channel:
1. Destination end pointer set to the plain text output buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with decryption key value (automatically generated in the
HWKEYx registers after the encryption process).
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1
b. KEYSIZE set to the appropriate number of bits for the key.
c. EDMD set to 1 for encryption.
d. KEYCPEN set to 1 to enable key capture at the end of the transaction.
e. The HCBCEN, HCTREN, XOREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
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12.7. Using the AES0 Module for Cipher Block Chaining (CBC)
The cipher block chaining (CBC) cipher algorithm significantly improves the strength of basic ECB encryption by
making each block encryption be a function of the previous block in addition to the current plain text and key. This
algorithm is shown in Figure 12.5.
Initialization Vector (IV)
Encryption
Key
Key
Decryption
Initialization Vector (IV)
Plain Text
Plain Text
XOR
XOR
Encryption
Module
Key
Encryption
Module
Encrypted (Cipher)
Text
Encrypted (Cipher)
Text
Encrypted (Cipher)
Text
Encrypted (Cipher)
Text
Encryption
Module
Key
Encryption
Module
XOR
XOR
Plain Text
Plain Text
Figure 12.5. Cipher Block Chaining (CBC) Algorithm Diagram
The AES module can perform this algorithm by using a DMA channel or by using the AES hardware to feed the
XOR data FIFO. Both of these methods are discussed.
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12.7.1. Hardware XOR Channel Cipher Block Chaining
The AES0 module has a hardware chaining mode that accelerates the execution of the CBC algorithm. The
module can reuse the hardware counter registers to temporarily store the previous result (CT(n-1)) for use with the
next block. This eliminates the need for a third DMA channel, freeing it for other use, and reduces the timing to be
identical with the counter (CTR) and much-simpler electronic codebook (ECB) algorithms. Any algorithms that use
this hardware path, however, should not use the hardware counter (HCTREN set to 1) feature.
The block diagram of the AES module performing this encryption algorithm using the hardware path is shown in
Figure 12.6. This decryption algorithm block diagram using the hardware path is shown in Figure 12.7. The active
data paths in this mode are shown in red.
AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
CT(n-1)
XOR Data FIFO
XORFIFO
Keystore
Figure 12.6. Hardware Cipher Block Chaining (CBC) AES Module Block Diagram—Encryption
AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
CT(n-1)
XOR Data FIFO
XORFIFO
Keystore
Figure 12.7. Hardware Cipher Block Chaining (CBC) AES Module Block Diagram—Decryption
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12.7.1.1. Configuring the DMA for Hardware CBC Encryption
To use the DMA with hardware CBC encryption, the DMA and AES modules should be configured as follows:
DMA Input Channel:
1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the plain text input buffer address location + 16 x N – 4, where N is the number of
blocks.
DMA Output Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
Initialization Vector:
The initialization vector should be initialized to the HWCTRx registers.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. XOREN bits set to 01b to enable the XOR input path.
d. EDMD set to 1 for encryption.
e. KEYCPEN set to 1 to enable key capture at the end of the transaction.
f. HCBCEN set to 1 to enable Hardware Cipher Block Chaining mode.
g. The HCTREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
When the encryption process finishes, the decryption key is available in the HWKEYx registers.
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12.7.1.2. Configuring the DMA for Hardware CBC Decryption
To use the DMA with Hardware CBC decryption, the DMA and AES modules should be configured as follows:
DMA Input Channel:
1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the cipher text input buffer address location + 16 x N – 4, where N is the number
of blocks.
DMA Output Channel:
1. Destination end pointer set to the plain text output buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
Initialization Vector:
The initialization vector should be initialized to the HWCTRx registers.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. XOREN set to 10b to enable the XOR output path.
d. EDMD set to 0 for decryption.
e. KEYCPEN set to 0 to disable key capture at the end of the transaction.
f. HCBCEN set to 1 to enable Hardware Cipher Block Chaining mode.
g. The HCTREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
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12.7.2. DMA XOR Channel Cipher Block Chaining
The block diagram of the AES module performing this encryption algorithm is shown in Figure 12.8. The block
diagram of the AES module performing this decryption algorithm is shown in Figure 12.9. The active data paths in
this mode are shown in red.
AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
XORFIFO
Keystore
Figure 12.8. Cipher Block Chaining (CBC) AES Module Block Diagram—Encryption
AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
XORFIFO
Keystore
Figure 12.9. Cipher Block Chaining (CBC) AES Module Block Diagram—Decryption
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12.7.2.1. Configuring the DMA for CBC Encryption
To use the DMA with CBC encryption, the DMA and AES modules should be configured as follows:
SiM3xxxx
Address Space
DMA Module
AESn Output Data
AESn Module
16 + 16*N - 4
16*N - 4
DMA Block
Initialization Vector
DATAFIFO
AESn Input Data
DMA Block
DMA Block
XORFIFO
Figure 12.10. DMA XOR Channel Cipher Block Chaining Memory Setup
DMA Input Channel:
1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the plain text input buffer address location + 16 x N – 4, where N is the number of
blocks.
DMA Output Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 + 16 x N – 4, where N is
the number of blocks.
2. Source end pointer set to the DATAFIFO register.
DMA XOR Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 x N – 4, where N is the
number of blocks. By programming the output 16 bytes ahead of the XOR channel, the XOR channel is
always one block behind (CT(n-1)).
2. Source end pointer set to the DATAFIFO register.
Initialization Vector:
The initialization vector should be initialized to the cipher text output buffer address location + 16 x N – 4.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. XOREN set to 01b to enable the XOR input path.
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d. EDMD set to 1 for encryption.
e. KEYCPEN set to 1 to enable key capture at the end of the transaction.
f. The HCBCEN, HCTREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
When the encryption process finishes, the decryption key is available in the HWKEYx registers.
12.7.2.2. Configuring the DMA for CBC Decryption
The decryption process is similar to the encryption process, except now the CT(n-1) value is taken before the data
is passed through the AES module instead of after, as shown in Figure 12.5. To use the DMA with CBC decryption,
the DMA and AES modules should be configured as follows:
DMA Input Channel:
1. Destination end pointer set to the DATAFIFO register.
2. Source end pointer set to the cipher text input buffer address location + 16 + 16 x N – 4, where N is the
number of blocks.
DMA Output Channel:
1. Destination end pointer set to the plain text output buffer address location + 16*N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
DMA XOR Channel:
1. Destination end pointer set to the cipher text input buffer address location + 16 x N – 4, where N is the
number of blocks. By programming the DMA input 16 bytes ahead of the XOR channel, the XOR channel is
always one block behind (CT(n-1)).
2. Source end pointer set to the DATAFIFO register.
Initialization Vector:
The initialization vector should be initialized to the cipher text input buffer address location + 16*N – 4.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. XOREN set to 10b to enable the XOR output path.
d. EDMD set to 0 for decryption.
e. KEYCPEN set to 0 to disable key capture at the end of the transaction.
f. The HCBCEN, HCTREN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
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12.8. Using the AES0 Module for Counter (CTR)
The counter (CTR) cipher algorithm is a stream cipher mode which improves upon the basic ECB algorithm by
adding a third block variable (a counter block in this case). This algorithm is shown in Figure 12.11.
Counter
(0x00000000)
Key
Encryption
Plain Text
Key
Decryption
Encrypted (Cipher) Text
Encryption
Module
XOR
Counter
(0x00000001)
Key
Plain Text
Encryption
Module
XOR
Encrypted (Cipher
Text)
Encrypted (Cipher
Text)
Counter
(0x00000000)
Counter
(0x00000001)
Encryption
Module
XOR
Key
Encrypted (Cipher) Text
Plain Text
Encryption
Module
XOR
Plain Text
Figure 12.11. Counter (CTR) Algorithm Diagram
Similar to CBC mode, the CTR algorithm requires an initialization vector to encrypt the first block. Unlike CBC, this
value is a counter instead of the previous block’s output. This counter is implemented in hardware in the AES0
module.
The block diagram of the AES module performing this algorithm (encryption and decryption) is shown in
Figure 12.12. The active data paths in this mode are shown in red.
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AESn Module
Data FIFO
DATAFIFO
XOR
Hardware Counter
CBC Block Cache
XOR
Hardware AES
Cipher Unit
XOR Data FIFO
XORFIFO
Keystore
Figure 12.12. Counter (CTR) AES Module Block Diagram—Encryption and Decryption
12.8.1. Configuring the DMA for CTR Encryption
To use the DMA with CTR encryption, the DMA and AES modules should be configured as follows:
DMA Output Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
DMA XOR Channel:
1. Destination end pointer set to the plain text input buffer address location + 16 x N – 4.
2. Source end pointer set to the XORFIFO register.
Initialization Vector:
The initialization vector should be initialized to the HWCTRx registers.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. EDMD set to 1 for encryption.
d. KEYCPEN set to 0 to disable key capture at the end of the transaction.
e. HCTREN set to 1 to enable Hardware Counter mode.
f. XOREN set to 10b to enable the XOR output path.
g. The HCBCEN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
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12.8.2. Configuring the DMA for CTR Decryption
This algorithm does not need the key capture output from the encryption process since the encryption and
decryption algorithms are exactly the same.
To use the DMA with CTR decryption, the DMA and AES modules should be configured as follows:
DMA Output Channel:
1. Destination end pointer set to the plain text input buffer address location + 16 x N – 4, where N is the
number of blocks.
2. Source end pointer set to the DATAFIFO register.
DMA XOR Channel:
1. Destination end pointer set to the cipher text output buffer address location + 16 x N – 4.
2. Source end pointer set to the XORFIFO register.
Initialization Vector:
The initialization vector should be initialized to the HWCTRx registers.
AES Module:
1. The XFRSIZE register should be set to N-1, where N is the number of 4-word blocks.
2. The HWKEYx registers should be written with the desired key in little endian format.
3. The CONTROL register should be set as follows:
a. ERRIEN set to 1.
b. KEYSIZE set to the appropriate number of bits for the key.
c. EDMD set to 1 for encryption.
d. KEYCPEN set to 0 to disable key capture at the end of the transaction.
e. HCTREN set to 1 to enable Hardware Counter mode.
f. XOREN set to 10b to enable the XOR output path.
g. The HCBCEN, BEN, SWMDEN bits should all be cleared to 0.
Once the DMA and AES settings have been set, the transfer should be started by writing 1 to the XFRSTA bit.
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12.9. Performing “In-Place” Ciphers
For the cipher examples described in Section 12.6, Section 12.7, and Section 12.8, the DMA channels are
described using plain text and cipher text address offsets. However, these addresses can be the same instead of
separate entities to reduce general-purpose memory usage. These in-place ciphers overwrite the plain text input
with the cipher text output data.
For example, the hardware cipher block chaining algorithm executed in place is shown in Figure 12.13.
Plain Text Input Pointer
Cipher Text Output Pointer
Encryption
Decryption
Initialization Vector
Initialization Vector
Initialization Vector
Plain Text 0
Cipher Text 0
Cipher Text 0
Plain Text 1
Plain Text 1
Cipher Text 1
Plain Text 2
Plain Text 2
Plain Text 2
Plain Text 3
Plain Text 3
Plain Text 3
Plain Text 4
Plain Text 4
Plain Text 4
Plain Text 5
Plain Text 5
Plain Text 5
Plain Text 6
Plain Text 6
Plain Text 6
Initialization Vector
Plain Text 0
Plain Text 0
Cipher Text 0
Cipher Text 0
Plain Text 1
Cipher Text 1
Cipher Text 1
Cipher Text 1
Cipher Text 2
Cipher Text 2
Cipher Text 2
Cipher Text 3
Cipher Text 3
Cipher Text 3
Cipher Text 4
Cipher Text 4
Cipher Text 4
Cipher Text 5
Cipher Text 5
Cipher Text 5
Cipher Text 6
Cipher Text 6
Cipher Text 6
Plain Text Output Pointer
Cipher Text Input Pointer
Figure 12.13. Memory Map of Hardware CBC Algorithm Performed In Place
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12.10. Using the AES0 Module in Software Mode
Software mode (SWMDEN bit set to 1) allows the firmware to perform smaller or more custom operations with the
AES module. When software mode is enabled, the AES module will not generate any DMA requests.
In software mode, each operation must consist of 4 words and follows this general encryption or decryption
sequence out of any device reset:
1. The RESET bit must be cleared to access the AES registers.
2. Configure the operation, including setting SWMDEN to 1.
3. Load the input/output data FIFO (DATAFIFO) with four words. These writes must be completed in word
form, since byte and half-word writes are not supported.
4. Load the XOR data FIFO (XORFIFO) with four words if XOREN is set to 01b or 10b. These writes must be
completed in word form, since byte and half-word writes are not supported.
5. Set KEYCPEN to 1 if key capture is required (EDMD must also be set to 1 for the key capture to occur).
6. Enable the operation complete interrupt by setting OCIEN to 1. Alternatively, firmware can poll XFRSTA or
BUSYF.
7. Set XFRSTA to 1 to start the AES operation on the 4-word block.
8. Wait for the completion interrupt or poll until the operation completes.
9. Read the input/output data FIFO (DATAFIFO) with four word reads to obtain the resulting cipher text
output.
If key capture (KEYCPEN set to 1) was enabled for an encryption operation, then the key is overwritten. The key
must be re-written if a subsequent operation is also an encryption.
The hardware counter and hardware cipher block chaining modes can be used in conjunction with software mode,
but bypass mode (BEN) is not available.
12.10.1. Software Mode Error Conditions
Care must be taken when reading or writing the input/output or XOR FIFOs:
Loading
more than four words into the input/output or XOR data FIFOs results in an overrun error.
less than four words into these data FIFOs prevents an operation from starting when the XFRSTA
bit is set to 1.
Reading the input/output data FIFO with more than four word reads results in an underrun error.
Firmware can check the current status of the FIFOs using the DFIFOLVL and XFIFOLVL fields in the STATUS
register. Failure to read the data from the input/output data FIFO leaves the FIFO full, so any subsequent writes to
this FIFO with new input data causes an overrun event. Any unwanted data in the data or XOR FIFOs can be
discarded by using a soft reset of the AES module (RESET).
Loading
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Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
12.11. AES0 Registers
This section contains the detailed register descriptions for AES0 registers.
Reset
1
0
0
0
0
Bit
15
14
13
12
11
Name
Reserved
Type
R
RW
0
0
RW
R
RW
0
0
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
XOREN
RW
RW
RW
0
0
0
0
22
21
20
19
18
17
16
Reserved
RW
R
RW
Reserved
XFRSTA
RW
23
KEYSIZE
Type
26
KEYCPEN
27
EDMD
Name
0
28
SWMDEN
29
ERRIEN
OCIEN
30
HCBCEN
Reserved
BEN
31
0
24
HCTREN
Bit
Reset
25
DBGMD
Register 12.1. AES0_CONTROL: Module Control
RESET
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
RW
R
RW
RW
RW
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_CONTROL = 0x4002_7000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 12.1. AES0_CONTROL Register Bit Descriptions
Bit
Name
31
RESET
Function
Module Soft Reset.
Must be cleared to access any other AES module bit.
0: AES module is not in soft reset.
1: AES module is in soft reset and none of the module bits can be accessed.
30
DBGMD
AES Debug Mode.
0: A debug breakpoint will cause the AES module to halt.
1: The AES module will continue to operate while the core is halted in debug mode.
29:26
Reserved
25
OCIEN
Must write reset value.
Operation Complete Interrupt Enable.
Enables the completion interrupt for each 4-word block.
0: Disable the operation complete interrupt.
1: Enable the operation complete interrupt.
24
ERRIEN
Error Interrupt Enable.
0: Disable the error interrupt.
1: Enable the error interrupt.
23:18
188
Reserved
Must write reset value.
Rev. 1.0
Table 12.1. AES0_CONTROL Register Bit Descriptions
Bit
Name
17:16
KEYSIZE
Function
Keystore Size Select.
Selects the size of the key used in the AES encryption or decryption process.
00: Key is composed of 128 bits.
01: Key is composed of 192 bits.
10: Key is composed of 256 bits.
11: Reserved.
15:14
Reserved
Must write reset value.
13
HCBCEN
Hardware Cipher-Block Chaining Mode Enable.
Enables the Hardware Cipher-Clock Chaining (CBC) mode. This causes the XOR
path to be fed automatically from hardware with CT(n-1), so there is no need for
firmware or the DMA to feed the XOR path in this mode.
0: Disable hardware cipher-block chaining (CBC) mode.
1: Enable hardware cipher-block chaining (CBC) mode.
12
HCTREN
Hardware Counter Mode Enable.
Enables the Hardware Counter Mode.
0: Disable hardware counter mode.
1: Enable hardware counter mode.
11:10
XOREN
XOR Enable.
Enables the input or output XOR path.
00: Disable the XOR paths.
01: Enable the XOR input path, disable the XOR output path.
10: Disable the XOR input path, enable the XOR output path.
11: Reserved.
9
BEN
Bypass AES Operation Enable.
If this bit is set to 1, the AES module hardware is bypassed, which allows firmware
to use the module as a memory copy. The XOR paths (output and input) are not
available in this mode.
0: Do not bypass AES operations.
1: Bypass AES operations.
8
SWMDEN
Software Mode Enable.
Setting this bit to 1 stops DMA requests from being generated. When this bit is 1,
firmware is responsible for loading the input FIFO with 4 words, loading the XOR
FIFO with 4 words (if applicable), and reading 4 words from the output FIFO after
receiving the done interrupt. If this bit is 1, the transfer size register (XFRSIZE)
should be cleared to 0. Bypass mode is not supported in conjunction with software
mode.
0: Disable software mode.
1: Enable software mode.
7:3
Reserved
2
EDMD
Must write reset value.
Encryption/Decryption Mode.
0: AES module performs a decryption operation
1: AES module performs an encryption operation.
Rev. 1.0
189
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Table 12.1. AES0_CONTROL Register Bit Descriptions
Bit
Name
1
KEYCPEN
Function
Key Capture Enable.
If this bit is set to 1, the current key in the keystore is overwritten during the module
operation. In the case where EDMD is set to 1 (encryption operation), this generated key is the proper decryption key after the last block is complete. If SWMDEN is
cleared to 0, the hardware only overwrites the key on the last block of the DMA
transfer. If SWMDEN is set to 1, the hardware overwrites the key for each operation
KEYCPEN is set to 1.
0: Disable key capture.
1: Enable key capture.
0
XFRSTA
AES Transfer Start.
If SWMDEN is set to 1, setting this bit to 1 starts an AES module operation on the 4word block. This bit is automatically cleared when the 4-word operation completes.
If SWMDEN is cleared to 0, setting this bit to 1 starts a series of AES module operations until the XFRSIZE register counts down to 0. This bit is automatically cleared
when the XFRSIZE regiser is 0 and the current operation completes.
190
Rev. 1.0
Register 12.2. AES0_XFRSIZE: Number of Blocks
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Name
Reserved
XFRSIZE
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_XFRSIZE = 0x4002_7010
Table 12.2. AES0_XFRSIZE Register Bit Descriptions
Bit
Name
Function
31:11
Reserved
Must write reset value.
10:0
XFRSIZE
Transfer Size.
The number of 4-word blocks such that XFRSIZE + 1 blocks will be processed and
transferred by the AES module. This value must match the DMA transfer size for
each relevant channel. This value is automatically decremented by hardware as
each block operation completes.
When the SWMDEN bit is set to 1, this register should be set to 0.
Rev. 1.0
191
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.3. AES0_DATAFIFO: Input/Output Data FIFO Access
Bit
31
30
29
28
27
26
25
24
23
22
Name
DATAFIFO[31:16]
Type
RW
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
DATAFIFO[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
AES0_DATAFIFO = 0x4002_7020
Table 12.3. AES0_DATAFIFO Register Bit Descriptions
Bit
Name
31:0
DATAFIFO
Function
Input/Output Data FIFO Access.
This data register interfaces with the AES Input/Output data FIFO.
For DMA operations, this register should be targeted by the DMA input data and
DMA output data (4-word transfers) in non-incrementing mode.
For software operations (SWMDEN bit is set to 1), this register can be written to set
the input data or read to access the output data in 4-word blocks. When doing soft
transfers, the register must be written or read 4 times to fill or empty the FIFO before
the AES operation can be initiated using the XFRSTA bit.
All reads and writes of this register must be word reads and writes. Byte and half
word reads and writes are not allowed. Any read or write operation will add or
remove an entire word to or from the FIFO, so non-word reads or writes may result
in data loss or FIFO errors.
Reads from this register will result in data pops from the Input/Output FIFO. Writes
to this register will result in data pushes to the Input/Output FIFO. Input/Output data
FIFO overflows and underruns will result in an error interrupt (if enabled).
Notes:
1. Reads of this register modify the state of hardware. Debug logic should take care when reading this register.
2. The access methods for this register are restricted. Do not use half-word or byte access methods on this register.
192
Rev. 1.0
Register 12.4. AES0_XORFIFO: XOR Data FIFO Access
Bit
31
30
29
28
27
26
25
24
23
Name
XORFIFO[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
XORFIFO[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
AES0_XORFIFO = 0x4002_7030
Table 12.4. AES0_XORFIFO Register Bit Descriptions
Bit
Name
31:0
XORFIFO
Function
XOR Data FIFO Access.
This data register interfaces with the AES XOR data FIFO.
For DMA operations, this register should be targeted by the DMA input XOR data
(4-word transfers) in non-incrementing mode.
For software operations (SWMDEN bit is set to 1), this register can be written to set
the input XOR data in 4-word blocks. When doing soft transfers, the register must
be written 4 times to fill or empty the FIFO before the AES operation can be initiated
using the XFRSTA bit.
All reads and writes of this register must be word reads and writes. Byte and half
word reads and writes are not allowed. Any write operation will add an entire word
to the FIFO.
Reads from this register have no effect. Writes to this register will result in data
pushes to the Input/Output FIFO. XOR data FIFO overflows will result in an error
interrupt (if enabled).
Notes:
1. Reads of this register modify the state of hardware. Debug logic should take care when reading this register.
2. The access methods for this register are restricted. Do not use half-word or byte access methods on this register.
Rev. 1.0
193
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.5. AES0_HWKEY0: Hardware Key Word 0
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY0[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY0[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY0 = 0x4002_7040
Table 12.5. AES0_HWKEY0 Register Bit Descriptions
Bit
Name
31:0
HWKEY0
Function
Hardware Key Word 0.
This register contains word 0 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
194
Rev. 1.0
Register 12.6. AES0_HWKEY1: Hardware Key Word 1
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY1[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY1[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY1 = 0x4002_7050
Table 12.6. AES0_HWKEY1 Register Bit Descriptions
Bit
Name
31:0
HWKEY1
Function
Hardware Key Word 1.
This register contains word 1 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
Rev. 1.0
195
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.7. AES0_HWKEY2: Hardware Key Word 2
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY2[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY2[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY2 = 0x4002_7060
Table 12.7. AES0_HWKEY2 Register Bit Descriptions
Bit
Name
31:0
HWKEY2
Function
Hardware Key Word 2.
This register contains word 2 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
196
Rev. 1.0
Register 12.8. AES0_HWKEY3: Hardware Key Word 3
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY3[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY3[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY3 = 0x4002_7070
Table 12.8. AES0_HWKEY3 Register Bit Descriptions
Bit
Name
31:0
HWKEY3
Function
Hardware Key Word 3.
This register contains word 3 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
Rev. 1.0
197
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.9. AES0_HWKEY4: Hardware Key Word 4
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY4[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY4[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY4 = 0x4002_7080
Table 12.9. AES0_HWKEY4 Register Bit Descriptions
Bit
Name
31:0
HWKEY4
Function
Hardware Key Word 4.
This register contains word 4 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
198
Rev. 1.0
Register 12.10. AES0_HWKEY5: Hardware Key Word 5
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY5[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY5[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY5 = 0x4002_7090
Table 12.10. AES0_HWKEY5 Register Bit Descriptions
Bit
Name
31:0
HWKEY5
Function
Hardware Key Word 5.
This register contains word 5 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
Rev. 1.0
199
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.11. AES0_HWKEY6: Hardware Key Word 6
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY6[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY6[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY6 = 0x4002_70A0
Table 12.11. AES0_HWKEY6 Register Bit Descriptions
Bit
Name
31:0
HWKEY6
Function
Hardware Key Word 6.
This register contains word 6 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
200
Rev. 1.0
Register 12.12. AES0_HWKEY7: Hardware Key Word 7
Bit
31
30
29
28
27
26
25
24
23
Name
HWKEY7[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWKEY7[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWKEY7 = 0x4002_70B0
Table 12.12. AES0_HWKEY7 Register Bit Descriptions
Bit
Name
31:0
HWKEY7
Function
Hardware Key Word 7.
This register contains word 7 of the keystore.
If the KEYCPEN bit is set to 1, the new key will be accessible using these registers
after the old key is overwritten.
Rev. 1.0
201
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.13. AES0_HWCTR0: Hardware Counter Word 0
Bit
31
30
29
28
27
26
25
24
23
Name
HWCTR0[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWCTR0[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWCTR0 = 0x4002_70C0
Table 12.13. AES0_HWCTR0 Register Bit Descriptions
Bit
Name
31:0
HWCTR0
Function
Hardware Counter Word 0.
This register contains word 0 of the 128-bit hardware counter. These registers are
little endian.
When the HCTREN bit is set to 1, this register should be written with the initial
counter value to seed the encryption or decryption process for a block of operations.
Reading this register always reflects the current value of the hardware counter.
Firmware should not modify the contents of this register when using hardware CBC
mode (HCBCEN = 1).
202
Rev. 1.0
Register 12.14. AES0_HWCTR1: Hardware Counter Word 1
Bit
31
30
29
28
27
26
25
24
23
Name
HWCTR1[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWCTR1[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWCTR1 = 0x4002_70D0
Table 12.14. AES0_HWCTR1 Register Bit Descriptions
Bit
Name
31:0
HWCTR1
Function
Hardware Counter Word 1.
This register contains word 1 of the 128-bit hardware counter. These registers are
little endian.
When the HCTREN bit is set to 1, this register should be written with the initial
counter value to seed the encryption or decryption process for a block of operations.
Reading this register always reflects the current value of the hardware counter.
Firmware should not modify the contents of this register when using hardware CBC
mode (HCBCEN = 1).
Rev. 1.0
203
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Register 12.15. AES0_HWCTR2: Hardware Counter Word 2
Bit
31
30
29
28
27
26
25
24
23
Name
HWCTR2[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWCTR2[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWCTR2 = 0x4002_70E0
Table 12.15. AES0_HWCTR2 Register Bit Descriptions
Bit
Name
31:0
HWCTR2
Function
Hardware Counter Word 2.
This register contains word 2 of the 128-bit hardware counter. These registers are
little endian.
When the HCTREN bit is set to 1, this register should be written with the initial
counter value to seed the encryption or decryption process for a block of operations.
Reading this register always reflects the current value of the hardware counter.
Firmware should not modify the contents of this register when using hardware CBC
mode (HCBCEN = 1).
204
Rev. 1.0
Register 12.16. AES0_HWCTR3: Hardware Counter Word 3
Bit
31
30
29
28
27
26
25
24
23
Name
HWCTR3[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
HWCTR3[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_HWCTR3 = 0x4002_70F0
Table 12.16. AES0_HWCTR3 Register Bit Descriptions
Bit
Name
31:0
HWCTR3
Function
Hardware Counter Word 3.
This register contains word 3 of the 128-bit hardware counter. These registers are
little endian.
When the HCTREN bit is set to 1, this register should be written with the initial
counter value to seed the encryption or decryption process for a block of operations.
Reading this register always reflects the current value of the hardware counter.
Firmware should not modify the contents of this register when using hardware CBC
mode (HCBCEN = 1).
Rev. 1.0
205
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
30
Name
Type
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XORF
DORF
DURF
29
28
27
26
25
24
23
22
21
18
17
16
R
R
R
R
0
0
0
0
R
R
XFIFOLVL
Reserved
RW
Reserved
DFIFOLVL
Type
R
R
R
R
0
19
Reserved
Name
Reset
20
BUSYF
31
ERRI
Bit
Reserved
Register 12.17. AES0_STATUS: Module Status
OCI
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
AES0_STATUS = 0x4002_7100
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 12.17. AES0_STATUS Register Bit Descriptions
Bit
Name
31
OCI
Function
Operation Complete Interrupt Flag.
This bit is set to 1 by hardware when the current AES operation is complete. This bit
must be cleared by software.
30
ERRI
Error Interrupt Flag.
This bit is set to 1 by hardware when an AES error has occurred (DURF, DORF, or
XORF set to 1). This bit must be cleared by software.
29:17
Reserved
16
BUSYF
Must write reset value.
Module Busy Flag.
0: AES module is not busy.
1: AES module is completing an operation.
15:11
Reserved
Must write reset value.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
206
Rev. 1.0
Table 12.17. AES0_STATUS Register Bit Descriptions
Bit
Name
10:8
XFIFOLVL
Function
XOR Data FIFO Level.
000: XOR data FIFO is empty.
001: XOR data FIFO contains 1 word.
010: XOR data FIFO contains 2 words.
011: XOR data FIFO contains 3 words.
100: XOR data FIFO contains 4 words (full).
101-111: Reserved.
7
Reserved
Must write reset value.
6:4
DFIFOLVL
Input/Output Data FIFO Level.
000: Input/Output data FIFO is empty.
001: Input/Output data FIFO contains 1 word.
010: Input/Output data FIFO contains 2 words.
011: Input/Output data FIFO contains 3 words.
100: Input/Output data FIFO contains 4 words (full).
101-111: Reserved.
3
Reserved
2
XORF
Must write reset value.
XOR Data FIFO Overrun Flag.
Firmware can recover from this condition by performing a soft reset on the AES
module by using the RESET bit.
0: No XOR data FIFO overrun.
1: An XOR data FIFO overrun has occurred.
1
DORF
Input/Output Data FIFO Overrun Flag.
Firmware can recover from this condition by performing a soft reset on the AES
module by using the RESET bit.
0: No input/output data FIFO overrun.
1: An input/output data FIFO overrun has occurred.
0
DURF
Input/Output Data FIFO Underrun Flag.
Firmware can recover from this condition by performing a soft reset on the AES
module by using the RESET bit.
0: No input/output data FIFO underrun.
1: An input/output data FIFO underrun has occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
207
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
12.12. AES0 Register Memory Map
Table 12.18. AES0 Memory Map
AES0_HWKEY0 AES0_XORFIFO AES0_DATAFIFO AES0_XFRSIZE AES0_CONTROL Register Name
0x4002_7040
0x4002_7030
0x4002_7020
ALL Address
0x4002_7010
0x4002_7000
ALL
ALL
ALL
ALL
ALL | SET | CLR Access Methods
Bit 31
RESET
Bit 30
DBGMD
Bit 29
Bit 28
Reserved
Bit 27
Bit 26
OCIEN
Bit 25
ERRIEN
Bit 24
Bit 23
Bit 22
Reserved
Bit 21
Reserved
Bit 20
Bit 19
Bit 18
Bit 17
KEYSIZE
Bit 16
HWKEY0
XORFIFO
DATAFIFO
Bit 15
Reserved
Bit 14
HCBCEN
Bit 13
HCTREN
Bit 12
Bit 11
XOREN
Bit 10
BEN
Bit 9
SWMDEN
Bit 8
Bit 7
Bit 6
XFRSIZE
Reserved
Bit 5
Bit 4
Bit 3
EDMD
Bit 2
KEYCPEN
Bit 1
XFRSTA
Bit 0
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
208
Rev. 1.0
AES0_HWKEY5 AES0_HWKEY4 AES0_HWKEY3 AES0_HWKEY2 AES0_HWKEY1 Register Name
0x4002_7090
0x4002_7080
0x4002_7070
0x4002_7060
0x4002_7050
ALL Address
ALL
ALL
ALL
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
HWKEY5
HWKEY4
HWKEY3
HWKEY2
HWKEY1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 12.18. AES0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
209
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Table 12.18. AES0 Memory Map
AES0_HWCTR2 AES0_HWCTR1 AES0_HWCTR0 AES0_HWKEY7 AES0_HWKEY6 Register Name
0x4002_70E0
0x4002_70D0
0x4002_70C0
0x4002_70B0
0x4002_70A0
ALL Address
ALL
ALL
ALL
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
HWCTR2
HWCTR1
HWCTR0
HWKEY7
HWKEY6
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
210
Rev. 1.0
AES0_STATUS AES0_HWCTR3 Register Name
0x4002_7100
0x4002_70F0
ALL Address
ALL | SET | CLR
ALL
Access Methods
OCI
Bit 31
ERRI
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
BUSYF
Bit 16
HWCTR3
Bit 15
Bit 14
Reserved
Bit 13
Bit 12
Bit 11
Bit 10
XFIFOLVL
Bit 9
Bit 8
Reserved
Bit 7
Bit 6
DFIFOLVL
Bit 5
Bit 4
Reserved
Bit 3
XORF
Bit 2
DORF
Bit 1
DURF
Bit 0
Table 12.18. AES0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
211
Advanced Encryption Standard (AES0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13. Capacitive Sensing (CAPSENSE0)
This section describes the Capacitive Sensing (CAPSENSE) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the CAPSENSE block, which is used by all device families covered in this
document.
13.1. Capacitive Sensing Features
The CAPSENSE0 module measures capacitance on external pins and converts it to a digital value. The module
includes the following features:
Nine
start-of-conversion sources, including timers, I2C timers and software “on-demand” triggers.
external I/O pin input channels.
Option to convert to 12, 13, 14, or 16 bits.
Automatic threshold comparison with programmable polarity (“less than or equal” or “greater than”).
Four operation modes: single conversion, single scan, continuous single conversion, and continuous scan.
Auto-accumulate mode that averages multiple samples from a single start of conversion signal.
Single bit retry options available to reduce the effect of noise during a conversion.
Supports channel bonding to monitor multiple channels connected together with a single conversion.
Scanning option allows the module to convert a single or series of channels and compare against the
threshold while the AHB clock is stopped and the core is in a low power mode.
Sixteen
212
Rev. 1.0
CAPSENSEn Module
CSnT0
CSnT1
CSnT2
CSnT3
CSnT15
CSn.0
Comparator
CSn.1
CSn.2
CSn.3
1x – 8x
gain
Capacitance to
Digital Converter
Accumulator
Channel Scan
CSn.x
Channel Binding
Pin Monitor
Figure 13.1. CAPSENSE Block Diagram
13.2. Overview
The capacitive sensing (CAPSENSE) module uses a capacitance-to-digital circuit to determine the capacitance on
an input pin. The module can take measurements from different physical pins using the module’s analog
multiplexer. In addition, the module can measure multiple pins in sequence using the scan modes, or multiple pins
at the same time using the multiple-channel measurement feature. The module can continue to make
measurements in one of the continuous modes if the AHB clock stops, allowing the module to wake a device from
a low power mode. The module is enabled only when the CSEN and BIASEN bits are set to 1; otherwise, the
module is in a low-power shutdown state.
A selectable gain circuit allows the module to adjust the maximum allowable capacitance. An accumulator is also
included, which can be configured to average multiple conversions on an input channel.
The hardware can generate an interrupt after completing a conversion, a series of conversions, or when the
measured value crosses a threshold defined in the CSTH register.
All pins used as inputs to the CAPSENSE module should be configured as analog inputs as described in the port
configuration section.
Rev. 1.0
213
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13.3. Measurement Overview
In single-conversion mode, the CAPSENSE module measures the channel selected by the CSMX field. This
measurement begins when the start of conversion source set by the CSCM field triggers. Hardware sets the
BUSYF flag to 1 while a conversion is in progress and automatically clears this bit when the conversion completes,
in addition to setting the conversion done (CDI) flag. Firmware can read the conversion result from the DATA
register. Figure 13.2 depicts this basic CAPSENSE measurement process.
Start of conversion
trigger
CAPSENSEn clock
Idle
Converting
Idle
Figure 13.2. Basic CAPSENSE Measurement
Firmware can disconnect the pin from the measurement circuitry by setting the CSDISC bit to 1.
Note: Enable the CAPSENSE bias (BIASEN = 1) before enabling the module (CSEN = 1). Firmware must wait at least 2 µs
after enabling the bias before starting a conversion.
13.3.1. Start of Conversion Sources
A capacitive sense conversion can be initiated in one of nine ways, depending on the programmed state of the start
of conversion (CSCM) field in the CONTROL register. The available options are detailed in Table 13.1.
Table 13.1. CAPSENSE0 Start of Conversion Sources
214
Trigger
Convert Start Description
Internal Signal
CS0T0
Internal Convert Start
“On Demand” by writing 1 to CSBUSY
CS0T1
Internal Convert Start
Timer 0 Low overflow
CS0T2
Internal Convert Start
Timer 0 High overflow
CS0T3
Internal Convert Start
Timer 1 Low overflow
CS0T4
Internal Convert Start
Timer 1 High overflow
CS0T5
Internal Convert Start
I2C0 Timer Byte 1 overflow
CS0T6
Internal Convert Start
I2C0 Timer Byte 3 overflow
CS0T7
Internal Convert Start
I2C1 Timer Byte 1 overflow
CS0T8
Internal Convert Start
I2C1 Timer Byte 3 overflow
Rev. 1.0
13.3.2. Inputs
The CAPSENSE module can select between multiple external inputs (up to 16 are available, depending on the
package type). These inputs can be measured individually, scanned using the single scan or continuous scan
modes, or connected together using the CONTROL.CSMCEN bit. The CAPSENSE module input channel settings
are located in the MUX.CSMX field and SCANM register. The CAPSENSE0 input channels vary between package
options, and are shown in Table 13.2.
Table 13.2. CAPSENSE0 Input Channels
CAPSENSE0
Input
CAPSENSE0 Input
Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
CS0.0
External Channel
PB0.1
Reserved
PB0.2
CS0.1
External Channel
PB0.2
PB0.0
PB0.3
CS0.2
External Channel
PB0.3
PB0.1
PB0.4
CS0.3
External Channel
PB0.4
PB0.2
PB0.6
CS0.4
External Channel
PB0.5
PB0.3
PB0.7
CS0.5
External Channel
PB0.6
PB0.4
Reserved
CS0.6
External Channel
PB0.7
PB0.5
Reserved
CS0.7
External Channel
PB0.8
PB0.6
PB0.0
CS0.8
External Channel
PB1.7
PB1.2
Reserved
CS0.9
External Channel
PB1.8
PB1.3
Reserved
CS0.10
External Channel
PB1.13
PB1.6
PB0.12
CS0.11
External Channel
PB1.14
PB1.7
PB0.13
CS0.12
External Channel
PB1.15
PB1.8
PB0.14
CS0.13
External Channel
PB2.0
PB1.9
PB0.15
CS0.14
External Channel
PB2.1
PB1.10
PB1.0
CS0.15
External Channel
PB2.2
PB1.11
PB1.1
Rev. 1.0
215
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13.4. Conversion and Input Modes
The CAPSENSE module has four conversion modes: single conversion, single scan, continuous single, and
continuous scan.
13.4.1. Single Conversion Mode
For single conversion mode (CMD = 0), the module takes a single conversion for each start of conversion trigger.
Hardware sets the conversion done (CDI) flag when the single conversion completes.
Firmware can use single conversion mode and multiplex through the input channels to measure multiple channels.
After polling on conversion done (CDI) or waiting for the conversion done interrupt, firmware can switch the CSMX
input multiplexor to the next input before moving the data out of the DATA register. Then, the next measurement
can be initiated by the start of conversion trigger after disabling (CSEN = 0) and reenabling (CSEN = 1) the
module.
13.4.2. Single Scan Mode
Scan mode is enabled by setting CMD to 1 for single scan mode or 3 for continuous scan mode. When operating in
scan mode and MCEN is cleared to 0, the CAPSENSE module will cycle through the channels defined by the
SCANEN field. Each bit in SCANEN represents a capacitive sensing channel, and setting a bit to 1 in the SCANEN
field enables that channel for the scan. The accumulator setting (ACCMD) determines the number of samples
takes for each channel in scan mode. Figure 13.3 illustrates single scan mode.
The module will stop taking measurements in single scan mode after measuring the last channel or if a compare
threshold event occurs. Using scan mode with the CAPSENSE comparator interrupt enabled allows a system to
detect a change in measured capacitance without requiring any additional dedicated core resources.
SCANEN
Field
CAPSENSEn
Channel
0
0
0
1
0
1
2
1
2
3
0
3
4
5
0
4
1
5
6
1
6
7
0
7
8
0
8
9
1
9
10
0
10
11
1
11
12
0
12
13
1
13
14
0
14
15
0
15
Figure 13.3. Single Scan Mode
13.4.3. Continuous Single and Scan Modes
Conversions can be configured to be initiated continuously through one of two methods. The module can convert
on a single channel continuously (CMD = 1), or it can be configured to convert continuously with scan enabled
(CMD = 3).
The module will continue to convert on the single or scan channels until a compare threshold event occurs, or
firmware disables the module by clearing CSEN to 0.
The CAPSENSE module can continue to make conversions in the continuous modes even if the AHB clock is
stopped. A new capacitive measurement operation cannot be started if the AHB clock is not running.
216
Rev. 1.0
13.5. Conversion Rate
The CAPSENSE module uses a method of successive approximation to determine the value of an external
capacitance. The number of bits the module converts is adjustable using the CNVR field. Conversions are 13 bits
long by default, but they can be adjusted to 12, 13, 14, or 16 bits. Unconverted bits will be set to 0. Shorter
conversion lengths produce faster conversion rates, and longer conversion lengths increase the conversion time.
Applications can take advantage of faster conversion rates when the unconverted bits fall below the noise floor.
13.6. Accumulation Modes
The capacitive sensing module can measure a channel multiple times and internally accumulate those
measurements. The ACCMD field selects the accumulation mode, and the module can accumulate 1, 4, 8, 16, 32,
or 64 samples. After the defined number of samples have been accumulated, the result is divided by either 1, 4, 8,
16, 32, or 64 depending on the ACCMD setting and copied to the DATA register in right-justified format. The
accumulator setting determines the number of samples takes for each channel in both single and scan modes.
The conversion done (CDI) flag behavior depends on the settings of the CAPSENSE accumulator. If the module is
configured to accumulate multiple conversions on an input channel, the hardware will set the conversion done
(CDI) flag after last conversion completes. Each measurement requires a separate start of conversion trigger.
13.7. Measuring Multiple Channels in a Single Measurement
The CAPSENSE module has the capability of measuring the total capacitance of multiple channels using a single
conversion. When the multiple channel feature is enabled (MCEN = 1), channels selected by SCANEN field are
internally shorted together, and the combined node is selected as the module input. This mode can be used to
detect a capacitance change on multiple channels using a single conversion.
The single scan and continuous scan modes should not be used when MCEN is set to 1.
13.8. Pin Monitoring
The CAPSENSE module provides accurate conversions in all operating modes of the core, peripherals, and pins.
The pin monitoring feature improves interference immunity from high-current output pin switching. The port match
register in the port configuration module controls the pin selection of the monitors.
Note: The APB clock must be greater than 5 MHz when using the pin monitoring feature with the capacitive sensing module.
Conversions in the capacitive sensing module are immune to any change on digital inputs and immune to most
output switching. Even high-speed serial data transmission will not affect CAPSENSE operation as long as the
output load is limited. Output changes that switch large loads, such as LEDs and heavily-loaded communications
lines, can affect conversion accuracy. For this reason, the module includes pin monitoring circuits that will, if
enabled, automatically adjust conversion timing if necessary to eliminate any effect from high-current output pin
switching.
The pin monitor enable bit in the device port configuration module should be set for any output signal that is
expected to drive a large load.
Pin monitors should not be enabled unless they are required. The pin monitor works by repeating any portion of a
conversion that may have been corrupted by a change on an output pin. As a result, enabling a pin monitor will
slow capacitive sensing conversions.
The frequency of CAPSENSE retry operations can be limited by setting the PMMD field. In the default state, all
converter retry requests will be performed. This is the recommended setting for all applications. The number of
retries per conversion can be limited to either two (PMMD = 1) or four (PMMD = 2) retries. Limiting the number of
retries per conversion ensures that conversions will be completed even in circumstances where extremely frequent
high-power output switching occurs, though there may be some loss of accuracy due to switching noise.
Activity of the pin monitor circuit can be detected by reading the pin monitor event (PMEF) flag. Hardware will set
this flag if any CAPSENSE converter retries have occurred. It remains set until cleared by firmware or a device
reset.
Rev. 1.0
217
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13.9. Compare Threshold
When enabled (CMPEN = 1), the module comparator compares the latest capacitive sensing conversion result with
the value stored in CSTH. The polarity of this conversion is controlled with the CMPPOL bit. If CMPPOL is set to 1,
hardware sets the compare threshold (CMPI) flag to 1 if the result is less than or equal to the stored value. If
CMPPOL is cleared to 0, hardware sets the CMPI flag to 1 if the result is greater than the threshold.
If the accumulator is configured to accumulate multiple conversions, a comparison will not be made until the last
conversion has been accumulated.
If the module is operating in scan mode, a compare threshold event will cause the module to stop converting until a
new start of conversion trigger occurs.
13.10. Interrupts
Hardware sets the conversion done (CDI) flag when a single conversion completes. The CDI flag behavior
depends on the settings of the CAPSENSE accumulator (ACCMD). If the module is configured to accumulate
multiple conversions on an input channel, the hardware will set the conversion done (CDI) flag after last conversion
completes. Hardware can also generate an interrupt when setting CDI, if enabled (CDIEN = 1).
If the module comparator is enabled (CMPEN = 1), the compare threshold (CMPI) flag sets when the result is less
than or equal to the threshold if CMPPOL is cleared to 0 or greater than the threshold if CMPPOL is set to 1. This
event will also generate an interrupt if the comparator is enabled (CMPEN = 1). The CMPI flag must be cleared by
disabling the module (CSEN = 1).
Hardware sets the end-of-scan (EOSI) flag when a single scan operation completes and can generate an interrupt
if EOSIEN is set to 1. This flag must be cleared by disabling the module (CSEN = 0).
13.11. Additional Options
13.11.1. Gain Adjustment
The gain of the capacitive measurement circuit can be adjusted in integer increments from 1x to 8x, where 8x is the
default setting. High gain gives the best sensitivity and resolution for small capacitors, such as those typically
implemented as touch-sensitive PCB features. To measure larger capacitance values, the gain should be lowered
accordingly. The CGSEL field sets the gain value.
13.11.2. Measuring Non-Typical Systems
There are several configuration options in the CAPSENSE module designed to modify the operation of the circuit
and address special situations. In particular, any circuit with more than 500 ohms of series impedance between the
sensor and the device pin may require adjustments for optimal performance. Typical applications which may
require adjustments include:
Touch
panel sensors fabricated using a resistive conductor such as indium-tin-oxide (ITO).
using a high-value series resistor to isolate the sensor element for high ESD protection.
Most systems will require no fine tuning, and the default settings for RAMPSEL, IASEL, and DTSEL should be
used.
Circuits
218
Rev. 1.0
13.12. Taking a Measurement
13.12.1. Initializing the Module
To configure the CAPSENSE module to take a measurement:
1. Enable the CAPSENSE bias (BIASEN = 1) before enabling the module. Firmware must wait at least 2 µs
after enabling the bias before starting a conversion.
2. Initialize the start of conversion mode select field (CSCM) to the desired trigger source.
3. Set the input channel using the CSMX field. Any pins used as an input must be set to analog mode.
4. (Optional) If using scan or multiple-channel measurement modes, set the SCANEN field to enable the
channels. Any pins used as an input must be set to analog mode.
5. Set the conversion mode using the CMD field.
6. Set the conversion rate using the CNVR field.
7. Set the accumulation mode using the ACCMD field.
8. (Optional) If using the compare threshold, set the threshold (CSTH), set the threshold polarity (CMPPOL),
and enable the comparator (CMPEN = 1).
9. Enable the module (CSEN = 1).
10. Initiate the conversions using the selected trigger source.
11. Disable the module (CSEN = 0) after the measurement.
12. Reenable the module (CSEN = 1) and start the next measurement operation.
13.12.2. Reconfiguring the Module
To reconfigure the capacitive sensing module after conversions have already taken place:
1. Disable the module (CSEN = 0) to clear any pending flags and reset the module.
2. Update any fields in the module.
3. Enable the module (CSEN = 1).
4. Initiate the conversions using the selected trigger source.
5. Disable the module after the operation (CSEN = 0).
Rev. 1.0
219
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13.13. CAPSENSE0 Registers
This section contains the detailed register descriptions for CAPSENSE0 registers.
Register 13.1. CAPSENSE0_CONTROL: Module Control
23
22
21
20
19
18
17
16
Name
Reserved
PMEF
24
Reserved
25
CMPEN
26
CDIEN
27
EOSIEN
28
Reserved
29
CMPI
30
CDI
31
EOSI
Bit
PMMD
Type
R
R
RW
R
R
RW
RW
RW
R
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CSCM
Type
RW
Reset
0
0
0
0
ACCMD
CNVR
CMD
BUSYF
0
CSEN
0
BIASEN
0
CMPPOL
Reset
MCEN
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
1
0
0
Register ALL Access Address
CAPSENSE0_CONTROL = 0x4002_3000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 13.3. CAPSENSE0_CONTROL Register Bit Descriptions
Bit
Name
31:27
Reserved
26
EOSI
Function
Must write reset value.
End-of-Scan Interrupt Flag.
This bit is set to 1 by hardware when a single scan operation is complete. This will
only occur in single scan mode. This bit can only be cleared by disabling the module
(CSEN = 0).
25
CDI
Conversion Done Interrupt Flag.
This bit is set to 1 by hardware when a data conversion is complete in single conversion mode. This bit must be cleared by firmware.
24
CMPI
Threshold Comparator Interrupt Flag.
Hardware sets this bit to 1 when a the compare threshold event occurs based on the
polarity set by CMPPOL if the internal comparator is enabled (CMPEN = 1). This bit
can only be cleared by disabling the module (CSEN = 0).
23
Reserved
Must write reset value.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
220
Rev. 1.0
Table 13.3. CAPSENSE0_CONTROL Register Bit Descriptions
Bit
Name
22
EOSIEN
Function
End-of-Scan Interrupt Enable.
0: Disable the single scan end-of-scan interrupt.
1: Enable the single scan end-of-scan interrupt.
21
CDIEN
Conversion Done Interrupt Enable.
0: Disable the single conversion done interrupt.
1: Enable the single conversion done interrupt.
20
CMPEN
Threshold Comparator Enable.
Enables the threshold comparator, which compares the accumulated capacitive
sensing conversion output to the value stored in CSTH. When enabled, the comparator threshold event will stop the continuous conversion modes. This bit also
enables the compare threshold interrupt.
0: Disable the threshold comparator.
1: Enable the threshold comparator.
19
Reserved
18
PMEF
Must write reset value.
Pin Monitor Event Flag.
Hardware sets this flag if any measurement retries have occurred due to a pin monitor event. This bit remains set until cleared by firmware.
0: A retry did not occur due to a pin monitor event during the last conversion.
1: A retry occurred due to a pin monitor event during the last conversion.
17:16
PMMD
Pin Monitor Mode.
00: Always retry on a pin state change.
01: Retry up to twice on consecutive bit cycles.
10: Retry up to four times on consecutive bit cycles.
11: Ignore monitored signal state change.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
221
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Table 13.3. CAPSENSE0_CONTROL Register Bit Descriptions
Bit
Name
15:12
CSCM
Function
Start of Conversion Mode Select.
0000: The CSnT0 trigger source starts conversions.
0001: The CSnT1 trigger source starts conversions.
0010: The CSnT2 trigger source starts conversions.
0011: The CSnT3 trigger source starts conversions.
0100: The CSnT4 trigger source starts conversions.
0101: The CSnT5 trigger source starts conversions.
0110: The CSnT6 trigger source starts conversions.
0111: The CSnT7 trigger source starts conversions.
1000: The CSnT8 trigger source starts conversions.
1001: The CSnT9 trigger source starts conversions.
1010: The CSnT10 trigger source starts conversions.
1011: The CSnT11 trigger source starts conversions.
1100: The CSnT12 trigger source starts conversions.
1101: The CSnT13 trigger source starts conversions.
1110: The CSnT14 trigger source starts conversions.
1111: The CSnT15 trigger source starts conversions.
11
MCEN
Multiple Channel Enable.
When this bit is set to 1, the channels selected by SCANEN are internally shorted
together and the combined node is selected as the measurement input. This mode
can be used to detect a capacitance change on multiple channels using a single
conversion.
0: Disable the multiple channel measurement feature.
1: Enable the multiple channel measurement feature.
10:8
ACCMD
Accumulator Mode Select.
When ACCMD is set to a value other than 0, the hardware will not set the conversion done or end-of-scan flags until all samples are taken and accumulated.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples.
100: Accumulate 32 samples.
101: Accumulate 64 samples.
110-111: Reserved.
7:6
CNVR
Conversion Rate.
00: Conversions last 12 internal CAPSENSE clocks and results are 12 bits in length.
01: Conversions last 13 internal CAPSENSE clocks and results are 13 bits in length.
10: Conversions last 14 internal CAPSENSE clocks and results are 14 bits in length.
11: Conversions last 16 internal CAPSENSE clocks and results are 16 bits in length.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
222
Rev. 1.0
Table 13.3. CAPSENSE0_CONTROL Register Bit Descriptions
Bit
Name
5:4
CMD
Function
Conversion Mode Select.
00: Single Conversion Mode: One conversion occurs on a single channel.
01: Single Scan Mode: One conversion on each channel selected by SCANEN
occurs. An end-of-scan interrupt indicates all channels have been measured.
10: Continuous Single Conversion Mode: Continuously converts on a single channel. This operation ends only if the module is disabled (CSEN = 0) or if a compare
threshold event occurs (CMPI = 1).
11: Continuous Scan Mode: Continuously loops through and converts on all the
channels selected by SCANEN. This operation ends only if the module is disabled
(CSEN = 0) or if a compare threshold event occurs (CMPI = 1).
3
CMPPOL
Digital Comparator Polarity Select.
0: The digital comparator generates an interrupt if the conversion is greater than the
CSTH threshold.
1: The digital comparator generates an interrupt if the conversion is less than or
equal to the CSTH threshold.
2
BIASEN
Bias Enable.
Enable the bias to the CAPSENSEn core. Firmware must wait at least 2 microseconds after enabling the bias before starting a conversion. Disabling the bias will
save power if no measurement is being taken.
0: Disable the bias.
1: Enable the bias.
1
CSEN
Module Enable.
The bit should be set to 1 after setting BIASEN to 1. The capacitive sensing module
should be disabled after each measurement operation, and all settings in the module should be adjusted while the module is disabled. The CMPI and EOSI flags can
only be cleared by clearing this bit to 0.
0: Disable the capacitive sensing module.
1: Enable the capacitive sensing module.
0
BUSYF
Start and Busy Flag.
Hardware sets this bit to 1 when a conversion in progress and clears this bit automatically when the conversion completes. Firmware can set this bit to 1 to initiate a
conversion if BUSYF is selected as the start of conversion source by the CSCM
field.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
223
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Register 13.2. CAPSENSE0_MODE: Measurement Mode
Bit
31
30
29
28
27
26
25
24
Name
23
22
21
20
19
18
17
16
Reserved
Type
R
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Reset
0
DTSEL
R
RW
0
0
0
IASEL
RAMPSEL
0
Reserved
Reset
Reserved
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Reserved
R
RW
RW
RW
0
0
0
0
0
0
0
CGSEL
R
0
0
RW
1
1
1
Register ALL Access Address
CAPSENSE0_MODE = 0x4002_3010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 13.4. CAPSENSE0_MODE Register Bit Descriptions
Bit
Name
31:15
Reserved
14:12
DTSEL
Function
Must write reset value.
Discharge Time Select.
This field adjusts the primary CAPSENSEn reset time. For most touch-sensitive
switches, the default (fastest) value is sufficient.
11
Reserved
10:8
IASEL
Must write reset value.
Output Current Select.
These bits allow firmware to adjust the output current used to charge up the capacitive sensor element. For most touch-sensitive switches, the default (highest) current
is sufficient.
7:6
RAMPSEL
Ramp Selection.
These bits are used to compensate capacitive sensing conversions for circuits
requiring slower ramp times. For most touch-sensitive switches, the default (fastest)
value is sufficient.
5:3
Reserved
2:0
CGSEL
Must write reset value.
Capacitance Gain Select.
These bits select the gain applied to the capacitance measurement. Lower gain values increase the size of the capacitance that can be measured with the CAPSENSE
module. The capacitance gain is equivalent to CGSEL + 1.
224
Rev. 1.0
Register 13.3. CAPSENSE0_DATA: Measurement Data
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
DATA
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CAPSENSE0_DATA = 0x4002_3020
Table 13.5. CAPSENSE0_DATA Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
DATA
Function
Must write reset value.
Capacitive Sensing Data.
This field stores the result from the last completed 12- to 16-bit capacitive sensing
conversion.
Rev. 1.0
225
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Register 13.4. CAPSENSE0_SCAN: Channel Scan Enable
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
SCANEN
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CAPSENSE0_SCAN = 0x4002_3030
Table 13.6. CAPSENSE0_SCAN Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
SCANEN
Channel Scan Enable.
This field selects which capacitive sensing channels will be included in the scan for
single scan or continuous scan modes. When MCEN is set to 1, the selected channels will be connected together internally for one capacitive measurement. A 1 in
this field enables the corresponding CSn.x channels. For example, a 1 in bit position
3 will enable the scan operation on CSn.3.
226
Rev. 1.0
Register 13.5. CAPSENSE0_CSTH: Compare Threshold
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
CSTH
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
CAPSENSE0_CSTH = 0x4002_3040
Table 13.7. CAPSENSE0_CSTH Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
CSTH
Compare Threshold.
When CMPEN is set to 1, this value is compared against the capacitive sensing
conversion result to generate an interrupt according to the polarity setting of CMPPOL.
Rev. 1.0
227
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Register 13.6. CAPSENSE0_MUX: Mux Channel Select
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
CSDISC
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Reserved
CSMX
RW
R
RW
1
0
0
0
0
Register ALL Access Address
CAPSENSE0_MUX = 0x4002_3050
Table 13.8. CAPSENSE0_MUX Register Bit Descriptions
Bit
Name
Function
31:8
Reserved
Must write reset value.
7
CSDISC
Channel Disconnect.
0: Connect the capacitive sensing circuit to the selected channel.
1: Disconnect the capacitive sensing input channel.
6:4
228
Reserved
Must write reset value.
Rev. 1.0
0
0
0
Table 13.8. CAPSENSE0_MUX Register Bit Descriptions
Bit
Name
3:0
CSMX
Function
Mux Channel Select.
This field selects one of the 16 input channels for the capacitive sensing conversion.
This selection is only used in single conversion and continuous single modes. In
scan modes, input selection is determined by the SCANEN field in the SCAN register.
0000: Select CSn.0.
0001: Select CSn.1.
0010: Select CSn.2.
0011: Select CSn.3.
0100: Select CSn.4.
0101: Select CSn.5.
0110: Select CSn.6.
0111: Select CSn.7.
1000: Select CSn.8.
1001: Select CSn.9.
1010: Select CSn.10.
1011: Select CSn.11.
1100: Select CSn.12.
1101: Select CSn.13.
1110: Select CSn.14.
1111: Select CSn.15.
Rev. 1.0
229
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
13.14. CAPSENSE0 Register Memory Map
Table 13.9. CAPSENSE0 Memory Map
CAPSENSE0_SCAN CAPSENSE0_DATA CAPSENSE0_MODE CAPSENSE0_CONTROL Register Name
0x4002_3030
ALL Address
0x4002_3010
0x4002_3020
0x4002_3000
ALL
Access Methods
ALL | SET | CLR
ALL
ALL | SET | CLR
Bit 31
Bit 30
Reserved
Bit 29
Bit 28
Bit 27
EOSI
Bit 26
CDI
Bit 25
CMPI
Bit 24
Reserved
Reserved
Reserved
Reserved
Bit 23
EOSIEN
Bit 22
CDIEN
Bit 21
CMPEN
Bit 20
Reserved
Bit 19
PMEF
Bit 18
Bit 17
PMMD
Bit 16
Bit 15
Bit 14
CSCM
DTSEL
Bit 13
Bit 12
Reserved
MCEN
Bit 11
Bit 10
IASEL
ACCMD
Bit 9
Bit 8
SCANEN
DATA
Bit 7
RAMPSEL
CNVR
Bit 6
Bit 5
CMD
Reserved
Bit 4
CMPPOL
Bit 3
BIASEN
Bit 2
CGSEL
CSEN
Bit 1
BUSYF
Bit 0
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
230
Rev. 1.0
CAPSENSE0_MUX CAPSENSE0_CSTH Register Name
0x4002_3050
0x4002_3040
ALL Address
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Reserved
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CSTH
CSDISC
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
CSMX
Bit 1
Bit 0
Table 13.9. CAPSENSE0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
231
Capacitive Sensing (CAPSENSE0)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
14. Comparator (CMP0 and CMP1)
This section describes the Comparator (CMP) module, and is applicable to all products in the following device
families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the CMP block, which is used by both CMP0 and CMP1 on all device families
covered in this document.
14.1. Comparator Features
The comparator takes two analog input voltages and outputs the relationship between these voltages (less than or
greater than). The comparator module includes the following features:
Multiple
sources for the positive and negative poles, including VDD, VREF, and up to 8 I/O pins.
outputs are available: a digital synchronous latched output and a digital asynchronous raw output.
Programmable hysteresis and response time.
Falling or rising edge interrupt options on the comparator output.
Two
CMPn Module
CMPnP.0
CMPnP.1
CMPnP.2
Programmable
Hysteresis
CMPnP.3
CMPnP.x
Inversion
Control
Internal
DAC
CMPn-
CMPnN.0
CMPnN.1
D
Q
Q
CMPnN.2
CMPnN.3
Programmable
Response Time
CMPnN.x
VSS
Figure 14.1. Comparator Block Diagram
232
CMPn_A
CMPn+
Rev. 1.0
CMPn_S
14.2. Overview
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs
that are optionally available at the port bank pins: a digital synchronous latched output (CMPn_S) and a digital
asynchronous raw output (CMPn_A). The asynchronous CMPn_A signal is available even when the system clock
is not active, allowing the comparator to operate and generate an output when the device is in some low power
modes.
The comparator also features an internal DAC that may be used to create a firmware-programmable threshold
voltage. The comparator DAC output level (DACLVL) field configures the DAC output voltage, and the input mux
select (INMUX) field enables the DAC output to the input of the comparator.
14.3. Inputs
When enabled (CMPEN = 1), the comparator performs an analog comparison of the voltage levels at its positive
(CMPn+) and negative (CMPn–) inputs. The CMPn+ and CMPn– inputs connect to select internal supplies or
external port pins through analog input multiplexers, configured by the positive analog input mux select (PMUX)
and negative analog input mux select (NMUX) fields in the MODE register. Any port bank pins selected as
comparator inputs should be configured as analog inputs, as described in the port configuration section. The CMP0
and CMP1 input channels vary between different package options, and are shown in table Table 14.1 and
Table 14.2. Note that for some selections, other device circuitry must be enabled.
The CMPn+ and CMPn– inputs have weak internal pull-ups that may be enabled by setting the positive input weak
pullup enable (PWPUEN) and negative input weak pullup enable (NWPUEN) bits.
Table 14.1. CMP0 Input Channels
CMP0 Input
CMP0 Input Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
CMP0P.0
External Positive Input
PB2.11
PB2.3
PB1.2
CMP0P.1
External Positive Input
PB2.13
PB3.0
PB3.0
CMP0P.2
External Positive Input
PB3.0
PB3.2
PB3.2
CMP0P.3
External Positive Input
PB3.2
PB3.4
Reserved
CMP0P.4
External Positive Input
PB3.4
PB3.6
Reserved
CMP0P.5
External Positive Input
PB3.6
PB3.8
Reserved
CMP0P.6
External Positive Input
PB3.8
Reserved
Reserved
CMP0P.7
External Positive Input
PB3.10
Reserved
Reserved
CMP0P.8
Internal Positive Input
Voltage at VREGIN / 4 (1)
CMP0P.9
Internal Positive Input
EXTVREG0 Current Sense (2)
CMP0P.10
Internal Positive Input
1.8 V Output of LDO
CMP0P.11
Internal Positive Input
Supply for Internal Oscillators (VDDOSC)
CMP0P.12
Internal Positive Input
VREF
Rev. 1.0
233
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Table 14.1. CMP0 Input Channels (Continued)
CMP0 Input
CMP0 Input Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
CMP0P.13
Internal Positive Input
VIO
CMP0P.14
Internal Positive Input
Voltage at VIOHD / 4 (3)
CMP0N.0
External Negative Input
PB2.12
PB2.2
PB1.3
CMP0N.1
External Negative Input
PB2.14
PB3.1
PB3.1
CMP0N.2
External Negative Input
PB3.1
PB3.3
PB3.3
CMP0N.3
External Negative Input
PB3.3
PB3.5
Reserved
CMP0N.4
External Negative Input
PB3.5
PB3.7
Reserved
CMP0N.5
External Negative Input
PB3.7
PB3.9
Reserved
CMP0N.6
External Negative Input
PB3.9
Reserved
Reserved
CMP0N.7
External Negative Input
PB3.11
Reserved
Reserved
CMP0N.8
Internal Negative Input
VDD
CMP0N.9
Internal Negative Input
VREF
Notes:
1. The VREGIN/4 option requires the VREGIN sense circuitry to be enabled within the VREG0 block
(VREG0_CONTROL.SENSEEN).
2. The EXTVREG0 Current Sense option requires the current sense circuit in the EXTVREG0 block to be
enabled (EXTVREG0_CSCONTROL.ADCISNSEN).
3. The VIOHD/4 option requires the VIOHD divider to be enabled within the PBHD block
(PBHD4_PBDRV.PBVTRKEN).
Table 14.2. CMP1 Input Channels
234
CMP1 Input
CMP1 Input Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
CMP1P.0
External Positive Input
PB2.11
PB2.3
PB1.2
CMP1P.1
External Positive Input
PB2.13
PB3.0
PB3.0
CMP1P.2
External Positive Input
PB3.0
PB3.2
PB3.2
CMP1P.3
External Positive Input
PB3.2
PB3.4
Reserved
CMP1P.4
External Positive Input
PB3.4
PB3.6
Reserved
Rev. 1.0
Table 14.2. CMP1 Input Channels (Continued)
CMP1 Input
CMP1 Input Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
CMP1P.5
External Positive Input
PB3.6
PB3.8
Reserved
CMP1P.6
External Positive Input
PB3.8
Reserved
Reserved
CMP1P.7
External Positive Input
PB3.10
Reserved
Reserved
CMP1P.8
Internal Positive Input
Voltage at VREGIN / 4 (1)
CMP1P.9
Internal Positive Input
EXTVREG0 Current Sense (2)
CMP1P.10
Internal Positive Input
1.8 V Output of LDO
CMP1P.11
Internal Positive Input
Supply for Internal Oscillators (VDDOSC)
CMP1P.12
Internal Positive Input
VREF
CMP1P.13
Internal Positive Input
VIO
CMP1P.14
Internal Positive Input
Voltage at VIOHD / 4 (3)
CMP1N.0
External Negative Input
PB2.12
PB2.2
PB1.3
CMP1N.1
External Negative Input
PB2.14
PB3.1
PB3.1
CMP1N.2
External Negative Input
PB3.1
PB3.3
PB3.3
CMP1N.3
External Negative Input
PB3.3
PB3.5
Reserved
CMP1N.4
External Negative Input
PB3.5
PB3.7
Reserved
CMP1N.5
External Negative Input
PB3.7
PB3.9
Reserved
CMP1N.6
External Negative Input
PB3.9
Reserved
Reserved
CMP1N.7
External Negative Input
PB3.11
Reserved
Reserved
CMP1N.8
Internal Negative Input
VDD
CMP1N.9
Internal Negative Input
VREF
Notes:
1. The VREGIN/4 option requires the VREGIN sense circuitry to be enabled within the VREG0 block
(VREG0_CONTROL.SENSEEN).
2. The EXTVREG0 Current Sense option requires the current sense circuit in the EXTVREG0 block to be
enabled (EXTVREG0_CSCONTROL.ADCISNSEN).
3. The VIOHD/4 option requires the VIOHD divider to be enabled within the PBHD block
(PBHD4_PBDRV.PBVTRKEN).
The CMPm module offers several different input modes shown in Table 14.3, configurable via the input mux select
(INMUX) field.
Rev. 1.0
235
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Table 14.3. Comparator Input Modes
INMUX Value
Input to CMPn+
Input to CMPn-
0
positive analog input mux output
negative analog input mux output
1
positive analog input mux output
VSS
2
DAC output with positive analog input mux
connected to internal DAC reference
negative analog input mux output
3
positive analog input mux output
DAC output with negative analog input mux
connected to internal DAC reference
Figure 14.2, Figure 14.3, Figure 14.4, and Figure 14.5 illustrate each of these configurations.
PMUX
CMPnP.0
CMPnP.1
CMPnP.2
CMPnP.3
CMPnP.x
CMPn+
NMUX
CMPnN.0
CMPn-
CMPnN.1
CMPnN.2
CMPnN.3
CMPnN.x
Figure 14.2. Comparator Input Mode 0 (INMUX = 0)
236
Rev. 1.0
PMUX
CMPnP.0
CMPnP.1
CMPnP.2
CMPnP.3
CMPn+
CMPnP.x
CMPnVSS
Figure 14.3. Comparator Input Mode 1 (INMUX = 1)
PMUX
CMPnP.0
CMPnP.1
CMPnP.2
CMPnP.3
Reference
CMPnP.x
DACLVL
CMPn+
Internal DAC
NMUX
CMPn-
CMPnN.0
CMPnN.1
CMPnN.2
CMPnN.3
CMPnN.x
Figure 14.4. Comparator Input Mode 2 (INMUX = 2)
Rev. 1.0
237
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
PMUX
CMPnP.0
CMPnP.1
CMPnP.2
CMPnP.3
CMPnP.x
CMPn+
NMUX
CMPnN.0
Reference
DACLVL
CMPnInternal DAC
CMPnN.1
CMPnN.2
CMPnN.3
CMPnN.x
Figure 14.5. Comparator Input Mode 3 (INMUX = 3)
238
Rev. 1.0
14.4. Outputs
When enabled (CMPEN = 1) and non-inverted (INVEN = 0), the comparator will output a 1 if the voltage at the
positive input (CMPn+) is higher than the voltage at the negative input (CMPn–). Firmware can set the INVEN bit to
1 to invert the comparator output polarity.
INVEN = 0
CMPnCMPn+
CMPn_S
INVEN = 1
CMPnCMPn+
CMPn_S
Figure 14.6. Output Configurations
The synchronous output (CMPn_S) is synchronized with the APB clock and may be polled by firmware, used as an
interrupt source, or routed to a port bank pin through the crossbar. The asynchronous comparator output
(CMPn_A) is not synchronized with the APB clock and is used by low power mode wake-up logic and reset
decision logic.
When the module is disabled (CMPEN = 0), the comparator will output a static 0 (INVEN = 0) or 1 (INVEN = 1).
Rev. 1.0
239
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
14.5. Response Time
The comparator response time may be configured in firmware using the CMPMD field. There are four settings
available, from Mode 0 (fastest response time and highest power) to Mode 3 (slowest response time and lowest
power). For lower power applications, selecting a slower response time reduces the module’s active supply
current.
The comparator rising edge and falling edge response times are typically not equal. The device data sheet
contains comparator timing and supply current specifications.
14.6. Hysteresis
The comparator module features programmable hysteresis that can be used to stabilize the comparator output
when a transition occurs on the input. The comparator output will not transition until the voltage on the comparator
CMPn+ input exceeds the threshold voltage on the CMPn– input by the amount programmed in the positive
hysteresis control (CMPHYP) field. Similarly, the comparator output will not transition until the voltage on the
comparator CMPn+ input falls below the threshold voltage on the CMPn– input by the amount programmed in the
negative hysteresis control (CMPHYN) field.
Figure 14.7 illustrates the programmable comparator hysteresis.
Positive programmable
hysteresis (CMPHYP)
CMPnCMPn+
Negative programmable
hysteresis (CMPHYN)
CMPn_S
Figure 14.7. Comparator Hysteresis
Both the positive and negative hysteresis control fields may be configured for 5, 10, or 20 mV hysteresis. Firmware
can disable positive or negative hysteresis by clearing CMPHYP or CMPHYN to 0.
14.7. Interrupts and Flags
The rising-edge (CMPRI) and falling-edge (CMPFI) interrupt flags allow firmware to determine whether the
comparator had a rising-edge or falling-edge output transition. The rising-edge interrupt enable (RIEN) and fallingedge interrupt enable (FIEN) bits can enable these flags as an interrupt source. The module hardware sets the
CMPRI and CMPFI flags when a corresponding rising or falling edge is detected, regardless of the interrupt enable
state. Once set, these flags remain set until cleared by firmware.
The comparator may detect false rising and falling edges during power-on or after changes are made to the
hysteresis or response time control bits. Firmware should explicitly clear the rising-edge and falling-edge flags to 0
a short time after enabling the comparator or changing the mode bits.
240
Rev. 1.0
14.8. CMP0 and CMP1 Registers
This section contains the detailed register descriptions for CMP0 and CMP1 registers.
Bit
31
30
Name
CMPEN
CMPOUT
Reserved
Type
RW
R
R
Reset
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Reserved
CMPRI
CMPFI
Register 14.1. CMPn_CONTROL: Module Control
29
28
Reserved
Type
R
RW
RW
R
Reset
0
0
0
0
27
0
26
0
25
24
0
0
23
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Register ALL Access Addresses
CMP0_CONTROL = 0x4001_F000
CMP1_CONTROL = 0x4002_0000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 14.4. CMPn_CONTROL Register Bit Descriptions
Bit
Name
31
CMPEN
Function
Comparator Enable.
0: Disable the comparator.
1: Enable the comparator.
30
CMPOUT
Output State.
This bit indicates the logic level of the comparator output. When INVEN is set, it
directly inverts the meaning of this bit.
0: Voltage on CMP+ < CMP- (INVEN = 0).
1: Voltage on CMP+ > CMP- (INVEN = 0).
29:15
Reserved
14
CMPRI
Must write reset value.
Rising Edge Interrupt Flag.
0: No comparator rising edge has occurred since this flag was last cleared.
1: A comparator rising edge occurred since last flag was cleared.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
241
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Table 14.4. CMPn_CONTROL Register Bit Descriptions
Bit
Name
13
CMPFI
Function
Falling Edge Interrupt Flag.
0: No comparator falling edge has occurred since this flag was last cleared.
1: A comparator falling edge occurred since last flag was cleared.
12:0
Reserved
Must write reset value.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
242
Rev. 1.0
30
29
Name
INVEN
Reserved
Type
RW
RW
R
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
Name
RIEN
FIEN
Reserved
24
23
22
CMPHYP
CMPHYN
NWPUEN
31
Reserved
28
PWPUEN
Bit
Reserved
Register 14.2. CMPn_MODE: Input and Module Mode
27
DACLVL
RW
RW
RW
RW
RW
0
0
0
0
0
0
8
7
6
5
4
3
CMPMD
INMUX
PMUX
NMUX
Type
R
RW
RW
R
RW
RW
RW
RW
Reset
0
0
0
0
1
26
0
25
0
0
0
21
0
0
20
0
19
0
18
17
16
0
0
0
2
1
0
0
0
0
Register ALL Access Addresses
CMP0_MODE = 0x4001_F010
CMP1_MODE = 0x4002_0010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 14.5. CMPn_MODE Register Bit Descriptions
Bit
Name
31
Reserved
30
INVEN
Function
Must write reset value.
Invert Comparator Output Enable.
0: Do not invert the comparator output.
1: Invert the comparator output.
29:28
Reserved
Must write reset value.
27:26
CMPHYP
Positive Hysteresis Control.
00: Disable positive hysteresis.
01: Set positive hysteresis to 5 mV.
10: Set positive hysteresis to 10 mV.
11: Set positive hysteresis to 20 mV.
25:24
CMPHYN
Negative Hysteresis Control.
00: Disable negative hysteresis.
01: Set negative hysteresis to 5 mV.
10: Set negative hysteresis to 10 mV.
11: Set negative hysteresis to 20 mV.
23
PWPUEN
Positive Input Weak Pullup Enable.
0: Disable the positive input weak pull up.
1: Enable the positive input weak pull up.
Rev. 1.0
243
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Table 14.5. CMPn_MODE Register Bit Descriptions
Bit
Name
22
NWPUEN
Function
Negative Input Weak Pullup Enable.
0: Disable the negative input weak pull up.
1: Enable the negative input weak pull up.
21:16
DACLVL
Comparator DAC Output Level.
These bits control the comparator reference DAC's output voltage. The voltage is
given by:
DACLVL
DAC Output = VREF   -----------------------
64
where VREF is the positive or negative comparator mux selection, as defined by
INMUX.
15
Reserved
14
RIEN
Must write reset value.
Rising Edge Interrupt Enable.
0: Disable the comparator rising edge interrupt.
1: Enable the comparator rising edge interrupt.
13
FIEN
Falling Edge Interrupt Enable.
0: Disable the comparator falling edge interrupt.
1: Enable the comparator falling edge interrupt.
12
Reserved
Must write reset value.
11:10
CMPMD
Comparator Mode.
00: Mode 0 (fastest response time, highest power consumption).
01: Mode 1.
10: Mode 2.
11: Mode 3 (slowest response time, lowest power consumption).
9:8
INMUX
Input MUX Select.
00: Connects the NMUX signal to CMP- and the PMUX signal to CMP+.
01: Connects VSS to CMP- and the PMUX signal to CMP+.
10: Connects the NMUX signal to CMP-, the PMUX signal to the Comparator DAC
voltage reference, and the DAC output to CMP+.
11: Connects the PMUX signal to CMP+, the NMUX signal to the Comparator DAC
voltage reference, and the DAC output to CMP-.
244
Rev. 1.0
Table 14.5. CMPn_MODE Register Bit Descriptions
Bit
Name
7:4
PMUX
Function
Positive Input Select.
0000: Select CMPnP.0.
0001: Select CMPnP.1.
0010: Select CMPnP.2.
0011: Select CMPnP.3.
0100: Select CMPnP.4.
0101: Select CMPnP.5.
0110: Select CMPnP.6.
0111: Select CMPnP.7.
1000: Select CMPnP.8.
1001: Select CMPnP.9.
1010: Select CMPnP.10.
1011: Select CMPnP.11.
1100: Select CMPnP.12.
1101: Select CMPnP.13.
1110: Select CMPnP.14.
1111: Select CMPnP.15.
3:0
NMUX
Negative Input Select.
0000: Select CMPnN.0.
0001: Select CMPnN.1.
0010: Select CMPnN.2.
0011: Select CMPnN.3.
0100: Select CMPnN.4.
0101: Select CMPnN.5.
0110: Select CMPnN.6.
0111: Select CMPnN.7.
1000: Select CMPnN.8.
1001: Select CMPnN.9.
1010: Select CMPnN.10.
1011: Select CMPnN.11.
1100: Select CMPnN.12.
1101: Select CMPnN.13.
1110: Select CMPnN.14.
1111: Select CMPnN.15.
Rev. 1.0
245
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
14.9. CMPn Register Memory Map
Table 14.6. CMPn Memory Map
CMPn_MODE CMPn_CONTROL Register Name
ALL Offset
0x10
0x0
ALL | SET | CLR ALL | SET | CLR Access Methods
Reserved
Bit 31
CMPEN
INVEN
Bit 30
CMPOUT
Bit 29
Reserved
Bit 28
Bit 27
CMPHYP
Bit 26
Bit 25
CMPHYN
Bit 24
PWPUEN
Bit 23
Reserved
NWPUEN
Bit 22
Bit 21
Bit 20
Bit 19
DACLVL
Bit 18
Bit 17
Bit 16
Reserved
Bit 15
RIEN
CMPRI
Bit 14
FIEN
CMPFI
Bit 13
Reserved
Bit 12
Bit 11
CMPMD
Bit 10
Bit 9
INMUX
Bit 8
Bit 7
Reserved
Bit 6
PMUX
Bit 5
Bit 4
Bit 3
Bit 2
NMUX
Bit 1
Bit 0
Comparator (CMP0 and CMP1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: CMP0 = 0x4001_F000, CMP1 = 0x4002_0000
246
Rev. 1.0
15. Cyclic Redundancy Check (CRC0)
This section describes the Cyclic Redundancy Check (CRC) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the CRC block, which is used by all device families covered in this document.
15.1. CRC Features
The CRC module includes the following features:
Support
for four common polynomials (one 32-bit and three 16-bit options).
bit reversal for the CRC input.
Byte-order reorientation of words for the CRC input.
Word or half-word bit reversal of the CRC result.
Ability to configure and seed an operation in a single register write.
Support for single-cycle parallel (unrolled) CRC computation for 32- or 8-bit blocks.
Capability to CRC 32 bits of data per peripheral bus (APB) clock.
Byte-level
CRCn Module
RDATA
word or half-word
bit reversal
32-bit
byte
reorder
DATA
16-bit
byte
reorder
byte-level
bit
reversal
Seed
Hardware CRC
Calculation Unit
Polynomial
Figure 15.1. CRC0 Block Diagram
Rev. 1.0
247
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
15.2. Overview
The CRC module is designed to provide hardware calculations for flash memory verification and communications
protocols.
The CRC module supports four common polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE
802.3). The three supported 16-bit polynomials are 0x1021 (CCITT–16), 0x3D65 (IEC16–MBus), and 0x8005
(ZigBee, 802.15.4, and USB).
The CRC module will automatically detect non-word writes (byte, half-word, and non-aligned byte) and adjust the
internal calculation to only process the least-significant byte. Any word writes are treated as an entire word and all
32 bits will be considered in the CRC calculation update. The BMDEN bit can be used to force the CRC module to
treat all writes as bytes.
15.3. Interrupts
The CRC module does not have any interrupts associated with it.
15.4. DMA Configuration and Usage
A DMA channel may be used to transfer data into the CRC module. The CRC DATA register only supports word
and byte writes. Half-word writes to this register will be treated as byte writes. The recommended DMA usage
model is to use the DMA to transfer all available words of data and use firmware writes to capture any remaining
bytes. To write data into the CRC module, the DMA must move one word of data at a time from the source location
in memory to the internal DATA register in non-incrementing mode. Firmware can then write any remaining bytes to
the DATA register and read the CRC result from the DATA register. The CRC DATA register should not be directly
written to or read from when targeted by a DMA channel.
SiM3xxxx
Address Space
DMA Module
CRCn Input Data
DMA Block
CRCn Module
RDATA
word or half-word
bit reversal
DMA Block
32-bit
byte
reorder
DATA
16-bit
byte
reorder
byte-level
bit
reversal
Seed
DMA Block
Polynomial
Figure 15.2. CRC DMA Configuration
248
Rev. 1.0
Hardware CRC
Calculation Unit
For the CRC module, the DMA channel should be set up as follows:
Source
size and Destination Size are 2 for a word transfer.
of transfers is N - 1, where N is the number of 4-byte words.
RPOWER = 0 (1 word transfer per transaction).
To start a DMA operation with the CRC module out of any device reset:
Number
1. Set up the DMA channel for the CRC Input.
2. Configure the CRC peripheral operation in the CONTROL register.
3. Start the DMA transfer.
4. Wait for DMA completion interrupt.
5. Write any remaining bytes to the DATA register to complete the CRC calculation for the memory block.
6. Read the CRC result from DATA or the bit-reversed CRC result from RDATA.
15.5. Byte-Level Bit Reversal and Byte Reordering
The byte-level bit reversal and byte reordering operations occur before the data is used in the CRC calculation.
These operations can occur on words or half words. The hardware ignores the ORDER field with any byte writes or
operations with byte mode enabled (BMDEN = 1), but the bit reversal settings (BBREN) are still applied to the byte.
Using an ORDER bits setting of 10b for 32-bit big endian byte order with BBREN set to 1 for byte-level bit reversal
allows big endian data to be treated like 32-bit little endian data with MSB-first bit ordering, as shown in
Figure 15.3.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 0
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 2
bit 2
bit 3
bit 4
bit 5
bit 6
Input data is big endian
bit 7
Byte 3
ORDER bits set to 10b for
32-bit big endian swap
bit 2
bit 1
bit 0
bit 5
bit 6
bit 7
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 3
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 2
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Byte 0
BBREN bit set to 1 for
byte-level bit reversal
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 3
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 2
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 1
bit 5
bit 4
bit 3
bit 2
bit 1
Data is now little endian for
CRC calculation
bit 0
Byte 0
Figure 15.3. CRC Data Ordering Example—Big Endian to Little Endian
Rev. 1.0
249
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Using an ORDER bits setting of 01b for 16-bit big endian byte order with BBREN set to 1 for byte-level bit reversal
allows big endian data to be treated by 16-bit little endian data with MSB-first bit ordering, as shown in Figure 15.4.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 0
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 2
bit 2
bit 3
bit 4
bit 5
bit 6
Input data is big endian
bit 7
Byte 3
ORDER bits set to 01b for
16-bit big endian swap
bit 2
bit 1
bit 0
bit 5
bit 6
bit 7
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 0
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
Byte 3
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Byte 2
BBREN bit set to 1 for
byte-level bit reversal
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 1
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Byte 3
bit 5
bit 4
bit 3
bit 2
Data is now 16-bit little
endian for CRC calculation
bit 1
Byte 2
bit 0
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Figure 15.4. CRC Data Ordering Example—Big Endian to 16-bit Little Endian
250
Rev. 1.0
Assuming a word input byte order of B3 B2 B1 B0, the values used in the CRC calculation for the various settings
of the byte-level bit reversal and byte reordering are shown in Table 15.1.
Table 15.1. Byte-Level Bit Reversal and Byte Reordering Results (B3 B2 B1 B0 Input Order)
Original CRC Calculation Method
Polynomial
Width (bits)
Byte Order
32
little endian
LSB
32
little endian
32
Equivalent CRC Settings
Bit Order
ORDER bits
(MSB/LSB first)
setting
BBREN bit
setting
Input to CRC
calculation
00 (none)
0
B3 B2 B1 B0
MSB
10 (32-bit)
1
‘B0 ‘B1 ‘B2 ‘B3
big endian
LSB
10 (32-bit)
0
B0 B1 B2 B3
32
big endian
MSB
00 (none)
1
‘B3 ‘B2 ‘B1 ‘B0
16
little endian
LSB
00 (none)
0
B3 B2 B1 B0
16
little endian
MSB
01 (16-bit)
1
‘B2 ‘B3 ‘B0 ‘B1
16
big endian
LSB
01 (16-bit)
0
B2 B3 B0 B1
16
big endian
MSB
00 (none)
1
‘B3 ‘B2 ‘B1 ‘B0
8
—
LSB
—
0
XX XX XX B0
8
—
MSB
—
1
XX XX XX ‘B0
Notes:
3. X indicates a “don’t care.”
4. Bn is the byte field within the word.
5. ‘Bn is the bit-reversed byte field within the word.
Rev. 1.0
251
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
15.6. CRC0 Registers
This section contains the detailed register descriptions for CRC0 registers.
Register 15.1. CRC0_CONTROL: Module Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RW
R
Name
Reserved
ORDER
Type
R
RW
RW
0
0
Reset
0
0
0
0
0
0
0
0
0
SINITEN
0
SEED
0
CRCEN
0
Reserved
0
POLYSEL
0
BMDEN
Reset
BBREN
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
RW
R
RW
W
W
0
0
0
0
0
Register ALL Access Address
CRC0_CONTROL = 0x4002_8000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 15.2. CRC0_CONTROL Register Bit Descriptions
Bit
Name
31:12
Reserved
11:10
ORDER
Function
Must write reset value.
Input Processing Order.
Controls the input order of the bytes in a 32-bit word to the CRC calculation unit.
This setting has no effect in byte mode.
00: No byte reorientation (output is same order as input).
01: Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1).
10: Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3).
11: Reserved.
9
BBREN
Byte-Level Bit Reversal Enable.
Controls the input order of the bits in each byte to the CRC calculation unit. When
set to 1, byte-level bit reversal is enabled and the bits in each byte are reversed.
0: No byte-level bit reversal (input is same order as written).
1: Byte-level bit reversal enabled (the bits in each byte are reversed).
8
BMDEN
Byte Mode Enable.
Enables byte mode, where all writes to the DATA register are considered as 8-bit
writes. When set to 1, only the least-significant byte of the data word will be used for
the CRC calculation.
0: Disable byte mode (word/byte width is determined automatically by the hardware).
1: Enable byte mode (all writes are considered as bytes).
252
Rev. 1.0
Table 15.2. CRC0_CONTROL Register Bit Descriptions
Bit
Name
Function
7:6
Reserved
Must write reset value.
5:4
POLYSEL
Polynomial Selection.
Selects the polynomial used by the CRC calculations.
00: Select 32-bit polynomial: 0x04C11DB7.
01: Select 16-bit polynomial: 0x1021.
10: Select 16-bit polynomial: 0x3D65.
11: Select 16-bit polynomial: 0x8005.
3
Reserved
2
CRCEN
Must write reset value.
CRC Enable.
Enables CRC functionality. Until this bit is set to 1, writes to the DATA register do not
result in CRC operations. Byte reorientation and bit reversal is still active even if
CRCEN is cleared to 0.
0: Disable CRC operations.
1: Enable CRC operations.
1
SEED
Seed Setting.
Determines the value of all CRC register bits when a 1 is written to the SINITEN bit.
This bit always reads back as 0.
0: CRC seed value is all 0's (0x00000000)
1: CRC seed value is all 1's (0xFFFFFFFF).
0
SINITEN
Seed Initialization Enable.
When this bit is set to 1, all bits of the CRC register are initialized to the value determined by the SEED bit setting. This bit always reads back as 0.
0: Do not initialize the CRC module to the value set by the SEED bit.
1: Initialize the CRC module to the value set by the SEED bit.
Rev. 1.0
253
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Register 15.2. CRC0_DATA: Input/Result Data
Bit
31
30
29
28
27
26
25
24
23
Name
DATA[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
DATA[15:0]
Type
RW
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Address
CRC0_DATA = 0x4002_8010
Table 15.3. CRC0_DATA Register Bit Descriptions
Bit
Name
31:0
DATA
Function
Input/Result Data.
If the CRCEN bit is set to 1, data written to this register will be used for CRC calculations, byte-level bit reversal, and byte reordering. The current CRC result can be
read from this register at any time.
If the CRCEN bit is cleared to 0, data written to this register will be used for bytelevel bit reversal and byte reordering only.
No delay is required between writing the data and reading the CRC or reordering
result.
Notes:
1. Reads of this register modify the state of hardware. Debug logic should take care when reading this register.
2. The access methods for this register are restricted. Do not use half-word access methods on this register.
254
Rev. 1.0
Register 15.3. CRC0_RDATA: Bit-Reversed Output Data
Bit
31
30
29
28
27
26
25
24
23
Name
RDATA[31:16]
Type
R
22
21
20
19
18
17
16
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
RDATA[15:0]
Type
R
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Address
CRC0_RDATA = 0x4002_8020
Table 15.4. CRC0_RDATA Register Bit Descriptions
Bit
Name
31:0
RDATA
Function
Bit-Reversed Output Data.
This register provides the bit reversed version of the DATA register. When the 32-bit
CRC polynomial is selected, the reversal occurs on the entire 32-bit word. When a
16-bit CRC polynomial is selected, the least-significant half-word (bits [15:0]) is
reversed.
Rev. 1.0
255
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
15.7. CRC0 Register Memory Map
Table 15.5. CRC0 Memory Map
CRC0_RDATA CRC0_DATA CRC0_CONTROL Register Name
ALL Address
0x4002_8020 0x4002_8010
0x4002_8000
ALL
ALL
ALL | SET | CLR Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Reserved
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RDATA
DATA
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
ORDER
Bit 10
BBREN
Bit 9
BMDEN
Bit 8
Bit 7
Reserved
Bit 6
Bit 5
POLYSEL
Bit 4
Reserved
Bit 3
CRCEN
Bit 2
SEED
Bit 1
SINITEN
Bit 0
Cyclic Redundancy Check (CRC0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
256
Rev. 1.0
16. DMA Controller (DMACTRL0)
This section describes the DMA Controller (DMACTRL) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the DMATRL block, which is used by all device families covered in this
document.
16.1. DMA Controller Features
The DMA Controller module includes the following features:
Utilizes
ARM PrimeCell uDMA architecture.
16 channels.
DMA crossbar supports direct peripheral data requests and maps peripherals to each channel.
Supports primary, alternate, and scatter-gather channel transfer structures to implement various types of
transfers.
Access allowed to all APB and AHB memory space.
The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without
spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the
system, as the device can spend more time in low-power modes.
Implements
Rev. 1.0
257
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMAXBARn
Module
Peripheral 0.0
SiM3xxxx
RAM
DMACTRLn
Module
Channel Control
Channel Status
DMA Channel 0
(DMAn_CH0)
DMA Channel 1
(DMAn_CH1)
Peripheral 0.2
Peripheral 0.3
Source Pointer
Destination Pointer
Configuration
Source Pointer
Destination Pointer
Configuration
Peripheral 0.x
Peripheral 1.0
Peripheral 1.1
Peripheral 1.2
Channel Software
Transfer Request
Peripheral 1.3
Global Controller
State and Enable
DMA Channel n
(DMAn_CHx)
Arbitration
Peripheral 0.1
Source Pointer
Destination Pointer
Peripheral 1.y
Configuration
Peripheral n.0
Peripheral n.1
Peripheral n.2
Peripheral n.3
Peripheral n.z
Figure 16.1. DMACTRL and DMACH Block Diagram
258
Rev. 1.0
16.2. Overview
The DMA controller provides a single access point for all 16 DMA channels and the global DMA controls. The
controller is also responsible for handling arbitration between channels.
Each channel has separate enables, alternate enables, masks, software requests, programmable priority, and
status flags. The channels operate independently, but have a fixed arbitration order.
The channels have controls and flags in the DMACTRL registers. In addition, each channel has several transfer
structures stored in memory that describe the data transfer in detail. Each channel can have a primary, alternate, or
scatter-gather structures. The BASEPTR and ABASEPTR registers point to the starting address of these
structures in memory. Firmware sets the BASEPTR field, and the controller hardware automatically sets the
ABASEPTR field based on the number of channels implemented in the module.
The NUMCHAN field in the STATUS register reports the number of channels implemented on a device. The STATE
field reports the current status of the DMA controller, and the DMAENS bit indicates whether the global DMA
enable is set.
16.3. Interrupts
Each DMA channel has a separate interrupt vector, and a channel will generate an interrupt at the end of the
current transfer. Firmware can enable or disable the interrupts in the NVIC.
16.4. Configuring a DMA Channel
To configure a DMA channel for a data transfer:
1. Enable the DMA module (DMAEN = 1).
2. Set the address location of the channel transfer structures (BASEPTR) according to the restrictions in
Table 16.1.
3. Create the primary and any alternate or scatter-gather data structures in memory for the desired transfer.
4. Enable the DMA channel using the CHENSET register.
5. Submit a request to start the transfer.
For software-initiated transfers, a request starts by setting the channel’s software request in the CHSWRCN
register. It is recommended that firmware set the channel request mask (CHREQMSET) for channels using
software-initiated transfers to avoid any peripherals connected to the channel from requesting DMA transfers.
For peripheral transfers, firmware should configure the peripheral for the DMA transfer and set the device’s DMA
crossbar (DMAXBAR) to map a DMA channel to the peripheral. The peripheral will request data as needed. The
channel request mask (CHREQMCLR) must be cleared for the channel to use peripheral transfers.
The CHALTSET register can set a DMA channel to use the alternate structure instead of the primary structure.
Firmware can use the CHALTCLR register to set the channel back to the primary structure. The controller
automatically updates the CHALTSET fields to indicate which structure is in use during transfers that use the
alternate structure (ping-pong and scatter-gather).
Rev. 1.0
259
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
16.5. DMA Channel Transfer Structures
Each channel has transfer structures stored in memory that describe the data transfer in detail. Each structure is
composed of four 32-bit words in memory organized as follows:
1. Source End Pointer (word 1): The address of the last source data in the transfer.
2. Destination End Pointer (word 2): The last destination address of the transfer.
3. Channel Configuration (word 3): Configuration details for the transfer.
4. Alignment padding (word 4): Not used by the DMA controller. Firmware my use this word for any purpose.
Each channel can have a primary, alternate, and scatter-gather structures. The primary and alternate structures
are organized in contiguous blocks in memory for each of the channels. The spacing for these structures is fixed,
so any unused channels must still be accounted for when placing structures in memory. In addition to the fixed
structure, the base address (BASEPTR) supports between 22- and 27-bit addresses, depending on the number of
channels implemented. The primary structures must be placed at the start of an address block sized for both the
primary and alternate structures. Table 16.1 shows the valid base pointer addresses for each range of
implemented channels.
The scatter-gather structures are more flexible and can appear anywhere in memory.
Table 16.1. Valid Base Pointer Addresses
Number of Channels
Implemented
Base Pointer Size
(BASEPTR)
Valid Primary Channel Transfer
Structure Addresses
Required Number of Bytes
(Primary and Alternate)
1
27 bits [31:5]
multiples of 16 (0x00000010)
32
2
26 bits [31:6]
multiples of 32 (0x00000020)
64
3-4
25 bits [31:7]
multiples of 64 (0x00000040)
128
5-8
24 bits [31:8]
multiples of 128 (0x00000080)
256
9-16
23 bits [31:9]
multiples of 256 (0x00000100)
512
17-32
22 bits [31:10]
multiples of 512 (0x00000200)
1024
Channel 0’s primary structure begins at address offset 0x0000, Channel 1’s primary structure starts at offset
0x0010, and so on. The alternate structures begin after the last primary structure location for the number of
implemented channels, regardless of whether or not the channels are in use.
Firmware originally sets the channel configuration descriptor; the DMA controller will modify this word as the
transfer progresses, so firmware should not access this descriptor until any active transfers for the channel
complete.
Figure 16.2 shows the fixed memory configuration for the structures.
260
Rev. 1.0
SiM3xxxx
Address Space (RAM)
CONFIG
DSTEND
Channel 0
SG 2
SRCEND
CONFIG
DSTEND
(Optional)
Scatter-Gather
Structures
Channel 0
SG 1
SRCEND
CONFIG
DSTEND
Channel x
SRCEND
Alternate
Structures
CONFIG
DSTEND
Channel 1
SRCEND
CONFIG
DSTEND
ABASEPTR
Channel 0
SRCEND
CONFIG
DSTEND
Channel x
SRCEND
Primary
Structures
CONFIG
DSTEND
Channel 1
SRCEND
CONFIG
DSTEND
BASEPTR
Channel 0
SRCEND
Figure 16.2. Channel Transfer Structure Memory Configuration
Rev. 1.0
261
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
16.5.1. Channel Transfer Structure Descriptors
Table 16.2, Table 16.3, Table 16.4 describe the source end pointer, destination pointer, and configuration
descriptors for the primary, alternate, and scatter-gather DMA channel structures.
Table 16.2. DMA0_CHx_SRCEND: Source End Pointer
Bit
31
30
29
28
27
26
25
Name
Bit
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
SRCEND[31:16]
15
14
13
12
11
10
9
8
Name
7
SRCEND[15:0]
Address in Channel Transfer Structure: 0x0000
Bit
Name
31:0
SRCEND
Function
Source End Pointer.
This field is the address of the last source data in the DMA transfer.
Table 16.3. DMA0_CHx_DSTEND: Destination End Pointer
Bit
31
30
29
28
27
26
25
Name
Bit
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DSTEND[31:16]
15
14
13
12
11
10
9
Name
8
7
DSTEND[15:0]
Address in Channel Transfer Structure: 0x0004
Bit
Name
31:0
DSTEND
Function
Destination End Pointer.
This field is the last destination address of the DMA transfer.
262
Rev. 1.0
Table 16.4. DMA0_CHx_CONFIG: Channel Configuration
15
14
13
26
25
12
11
23
22
SRCSIZE
24
10
9
21
20
19
18
17
3
2
1
Reserved
8
7
6
5
4
NCOUNT
16
RPOWER[3:2]
27
SRCAIMD
28
Reserved
Name
29
DSTSIZE
Name
Bit
30
DSTAIMD
31
RPOWER[1:0]
Bit
0
TMD
Address in Channel Transfer Structure: 0x0008
Bit
Name
31:30
DSTAIMD
Function
Destination Address Increment Mode.
This field must be set to a value that's equal to or greater than the DSTSIZE setting.
00: The destination address increments by one byte after each data transfer.
01: The destination address increments by one half-word after each data transfer.
10: The destination address increments by one word after each data transfer.
11: The destination address does not increment.
29:28
DSTSIZE
Destination Data Size Select.
The destination size (DSTSIZE) must equal the source size (SRCSIZE).
00: Each DMA destination data transfer writes a byte.
01: Each DMA destination data transfer writes a half-word.
10: Each DMA destination data transfer writes a word.
11: Reserved.
27:26
SRCAIMD
Source Address Increment Mode.
This field must be set to a value that's equal to or greater than the SRCSIZE setting.
00: The source address increments by one byte after each data transfer.
01: The source address increments by one half-word after each data transfer.
10: The source address increments by one word after each data transfer.
11: The source address does not increment.
25:24
SRCSIZE
Source Data Size Select.
The destination size (DSTSIZE) must equal the source size (SRCSIZE).
00: Each DMA source data transfer reads a byte.
01: Each DMA source data transfer reads a half-word.
10: Each DMA source data transfer reads a word.
11: Reserved.
23:18
Reserved
Must write 0 to this field.
Rev. 1.0
263
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Bit
Name
17:14
RPOWER
Function
Transfer Size Select.
This field determines the number of data transfers between each DMA channel re-arbitration. The number of data transfers is given by:
Number of Transfers = 2
RPOWER
This field is ignored for peripherals that support single data requests only. A value of 0
for RPOWER should be used for channels interfacing with these types of peripherals.
13:4
NCOUNT
Transfer Total.
This field is the total number of transfers for the DMA channel. The total number is
NCOUNT + 1, so software requiring a total of 4 transfers would set the NCOUNT field
to 3.
The DMA controller decrements this field as transfers are made.
3
Reserved
2:0
TMD
Must write 0 to this bit.
Transfer Mode.
000: Stop the DMA channel.
001: Use the Basic transfer type (single structure only).
010: Use the Auto-Request transfer type (single structure only).
011: Use the Ping-Pong transfer type (primary and alternate structures).
100: Use the Memory Scatter-Gather Primary transfer type (primary, alternate, and
scattered structures).
101: Use the Memory Scatter-Gather Alternate transfer type (primary, alternate, and
scattered structures).
110: Use the Peripheral Scatter-Gather Primary transfer type (primary, alternate, and
scattered structures).
111: Use the Peripheral Scatter-Gather Alternate transfer type (primary, alternate, and
scattered structures).
264
Rev. 1.0
16.6. Transfer Types
The DMA channels support five transfer types: basic, auto-request, ping-pong, memory scatter-gather, and
peripheral scatter-gather. Table 16.5 shows the memory requirements for each transfer type.
Table 16.5. Transfer Memory Requirements
Transfer Type
Transfer Structures Required
Primary Alternate ScatterGather
Memory (RAM) Required (bytes)
5-8 Channels
Implemented
9-16 Channels 17-32 Channels
Implemented
Implemented
Basic

128
256
512
Auto-Request

128
256
512
Ping-Pong


256
512
1024
Memory Scatter-Gather



256 + SG
512 + SG
1024 + SG
Peripheral Scatter-Gather



256 + SG
512 + SG
1024 + SG
16.6.1. Basic Transfers
The basic transfer type uses only one structure (primary or alternate). In this mode, the channel will make
NCOUNT + 1 data moves in 2RPOWER bursts. Each data request moves one 2RPOWER set of data. The number of
requests required for a transfer is:
NCOUNT + 1Number of Requests = -----------------------------------RPOWER
2
Equation 16.1. Number of Requests for Basic Transfers
Any data remaining can be transferred by firmware or use an extra DMA data request.
After the final data transfer:
1. The DMA channel will write the primary structure TMD field with 0.
2. The primary structure NCOUNT field will contain 0.
3. The controller automatically disables the channel (the channel bit in CHENSET will read 0).
Figure 16.3 illustrates the DMA memory structures for a basic transfer.
This transfer type is recommended for peripheral to memory or memory to peripheral transfers.
Rev. 1.0
265
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
ABASEPTR
SiM3xxxx
Address Space (RAM)
Primary
Structures
CONFIG
DSTEND
BASEPTR
Channel 0
SRCEND
Figure 16.3. Basic and Auto-Request Transfer Memory Configuration
16.6.2. Auto-Request Transfers
Auto-request transfers use only one structure (primary or alternate). This transfer type only requires one data
request to transfer all of the data. The controller will arbitrate as normal (every 2RPOWER transfers), and a channel
interrupt will occur when the transfer completes. This transfer type is recommended for memory to memory
transfers.
After the final data transfer:
1. The DMA channel will write the primary structure TMD field with 0.
2. The primary structure NCOUNT field will contain 0.
3. The controller automatically disables the channel (the channel bit in CHENSET will read 0).
The auto-request memory configuration is identical to the basic transfer shown in Figure 16.3.
266
Rev. 1.0
16.6.3. Ping-Pong Transfers
Ping-pong transfers use both the primary and alternate channel structures. When the channel completes the
transfer described by the first structure, it clears the TMD field in the original structure to 0 and toggles to point to
the other structure. A channel interrupt will occur to allow firmware to update the completed transfer’s structure, as
the ping-pong operation will stop without intervention.
As with basic transfers, each 2RPOWER data moves require a new data request. The number of requests is given by
Equation 16.1.
Figure 16.4 shows an example where a channel’s primary structure has an RPOWER of 1 with an NCOUNT of 3
and the alternate structure has an RPOWER of 0 with an NCOUNT of 4. These structures are both configured to
move words (DSTSIZE and SRCSIZE set to 2) in ping-pong mode (TMD = 3).
Figure 16.5 illustrates the ping-pong memory configuration.
alternate structure TMD set to 0,
channel switches to primary
primary structure
TMD set to 0,
channel switches to
alternate
data request data request
DMA
Channel 0
moves
2 words
Idle
data request
moves
2 words
Idle
moves
moves moves
Idle
1 word
1 word 1 word
DMA channel
interrupt
Firmware
loads
primary
structure
loads
alternate
structure
idle or performing other
tasks
Primary Structure
(RPOWER = 1,
NCOUNT = 3)
data request
data request
data request
data request
Idle
moves moves
1 word 1 word
DMA channel
interrupt
loads
primary
structure
idle or performing other tasks
primary structure TMD set to 0,
all transfers stop until firmware
configures a structure
passes
through ISR,
data moves
are done
Idle
DMA channel
interrupt
idle or
performing
other tasks
passes
through ISR,
data moves
are done
Primary Structure
(RPOWER = 0,
NCOUNT = 3)
Alternate Structure
(RPOWER = 0,
NCOUNT = 4)
Figure 16.4. Ping-Pong Transfer Example
Rev. 1.0
267
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
SiM3xxxx
Address Space (RAM)
Alternate
Structures
CONFIG
DSTEND
ABASEPTR
Channel 0
SRCEND
Primary
Structures
CONFIG
DSTEND
BASEPTR
Channel 0
SRCEND
Figure 16.5. Ping-Pong Transfer Memory Configuration
268
Rev. 1.0
16.6.4. Memory Scatter-Gather Transfers
The memory scatter-gather transfer uses primary, alternate, and scatter-gather structures. This transfer type allows
a DMA channel to be set for multiple transfers at once without core intervention at the price of extra memory for the
scatter-gather structures.
The primary structure in this mode contains the number and location of the scatter-gather structures. The primary
structure should be programmed as follows:
1. Memory scatter-gather primary mode (TMD = 4).
2. RPOWER = 2.
3. NCOUNT set to the value specified by Equation 16.2.
4. SRCEND is set to the location of the last word of all the scatter-gather structures.
5. DSTEND is set to the location of the last word in the single alternate structure.
NCOUNT =  Number of SG Structures  4  – 1
Equation 16.2. NCOUNT Value for Scatter-Gather Transfers
The scatter-gather structures must be stacked contiguously in memory. The channel will copy the scatter-gather
structures into the alternate structure location and execute them one by one. The scatter-gather structures should
be programmed to memory scatter-gather alternate mode (TMD = 5), except for the last structure, which should
use the basic or auto-request transfer types (TMD = 1 or 2).
Once started, the DMA channel execution process is as follows:
1. Copy scatter-gather 1 (SG1) to the alternate structure.
2. Jump to the alternate structure and execute.
3. Jump back to the primary structure.
4. Copy scatter-gather 2 (SG2) to the alternate structure.
5. Jump to the alternate structure and execute.
6. Jump back to the primary structure.
The channel will continue in this pattern until the channel encounters a scatter-gather structure set to a basic or
auto-request transfer.
Only one data request is required to execute all of the scattered transactions. The channel interrupt will occur once
the last scatter-gather structure (programmed to a basic transfer) executes, if enabled. Arbitration occurs every
2RPOWER of the scatter-gather structures.
Figure 16.6 shows the memory scatter-gather memory configuration.
Rev. 1.0
269
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
SiM3xxxx
Address Space (RAM)
CONFIG
DSTEND
Channel 0
SG 2
SRCEND
CONFIG
DSTEND
(Optional)
Scatter-Gather
Structures
Channel 0
SG 1
SRCEND
Alternate
Structures
CONFIG
DSTEND
ABASEPTR
Channel 0
SRCEND
Primary
Structures
CONFIG
DSTEND
BASEPTR
Channel 0
SRCEND
Figure 16.6. Memory and Peripheral Scatter-Gather Transfer Memory Configuration
270
Rev. 1.0
16.6.5. Peripheral Scatter-Gather Transfers
The peripheral scatter-gather transfer is very similar to the memory scatter-gather transfer and uses primary,
alternate, and scatter-gather structures. This transfer type allows a DMA channel to be set for multiple transfers at
once without core intervention at the price of extra memory for the scatter-gather structures. A data request is
required for each 2RPOWER data move of the scatter-gather structure tasks. The RPOWER value can be different
for each scatter-gather task. Equation 16.1 describes the total number of data requests required to complete a
transfer.
The primary structure in this mode contains the number and location of the scatter-gather structures. The primary
structure should be programmed as follows:
1. Peripheral scatter-gather primary mode (TMD = 6).
2. RPOWER = 2.
3. NCOUNT set to the value specified by Equation 16.2.
4. SRCEND is set to the location of the last word of all the scatter-gather structures.
5. DSTEND is set to the location of the last word in the single alternate structure.
The scatter-gather structures must be stacked contiguously in memory. The channel will copy the scatter-gather
structures into the alternate structure location and execute them one by one. The scatter-gather structures should
be programmed to peripheral scatter-gather alternate mode (TMD = 7), except for the last structure, which should
use the basic or auto-request transfer types (TMD = 1 or 2).
Once started, the DMA channel execution process is as follows:
1. Copy scatter-gather 1 (SG1) to the alternate structure.
2. Jump to the alternate structure and execute.
3. Jump back to the primary structure.
4. Copy scatter-gather 2 (SG2) to the alternate structure.
5. Jump to the alternate structure and execute.
6. Jump back to the primary structure.
The channel will continue in this pattern until the channel encounters a scatter-gather structure set to a basic or
auto-request transfer.
The channel interrupt will occur once the last scatter-gather structure (programmed to a basic transfer) executes, if
enabled.
Figure 16.6 shows the peripheral scatter-gather memory configuration.
Rev. 1.0
271
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
16.7. Data Requests
Each DMA channel has two data requests: single and burst. Peripherals can support single requests, burst
requests, or both. If configured to use a DMA channel, peripherals request data as needed using the appropriate
request type. Table 16.6 lists the supported requests for the supported triggers and peripherals.
The RPOWER field is only valid for peripherals that support burst requests. For peripherals that only support single
requests, the RPOWER field is ignored and re-arbitration occurs after every single data move.
Table 16.6. Supported Trigger or Peripheral Data Requests
Peripheral Module
Supported
Request Types
AESn
burst only
EPCAn
burst only
I2Cn
single only
I2Sn
burst only
IDACn
burst only
SARADCn
burst only
SPIn
burst only
TIMERn overflow
burst only
USARTn
single only
USBn
both
External Trigger
burst only
Software Trigger
burst only
In addition to peripheral-initiated transfers, all of the supported DMA channels can select the rising or falling edges
of one of the DMA external transfer start signals to initiate data transfers. When the selected edge occurs on the
external signal, the DMA channels with the DMA0T0/1 signals selected in the DMAXBARx.CHANnSEL field will
start the corresponding channel’s data transfer as defined by the DMA channel data structure in memory. The DMA
module external trigger sources vary between package options, and are detailed in Table 16.7.
Table 16.7. DMA External Triggers
272
DMA Trigger
DMA Trigger Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
DMA0T0
External Transfer Start
PB1.10
PB1.4
PB0.10
DMA0T1
External Transfer Start
PB1.11
PB1.5
PB0.11
Rev. 1.0
16.8. Masking Channels
DMA channels can be temporarily disabled by setting the channel bit in CHREQMSET. Setting this bit to 1 causes
the DMA channel to no longer respond to data requests from peripherals. The channel will always respond to
software-initiated transfer requests, even if CHREQMSET is set for the channel. Firmware can write a 1 to the
CHREQMCLR register to clear the mask for a channel.
It is recommended that firmware set the channel request mask (CHREQMSET) for channels using softwareinitiated transfers to avoid any peripherals connected to the channel from requesting DMA transfers.
16.9. Errors
The ERROR bit in the BERRCLR register indicates when a DMA bus error occurs. This bit may or may not
generate an interrupt on a SiM3U1xx/SiM3C1xx device. For devices that do not support DMA bus error interrupts,
firmware should check this flag after a DMA transfer to determine if an error occurred.
Rev. 1.0
273
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
16.10. Arbitration
The DMA controller is a master on the AHB bus. This allows the module to control data transfers without any
interaction with the core.
The channels are in a fixed priority order. Channel 0 has the highest priority, and the last implemented channel has
the lowest priority. This fixed order can be superceded by using the programmable high priority setting
(CHHPSET). At each re-arbitration period, the controller gives control of the bus to the highest priority channel with
a pending data request.
The RPOWER field in the channel transfer structures determines when the re-arbitration periods occur. The
channel in control of the bus will make 2RPOWER data moves before the controller re-arbitrates. If the channel still
has the highest priority, it can transfer again until the next re-arbitration period. The RPOWER field is only valid for
peripherals that support burst requests. For peripherals that only support single requests, re-arbitration will occur
after each single data move.
Figure 16.7 shows an example controller arbitration with two channels active. Channel 0 has an RPOWER of 1 (2
data moves), and channel 1 has an RPOWER of 0 (1 data move). Both channels are set to move words (DSTSIZE
and SRCSIZE set to 2).
data request
Channel 0
(RPOWER = 1)
Idle
moves
2 words
Re-arbitration period
Channel 0 has a pending
request and highest priority
Channel 1
(RPOWER = 0)
Idle
moves
2 words
Idle
Re-arbitration period
Channel 0 has a pending
request and highest priority
moves
1 word
data request
Re-arbitration period
Channel 1 has a pending
request and highest priority
data request
Idle
moves
1 word
data request
Re-arbitration period
no pending data requests
Idle
moves
1 word
data request
Figure 16.7. DMA Arbitration Example
274
Rev. 1.0
Idle
16.11. DMACTRL0 Registers
This section contains the detailed register descriptions for DMACTRL0 registers.
Register 16.1. DMACTRL0_STATUS: Controller Status
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
NUMCHAN
Type
R
R
16
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
STATE
Reserved
DMAENSTS
Reset
Type
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_STATUS = 0x4003_6000
Table 16.8. DMACTRL0_STATUS Register Bit Descriptions
Bit
Name
31:21
Reserved
20:16
NUMCHAN
Function
Must write reset value.
Number of Supported DMA Channels.
This value represents one less than the number of supported DMA channels on the
device. For example, a value of 15 in this field means 16 channels are supported on
the device.
15:8
Reserved
Must write reset value.
7:4
STATE
State Machine State.
This field indicates the current state of the control state machine.
0000: Idle.
0001: Reading channel controller data.
0010: Reading source data end pointer.
0011: Reading destination data end pointer.
0100: Reading source data.
0101: Writing destination data.
0110: Waiting for a DMA request to clear.
0111: Writing channel controller data.
1000: Stalled.
1001: Done.
1010: Peripheral scatter-gather transition.
1011-1111: Reserved.
Rev. 1.0
275
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.8. DMACTRL0_STATUS Register Bit Descriptions
Bit
Name
3:1
Reserved
0
DMAENSTS
Function
Must write reset value.
DMA Enable Status.
0: DMA controller is disabled
1: DMA controller is enabled.
276
Rev. 1.0
Register 16.2. DMACTRL0_CONFIG: Controller Configuration
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
W
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
DMAEN
Reset
Type
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CONFIG = 0x4003_6004
Table 16.9. DMACTRL0_CONFIG Register Bit Descriptions
Bit
Name
31:1
Reserved
0
DMAEN
Function
Must write reset value.
DMA Enable.
0: Disable the DMA controller.
1: Enable the DMA controller.
Rev. 1.0
277
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.3. DMACTRL0_BASEPTR: Base Pointer
Bit
31
30
29
28
27
26
25
24
23
Name
BASEPTR[26:11]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Name
BASEPTR[10:0]
Reserved
Type
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_BASEPTR = 0x4003_6008
Table 16.10. DMACTRL0_BASEPTR Register Bit Descriptions
Bit
Name
31:5
BASEPTR
Function
Control Base Pointer.
This field points to the base location in memory for the DMA channel control data
structure. This field is left justified and is a different size depending on the number of
channels implemented on the device.
1 channel: bits [31:5] specify the base address (multiples of 16).
2 channels: bits [31:6] specify the base address (multiples of 32).
3-4 channels: bits [31:7] specify the base address (multiples of 64).
5-8 channels: bits [31:8] specify the base address (multiples of 128).
9-16 channels: bits [31:9] specify the base address (multiples of 256).
17-32 channels: bits [31:10] specify the base address (multiples of 512).
Any unused bits are undefined and should be written to 0. The primary structures
must be placed at the start of an address block sized for both the primary and alternate structures.
4:0
278
Reserved
Must write reset value.
Rev. 1.0
Register 16.4. DMACTRL0_ABASEPTR: Alternate Base Pointer
Bit
31
30
29
28
27
26
25
24
23
22
Name
ABASEPTR[31:16]
Type
R
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
ABASEPTR[15:0]
Type
R
Reset
0
0
0
0
0
0
0
1
0
Register ALL Access Address
DMACTRL0_ABASEPTR = 0x4003_600C
Table 16.11. DMACTRL0_ABASEPTR Register Bit Descriptions
Bit
Name
31:0
ABASEPTR
Function
Alternate Control Base Pointer.
This read-only field points to the base location in memory for the alternate DMA
channel control data structure. This address depends on the number of channels
implemented on the device.
Rev. 1.0
279
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.5. DMACTRL0_CHSTATUS: Channel Status
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
R
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Register ALL Access Address
DMACTRL0_CHSTATUS = 0x4003_6010
Table 16.12. DMACTRL0_CHSTATUS Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Status.
0: DMA Channel 15 is not waiting for a data request.
1: DMA Channel 15 is waiting for a data request.
14
CH14
Channel 14 Status.
0: DMA Channel 14 is not waiting for a data request.
1: DMA Channel 14 is waiting for a data request.
13
CH13
Channel 13 Status.
0: DMA Channel 13 is not waiting for a data request.
1: DMA Channel 13 is waiting for a data request.
12
CH12
Channel 12 Status.
0: DMA Channel 12 is not waiting for a data request.
1: DMA Channel 12 is waiting for a data request.
11
CH11
Channel 11 Status.
0: DMA Channel 11 is not waiting for a data request.
1: DMA Channel 11 is waiting for a data request.
10
CH10
Channel 10 Status.
0: DMA Channel 10 is not waiting for a data request.
1: DMA Channel 10 is waiting for a data request.
9
CH9
Channel 9 Status.
0: DMA Channel 9 is not waiting for a data request.
1: DMA Channel 9 is waiting for a data request.
280
Rev. 1.0
Table 16.12. DMACTRL0_CHSTATUS Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Status.
0: DMA Channel 8 is not waiting for a data request.
1: DMA Channel 8 is waiting for a data request.
7
CH7
Channel 7 Status.
0: DMA Channel 7 is not waiting for a data request.
1: DMA Channel 7 is waiting for a data request.
6
CH6
Channel 6 Status.
0: DMA Channel 6 is not waiting for a data request.
1: DMA Channel 6 is waiting for a data request.
5
CH5
Channel 5 Status.
0: DMA Channel 5 is not waiting for a data request.
1: DMA Channel 5 is waiting for a data request.
4
CH4
Channel 4 Status.
0: DMA Channel 4 is not waiting for a data request.
1: DMA Channel 4 is waiting for a data request.
3
CH3
Channel 3 Status.
0: DMA Channel 3 is not waiting for a data request.
1: DMA Channel 3 is waiting for a data request.
2
CH2
Channel 2 Status.
0: DMA Channel 2 is not waiting for a data request.
1: DMA Channel 2 is waiting for a data request.
1
CH1
Channel 1 Status.
0: DMA Channel 1 is not waiting for a data request.
1: DMA Channel 1 is waiting for a data request.
0
CH0
Channel 0 Status.
0: DMA Channel 0 is not waiting for a data request.
1: DMA Channel 0 is waiting for a data request.
Rev. 1.0
281
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.6. DMACTRL0_CHSWRCN: Channel Software Request Control
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
W
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHSWRCN = 0x4003_6014
Table 16.13. DMACTRL0_CHSWRCN Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Software Request.
0: DMA Channel 15 does not generate a software data request.
1: DMA Channel 15 generates a software data request.
14
CH14
Channel 14 Software Request.
0: DMA Channel 14 does not generate a software data request.
1: DMA Channel 14 generates a software data request.
13
CH13
Channel 13 Software Request.
0: DMA Channel 13 does not generate a software data request.
1: DMA Channel 13 generates a software data request.
12
CH12
Channel 12 Software Request.
0: DMA Channel 12 does not generate a software data request.
1: DMA Channel 12 generates a software data request.
11
CH11
Channel 11 Software Request.
0: DMA Channel 11 does not generate a software data request.
1: DMA Channel 11 generates a software data request.
10
CH10
Channel 10 Software Request.
0: DMA Channel 10 does not generate a software data request.
1: DMA Channel 10 generates a software data request.
9
CH9
Channel 9 Software Request.
0: DMA Channel 9 does not generate a software data request.
1: DMA Channel 9 generates a software data request.
282
Rev. 1.0
Table 16.13. DMACTRL0_CHSWRCN Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Software Request.
0: DMA Channel 8 does not generate a software data request.
1: DMA Channel 8 generates a software data request.
7
CH7
Channel 7 Software Request.
0: DMA Channel 7 does not generate a software data request.
1: DMA Channel 7 generates a software data request.
6
CH6
Channel 6 Software Request.
0: DMA Channel 6 does not generate a software data request.
1: DMA Channel 6 generates a software data request.
5
CH5
Channel 5 Software Request.
0: DMA Channel 5 does not generate a software data request.
1: DMA Channel 5 generates a software data request.
4
CH4
Channel 4 Software Request.
0: DMA Channel 4 does not generate a software data request.
1: DMA Channel 4 generates a software data request.
3
CH3
Channel 3 Software Request.
0: DMA Channel 3 does not generate a software data request.
1: DMA Channel 3 generates a software data request.
2
CH2
Channel 2 Software Request.
0: DMA Channel 2 does not generate a software data request.
1: DMA Channel 2 generates a software data request.
1
CH1
Channel 1 Software Request.
0: DMA Channel 1 does not generate a software data request.
1: DMA Channel 1 generates a software data request.
0
CH0
Channel 0 Software Request.
0: DMA Channel 0 does not generate a software data request.
1: DMA Channel 0 generates a software data request.
Rev. 1.0
283
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.7. DMACTRL0_CHREQMSET: Channel Request Mask Set
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
RW
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH0
0
CH1
0
CH2
0
CH3
0
CH4
0
CH5
0
CH6
0
CH7
0
CH8
0
CH9
0
CH10
0
CH11
0
CH12
0
CH13
0
CH14
Reset
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHREQMSET = 0x4003_6020
Table 16.14. DMACTRL0_CHREQMSET Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Request Mask Enable.
Read:
0: DMA Channel 15 peripheral data requests enabled.
1: DMA Channel 15 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 15 peripheral data requests.
14
CH14
Channel 14 Request Mask Enable.
Read:
0: DMA Channel 14 peripheral data requests enabled.
1: DMA Channel 14 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 14 peripheral data requests.
13
CH13
Channel 13 Request Mask Enable.
Read:
0: DMA Channel 13 peripheral data requests enabled.
1: DMA Channel 13 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 13 peripheral data requests.
284
Rev. 1.0
Table 16.14. DMACTRL0_CHREQMSET Register Bit Descriptions
Bit
Name
12
CH12
Function
Channel 12 Request Mask Enable.
Read:
0: DMA Channel 12 peripheral data requests enabled.
1: DMA Channel 12 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 12 peripheral data requests.
11
CH11
Channel 11 Request Mask Enable.
Read:
0: DMA Channel 11 peripheral data requests enabled.
1: DMA Channel 11 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 11 peripheral data requests.
10
CH10
Channel 10 Request Mask Enable.
Read:
0: DMA Channel 10 peripheral data requests enabled.
1: DMA Channel 10 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 10 peripheral data requests.
9
CH9
Channel 9 Request Mask Enable.
Read:
0: DMA Channel 9 peripheral data requests enabled.
1: DMA Channel 9 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 9 peripheral data requests.
8
CH8
Channel 8 Request Mask Enable.
Read:
0: DMA Channel 8 peripheral data requests enabled.
1: DMA Channel 8 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 8 peripheral data requests.
7
CH7
Channel 7 Request Mask Enable.
Read:
0: DMA Channel 7 peripheral data requests enabled.
1: DMA Channel 7 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 7 peripheral data requests.
Rev. 1.0
285
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.14. DMACTRL0_CHREQMSET Register Bit Descriptions
Bit
Name
6
CH6
Function
Channel 6 Request Mask Enable.
Read:
0: DMA Channel 6 peripheral data requests enabled.
1: DMA Channel 6 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 6 peripheral data requests.
5
CH5
Channel 5 Request Mask Enable.
Read:
0: DMA Channel 5 peripheral data requests enabled.
1: DMA Channel 5 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 5 peripheral data requests.
4
CH4
Channel 4 Request Mask Enable.
Read:
0: DMA Channel 4 peripheral data requests enabled.
1: DMA Channel 4 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 4 peripheral data requests.
3
CH3
Channel 3 Request Mask Enable.
Read:
0: DMA Channel 3 peripheral data requests enabled.
1: DMA Channel 3 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 3 peripheral data requests.
2
CH2
Channel 2 Request Mask Enable.
Read:
0: DMA Channel 2 peripheral data requests enabled.
1: DMA Channel 2 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 2 peripheral data requests.
1
CH1
Channel 1 Request Mask Enable.
Read:
0: DMA Channel 1 peripheral data requests enabled.
1: DMA Channel 1 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 1 peripheral data requests.
286
Rev. 1.0
Table 16.14. DMACTRL0_CHREQMSET Register Bit Descriptions
Bit
Name
0
CH0
Function
Channel 0 Request Mask Enable.
Read:
0: DMA Channel 0 peripheral data requests enabled.
1: DMA Channel 0 peripheral data requests disabled.
Write:
0: No effect (use CHREQMCLR to clear).
1: Disable DMA Channel 0 peripheral data requests.
Rev. 1.0
287
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.8. DMACTRL0_CHREQMCLR: Channel Request Mask Clear
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
W
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHREQMCLR = 0x4003_6024
Table 16.15. DMACTRL0_CHREQMCLR Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 15 peripheral data requests.
14
CH14
Channel 14 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 14 peripheral data requests.
13
CH13
Channel 13 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 13 peripheral data requests.
12
CH12
Channel 12 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 12 peripheral data requests.
11
CH11
Channel 11 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 11 peripheral data requests.
10
CH10
Channel 10 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 10 peripheral data requests.
9
CH9
Channel 9 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 9 peripheral data requests.
288
Rev. 1.0
Table 16.15. DMACTRL0_CHREQMCLR Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 8 peripheral data requests.
7
CH7
Channel 7 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 7 peripheral data requests.
6
CH6
Channel 6 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 6 peripheral data requests.
5
CH5
Channel 5 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 5 peripheral data requests.
4
CH4
Channel 4 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 4 peripheral data requests.
3
CH3
Channel 3 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 3 peripheral data requests.
2
CH2
Channel 2 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 2 peripheral data requests.
1
CH1
Channel 1 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 1 peripheral data requests.
0
CH0
Channel 0 Request Mask Disable.
0: No effect.
1: Enable DMA Channel 0 peripheral data requests.
Rev. 1.0
289
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.9. DMACTRL0_CHENSET: Channel Enable Set
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
RW
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH0
0
CH1
0
CH2
0
CH3
0
CH4
0
CH5
0
CH6
0
CH7
0
CH8
0
CH9
0
CH10
0
CH11
0
CH12
0
CH13
0
CH14
Reset
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHENSET = 0x4003_6028
Table 16.16. DMACTRL0_CHENSET Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Enable.
Read:
0: DMA Channel 15 disabled.
1: DMA Channel 15 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 15.
14
CH14
Channel 14 Enable.
Read:
0: DMA Channel 14 disabled.
1: DMA Channel 14 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 14.
Notes:
1. The controller will automatically disable a channel when: 1) the controller completes the DMA cycle, 2) it reads a
channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR = 1) occurs on the AHB
bus.
290
Rev. 1.0
Table 16.16. DMACTRL0_CHENSET Register Bit Descriptions
Bit
Name
13
CH13
Function
Channel 13 Enable.
Read:
0: DMA Channel 13 disabled.
1: DMA Channel 13 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 13.
12
CH12
Channel 12 Enable.
Read:
0: DMA Channel 12 disabled.
1: DMA Channel 12 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 12.
11
CH11
Channel 11 Enable.
Read:
0: DMA Channel 11 disabled.
1: DMA Channel 11 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 11.
10
CH10
Channel 10 Enable.
Read:
0: DMA Channel 10 disabled.
1: DMA Channel 10 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 10.
9
CH9
Channel 9 Enable.
Read:
0: DMA Channel 9 disabled.
1: DMA Channel 9 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 9.
Notes:
1. The controller will automatically disable a channel when: 1) the controller completes the DMA cycle, 2) it reads a
channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR = 1) occurs on the AHB
bus.
Rev. 1.0
291
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.16. DMACTRL0_CHENSET Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Enable.
Read:
0: DMA Channel 8 disabled.
1: DMA Channel 8 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 8.
7
CH7
Channel 7 Enable.
Read:
0: DMA Channel 7 disabled.
1: DMA Channel 7 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 7.
6
CH6
Channel 6 Enable.
Read:
0: DMA Channel 6 disabled.
1: DMA Channel 6 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 6.
5
CH5
Channel 5 Enable.
Read:
0: DMA Channel 5 disabled.
1: DMA Channel 5 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 5.
4
CH4
Channel 4 Enable.
Read:
0: DMA Channel 4 disabled.
1: DMA Channel 4 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 4.
Notes:
1. The controller will automatically disable a channel when: 1) the controller completes the DMA cycle, 2) it reads a
channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR = 1) occurs on the AHB
bus.
292
Rev. 1.0
Table 16.16. DMACTRL0_CHENSET Register Bit Descriptions
Bit
Name
3
CH3
Function
Channel 3 Enable.
Read:
0: DMA Channel 3 disabled.
1: DMA Channel 3 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 3.
2
CH2
Channel 2 Enable.
Read:
0: DMA Channel 2 disabled.
1: DMA Channel 2 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 2.
1
CH1
Channel 1 Enable.
Read:
0: DMA Channel 1 disabled.
1: DMA Channel 1 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 1.
0
CH0
Channel 0 Enable.
Read:
0: DMA Channel 0 disabled.
1: DMA Channel 0 enabled.
Write:
0: No effect (use CHENCLR to clear).
1: Enable DMA Channel 0.
Notes:
1. The controller will automatically disable a channel when: 1) the controller completes the DMA cycle, 2) it reads a
channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR = 1) occurs on the AHB
bus.
Rev. 1.0
293
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.10. DMACTRL0_CHENCLR: Channel Enable Clear
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
W
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHENCLR = 0x4003_602C
Table 16.17. DMACTRL0_CHENCLR Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
CH15
Channel 15 Disable.
0: No effect.
1: Disable DMA Channel 15.
14
CH14
Channel 14 Disable.
0: No effect.
1: Disable DMA Channel 14.
13
CH13
Channel 13 Disable.
0: No effect.
1: Disable DMA Channel 13.
12
CH12
Channel 12 Disable.
0: No effect.
1: Disable DMA Channel 12.
11
CH11
Channel 11 Disable.
0: No effect.
1: Disable DMA Channel 11.
10
CH10
Channel 10 Disable.
0: No effect.
1: Disable DMA Channel 10.
Notes:
1. The controller will automatically disable a channel by setting the appropriate bit when: 1) the controller completes the
DMA cycle, 2) it reads a channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR
= 1) occurs on the AHB bus.
294
Rev. 1.0
Table 16.17. DMACTRL0_CHENCLR Register Bit Descriptions
Bit
Name
9
CH9
Function
Channel 9 Disable.
0: No effect.
1: Disable DMA Channel 9.
8
CH8
Channel 8 Disable.
0: No effect.
1: Disable DMA Channel 8.
7
CH7
Channel 7 Disable.
0: No effect.
1: Disable DMA Channel 7.
6
CH6
Channel 6 Disable.
0: No effect.
1: Disable DMA Channel 6.
5
CH5
Channel 5 Disable.
0: No effect.
1: Disable DMA Channel 5.
4
CH4
Channel 4 Disable.
0: No effect.
1: Disable DMA Channel 4.
3
CH3
Channel 3 Disable.
0: No effect.
1: Disable DMA Channel 3.
2
CH2
Channel 2 Disable.
0: No effect.
1: Disable DMA Channel 2.
1
CH1
Channel 1 Disable.
0: No effect.
1: Disable DMA Channel 1.
0
CH0
Channel 0 Disable.
0: No effect.
1: Disable DMA Channel 0.
Notes:
1. The controller will automatically disable a channel by setting the appropriate bit when: 1) the controller completes the
DMA cycle, 2) it reads a channel configuration memory location and the cycle control field is 0, or 3) an error (ERROR
= 1) occurs on the AHB bus.
Rev. 1.0
295
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.11. DMACTRL0_CHALTSET: Channel Alternate Select Set
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
RW
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH0
0
CH1
0
CH2
0
CH3
0
CH4
0
CH5
0
CH6
0
CH7
0
CH8
0
CH9
0
CH10
0
CH11
0
CH12
0
CH13
0
CH14
Reset
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHALTSET = 0x4003_6030
Table 16.18. DMACTRL0_CHALTSET Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Alternate Enable.
Read:
0: DMA Channel 15 is using primary data structure.
1: DMA Channel 15 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 15.
14
CH14
Channel 14 Alternate Enable.
Read:
0: DMA Channel 14 is using primary data structure.
1: DMA Channel 14 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 14.
Notes:
1. The controller toggles the value of the channel bit after it completes: 1) the four transfers that the primary data structure
specifies for a memory scatter-gather or peripheral scatter-gather DMA cycle, 2) all the transfers that the primary data
structure specifies for a ping-pong DMA cycle, or 3) all the transfers that the alternate data structure specifies for the
following DMA cycle types (ping-pong, memory scatter-gather, peripheral scatter-gather).
296
Rev. 1.0
Table 16.18. DMACTRL0_CHALTSET Register Bit Descriptions
Bit
Name
13
CH13
Function
Channel 13 Alternate Enable.
Read:
0: DMA Channel 13 is using primary data structure.
1: DMA Channel 13 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 13.
12
CH12
Channel 12 Alternate Enable.
Read:
0: DMA Channel 12 is using primary data structure.
1: DMA Channel 12 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 12.
11
CH11
Channel 11 Alternate Enable.
Read:
0: DMA Channel 11 is using primary data structure.
1: DMA Channel 11 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 11.
10
CH10
Channel 10 Alternate Enable.
Read:
0: DMA Channel 10 is using primary data structure.
1: DMA Channel 10 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 10.
9
CH9
Channel 9 Alternate Enable.
Read:
0: DMA Channel 9 is using primary data structure.
1: DMA Channel 9 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 9.
Notes:
1. The controller toggles the value of the channel bit after it completes: 1) the four transfers that the primary data structure
specifies for a memory scatter-gather or peripheral scatter-gather DMA cycle, 2) all the transfers that the primary data
structure specifies for a ping-pong DMA cycle, or 3) all the transfers that the alternate data structure specifies for the
following DMA cycle types (ping-pong, memory scatter-gather, peripheral scatter-gather).
Rev. 1.0
297
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.18. DMACTRL0_CHALTSET Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Alternate Enable.
Read:
0: DMA Channel 8 is using primary data structure.
1: DMA Channel 8 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 8.
7
CH7
Channel 7 Alternate Enable.
Read:
0: DMA Channel 7 is using primary data structure.
1: DMA Channel 7 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 7.
6
CH6
Channel 6 Alternate Enable.
Read:
0: DMA Channel 6 is using primary data structure.
1: DMA Channel 6 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 6.
5
CH5
Channel 5 Alternate Enable.
Read:
0: DMA Channel 5 is using primary data structure.
1: DMA Channel 5 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 5.
4
CH4
Channel 4 Alternate Enable.
Read:
0: DMA Channel 4 is using primary data structure.
1: DMA Channel 4 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 4.
Notes:
1. The controller toggles the value of the channel bit after it completes: 1) the four transfers that the primary data structure
specifies for a memory scatter-gather or peripheral scatter-gather DMA cycle, 2) all the transfers that the primary data
structure specifies for a ping-pong DMA cycle, or 3) all the transfers that the alternate data structure specifies for the
following DMA cycle types (ping-pong, memory scatter-gather, peripheral scatter-gather).
298
Rev. 1.0
Table 16.18. DMACTRL0_CHALTSET Register Bit Descriptions
Bit
Name
3
CH3
Function
Channel 3 Alternate Enable.
Read:
0: DMA Channel 3 is using primary data structure.
1: DMA Channel 3 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 3.
2
CH2
Channel 2 Alternate Enable.
Read:
0: DMA Channel 2 is using primary data structure.
1: DMA Channel 2 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 2.
1
CH1
Channel 1 Alternate Enable.
Read:
0: DMA Channel 1 is using primary data structure.
1: DMA Channel 1 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 1.
0
CH0
Channel 0 Alternate Enable.
Read:
0: DMA Channel 0 is using primary data structure.
1: DMA Channel 0 is using alternate data structure.
Write:
0: No effect (use CHALTCLR to clear).
1: Use the alternate data structure for DMA Channel 0.
Notes:
1. The controller toggles the value of the channel bit after it completes: 1) the four transfers that the primary data structure
specifies for a memory scatter-gather or peripheral scatter-gather DMA cycle, 2) all the transfers that the primary data
structure specifies for a ping-pong DMA cycle, or 3) all the transfers that the alternate data structure specifies for the
following DMA cycle types (ping-pong, memory scatter-gather, peripheral scatter-gather).
Rev. 1.0
299
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.12. DMACTRL0_CHALTCLR: Channel Alternate Select Clear
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
W
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHALTCLR = 0x4003_6034
Table 16.19. DMACTRL0_CHALTCLR Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 15.
14
CH14
Channel 14 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 14.
13
CH13
Channel 13 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 13.
12
CH12
Channel 12 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 12.
11
CH11
Channel 11 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 11.
10
CH10
Channel 10 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 10.
9
CH9
Channel 9 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 9.
300
Rev. 1.0
Table 16.19. DMACTRL0_CHALTCLR Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 8.
7
CH7
Channel 7 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 7.
6
CH6
Channel 6 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 6.
5
CH5
Channel 5 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 5.
4
CH4
Channel 4 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 4.
3
CH3
Channel 3 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 3.
2
CH2
Channel 2 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 2.
1
CH1
Channel 1 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 1.
0
CH0
Channel 0 Alternate Disable.
0: No effect.
1: Use the primary data structure for DMA Channel 0.
Rev. 1.0
301
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.13. DMACTRL0_CHHPSET: Channel High Priority Set
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
RW
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH0
0
CH1
0
CH2
0
CH3
0
CH4
0
CH5
0
CH6
0
CH7
0
CH8
0
CH9
0
CH10
0
CH11
0
CH12
0
CH13
0
CH14
Reset
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHHPSET = 0x4003_6038
Table 16.20. DMACTRL0_CHHPSET Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 High Priority Enable.
Read:
0: DMA Channel 15 is using the default priority level.
1: DMA Channel 15 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 15.
14
CH14
Channel 14 High Priority Enable.
Read:
0: DMA Channel 14 is using the default priority level.
1: DMA Channel 14 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 14.
13
CH13
Channel 13 High Priority Enable.
Read:
0: DMA Channel 13 is using the default priority level.
1: DMA Channel 13 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 13.
302
Rev. 1.0
Table 16.20. DMACTRL0_CHHPSET Register Bit Descriptions
Bit
Name
12
CH12
Function
Channel 12 High Priority Enable.
Read:
0: DMA Channel 12 is using the default priority level.
1: DMA Channel 12 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 12.
11
CH11
Channel 11 High Priority Enable.
Read:
0: DMA Channel 11 is using the default priority level.
1: DMA Channel 11 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 11.
10
CH10
Channel 10 High Priority Enable.
Read:
0: DMA Channel 10 is using the default priority level.
1: DMA Channel 10 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 10.
9
CH9
Channel 9 High Priority Enable.
Read:
0: DMA Channel 9 is using the default priority level.
1: DMA Channel 9 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 9.
8
CH8
Channel 8 High Priority Enable.
Read:
0: DMA Channel 8 is using the default priority level.
1: DMA Channel 8 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 8.
7
CH7
Channel 7 High Priority Enable.
Read:
0: DMA Channel 7 is using the default priority level.
1: DMA Channel 7 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 7.
Rev. 1.0
303
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.20. DMACTRL0_CHHPSET Register Bit Descriptions
Bit
Name
6
CH6
Function
Channel 6 High Priority Enable.
Read:
0: DMA Channel 6 is using the default priority level.
1: DMA Channel 6 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 6.
5
CH5
Channel 5 High Priority Enable.
Read:
0: DMA Channel 5 is using the default priority level.
1: DMA Channel 5 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 5.
4
CH4
Channel 4 High Priority Enable.
Read:
0: DMA Channel 4 is using the default priority level.
1: DMA Channel 4 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 4.
3
CH3
Channel 3 High Priority Enable.
Read:
0: DMA Channel 3 is using the default priority level.
1: DMA Channel 3 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 3.
2
CH2
Channel 2 High Priority Enable.
Read:
0: DMA Channel 2 is using the default priority level.
1: DMA Channel 2 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 2.
1
CH1
Channel 1 High Priority Enable.
Read:
0: DMA Channel 1 is using the default priority level.
1: DMA Channel 1 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 1.
304
Rev. 1.0
Table 16.20. DMACTRL0_CHHPSET Register Bit Descriptions
Bit
Name
0
CH0
Function
Channel 0 High Priority Enable.
Read:
0: DMA Channel 0 is using the default priority level.
1: DMA Channel 0 is using the high priority level.
Write:
0: No effect (use CHHPCLR to clear).
1: Use the high priority level for DMA Channel 0.
Rev. 1.0
305
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.14. DMACTRL0_CHHPCLR: Channel High Priority Clear
Bit
31
30
29
28
27
26
25
24
23
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
16
CH9
17
CH10
18
CH11
W
19
CH12
Type
20
CH13
Reserved
21
CH14
Name
22
CH15
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_CHHPCLR = 0x4003_603C
Table 16.21. DMACTRL0_CHHPCLR Register Bit Descriptions
Bit
Name
31:16
Reserved
15
CH15
Function
Must write reset value.
Channel 15 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 15.
14
CH14
Channel 14 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 14.
13
CH13
Channel 13 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 13.
12
CH12
Channel 12 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 12.
11
CH11
Channel 11 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 11.
10
CH10
Channel 10 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 10.
9
CH9
Channel 9 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 9.
306
Rev. 1.0
Table 16.21. DMACTRL0_CHHPCLR Register Bit Descriptions
Bit
Name
8
CH8
Function
Channel 8 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 8.
7
CH7
Channel 7 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 7.
6
CH6
Channel 6 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 6.
5
CH5
Channel 5 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 5.
4
CH4
Channel 4 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 4.
3
CH3
Channel 3 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 3.
2
CH2
Channel 2 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 2.
1
CH1
Channel 1 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 1.
0
CH0
Channel 0 High Priority Disable.
0: No effect.
1: Use the high default level for DMA Channel 0.
Rev. 1.0
307
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Register 16.15. DMACTRL0_BERRCLR: Bus Error Clear
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
ERROR
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMACTRL0_BERRCLR = 0x4003_604C
Table 16.22. DMACTRL0_BERRCLR Register Bit Descriptions
Bit
Name
Function
31:1
Reserved
Must write reset value.
0
ERROR
DMA Bus Error Clear.
Read:
0: DMA error did not occur.
1: DMA error occurred since the last time ERROR was cleared.
Write:
0: No effect.
1: Clear the DMA error flag.
308
Rev. 1.0
0
0
0
16.12. DMACTRL0 Register Memory Map
DMACTRL0_BASEPTR DMACTRL0_CONFIG DMACTRL0_STATUS Register Name
0x4003_6004
0x4003_6008
ALL Address
0x4003_6000
ALL
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Reserved
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
NUMCHAN
BASEPTR
Bit 18
Bit 17
Reserved
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Reserved
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
STATE
Bit 5
Bit 4
Bit 3
Reserved
Reserved
Bit 2
Bit 1
DMAENSTS
DMAEN
Bit 0
Table 16.23. DMACTRL0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
309
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.23. DMACTRL0 Memory Map
DMACTRL0_CHSWRCN DMACTRL0_CHSTATUS DMACTRL0_ABASEPTR Register Name
0x4003_6010
0x4003_600C
ALL Address
0x4003_6014
ALL
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
ABASEPTR
CH15
CH15
Bit 15
CH14
CH14
Bit 14
CH13
CH13
Bit 13
CH12
CH12
Bit 12
CH11
CH11
Bit 11
CH10
CH10
Bit 10
CH9
CH9
Bit 9
CH8
CH8
Bit 8
CH7
CH7
Bit 7
CH6
CH6
Bit 6
CH5
CH5
Bit 5
CH4
CH4
Bit 4
CH3
CH3
Bit 3
CH2
CH2
Bit 2
CH1
CH1
Bit 1
CH0
CH0
Bit 0
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
310
Rev. 1.0
DMACTRL0_CHENSET DMACTRL0_CHREQMCLR DMACTRL0_CHREQMSET Register Name
0x4003_6020
ALL Address
0x4003_6028
0x4003_6024
ALL
Access Methods
ALL
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
CH15
CH15
CH15
Bit 15
CH14
CH14
CH14
Bit 14
CH13
CH13
CH13
Bit 13
CH12
CH12
CH12
Bit 12
CH11
CH11
CH11
Bit 11
CH10
CH10
CH10
Bit 10
CH9
CH9
CH9
Bit 9
CH8
CH8
CH8
Bit 8
CH7
CH7
CH7
Bit 7
CH6
CH6
CH6
Bit 6
CH5
CH5
CH5
Bit 5
CH4
CH4
CH4
Bit 4
CH3
CH3
CH3
Bit 3
CH2
CH2
CH2
Bit 2
CH1
CH1
CH1
Bit 1
CH0
CH0
CH0
Bit 0
Table 16.23. DMACTRL0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
311
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Table 16.23. DMACTRL0 Memory Map
DMACTRL0_CHALTCLR DMACTRL0_CHALTSET DMACTRL0_CHENCLR Register Name
0x4003_602C
ALL Address
0x4003_6034
0x4003_6030
ALL
Access Methods
ALL
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
CH15
CH15
CH15
Bit 15
CH14
CH14
CH14
Bit 14
CH13
CH13
CH13
Bit 13
CH12
CH12
CH12
Bit 12
CH11
CH11
CH11
Bit 11
CH10
CH10
CH10
Bit 10
CH9
CH9
CH9
Bit 9
CH8
CH8
CH8
Bit 8
CH7
CH7
CH7
Bit 7
CH6
CH6
CH6
Bit 6
CH5
CH5
CH5
Bit 5
CH4
CH4
CH4
Bit 4
CH3
CH3
CH3
Bit 3
CH2
CH2
CH2
Bit 2
CH1
CH1
CH1
Bit 1
CH0
CH0
CH0
Bit 0
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
312
Rev. 1.0
DMACTRL0_BERRCLR DMACTRL0_CHHPCLR DMACTRL0_CHHPSET Register Name
0x4003_6038
ALL Address
0x4003_604C
0x4003_603C
ALL
Access Methods
ALL
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Reserved
Bit 16
CH15
CH15
Bit 15
CH14
CH14
Bit 14
CH13
CH13
Bit 13
CH12
CH12
Bit 12
CH11
CH11
Bit 11
CH10
CH10
Bit 10
CH9
CH9
Bit 9
CH8
CH8
Bit 8
CH7
CH7
Bit 7
CH6
CH6
Bit 6
CH5
CH5
Bit 5
CH4
CH4
Bit 4
CH3
CH3
Bit 3
CH2
CH2
Bit 2
CH1
CH1
Bit 1
ERROR
CH0
CH0
Bit 0
Table 16.23. DMACTRL0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
313
DMA Controller (DMACTRL0)
SiM3U1xx/SiM3C1xx
17. DMA Crossbar (DMAXBAR0)
This section describes the DMA Crossbar, and is applicable to all products in the following device families, unless
otherwise stated
SiM3U1xx
SiM3C1xx
17.1. DMA Crossbar Features
The DMA Crossbar includes the following features:
Maps
multiple peripherals to 16 DMA channels to provide flexibility.
Default arbitration priority assignment (Channel 0 highest, Channel 15 lowest).
Peripherals are assigned to various channels, and the DMA Crossbar can be used to assign a channel to a
particular peripheral. These assignments are shown in Table 17.1.
DMA Channel 13
DMA Channel 14
DMA Channel 15






DMAXT1


























AES0 XOR
EPCA0 Capture
EPCA0 Control

I2C0 RX

I2C0 TX














SARADC1




SARADC0
314


IDAC0
SPI0 TX


I2S TX
SPI0 RX


I2S RX
IDAC1


AES0 TX
DMA Channel 12


AES0 RX
DMA Channel 11

DMA Channel 9

DMA Channel 8

DMA Channel 7

DMA Channel 6

DMA Channel 5

DMA Channel 4

DMA Channel 3

DMA Channel 2

DMA Channel 1
DMAXT0
Peripheral
DMA Channel 10
Table 17.1. DMA Crossbar Channel Peripheral Assignments
DMA Channel 0
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx






Rev. 1.0

TIMER0L Overflow

TIMER0H Overflow

TIMER1L Overflow


TIMER1H Overflow


USART0 RX




























USART1 TX




USART0 TX




USB0 EP1 IN


USB0 EP2 IN


USB0 EP3 IN


USB0 EP4 IN


USB0 EP1 OUT


USB0 EP2 OUT


USB0 EP3 OUT
USB0 EP4 OUT

Software Trigger

DMA Channel 15
DMA Channel 14
DMA Channel 13
DMA Channel 12
DMA Channel 11
DMA Channel 10
DMA Channel 9

SPI1 TX
USART1 RX
DMA Channel 8
DMA Channel 7
DMA Channel 6
DMA Channel 5
DMA Channel 4
DMA Channel 3

DMA Channel 2
SPI1 RX
DMA Channel 1
Peripheral
DMA Channel 0
Table 17.1. DMA Crossbar Channel Peripheral Assignments (Continued)

















Notes:
1. USB0 Peripheral only available on SiM3U1xx devices.
17.2. Channel Priority
In addition to the default priority order where DMA Channel 0 has the highest priority and DMA Channel 15 has the
lowest priority, each channel supports a programmable priority. This priority can be programmed in the DMA
Controller module (DMACTRLn).
Rev. 1.0
315
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
17.3. DMAXBAR0 Registers
This section contains the detailed register descriptions for DMAXBAR0 registers.
Register 17.1. DMAXBAR0_DMAXBAR0: Channel 0-7 Trigger Select
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
CH7SEL
CH6SEL
CH5SEL
CH4SEL
Type
RW
RW
RW
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH3SEL
CH2SEL
CH1SEL
CH0SEL
Type
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMAXBAR0_DMAXBAR0 = 0x4003_7000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 17.2. DMAXBAR0_DMAXBAR0 Register Bit Descriptions
Bit
Name
31:28
CH7SEL
Function
DMA Channel 7 Peripheral Select.
0000: Service USB0 EP1 IN data requests.
0001: Service AES0 XOR data requests.
0010: Service SPI1 TX data requests.
0011: Service USART0 TX data requests.
0100: Service DMAXT0 rising edge data requests.
0101: Service DMAXT0 falling edge data requests.
0110: Service DMAXT1 rising edge data requests.
0111: Service DMAXT1 falling edge data requests.
1000: Service TIMER0L overflow data requests.
1001: Service TIMER1L overflow data requests.
1010: Service TIMER1H overflow data requests.
1011-1111: Reserved.
316
Rev. 1.0
0
0
0
Table 17.2. DMAXBAR0_DMAXBAR0 Register Bit Descriptions
Bit
Name
27:24
CH6SEL
Function
DMA Channel 6 Peripheral Select.
0000: Service USB0 EP2 IN data requests.
0001: Service AES0 RX data requests.
0010: Service USART0 RX data requests.
0011: Service I2C0 RX data requests.
0100: Service IDAC0 data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001: Service TIMER0H overflow data requests.
1010-1111: Reserved.
23:20
CH5SEL
DMA Channel 5 Peripheral Select.
0000: Service USB0 EP3 IN data requests.
0001: Service AES0 TX data requests.
0010: Service USART1 TX data requests.
0011: Service SARADC0 data requests.
0100: Service I2S0 RX data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001-1111: Reserved.
19:16
CH4SEL
DMA Channel 4 Peripheral Select.
0000: Service USB0 EP4 IN data requests.
0001: Service SPI1 TX data requests.
0010: Service USART0 TX data requests.
0011: Service SARADC0 data requests.
0100: Service I2S0 RX data requests.
0101: Service EPCA0 capture data requests.
0110: Service DMAXT0 rising edge data requests.
0111: Service DMAXT0 falling edge data requests.
1000: Service DMAXT1 rising edge data requests.
1001: Service DMAXT1 falling edge data requests.
1010: Service TIMER0H overflow data requests.
1011-1111: Reserved.
Rev. 1.0
317
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
Table 17.2. DMAXBAR0_DMAXBAR0 Register Bit Descriptions
Bit
Name
15:12
CH3SEL
Function
DMA Channel 3 Peripheral Select.
0000: Service USB0 EP1 OUT data requests.
0001: Service SARADC1 data requests.
0010: Service IDAC0 data requests.
0011: Service I2S0 TX data requests.
0100: Service EPCA0 capture data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001: Service TIMER1H overflow data requests.
1010-1111: Reserved.
11:8
CH2SEL
DMA Channel 2 Peripheral Select.
0000: Service USB0 EP2 OUT data requests.
0001: Service SPI0 TX data requests.
0010: Service USART0 TX data requests.
0011: Service SARADC0 data requests.
0100: Service IDAC1 data requests.
0101: Service I2S0 TX data requests.
0110: Service EPCA0 control data requests.
0111: Service DMAXT0 rising edge data requests.
1000: Service DMAXT0 falling edge data requests.
1001: Service DMAXT1 rising edge data requests.
1010: Service DMAXT1 falling edge data requests.
1011-1111: Reserved.
7:4
CH1SEL
DMA Channel 1 Peripheral Select.
0000: Service USB0 EP3 OUT data requests.
0001: Service SPI0 RX data requests.
0010: Service USART1 RX data requests.
0011: Service I2C0 RX data requests.
0100: Service IDAC1 data requests.
0101: Service EPCA0 control data requests.
0110: Service DMAXT0 rising edge data requests.
0111: Service DMAXT0 falling edge data requests.
1000: Service DMAXT1 rising edge data requests.
1001: Service DMAXT1 falling edge data requests.
1010: Service TIMER0L overflow data requests.
1011: Service TIMER1L overflow data requests.
1100: Service TIMER1H overflow data requests.
1101-1111: Reserved.
318
Rev. 1.0
Table 17.2. DMAXBAR0_DMAXBAR0 Register Bit Descriptions
Bit
Name
3:0
CH0SEL
Function
DMA Channel 0 Peripheral Select.
0000: Service USB0 EP4 OUT data requests.
0001: Service SPI1 RX data requests.
0010: Service USART0 RX data requests.
0011: Service I2C0 TX data requests.
0100: Service DMAXT0 rising edge data requests.
0101: Service DMAXT0 falling edge data requests.
0110: Service DMAXT1 rising edge data requests.
0111: Service DMAXT1 falling edge data requests.
1000: Service TIMER0L overflow data requests.
1001: Service TIMER0H overflow data requests.
1010: Service TIMER1L overflow data requests.
1011: Service TIMER1H overflow data requests.
1100-1111: Reserved.
Rev. 1.0
319
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
Register 17.2. DMAXBAR0_DMAXBAR1: Channel 8-15 Trigger Select
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
CH15SEL
CH14SEL
CH13SEL
CH12SEL
Type
RW
RW
RW
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CH11SEL
CH10SEL
CH9SEL
CH8SEL
Type
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
DMAXBAR0_DMAXBAR1 = 0x4003_7010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 17.3. DMAXBAR0_DMAXBAR1 Register Bit Descriptions
Bit
Name
31:28
CH15SEL
Function
DMA Channel 15 Peripheral Select.
0000: Service USB0 EP1 IN data requests.
0001: Service SARADC1 data requests.
0010: Service IDAC0 data requests.
0011: Service EPCA0 control data requests.
0100: Service DMAXT0 rising edge data requests.
0101: Service DMAXT0 falling edge data requests.
0110: Service DMAXT1 rising edge data requests.
0111: Service DMAXT1 falling edge data requests.
1000: Service TIMER0H overflow data requests.
1001: Service TIMER1H overflow data requests.
1010-1111: Reserved.
27:24
CH14SEL
DMA Channel 14 Peripheral Select.
0000: Service USB0 EP2 IN data requests.
0001: Service SPI0 TX data requests.
0010: Service USART0 TX data requests.
0011: Service IDAC0 data requests.
0100: Service EPCA0 control data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001: Service TIMER0L overflow data requests.
1010: Service TIMER1L overflow data requests.
1011-1111: Reserved.
320
Rev. 1.0
0
0
0
Table 17.3. DMAXBAR0_DMAXBAR1 Register Bit Descriptions
Bit
Name
23:20
CH13SEL
Function
DMA Channel 13 Peripheral Select.
0000: Service USB0 EP3 IN data requests.
0001: Service SPI0 RX data requests.
0010: Service USART0 RX data requests.
0011: Service IDAC1 data requests.
0100: Service I2S0 TX data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001: Service TIMER0H overflow data requests.
1010-1111: Reserved.
19:16
CH12SEL
DMA Channel 12 Peripheral Select.
0000: Service USB0 EP4 IN data requests.
0001: Service AES0 XOR data requests.
0010: Service USART1 TX data requests.
0011: Service SPI1 TX data requests.
0100: Service IDAC1 data requests.
0101: Service I2S0 TX data requests.
0110: Service DMAXT0 rising edge data requests.
0111: Service DMAXT0 falling edge data requests.
1000: Service DMAXT1 rising edge data requests.
1001: Service DMAXT1 falling edge data requests.
1010: Service TIMER0L overflow data requests.
1011: Service TIMER1L overflow data requests.
1100: Service TIMER1H overflow data requests.
1101-1111: Reserved.
15:12
CH11SEL
DMA Channel 11 Peripheral Select.
0000: Service USB0 EP1 OUT data requests.
0001: Service AES0 RX data requests.
0010: Service USART1 RX data requests.
0011: Service USART0 RX data requests.
0100: Service I2C0 RX data requests.
0101: Service I2S0 RX data requests.
0110: Service DMAXT0 rising edge data requests.
0111: Service DMAXT0 falling edge data requests.
1000: Service DMAXT1 rising edge data requests.
1001: Service DMAXT1 falling edge data requests.
1010: Service TIMER0H overflow data requests.
1011-1111: Reserved.
Rev. 1.0
321
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
Table 17.3. DMAXBAR0_DMAXBAR1 Register Bit Descriptions
Bit
Name
11:8
CH10SEL
Function
DMA Channel 10 Peripheral Select.
0000: Service USB0 EP2 OUT data requests.
0001: Service AES0 TX data requests.
0010: Service SARADC1 data requests.
0011: Service I2S0 RX data requests.
0100: Service DMAXT0 rising edge data requests.
0101: Service DMAXT0 falling edge data requests.
0110: Service DMAXT1 rising edge data requests.
0111: Service DMAXT1 falling edge data requests.
1000: Service TIMER1H overflow data requests.
1001-1111: Reserved.
7:4
CH9SEL
DMA Channel 9 Peripheral Select.
0000: Service USB0 EP3 OUT data requests.
0001: Service USART1 TX data requests.
0010: Service I2C0 TX data requests.
0011: Service EPCA0 capture data requests.
0100: Service DMAXT0 rising edge data requests.
0101: Service DMAXT0 falling edge data requests.
0110: Service DMAXT1 rising edge data requests.
0111: Service DMAXT1 falling edge data requests.
1000: Service TIMER0H overflow data requests.
1001-1111: Reserved.
3:0
CH8SEL
DMA Channel 8 Peripheral Select.
0000: Service USB0 EP4 OUT data requests.
0001: Service USART1 RX data requests.
0010: Service SPI1 RX data requests.
0011: Service USART0 RX data requests.
0100: Service EPCA0 capture data requests.
0101: Service DMAXT0 rising edge data requests.
0110: Service DMAXT0 falling edge data requests.
0111: Service DMAXT1 rising edge data requests.
1000: Service DMAXT1 falling edge data requests.
1001-1111: Reserved.
322
Rev. 1.0
17.4. DMAXBAR0 Register Memory Map
DMAXBAR0_DMAXBAR1 DMAXBAR0_DMAXBAR0 Register Name
ALL Address
0x4003_7010
0x4003_7000
Access Methods
ALL | SET | CLR
ALL | SET | CLR
Bit 31
Bit 30
CH15SEL
CH7SEL
Bit 29
Bit 28
Bit 27
Bit 26
CH14SEL
CH6SEL
Bit 25
Bit 24
Bit 23
Bit 22
CH13SEL
CH5SEL
Bit 21
Bit 20
Bit 19
Bit 18
CH12SEL
CH4SEL
Bit 17
Bit 16
Bit 15
Bit 14
CH11SEL
CH3SEL
Bit 13
Bit 12
Bit 11
Bit 10
CH10SEL
CH2SEL
Bit 9
Bit 8
Bit 7
Bit 6
CH9SEL
CH1SEL
Bit 5
Bit 4
Bit 3
Bit 2
CH8SEL
CH0SEL
Bit 1
Bit 0
Table 17.4. DMAXBAR0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
323
DMA Crossbar (DMAXBAR0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18. External Memory Interface (EMIF0)
This section describes the External Memory Interface (EMIF) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the EMIF block, which is used by all device families covered in this document.
18.1. EMIF Features
The External Memory Interface allows external parallel asynchronous devices, like SRAMs, NOR flash memories,
and LCD controllers, to appear as part of the system memory map. The EMIF module includes the following
features:
Provides
a memory mapped view of multiple external devices.
for byte, half-word and word accesses regardless of external device data-width.
Error indicator for certain invalid transfers.
Minimum external timing allows for 3 clocks per write or 4 clocks per read.
Output bus can be shared between non-muxed and muxed devices.
Extended address output allows for up to 16-bit (non-muxed mode) or 24-bit (muxed mode) address.
Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals.
Support for internally muxed devices with dynamic address shifting.
Fully programmable control signal waveforms.
Support
PBCFG0 Module
SiM3xxxx
External RAM
EMIF Enable
EMIF0 Module
EMIF Width
Global Interface
Control
CS1 and BE0b
Enable
Global EMIF
Status
PBn Modules
AD0m / D0
AD1m / D1
EMIF0_IF0 Interface
AD7m / D7
AD8m / A0
Interface
Configuration
Interface State
Control
AD15m / A7
A16m / A8
Interface Timing
Interface State
Control
A22m / A14
A23m / A15
WR
EMIF0_IF1 Interface
OE
ALEm
Interface
Configuration
Interface State
Control
Interface Timing
Interface State
Control
CS0
BE1
CS1 (optional)
Figure 18.1. EMIF and EMIFIF Block Diagram (Muxed Configuration)
324
Rev. 1.0
BE0 (optional)
18.2. Overview
The EMIF module is a parallel bus that consists of one global control and multiple, independent interfaces. Each
address or data bit requires a separate physical pin to implement the parallel EMIF interface. The global control
and status registers enable the interfaces individually (IFxEN) and report the status of the EMIF pins.
The EMIF0_IFx interfaces are accessed using different memory spaces in the external RAM region of the device,
starting at address 0x60000000. Each interface is 16 MB in size, so interface 0 begins at address 0x60000000 and
interface 1 begins at 0x68000000. The interfaces have separate chip select (CSx) signals. Writing to or reading
from the address space of an interface automatically triggers the associated chip select signal. These signals may
need to be separately enabled using the device port configuration module.
SiM3xxxx
External RAM
EMIFn_IF1 Interface
0x70000000
0x68000000
Interface
Configuration
Interface State
Control
Interface Timing
Interface State
Control
EMIFn_IF0 Interface
0x60000000
Interface
Configuration
Interface State
Control
Interface Timing
Interface State
Control
Figure 18.2. External Memory Organization
The EMIF module supports two bus configurations: multiplexed, and non-multiplexed. In non-multiplexed mode,
the address and data signals are separate. In multiplexed mode, the address and data signals are shared. An
external latch that triggers from the address latch enable (ALEm) control output is required when an interface
operates in multiplexed mode and interfaces with a non-multiplexed slave device. This external latch captures the
address in the first half of the transaction so the pins can transition to the data phase in the second half of the
transaction. For internally multiplexed slave devices, the EMIF module supports dynamic address shifting and
separate byte enable signals.
In addition to the two supported bus configurations, when used in multiplexed mode the EMIF interfaces support
both 8-bit and 16-bit data bus widths.
The EMIF interfaces can be independently configured to use different bus configurations and bus widths.
Rev. 1.0
325
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.3. Signal Descriptions
The EMIF consists of the following signals: address and data, write signal (WR), output enable (OE), address latch
enable (ALEm), chip select (CSx), and byte enable (BE0, BE1). The chip select signals are unique for each
interface supported, but all other signals are shared between interfaces.
18.3.1. Address and Data
The address and data signals are A16m-A23m, AD0m-AD15m in multiplexed mode and A0-A15, D0-D7 in nonmultiplexed mode. Each address or data bit requires a separate physical pin to implement the parallel EMIF
interface. The timing of the address and data signals are controlled by the address and data setup and hold times
for each interface. Non-multiplexed mode supports an 8-bit data bus. Multiplexed mode supports 8 or 16-bit data
buses. The BUSWIDTH bit in the EMIF interfaces selects the width of the data bus for that interface.
The EMIF address width is configured using the EMIFWIDTH field in the PBCFG0_CONTROL1 register. In nonmultiplexed mode, the device supports address widths between 0 and 16. The EMIFWIDTH field directly
determines how many address lines are used. In multiplexed mode, the device supports address widths between 8
and 24. In muxed mode, the number of address lines are equal to EMIFWIDTH + 8. An additional option when
operating in multiplexed mode with a 16-bit data bus is “dynamic address shifting”, in which the address signals
A23-A1 are shifted relative to the data signals. More information on dynamic address shifting can be found in
“18.6.1. Dynamic Address Shifting” .
Table 18.1 shows the signal mapping for each of the configuration options. These pins are shared between all
interfaces supported on the device.
Table 18.1. Address and Data Signal Mapping
Data sheet
Pin Name
Non-Multiplexed
Mode (MUXMD = 0)
Multiplexed Mode (MUXMD = 1)
8-bit Data Bus
(BUSWIDTH = 0)
8-bit Data Bus
(BUSWIDTH = 0)
AD0m / D0
AD1m / D1
--AD6m / D6
AD7m / D7
D0
D1
--D6
D7
AD8m / A0
AD9m / A1
--AD14m / A6
AD15m / A7
A16m / A8
A17m / A9
--A22m / A14
A23m / A15
326
16-bit Data Bus (BUSWIDTH = 1)
Address Shift
Disabled (ASEN = 0)
Address Shift
Enabled (ASEN = 1)
AD0
AD1
--AD6
AD7
AD0
AD1
--AD6
AD7
A1 / D0
A2 / D1
--A7 / D6
A8 / D7
A0
A1
--A6
A7
A8
A9
--A14
A15
AD8
AD9
--AD14
AD15
A9 / D8
A10 / D9
--A15 / D14
A16 / D15
A8
A9
--A14
A15
A16
A17
--A22
A23
A16
A17
--A22
A23
A17
A18
--A23
Rev. 1.0
18.3.2. Write Signal (WR)
The write signal pin (WR) indicates when a write to the slave device occurs. The state of the write signal pin during
address setup, address hold, data setup, and data hold is programmable for both read (IFRCST) and write
(IFWCST) transactions.
This pin is shared between all interfaces supported on the device.
18.3.3. Output Enable (OE)
The output enable (OE) signal enables the slave output pins for read operations. The state of the output enable pin
during address setup, address hold, data setup, and data hold is programmable for both read (IFRCST) and write
(IFWCST) transactions.
In addition to the programmable states, each interface supports an optional output enable delay configured using
the DELAYOE bit. When DELAYOE is set to 1, the interface will delay the assertion of the output enable signal by
half an AHB clock period.
This pin is shared between all interfaces supported on the device.
18.3.4. Address Latch Enable (ALEm)
The address latch enable (ALEm) signal is used in multiplexed bus modes with non-multiplexed slave devices only.
This signal controls the external address latch to capture the address during the first phase of the transaction, so
the pins can transition to the data in the second phase of the transaction.
The state of the ALEm pin during address setup, address hold, data setup, and data hold is programmable for both
read (IFRCST) and write (IFWCST) transactions.
This signal is also called the address valid (ADVm) signal and is shared between all interfaces supported on the
device.
18.3.5. Chip Select (CSx)
The chip select (CSx) signal is separate for each interface. The state of the CSx pin during address setup, address
hold, data setup, and data hold is programmable for both read (IFRCST) and write (IFWCST) transactions.
18.3.6. Byte Enable (BE0, BE1)
The byte enable signals are used in multiplexed bus modes, and most EMIF slave devices use active-low byteenable controls. When connecting to a non-multiplexed slave device that requires an external address latch, the
lower byte enable signal on the slave device can be connected to the latched version of the least-significant bit of
the address.
The EMIF module supports dynamic address shifting to also support internally muxed devices. This means that the
least-significant address bit is not available to serve as the lower byte enable. Instead, the EMIF module provides a
dedicated byte enable signal that acts as the lower-byte enable. This optional byte enable BE0 is enabled in the
device port configuration module.
The EMIF module also supports an optional upper byte enable (BE1). If the data size is greater than a byte, this
upper byte enable will always be logic 0. Otherwise, this upper byte enable will only be logic 0 when accessing the
upper byte in a half word. In the case of read operations from a 16-bit device, the EMIF module always asserts both
byte enables.
These pins are shared between all interfaces supported on the device.
Rev. 1.0
327
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.4. Memory Interface
The EMIF memory interface accepts byte, half-word, or word accesses of any justification. The output of the bus
for each of these accesses depends on the bus width of the interface, specified by the BUSWIDTH bit. Figure 18.3
and Figure 18.4 show the generated bus output for the different external RAM accesses.
Data written to external RAM
31
EMIF data
EMIF byte
address
B0
A
B1
A+1
B2
A+2
B3
A+3
B0
A
B1
A+1
B0
A+2
B1
A+3
B0
A
B0
A+1
B0
A+2
B0
A+3
0
B3
B2
B1
B0
31
0
B1
B0
31
0
B1
B0
31
0
B0
31
0
B0
31
0
B0
31
0
B0
Figure 18.3. EMIF Decoding with 8-bit Bus (BUSWIDTH = 0)
328
Rev. 1.0
Data written to external RAM
EMIF data
31
EMIF byte
address
BE1 BE0
0
B3
B2
B1
B0
31
B1
B0
A
0
0
B3
B2
A+2
0
0
B1
B0
A
0
0
B1
B0
A+2
0
0
B0
A
1
0
A+1
0
1
A+2
1
0
A+3
0
1
0
B1
B0
31
0
B1
B0
31
0
B0
31
0
B0
31
B0
0
B0
31
B0
0
B0
B0
Figure 18.4. EMIF Decoding with 16-bit Bus in Multiplexed Mode (BUSWIDTH = 1)
Rev. 1.0
329
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.5. Non-Multiplexed Output Mode
Non-multiplexed mode is enabled by setting the MUXMD bit to 0 in the interface registers. Non-multiplexed mode
requires more pins than multiplexed mode, but doesn’t require an address latch or dynamic address shifting.
Figure 18.5 shows an example non-multiplexed hardware configuration.
SiM3xxxx Device
Slave Device
A[15:0]
A[15:0]
D[7:0]
D[7:0]
EMIFn_IFx
Interface
WR
WR
OE
OE
CS
CSx
Figure 18.5. Example 8-bit Non-Multiplexed Configuration
The ALEm signal is unused in non-multiplexed mode. In addition, the maximum supported data width is 8 bits, and
dynamic address shifting is automatically disabled.
18.6. Multiplexed Output Mode
When the interface MUXMD field is set to 1, the interface operates in multiplexed mode. The address and data pins
are shared in this mode. For non-multiplexed slave devices, an external address latch controlled by the ALEm
signal is required. Multiplexed mode supports both 8 and 16-bit external data bus widths.
Figure 18.6 shows an example multiplexed hardware configuration with a non-multiplexed slave device supporting
16-bit data and 24-bit address.
SiM3xxxx Device
Slave Device
A[23:16]
A[23:16]m
D[15:0]
AD[15:0]m
EMIFn_IFx
Interface
D
Q
A[15:0]
G
ALEm
WR
WR
OE
OE
CS
CSx
Figure 18.6. Example 8-bit Multiplexed Configuration with Non-Multiplexed Slave Device
330
Rev. 1.0
18.6.1. Dynamic Address Shifting
The EMIF module supports dynamic address shifting for slave devices that only support an internally multiplexed
EMIF interface. These interfaces shift the address A[23:1] to A[22:0]. This address shift cannot be performed using
a static external latch like the non-multiplexed slave devices, since the shift would then apply to the data phase and
corrupt the data. This dynamic address shifting can be enabled by setting ASEN to 1 in the interface.
All slaves with multiplexed interfaces also include an address valid input (ADVm), which is shared with the EMIF
ALEm signal. The ALEm signal pulses low during the address phase, and the slave device samples the address on
the rising edge of this signal. When ADVm is de-asserted, the slave device expects valid data to be driven on this
same bus.
18.7. Mixing Configurations
Multiple interfaces can mix non-multiplexed and multiplexed modes, in addition to using different bus widths.
In the example shown in Figure 18.7, interface 0 is configured for 8-bit multiplexed mode with a non-multiplexed
slave, and interface 1 is configured for 8-bit non-multiplexed mode. Note that the multiplexed ADm[15:8] pins are
physically shared with the non-multiplexed A[7:0], and the multiplexed ADm[7:0] pins are physically shared with
non-multiplexed D[7:0].
Slave Device 2
A[15:8]
A[7:0]
D[7:0]
WR
OE
CS
SiM3xxxx Device
Slave Device 1
A[15:8]
A[15:8]
ADm[15:8]
D[7:0]
EMIFn
Module
Interface 0
Interface 1
ADm[7:0]
D
Q
A[7:0]
G
ALEm
WR
WR
OE
OE
CS
CS0
CS1
Figure 18.7. Example Mixed Configuration with Multiple Slaves
Rev. 1.0
331
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.8. Transaction Timing
Each EMIF interface transaction consists of four states: address setup, address hold, data wait, and data hold. The
timing for these states is programmable for both read and write operations. Figure 18.8, Figure 18.9, Figure 18.10,
and Figure 18.11 illustrate the states of each transaction.
Address
A[15:0]
Data out
previous data
D[7:0]
WR
WRWAS
WRWAH
WRWDW
WRWDH
OE
OEWAS
OEWAH
OEWDW
OEWDH
CSx
CSWAS
CSWAH
CSWDW
CSWDH
Address Setup
Address Hold
Data Wait
Idle or Off
Data Hold
Idle
Figure 18.8. EMIF Non-Multiplexed Transaction Timing (8-bit Bus, Write)
Address
A[15:0]
Data in
D[7:0]
WR
WRRAS
WRRAH
WRRDW
WRRDH
OE
OERAS
OERAH
OERDW
OERDH
CSx
CSRAS
CSRAH
CSRDW
CSRDH
Address Setup
Address Hold
Data Wait
Idle or Off
Data Hold
Idle
Figure 18.9. EMIF Non-Multiplexed Transaction Timing (8-bit Bus, Read)
332
Rev. 1.0
Address /
Data out
A[15:0]
D[15:0]
WR
WRWAS
WRWAH
WRWDW
WRWDH
OE
OEWAS
OEWAH
OEWDW
OEWDH
ALEm
ALEWAS
ALEWAH
ALEWDW
ALEWDH
CSx
CSWAS
CSWAH
CSWDW
CSWDH
Address Setup
Address Hold
Data Wait
Idle or Off
Data Hold
Idle
Figure 18.10. EMIF Multiplexed Transaction Timing (16-bit Bus, Write)
Address /
Data in
A[15:0]
D[15:0]
WR
WRRAS
WRRAH
WRRDW
WRRDH
OE
OERAS
OERAH
OERDW
OERDH
ALEm
ALERAS
ALERAH
ALERDW
ALERDH
CSRAS
CSRAH
CSRDW
CSRDH
Address Setup
Address Hold
Data Wait
CSx
Idle or Off
Data Hold
Idle
Figure 18.11. EMIF Multiplexed Transaction Timing (16-bit Bus, Read)
The RASET, RAHOLD, RDHOLD, and RDWAIT fields control the state timing for read operations. The WASET,
WAHOLD, WDHOLD, and WDWAIT fields control the timing for write operations.
Rev. 1.0
333
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.9. Idle and Off States
The interface returns to the idle state set by the pin latches in between transactions. Firmware can check whether
the EMIF module has been idle for 4 cycles using the IDLESTS bit.
The EMIF module can optionally transition to the off state after 4 idle cycles. When off, the EMIF pins will
automatically disable their output drivers, allowing the slave device to be shared amongst multiple master devices.
The drivers will re-enable automatically when firmware reads or writes an address in the external RAM memory
space. This feature can be enabled by setting OFFSTEN to 1. Firmware can check the status of the EMIF using the
OFFSTS bit.
18.10. Additional Features
18.10.1. Read-Only Mode
An interface can be placed in read-only mode by setting the ROEN interface bit to 1. When ROEN is cleared to 0,
the interface supports both read and write operations. A write operation initiated with an interface that is read-only
can generate an AHB error.
18.10.2. Write Data Hold Inhibit
When WDHINH is set to 1, the interface inhibits the data hold state for write transfers. This can speed up write
transactions for slave devices that can support it and allows for a minimum of 3 clocks per write transaction. The
WDHOLD field is ignored when WDHINH is set to 1.
18.10.3. Keep Last Read Enable
When KLREN is set to 1, the interface drives the last value read on the interface bus until the next active request.
The interface will drive the idle states on the pins when idle until the first read operation.
18.11. Configuring the External Memory Interface
To configure the EMIF module:
1. Configure the output modes of the associated port pins as either push-pull or open-drain (push-pull is most
common), and skip the associated pins in the crossbars using the port configuration module.
2. Configure the Port Bank latches in the device port configuration module to set the idle states for the EMIF
pins.
3. Select multiplexed mode or non-multiplexed mode using the interface MUXMD bit.
4. If in multiplexed mode, select the data bus width for the interface using the BUSWIDTH bit. BUSWIDTH
should be 0 (8-bits) for non-multiplexed mode.
5. Select the desired EMIF address width using the EMIFWIDTH field in the PBCFG0_CONTROL1 register.
6. (Optional) Enable dynamic address shifting for internally multiplexed slave devices (ASEN = 1).
7. (Optional) Enable the off state (OFFSTEN = 1) for multi-master configurations.
8. (Optional) Enable the optional chip select and output byte enable using the device port configuration
module.
9. Set the CSx, OE, WR, and ALEm states for read and write operations using the IFRCST and IFWCST
registers.
10. Configure the interface timing (RASET, RAHOLD, RDHOLD, RDWAIT, WASET, WAHOLD, WDHOLD,
and WDWAIT fields) to values compatible with the slave device or devices.
11. Enable the interface using the IFxEN bit.
Firmware can then read and write the slave device by writing or reading the correct addresses in the external RAM
memory space.
334
Rev. 1.0
18.12. EMIF0 Registers
This section contains the detailed register descriptions for EMIF0 registers.
Register 18.1. EMIF0_CONTROL: Module Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
0
0
0
Reserved
IF0EN
0
IF1EN
0
OFFSTEN
Reset
RW
R
RW
RW
0
0
1
0
0
Register ALL Access Address
EMIF0_CONTROL = 0x4002_6000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 18.2. EMIF0_CONTROL Register Bit Descriptions
Bit
Name
Function
31:5
Reserved
Must write reset value.
4
OFFSTEN
OFF Output State Enable.
This bit causes the EMIF to go into an off state after 4 idle cycles, disabling the signal drivers.
0: EMIF will not enter the off state after 4 idle cycles.
1: EMIF will enter the off state after 4 idle cycles.
3:2
Reserved
1
IF1EN
Must write reset value.
Interface 1 Enable.
Writing or reading from the interface 1 addresses when interface 1 is enabled will
cause the associated chip select (CS1) to activate. If interface 1 is disabled, writing
or reading from the interface 1 addresses will cause a Hard Fault error.
0
IF0EN
Interface 0 Enable.
Writing or reading from the interface 0 addresses when interface 0 is enabled will
cause the associated chip select (CS0) to activate. If interface 0 is disabled, writing
or reading from the interface 0 addresses will cause a Hard Fault error.
Rev. 1.0
335
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Register 18.2. EMIF0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
OFFSTS
Reset
IDLESTS
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Type
R
R
R
0
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EMIF0_STATUS = 0x4002_6020
Table 18.3. EMIF0_STATUS Register Bit Descriptions
Bit
Name
Function
31:2
Reserved
Must write reset value.
1
IDLESTS
EMIF IDLE Status.
0: The EMIF has not been idle for four cycles.
1: The EMIF has been idle for four four cycles.
0
OFFSTS
EMIF OFF Status.
0: The EMIF bus is active.
1: The EMIF is in the off bus state.
336
Rev. 1.0
0
0
18.13. EMIF0 Register Memory Map
EMIF0_STATUS EMIF0_CONTROL Register Name
0x4002_6020
ALL Address
0x4002_6000
ALL
ALL | SET | CLR Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Reserved
Bit 18
Bit 17
Reserved
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
OFFSTEN
Bit 4
Bit 3
Reserved
Bit 2
IF1EN
IDLESTS
Bit 1
IF0EN
OFFSTS
Bit 0
Table 18.4. EMIF0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
337
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.14. EMIF0_IFx Registers
This section contains the detailed register descriptions for EMIF0_IF0 and EMIF0_IF1 registers.
Register 18.3. EMIFn_IFx_CONFIG: Interface Configuration
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
KLREN
Bit
Type
R
RW
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
R
Reset
0
0
0
Reserved
RW
R
0
0
0
Reserved
BUSWIDTH
0
Reserved
0
MUXMD
0
ASEN
0
ROEN
0
WDHINH
Reset
DELAYOE
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
RW
R
RW
RW
RW
R
RW
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
EMIF0_IF0_CONFIG = 0x4002_6080
EMIF0_IF1_CONFIG = 0x4002_6100
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 18.5. EMIFn_IFx_CONFIG Register Bit Descriptions
Bit
Name
31:17
Reserved
16
KLREN
Function
Must write reset value.
Keep Last Read Enable.
When KLREN is set to 1, the interface drives the last read value out on the interface
bus until the next active request.
0: The bus is driven to the idle state between active requests.
1: The bus drives the last value read on the interface between active requests.
15:13
Reserved
Must write reset value.
12
DELAYOE
Output Enable Delay.
When DELAYOE is set to 1, the interface will delay the assertion of the output
enable signal (OE) by 1/2 an AHB cycle.
0: The output enable signal (OE) is not delayed.
1: The output enable signal (OE) is delayed.
11:9
338
Reserved
Must write reset value.
Rev. 1.0
Table 18.5. EMIFn_IFx_CONFIG Register Bit Descriptions
Bit
Name
8
WDHINH
Function
Write Data Hold State Inhibit.
When WDHINH is set to 1, the interface inhibits the data hold state for write transfers.
0: Enable the write data hold state.
1: Inhibit the write data hold state.
7:5
Reserved
4
ROEN
Must write reset value.
Interface Read Only Enable.
0: The interface supports reads and writes.
1: The interface supports only reads.
3
ASEN
Interface Automatic Address Shift Enable.
When connecting to a 16-bit internally muxed device and ASEN is set, the EMIF will
automatically shift the address on the address/data bus during the address phase.
This feature must be used with a bus width of 16 bits (BUSWIDTH = 1) and muxed
mode (MUXMD = 1). If BUSWIDTH or MUXMD is not set to 1, setting this bit will
have no effect.
0: The address is not automatically shifted.
1: The address is automatically shifted.
2
MUXMD
Interface Mux Mode.
When MUXMD is set to 1, the lower bits of the address are driven on the lower bits
of the bus during the address setup and address hold states.
0: The interface operates in non-multiplexed mode.
1: The interface operates in multiplexed mode.
1
Reserved
0
BUSWIDTH
Must write reset value.
Interface Bus Data Width.
0: The data bus is 8-bits wide.
1: The data bus is 16-bits wide. This option should only be used in multiplexed
mode (MUXMD = 1).
Rev. 1.0
339
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Register 18.4. EMIFn_IFx_IFRT: Interface Read Timing
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Name
Reserved
RDWAIT
Type
R
RW
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
RDHOLD
RAHOLD
RASET
Type
R
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
EMIF0_IF0_IFRT = 0x4002_6090
EMIF0_IF1_IFRT = 0x4002_6110
Table 18.6. EMIFn_IFx_IFRT Register Bit Descriptions
Bit
Name
Function
31:22
Reserved
Must write reset value.
21:16
RDWAIT
Interface Read Data Wait Delay.
The read data wait state delay is set by this field according to the equation:
 RDWAIT + 1 
t RDW = -------------------------------------F AHB
15:12
Reserved
Must write reset value.
11:8
RDHOLD
Interface Read Data Hold Delay.
The read data hold state delay is set by this field according to the equation:
 RDHOLD + 1 
t RDH = --------------------------------------F AHB
7:4
RAHOLD
Interface Read Address Hold Delay.
The read address hold state delay is set by this field according to the equation:
RAHOLD
t RAH = ------------------------F AHB
340
Rev. 1.0
0
Table 18.6. EMIFn_IFx_IFRT Register Bit Descriptions
Bit
Name
3:0
RASET
Function
Interface Read Address Setup Delay .
The read address setup state delay is set by this field according to the equation:
 RASET + 1 
t RAS = ---------------------------------F AHB
Rev. 1.0
341
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Register 18.5. EMIFn_IFx_IFWT: Interface Write Timing
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Name
Reserved
WDWAIT
Type
R
RW
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
WDHOLD
WAHOLD
WASET
Type
R
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
EMIF0_IF0_IFWT = 0x4002_60A0
EMIF0_IF1_IFWT = 0x4002_6120
Table 18.7. EMIFn_IFx_IFWT Register Bit Descriptions
Bit
Name
Function
31:22
Reserved
Must write reset value.
21:16
WDWAIT
Interface Write Data Wait Delay.
The write data wait state delay is set by this field according to the equation:
 WDWAIT + 1 
t WDW = --------------------------------------F AHB
15:12
Reserved
Must write reset value.
11:8
WDHOLD
Interface Write Data Hold Delay.
The write data hold state delay is set by this field according to the equation:
 WDHOLD + 1 
t WDH = ----------------------------------------F AHB
7:4
WAHOLD
Interface Write Address Hold Delay.
The write address hold state delay is set by this field according to the equation:
WAHOLD
t WAH = -------------------------F AHB
342
Rev. 1.0
0
Table 18.7. EMIFn_IFx_IFWT Register Bit Descriptions
Bit
Name
3:0
WASET
Function
Interface Write Address Setup Delay .
The write address setup state delay is set by this field according to the equation:
 WASET + 1 
t WAS = ----------------------------------F AHB
Rev. 1.0
343
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Register 18.6. EMIFn_IFx_IFRCST: Interface Read Control States
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CSRAS
0
CSRAH
0
CSRDW
0
CSRDH
0
OERAS
0
OERAH
0
OERDW
0
OERDH
0
WRRAS
0
WRRAH
0
WRRDW
0
WRRDH
0
ALERAS
0
ALERAH
0
ALERDW
Reset
ALERDH
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
1
1
1
1
1
0
1
1
1
0
1
1
Register ALL Access Addresses
EMIF0_IF0_IFRCST = 0x4002_60B0
EMIF0_IF1_IFRCST = 0x4002_6130
Table 18.8. EMIFn_IFx_IFRCST Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
ALERDH
Address Latch Enable Read Data Hold State.
0: Set address latch enable (ALEm) to low during the read data hold state.
1: Set address latch enable (ALEm) to high during the read data hold state.
14
ALERDW
Address Latch Enable Read Data Wait State.
0: Set address latch enable (ALEm) to low during the read data wait state.
1: Set address latch enable (ALEm) to high during the read data wait state.
13
ALERAH
Address Latch Enable Read Address Hold State.
0: Set address latch enable (ALEm) to low during the read address hold state.
1: Set address latch enable (ALEm) to high during the read address hold state.
12
ALERAS
Address Latch Enable Read Address Setup State.
0: Set address latch enable (ALEm) to low during the read address setup state.
1: Set address latch enable (ALEm) to high during the read address setup state.
11
WRRDH
Write Signal Read Data Hold State.
0: Set write signal (WR) to low during the read data hold state.
1: Set write signal (WR) to high during the read data hold state.
10
WRRDW
Write Signal Read Data Wait State.
0: Set write signal (WR) to low during the read data wait state.
1: Set write signal (WR) to high during the read data wait state.
344
Rev. 1.0
Table 18.8. EMIFn_IFx_IFRCST Register Bit Descriptions
Bit
Name
9
WRRAH
Function
Write Signal Read Address Hold State.
0: Set write signal (WR) to low during the read address hold state.
1: Set write signal (WR) to high during the read address hold state.
8
WRRAS
Write Signal Read Address Setup State.
0: Set write signal (WR) to low during the read address setup state.
1: Set write signal (WR) to high during the read address setup state.
7
OERDH
Output Enable Read Data Hold State.
0: Set output enable (OE) to low during the read data hold state.
1: Set output enable (OE) to high during the read data hold state.
6
OERDW
Output Enable Read Data Wait State.
0: Set output enable (OE) to low during the read data wait state.
1: Set output enable (OE) to high during the read data wait state.
5
OERAH
Output Enable Read Address Hold State.
0: Set output enable (OE) to low during the read address hold state.
1: Set output enable (OE) to high during the read address hold state.
4
OERAS
Output Enable Read Address Setup State.
0: Set output enable (OE) to low during the read address setup state.
1: Set output enable (OE) to high during the read address setup state.
3
CSRDH
Chip Select Read Data Hold State.
0: Set chip select (CSx) to low during the read data hold state.
1: Set chip select (CSx) to high during the read data hold state.
2
CSRDW
Chip Select Read Data Wait State.
0: Set chip select (CSx) to low during the read data wait state.
1: Set chip select (CSx) to high during the read data wait state.
1
CSRAH
Chip Select Read Address Hold State.
0: Set chip select (CSx) to low during the read address hold state.
1: Set chip select (CSx) to high during the read address hold state.
0
CSRAS
Chip Select Read Address Setup State.
0: Set chip select (CSx) to low during the read address setup state.
1: Set chip select (CSx) to high during the read address setup state.
Rev. 1.0
345
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Register 18.7. EMIFn_IFx_IFWCST: Interface Write Control States
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CSWAS
0
CSWAH
0
CSWDW
0
CSWDH
0
OEWAS
0
OEWAH
0
OEWDW
0
OEWDH
0
WRWAS
0
WRWAH
0
WRWDW
0
WRWDH
0
ALEWAS
0
ALEWAH
0
ALEWDW
Reset
ALEWDH
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
1
Register ALL Access Addresses
EMIF0_IF0_IFWCST = 0x4002_60C0
EMIF0_IF1_IFWCST = 0x4002_6140
Table 18.9. EMIFn_IFx_IFWCST Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
ALEWDH
Address Latch Enable Write Data Hold State.
0: Set address latch enable (ALEm) to low during the write data hold state.
1: Set address latch enable (ALEm) to high during the write data hold state.
14
ALEWDW
Address Latch Enable Write Data Wait State.
0: Set address latch enable (ALEm) to low during the write data wait state.
1: Set address latch enable (ALEm) to high during the write data wait state.
13
ALEWAH
Address Latch Enable Write Address Hold State.
0: Set address latch enable (ALEm) to low during the write address hold state.
1: Set address latch enable (ALEm) to high during the write address hold state.
12
ALEWAS
Address Latch Enable Write Address Setup State.
0: Set address latch enable (ALEm) to low during the write address setup state.
1: Set address latch enable (ALEm) to high during the write address setup state.
11
WRWDH
Write Signal Write Data Hold State.
0: Set write signal (WR) to low during the write data hold state.
1: Set write signal (WR) to high during the write data hold state.
10
WRWDW
Write Signal Write Data Wait State.
0: Set write signal (WR) to low during the write data wait state.
1: Set write signal (WR) to high during the write data wait state.
346
Rev. 1.0
Table 18.9. EMIFn_IFx_IFWCST Register Bit Descriptions
Bit
Name
9
WRWAH
Function
Write Signal Write Address Hold State.
0: Set write signal (WR) to low during the write address hold state.
1: Set write signal (WR) to high during the write address hold state.
8
WRWAS
Write Signal Write Address Setup State.
0: Set write signal (WR) to low during the write address setup state.
1: Set write signal (WR) to high during the write address setup state.
7
OEWDH
Output Enable Write Data Hold State.
0: Set output enable (OE) to low during the write data hold state.
1: Set output enable (OE) to high during the write data hold state.
6
OEWDW
Output Enable Write Data Wait State.
0: Set output enable (OE) to low during the write data wait state.
1: Set output enable (OE) to high during the write data wait state.
5
OEWAH
Output Enable Write Address Hold State.
0: Set output enable (OE) to low during the write address hold state.
1: Set output enable (OE) to high during the write address hold state.
4
OEWAS
Output Enable Write Address Setup State.
0: Set output enable (OE) to low during the write address setup state.
1: Set output enable (OE) to high during the write address setup state.
3
CSWDH
Chip Select Write Data Hold State.
0: Set chip select (CSx) to low during the write data hold state.
1: Set chip select (CSx) to high during the write data hold state.
2
CSWDW
Chip Select Write Data Wait State.
0: Set chip select (CSx) to low during the write data wait state.
1: Set chip select (CSx) to high during the write data wait state.
1
CSWAH
Chip Select Write Address Hold State.
0: Set chip select (CSx) to low during the write address hold state.
1: Set chip select (CSx) to high during the write address hold state.
0
CSWAS
Chip Select Write Address Setup State.
0: Set chip select (CSx) to low during the write address setup state.
1: Set chip select (CSx) to high during the write address setup state.
Rev. 1.0
347
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
18.15. EMIFn_IFx Register Memory Map
Table 18.10. EMIFn_IFx Memory Map
EMIFn_IFx_IFWT EMIFn_IFx_IFRT EMIFn_IFx_CONFIG Register Name
0x20
0x10
ALL Offset
0x0
ALL
ALL
Access Methods
ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Reserved
Reserved
Bit 26
Bit 25
Reserved
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
WDWAIT
RDWAIT
Bit 18
Bit 17
KLREN
Bit 16
Bit 15
Reserved
Bit 14
Reserved
Reserved
Bit 13
DELAYOE
Bit 12
Bit 11
Reserved
Bit 10
WDHOLD
RDHOLD
Bit 9
WDHINH
Bit 8
Bit 7
Reserved
Bit 6
WAHOLD
RAHOLD
Bit 5
ROEN
Bit 4
ASEN
Bit 3
MUXMD
Bit 2
WASET
RASET
Reserved
Bit 1
BUSWIDTH
Bit 0
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: EMIF0_IF0 = 0x4002_6080, EMIF0_IF1 = 0x4002_6100
348
Rev. 1.0
EMIFn_IFx_IFWCST EMIFn_IFx_IFRCST Register Name
0x30
ALL Offset
0x40
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
ALEWDH
ALERDH
Bit 15
ALEWDW
ALERDW
Bit 14
ALEWAH
ALERAH
Bit 13
ALEWAS
ALERAS
Bit 12
WRWDH
WRRDH
Bit 11
WRWDW
WRRDW
Bit 10
WRWAH
WRRAH
Bit 9
WRWAS
WRRAS
Bit 8
OEWDH
OERDH
Bit 7
OEWDW
OERDW
Bit 6
OEWAH
OERAH
Bit 5
OEWAS
OERAS
Bit 4
CSWDH
CSRDH
Bit 3
CSWDW
CSRDW
Bit 2
CSWAH
CSRAH
Bit 1
CSWAS
CSRAS
Bit 0
Table 18.10. EMIFn_IFx Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: EMIF0_IF0 = 0x4002_6080, EMIF0_IF1 = 0x4002_6100
Rev. 1.0
349
External Memory Interface (EMIF0)
SiM3U1xx/SiM3C1xx
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
19. External Oscillator (EXTOSC0)
This section describes the External Oscillator (EXTOSC) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the EXTOSC block, which is used by all device families covered in this
document.
19.1. External Oscillator Features
The External Oscillator control has the following features:
Support
for external crystal or ceramic resonator, RC, C, or CMOS oscillators.
external CMOS frequencies from 10 kHz to 50 MHz and external crystal frequencies from 10 kHz
to 30 MHz.
Various drive strengths for flexible crystal oscillator support.
Internal frequency divide-by-two option available for some oscillator modes.
Available as an input to the PLL.
Support
External RC
Oscillator
External C
Oscillator
VIO
XTAL2
XTAL2
EXTOSCn Module
XTAL1
External Crystal
XTAL2
External Oscillator
Control
XTAL1
10 M
XTAL2
External CMOS
Oscillator
XTAL2
Figure 19.1. External Oscillator Block Diagram
350
Rev. 1.0
EXTOSCn clock
19.2. Introduction
The EXTOSC external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network.
A CMOS clock may also provide a clock input. The external oscillator output may be selected as the AHB clock or
used to clock other modules independent of the AHB clock selection.
19.3. External Crystal Oscillator
When OSCMD is 6 or 7, the EXTOSC module is in crystal oscillator mode. The crystal or ceramic resonator and a
10 M resistor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 19.2. Appropriate loading
capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog mode as
described in the port configuration module.
SiM3xxxx Device
C
XTAL1
10 M
C
EXTOSCn
Module
XTAL2
Figure 19.2. External Crystal Oscillator Configuration
The capacitors provide the load capacitance required by the crystal for correct oscillation. These capacitors are “in
series” as seen by the crystal and “in parallel” with the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Refer to the crystal data sheet
when completing these calculations.
Equation 19.1 describes the equation for determining the load capacitance for the two capacitors. The CA and CB
values are the capacitors connected to the crystal leads. The CS value is the total stray capacitance of the PCB.
CA  CB
C L = --------------------- + C S
CA + CB
Equation 19.1. Crystal Load Capacitors
If CA and CB are the same (C), the resulting equation is shown in Equation 19.2.
C
C L = ---- + C S
2
Equation 19.2. Simplified Crystal Load Capacitors
For example, using Equation 19.2 with a 32.768 kHz tuning-fork crystal with a recommended load capacitance of
12.5 pF placed as close to the pins as possible (assuming 6 pF total stray capacitance) results in crystal load
capacitors of 13 pF each.
Note: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL
pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces that
could introduce noise or interference.
Rev. 1.0
351
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
Setting OSCMD to 6 places EXTOSC in crystal oscillator mode, and setting OSCMD to 7 sets the module in crystal
oscillator divided by 2 mode. This divide-by-2 stage ensures that the clock derived from the external oscillator has
a duty cycle of 50%. When operating in either crystal mode, the frequency control (FREQCN) field must be set to
the appropriate value based on the crystal frequency.
Table 19.1. Frequency Control for Crystal Oscillators
Crystal
Frequency
FREQCN
Value
10 kHz < f < 20 kHz
0
20 kHz < f < 58 kHz
1
58 kHz < f < 155 kHz
2
155 kHz < f < 415 kHz
3
415 kHz < f < 1.1 MHz
4
1.1 MHz < f < 3.1 MHz
5
3.1 MHz < f < 8.2 MHz
6
8.2 MHz < f < 25 MHz
7
19.3.1. Configuring for Crystal Oscillator Mode
The recommended procedure for starting the crystal is as follows:
1. Configure the XTAL1 and XTAL2 pins for analog mode using the device port configuration module.
2. Disable the XTAL1 and XTAL2 digital output drivers by writing 1’s to the pin latch in the Port Bank registers.
3. Configure the FREQCN field for the crystal frequency according to Table 19.1.
4. Set the OSCMD field to 6 for crystal mode or 7 for crystal divided by 2 mode.
5. Wait at least 1 ms.
6. Poll on the OSCVLDF flag to determine if the oscillator is running and stable.
7. Set the EXTOSCEN bit in CLKCTRL0_CONFIG to 1, to enable the external oscillator as a clock source.
8. Select the external oscillator as the AHB clock or as the input clock for a module.
19.4. External CMOS Oscillator
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2, and the
XTAL2 pin should be configured as a digital input using the device port configuration module. XTAL1 is not used in
external CMOS clock mode.
The CMOS oscillator mode is available with a divide by 2 stage, which ensures that the clock derived from the
external oscillator has a duty cycle of 50%.
The external oscillator valid (OSCVLDF) flag will always return zero when the external oscillator is configured to
external CMOS clock mode.
19.4.1. Configuring for CMOS Oscillator Mode
The recommended procedure for enabling the CMOS oscillator is:
1. Configure the XTAL2 pins for digital input mode using the device port configuration module.
2. Set the OSCMD field to 2 for CMOS mode or 3 for CMOS mode with divide by 2 stage.
3. Set the EXTOSCEN bit in CLKCTRL0_CONFIG to 1, to enable the external oscillator as a clock source.
4. Select the external oscillator as the AHB clock or as the input clock for a module.
352
Rev. 1.0
19.5. External RC Oscillator
When using the EXTOSC module with an external RC network, firmware should set the OSCMD field to 4 for RC
divided by 2 mode. The RC network should be added to XTAL2, and XTAL2 should be configured for analog mode
with the digital output drivers disabled. XTAL1 is not affected in RC mode. Figure 19.3 shows this hardware
configuration.
SiM3xxxx Device
VIO
XTAL1
EXTOSCn
Module
R
XTAL2
C
Figure 19.3. External RC Oscillator Configuration
The capacitor used in the RC network should have a value no greater than 100 pF, and the resistor should be no
smaller than 10 k. For very small capacitors, the parasitic capacitance in the PCB layout may dominate the total
capacitance. The oscillation frequency can be determined by Equation 19.3, where F is the frequency in MHz, R is
the pull-up resistor value in k., and C is the capacitor value in the XTAL2 pin in pF.
3
1.23  10
F = --------------------------RC
Equation 19.3. RC Oscillation Frequency
To determine the required frequency control (FREQCN), first select the RC network value to produce the desired
frequency of oscillation. For example, if the desired frequency is 100 kHz, let R = 246 k. and C = 50 pF.
3
3
1.23  10
1.23  10
F = --------------------------- = --------------------------- = 100 kHz
RC
246  50
Table 19.2 shows the frequency ranges for the frequency control (FREQCN) bit in RC oscillator mode. The
recommended FREQCN setting for this example is 2.
The RC oscillator mode is only available with a divide by 2 stage, which ensures that the clock derived from the
external oscillator has a duty cycle of 50%. The equation for the EXTOSC output frequency is shown in
Equation 19.4.
3
F
1.23  10
F OUT = --- = --------------------------2
2RC
Equation 19.4. EXTOSC Output Frequency in RC Mode
Rev. 1.0
353
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
Table 19.2. Frequency Control for RC Oscillators
RC Oscillator
Frequency
EXTOSC Output
Frequency (fOUT)
FREQCN
Value
f < 25 kHz
fOUT < 12.5 kHz
0
25 kHz < f < 50 kHz
12.5 kHz < fOUT < 25 kHz
1
50 kHz < f < 100 kHz
25 kHz < fOUT < 50 kHz
2
100 kHz < f < 200 kHz
50 kHz < fOUT < 100 kHz
3
200 kHz < f < 400 kHz
100 kHz < fOUT < 200 kHz
4
400 kHz < f < 800 kHz
200 kHz < fOUT < 400 kHz
5
800 kHz < f < 1.6 MHz
400 kHz < fOUT < 800 kHz
6
1.6 MHz < f < 3.2 MHz
800 kHz < fOUT < 1.6 MHz
7
19.5.1. Configuring for RC Oscillator Mode
The recommended procedure for enabling the RC oscillator is:
1. Configure the XTAL2 pin for analog mode using the device port configuration module.
2. Disable the XTAL2 digital output driver by writing 1 to the pin latch in the Port Bank registers.
3. Configure the FREQCN field for the RC frequency according to Table 19.2.
4. Set the OSCMD field to 4 for RC divided by 2 mode.
5. Wait at least 1 ms.
6. Poll on the OSCVLDF flag to determine if the oscillator is running and stable.
7. Set the EXTOSCEN bit in CLKCTRL0_CONFIG to 1, to enable the external oscillator as a clock source.
8. Select the external oscillator as the AHB clock or as the input clock for a module.
354
Rev. 1.0
19.6. External C Oscillator
Firmware can enable the external C oscillator by setting OSCMD to 5 for C oscillator divided by 2 mode. The
capacitor used should be no greater than 100 pF, and the parasitic capacitance in the PCB layout may dominate
very small capacitors. The hardware configuration for the external C oscillator is shown in Figure 19.4.
SiM3xxxx Device
XTAL1
EXTOSCn
Module
XTAL2
C
Figure 19.4. External C Oscillator Configuration
To determine the required frequency control (FREQCN) value (XFCN), select the capacitor to be used and find the
frequency of oscillation according to Equation 19.5, where F is the frequency of oscillation in MHz, C is the
capacitor value in pF, VBAT is the device power supply in Volts, and K is the K Factor.
K
F = -----------------------C  V BAT
Equation 19.5. C Oscillation Frequency
For example, assume VBAT is 3.0 V and the desired C oscillator frequency is 150 kHz. Since the frequency
desired is roughly 150 kHz, select the K Factor of 22 from Table 19.3.
22
0.150 = -----------------C  3.0
22
C = ----------------------------- = 48.8 pF
0.150  3.0
Therefore, the FREQCN value to use in this example is 3, and the external capacitor should be 50 pF.
The C oscillator mode is only available with a divide by 2 stage, which ensures that the clock derived from the
external oscillator has a duty cycle of 50%. The equation for the EXTOSC output frequency is shown in
Equation 19.6.
f
KF
f OUT = --- = --------------------------------2
2  C  V BAT
Equation 19.6. EXTOSC Output Frequency in C Mode
Rev. 1.0
355
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
Table 19.3. Frequency Control for C Oscillators
C Oscillator
Frequency
EXTOSC Output
Frequency (fOUT)
K Factor
(KF)
FREQCN
Value
f < 25 kHz
fOUT < 12.5 kHz
0.87
0
25 kHz < f < 50 kHz
12.5 kHz < fOUT < 25 kHz
2.6
1
50 kHz < f < 100 kHz
25 kHz < fOUT < 50 kHz
7.7
2
100 kHz < f < 200 kHz
50 kHz < fOUT < 100 kHz
22
3
200 kHz < f < 400 kHz
100 kHz < fOUT < 200 kHz
65
4
400 kHz < f < 800 kHz
200 kHz < fOUT < 400 kHz
180
5
800 kHz < f < 1.6 MHz
400 kHz < fOUT < 800 kHz
664
6
1.6 MHz < f < 3.2 MHz
800 kHz < fOUT < 1.6 MHz
1590
7
19.6.1. Configuring for C Oscillator Mode
The recommended procedure for enabling the C oscillator is:
1. Configure the XTAL2 pin for analog mode using the device port configuration module.
2. Disable the XTAL2 digital output driver by writing 1 to the pin latch in the Port Bank registers.
3. Configure the FREQCN field for the C frequency and K Factor according to Table 19.3.
4. Set the OSCMD field to 5 for C oscillator divided by 2 mode.
5. Wait at least 1 ms.
6. Poll on the OSCVLDF flag to determine if the oscillator is running and stable.
7. Set the EXTOSCEN bit in CLKCTRL0_CONFIG to 1, to enable the external oscillator as a clock source.
8. Select the external oscillator as the AHB clock or as the input clock for a module.
356
Rev. 1.0
19.7. EXTOSC0 Registers
This section contains the detailed register descriptions for EXTOSC0 registers.
Register 19.1. EXTOSC0_CONTROL: Oscillator Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
OSCMD
OSCVLDF
Reset
FREQCN
Type
R
RW
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EXTOSC0_CONTROL = 0x4003_C000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 19.4. EXTOSC0_CONTROL Register Bit Descriptions
Bit
Name
Function
31:7
Reserved
Must write reset value.
6:4
OSCMD
Oscillator Mode.
000: External oscillator off.
001: Reserved.
010: External CMOS clock mode.
011: External CMOS with divide by 2 stage.
100: RC oscillator mode with divide by 2 stage.
101: C oscillator mode with divide by 2 stage.
110: Crystal oscillator mode.
111: Crystal oscillator mode with divide by 2 stage.
3
OSCVLDF
Oscillator Valid Flag.
This bit indicates when the oscillator has stabilized after an initial startup condition.
Hardware will clear the bit to 0 when the external oscillator is disabled, and set the
bit to 1 once the oscillator is running properly. It will not clear automatically if oscillation fails. This bit is valid for all modes of operation except external CMOS clock and
external CMOS clock divide by 2 modes, when OSCVLDF always reads back as 0.
0: The external oscillator is unused or not yet stable.
1: The external oscillator is running and stable.
Rev. 1.0
357
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
Table 19.4. EXTOSC0_CONTROL Register Bit Descriptions
Bit
Name
2:0
FREQCN
Function
Frequency Control.
000: Set the external oscillator to range 0.
001: Set the external oscillator to range 1.
010: Set the external oscillator to range 2.
011: Set the external oscillator to range 3.
100: Set the external oscillator to range 4.
101: Set the external oscillator to range 5.
110: Set the external oscillator to range 6.
111: Set the external oscillator to range 7.
358
Rev. 1.0
19.8. EXTOSC0 Register Memory Map
EXTOSC0_CONTROL Register Name
ALL Address
0x4003_C000
Access Methods
ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Reserved
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OSCMD
Bit 5
Bit 4
OSCVLDF
Bit 3
Bit 2
FREQCN
Bit 1
Bit 0
Table 19.5. EXTOSC0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
359
External Oscillator (EXTOSC0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
20. External Regulator (EXTVREG0)
This section describes the External Regulator (EXTVREG) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the EXTVREG block, which is used by all device families covered in this
document.
20.1. External Regulator Features
The External Regulator module has the following features:
Interfaces
with either an NPN or PNP external transistor that serves as the pass device for the high current
regulator.
Automatic current limiting.
Automatic foldback limiting.
Sources up to 1 A for use by external circuitry.
Variable output voltage, adjustable in 100 mV steps.
The External Regulator provides all the circuitry needed for a high-power regulator except the power
transistor (NPN or PNP).
EXTVREGn Module
to other internal
modules
EXREGSP
Current
Sensor
EXREGSN
Current Limit
External
Regulator
EXREGBD
Output Voltage
external
circuitry
EXREGOUT
Figure 20.1. External Regulator Block Diagram
360
Rev. 1.0
20.2. Overview
The External Voltage Regulator (EXTVREGn) module interfaces with an external transistor and decoupling
capacitor to create a high current regulator. This external transistor can be either a PNP or an NPN bipolar
transistor, and the output voltage is programmable in 100 mV steps. The external decoupling capacitor should be a
minimum of 4.7 µF in normal operation and a minimum of 47 nF in stand-alone mode. In both cases, the capacitor
should be placed as close to the external regulator pins as possible.
In addition, the EXTVREGn module supports current sensing and limiting, foldback limiting, and internal resistors
to ensure regulator stability even with very small loads.
20.3. Operating Modes
In all operating modes, the external regulator is enabled by setting the EVREGEN bit to 1. Firmware can select the
output voltage using the VOUTSEL field. The output voltage is equal to VOUTSEL + 1.8 V, where each setting of
VOUTSEL represents 100 mV.
Any pins used with the external regulator should be placed in analog mode as described in the port configuration
module to disable the general weak pull-ups on the pins.
20.3.1. Normal Mode
When stand-alone mode is disabled (SAEN = 0), the external regulator operates normally and the output of the
external transistor must be connected to the EXREGOUT pin. In this mode, the regulator requires at least two pins:
one to drive the base of the external bipolar (EXREGBD), and one to sense the output voltage (EXREGOUT).
The PNSEL bit configures whether the external regulator is in PNP or NPN mode. Figure 20.2 shows the external
regulator in normal NPN mode, and Figure 20.3 shows the external regulator in normal PNP mode.
The decoupling capacitor on the output of the regulator must be a minimum of 4.7 µF in this mode and placed as
close to the output of the bipolar transistor as possible.
SiM3xxxx Device
EXREGSP
EXTVREGn
Module
EXREGSN
EXREGBD
external
circuitry
EXREGOUT
Figure 20.2. External Regulator Normal Mode NPN Configuration
Rev. 1.0
361
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
SiM3xxxx Device
EXREGSP
EXTVREGn
Module
EXREGSN
EXREGBD
external
circuitry
EXREGOUT
Figure 20.3. External Regulator Normal Mode PNP Configuration
20.3.2. Stand-Alone Mode
When SAEN is set to 1, the regulator transistor base driver (EXREGBD) is the only pin used by the regulator. This
allows the regulator to operate in standalone mode, where an external transistor is not used, and the module
operates as a voltage regulator with a maximum current output of approximately 12 mA. The supply to the VREGIN
pin is used as the supply for the regulator in this mode, and the remaining regulator pins can be used for other
functions.
The decoupling capacitor on the output of the regulator must be a minimum of 47 nF in this mode and placed as
close to the EXREGBD pin as possible.
SiM3xxxx Device
VREGIN
EXREGSP
EXTVREGn
Module
EXREGSN
external
circuitry
EXREGBD
EXREGOUT
Figure 20.4. External Regulator in Standalone Mode
362
Rev. 1.0
20.4. Current Sensing
The external regulator includes a current sensing feature that is enabled by placing a resistor in the current path of
the external bipolar transistor. When the current limiting feature described in “20.5. Current Limiting” is not in use,
the value of the resistor is not restricted, and firmware should set the IMAX field to the maximum value.
Current sensing has two outputs: one for the external regulator for use in voltage regulation and load control, and
one as a measurable input for other modules in the device. The current sensing feature is enabled only if one of
these outputs is enabled. Note that the current sensing feature relies on the VREG0 bandgap circuit to operate. It
is necessary to clear the BGDIS bit in VREG0_CONTROL to 0 before using current sensing. A detailed diagram of
the current sensing circuitry is shown in Figure 20.5.
The EXTVREGn module supports a variety of current sensing input configurations.
ISADCGAIN
to other internal
modules (ADC)
ADCISNSEN
Gain
Setting
Current
Sensor
Gain
Setting
EXREGSP
EXREGSN
ISOGAIN
to external
bipolar
transistor
ISNSEN
to voltage
regulator and
load control
Figure 20.5. Current Sensing
20.4.1. Current Sensing Configurations
The EXTVREGn module supports four different current sensing input configurations selected by the ISINSEL field.
Current sensing mode 0 (ISINSEL = 0) is the standard configuration, using all four of the external regulator pins
and providing the most accuracy of the available modes. This mode is shown in Figure 20.6.
SiM3xxxx Device
Current
Sensing
EXREGSP
EXREGSN
External
Regulator
EXREGBD
external
circuitry
EXREGOUT
Figure 20.6. Current Sensing Input Configuration Mode 0
Rev. 1.0
363
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
In input configuration mode 1 (ISINSEL = 1), the current sensing circuit measures on the low side of the bipolar
transistor. In this mode, the external transistor can be connected to higher supply voltages that exceed the
maximum ratings for the pins and still allow the regulator to sense the load current. The three pins used in this
mode are EXREGBD, EXREGOUT, and EXREGSP. The fourth pin, EXREGSN, is unused, and the second current
sensing circuit input is internally connected to the EXREGOUT signal. Figure 20.7 shows the mode 1 configuration.
SiM3xxxx Device
External
Regulator
EXREGBD
EXREGSP
external
circuitry
Current
Sensing
EXREGOUT
Figure 20.7. Current Sensing Input Configuration Mode 1
Current sensing input mode 2 (ISINSEL = 2) uses the VREGIN pin voltage as one of the inputs to the current
sensing circuitry along with the EXREGSN input. This mode requires that the source connected to the external
bipolar transistor is the same supply used by the internal voltage regulator (VREGN) module and can be less
accurate than input mode 0. The EXREGSP input is not used in this mode. Figure 20.8 shows the input
configuration for mode 2.
SiM3xxxx Device
VREGIN
Current
Sensing
EXREGSN
External
Regulator
EXREGBD
external
circuitry
EXREGOUT
Figure 20.8. Current Sensing Input Configuration Mode 2
364
Rev. 1.0
20.4.2. External Regulator Sensing
External regulator current sensing is enabled by setting the ISNSEN bit to 1. The regulator current sensing has a
programmable gain stage set using the ISOGAIN field with five settings: 1x, 2x, 4x, 8x, and 16x. This gain should
be selected based on the resistor value and the expected maximum current output of the regulator.
Equation 20.1 describes how to select the current sensing gain as a function of the maximum current and the
sense resistor value. In this equation, IBJTMAX is given in Amps, Rsense is given in ohms, and IMAX is given in µA.
I MAX
I BJTMAX = ------------------------------------------------------------------R sense  12.5  Gain sense
Equation 20.1. External Regulator Current Sensing
The IMAX value can be set by the IMAX field if using current limiting.
20.4.3. Other Internal Module Sensing (ADC)
The current sensing output for other modules is enabled by setting the ADCISNSEN bit to 1. This output is
primarily intended to be measured by an ADC on the device (like the SARADCn module, if available), but can also
be an input for other modules.
This output’s gain setting is independent form the external regulator gain setting and is selected using the
ISADCGAIN field with five settings: 1x, 2x, 4x, 8x, and 16x. If measuring the current sensing output using an ADC,
the gain setting should be selected to maximize the ADC’s dynamic range: when the external regulator reaches the
current limit set by the IMAX field, the ADC should measure a value close to its selected voltage reference.
The current sensing feature of the EXTVREGn module can be used even if the external regulator is disabled
(EVREGEN = 0).
20.5. Current Limiting
The current limiting feature of the external regulator utilizes the internal current sensing circuitry and limits the
output current of the regulator to the value specified by the IMAX field. Firmware can enable current limiting by
enabling current sensing and setting the IMAX field to a value less than or equal to the IMAX value in Equation 20.1.
To use the current limiting feature of the external regulator, the sensing resistor in the current path of the external
bipolar transistor must be less than or equal to 1 . Resistor values larger than 1 may cause instability in the
regulator.
Figure 20.9 illustrates the current limiting feature of the EXTVREGn module.
Current (I)
IMAX
IOUT
Voltage (V)
Figure 20.9. Regulator Current Limiting
Rev. 1.0
365
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
20.6. Foldback Limiting
The foldback limiting feature is a protection mechanism that allows the EXTVREGn module to limit the output
voltage and current to ranges that are within the tolerances of the external bipolar transistor. Bipolar transistors
have two specifications: maximum current, and maximum power. Foldback limiting can approximate power limiting.
The foldback limiting feature is fully programmable to allow the regulator to match the optimum characteristics of
the transistor safe operating area or region.
The maximum current of the external regulator can be specified with the IMAX field. The starting point of the
downward safe operating region slope is set by the FBVOSEL field, and the foldback rate or slope is adjusted by
the FBRATE field. The transistors then level off to a maximum current at higher voltages. This limit is set in the
regulator with the IMIN and IMINFINE fields. Figure 20.10 shows illustrates this voltage and current characteristic
curve.
transistor safe operating region
regulator foldback limiting
current
limiting
IMAX
Current (I)
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
FBRATE
foldback
limiting
IMIN and
IMINFINE
FBVOSEL
FBMAXF set
Voltage (V)
Figure 20.10. Transistor Characterization with Regulator Current and Foldback Limiting
The regulator monitors the voltage across the external transistor using the EXREGSN pin (FBPINSEL = 0) or the
VREGIN pin (FBPINSEL = 1).
The FBVOSEL value should be selected using Equation 20.2.
FBVOSEL  V BJT Supply – V OUT
Equation 20.2. Selecting the Foldback Offset Voltage
The foldback rate (FBRATE) value can be found using the slope of the safe operating region (maximum power
dissipation) of the transistor. Equation 20.3 describes this relationship, where PBJTMAX is given in Watts, Rsense is
given in ohms, and the FBRATE rate is µA/V.
366
Rev. 1.0
P BJTMAX  R sense  12.5  Gain sense
FBRATE = -----------------------------------------------------------------------------------------------2
 V BJT Supply – V OUT 
Equation 20.3. External Regulator Foldback Rate
Foldback limiting can be used independently of the current sensing or limiting features of the regulator. If current
limiting is not used, the IMAX field should be set to the maximum value, and the FBVOSEL field is ignored. The
foldback limiting slope defined by FBRATE will then govern the regulator output current at voltages below
FBVOSEL.
The lower current limit (IMIN and IMINFINE fields) prevents the regulator from dropping the output current to zero
when the output voltage reaches higher levels. If the output of the regulator is connected to ground due to a failure
in the external circuitry, the lower current limit determines how fast the output voltage can recover when the shortcircuit condition is no longer present. The maximum lower current limit can be found using Equation 20.4.
P BJTMAX
IMIN + IMINFINE  I MAX –  ---------------------------  R sense  12.5  Gain sense
 V BJT Supply
Equation 20.4. External Regulator Minimum Current
The PBJTMAX divided by VBJT Supply term is the actual maximum current the external regulator circuit can allow.
Hardware sets the FBMAXF flag to 1 when the regulator reaches maximum foldback at the output current defined
by IMIN and IMINFINE.
20.7. Regulator Stability
To ensure regulator stability even if the external load is very small or goes to zero, the EXTVREGn module also has
an optional pull-up or pull-down on the EXREGBD pin and an optional pull-down on the EXREGOUT pin. When
enabled (WPULLEN = 1), the EXREGBD resistor is connected to ground when in NPN mode (PNSEL = 0) and to
the VREGIN pin supply if the regulator is in PNP mode (PNSEL = 1). The EXREGOUT pull-down resistor is also
enabled by setting WPULLEN to 1. These resistors can also be used to turn off the bipolar when the regulator is
disabled.
These weak pull-up or pull-down resistors are completely independent of the normal weak pull-ups associated with
the pins as described in the port configuration section. Any pins used with the external regulator should be placed
in analog mode as described in the port configuration module to disable the general weak pull-ups on the pins.
Rev. 1.0
367
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
20.8. Configuring the External Regulator
To configure the external regulator:
1. Configure the pins to be used by the external regulator to analog mode.
2. If reset persistence is required, the PBCFG_CONTROL1.EVREGMD bit should be set to 1. This bit will
force the regulator pins to retain their state after any reset except for POR.
3. Select the hardware components.
a. Select the bipolar transistor, typically an NPN device (PNSEL = 0).
b. Select the decoupling capacitor (minimum of 4.7 µF in normal mode and 47 nF in stand-alone mode).
c. (Optional) Select the sense resistor (less than or equal to 1 when using current limiting) and current
sensing configuration.
4. Select the EXTVREGn output voltage using the VOUTSEL field.
5. (Optional) Configure regulator current sensing.
a. Set the current sensing gain (ISOGAIN) to an appropriate value for the sense resistor value and the
maximum current output of the regulator.
b. Enable regulator current sensing (ISNSEN = 1).
6. (Optional) Configure current sensing for other modules.
a. Select the sensing gain (ISADCGAIN). If measured by an ADC, the sensing gain should be set based
on the sense resistor value and the reference for the ADC.
b. Enable the current sensing output for other modules (ADCISNSEN = 1).
7. (Optional) Configure regulator current limiting (regulator current sensing must be enabled).
a. Set the IMAX field to a value below the maximum current rating for the transistor.
8. (Optional) Configure the foldback limiting.
a. Set the FBVOSEL, FBRATE, IMIN, and IMINFINE fields to match the bipolar transistor characteristics.
b. Select the desired foldback limiting sense pin (FBPINSEL).
c. Enable foldback limiting (FBLEN = 1).
9. Enable the regulator (EVREGNEN = 1).
10. Hardware will set the FBMAXF flag if the external regulator reaches maximum foldback.
368
Rev. 1.0
20.9. EXTVREG0 Registers
This section contains the detailed register descriptions for EXTVREG0 registers.
26
25
24
Reserved
FBPINSEL
PNSEL
FBLEN
WPULLEN
Bit
31
30
29
Name
Type
Reset
0
0
0
Bit
15
14
13
28
23
22
21
20
19
18
17
16
Reserved
RW
R
RW
RW
RW
RW
R
0
0
0
0
0
0
0
0
0
0
0
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
SAEN
27
EVREGEN
Register 20.1. EXTVREG0_CONTROL: Module Control
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EXTVREG0_CONTROL = 0x4004_2000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 20.1. EXTVREG0_CONTROL Register Bit Descriptions
Bit
Name
31
EVREGEN
Function
External Regulator Enable.
0: Disable the external regulator.
1: Enable the external regulator.
30:28
Reserved
Must write reset value.
27
FBPINSEL
Foldback Sensing Pin Select.
0: Use the input to the EXREGSN pin for foldback limiting.
1: Use the input to the VREGIN pin for foldback limiting.
26
PNSEL
NPN/PNP Type Select.
0: Select NPN Mode.
1: Select PNP Mode.
25
FBLEN
Foldback Limiting Enable.
0: Disable foldback limiting.
1: Enable foldback limiting.
Rev. 1.0
369
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
Table 20.1. EXTVREG0_CONTROL Register Bit Descriptions
Bit
Name
24
WPULLEN
Function
Weak Pull Up/Down Enable.
This bit enables or disables a weak pull-up or -down on the EXREGBD pin. The
resistor is connected to ground when in NPN mode (PNSEL = 0) and it is connected
to the VREGIN supply if the regulator is in PNP mode (PNSEL = 1). A pull-down
resistor connected to the EXREGOUT pin is also turned on if WPULLEN is set to 1
and the external regulator is enabled. This allows for a minimum load that will
ensure regulator stability even if the external load is very small or goes to zero.
These weak pull-up or pull-down resistors are completely independent of the normal
weak pull-ups associated with the pins, and a pin used with the external regulator
should be placed in analog mode to disable the general weak pull-up.
0: Disable the external regulator weak pull-up/down resistor on the EXREGBD pin
and weak pull-down resistor on the EXREGOUT pin.
1: Enable the external regulator weak pull-up/down resistor on the EXREGBD pin
and weak pull-down resistor on the EXREGOUT pin.
23:1
Reserved
0
SAEN
Must write reset value.
Stand-Alone Mode Enable.
When SAEN is cleared to 0, the external regulator operates normally and the output
of the external transistor must be connected to the EXREGOUT pin. In this mode,
the regulator requires 2 pins: one to drive the base of the external bipolar
(EXREGBD), and one to sense the output voltage (EXREGOUT).
When SAEN is set to 1, the voltage supply of the regulator is the VREGIN supply
and the transistor base driver (EXREGBD) is the regulator output. This allows the
regulator to operate in stand-alone mode, where an external transistor is not used.
The maximum current output of the regulator is 12.5 mA in stand-alone mode.
A decoupling capacitor is required on the regulator output in both normal and standalone modes.
0: Use the external regulator in normal mode.
1: Use the external regulator in stand-alone mode.
370
Rev. 1.0
Register 20.2. EXTVREG0_CONFIG: Module Configuration
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
VOUTSEL
Reserved
IMAX
Type
R
RW
R
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Reset
0
FBRATE
R
RW
0
0
0
FBVOSEL
Reserved
IMIN
IMINFINE
0
Reserved
0
Reserved
Reset
R
RW
R
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EXTVREG0_CONFIG = 0x4004_2010
Table 20.2. EXTVREG0_CONFIG Register Bit Descriptions
Bit
Name
Function
31:30
Reserved
Must write reset value.
29:24
VOUTSEL
Regulator Output Voltage Select.
The external regulator output voltage is VOUTSEL + 1.8 V, where VOUT is given in
100 mV steps. For example, a VOUTSEL setting of 0 is equivalent to a 1.8 V output
voltage and a setting of 12 is equivalent to a 3 V output voltage.
23:19
Reserved
18:16
IMAX
Must write reset value.
Maximum Current Select.
Regulator current sensing must be enabled (ISNSEN = 1) for the regulator to limit
the output current to the value specified by this field.
000: Maximum current limit is 2 A.
001: Maximum current limit is 3 A.
010: Maximum current limit is 4 A.
011: Maximum current limit is 5 A.
100: Maximum current limit is 6 A.
101: Maximum current limit is 7 A.
110: Maximum current limit is 8 A.
111: Maximum current limit is 9 A.
15
Reserved
Must write reset value.
Rev. 1.0
371
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
Table 20.2. EXTVREG0_CONFIG Register Bit Descriptions
Bit
Name
14:12
FBRATE
Function
Voltage Sense Gain Multiplier.
000: Set the foldback rate to 4 A/V.
001: Set the foldback rate to 2 A/V.
010: Set the foldback rate to 1 A/V.
011: Set the foldback rate to 0.5 A/V.
100: Reserved.
101: Set the foldback rate to 8 A/V.
110: Set the foldback rate to 16 A/V.
111: Set the foldback rate to 32 A/V.
11
Reserved
Must write reset value.
10:8
FBVOSEL
Foldback Voltage Offset Select.
000: Foldback voltage offset is 0 V.
001: Foldback voltage offset is 0.5 V.
010: Foldback voltage offset is 1 V.
011: Foldback voltage offset is 1.5 V.
100: Foldback voltage offset is 2 V.
101: Foldback voltage offset is 2.5 V.
110: Foldback voltage offset is 3 V.
111: Foldback voltage offset is 3.5 V.
7:5
Reserved
4:2
IMIN
Must write reset value.
Minimum Current Select.
000: Minimum current limit is 1 A + IMINFINE current.
001: Minimum current limit is 2 A + IMINFINE current.
010: Minimum current limit is 3 A + IMINFINE current.
011: Minimum current limit is 4 A + IMINFINE current.
100: Minimum current limit is 5 A + IMINFINE current.
101: Minimum current limit is 6 A + IMINFINE current.
110: Minimum current limit is 7 A + IMINFINE current.
111: Minimum current limit is 8 A + IMINFINE current.
1:0
IMINFINE
Minimum Current Fine Select.
00: Minimum current limit is IMIN current + 0 A.
01: Minimum current limit is IMIN current + 0.25 A.
10: Minimum current limit is IMIN current + 0.50 A.
11: Minimum current limit is IMIN current + 0.75 A.
372
Rev. 1.0
Register 20.3. EXTVREG0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
FBMAXF
Reset
Type
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EXTVREG0_STATUS = 0x4004_2020
Table 20.3. EXTVREG0_STATUS Register Bit Descriptions
Bit
Name
Function
31:1
Reserved
Must write reset value.
0
FBMAXF
Maximum Foldback Flag.
0: Maximum foldback has not been reached.
1: Maximum foldback has been reached.
Rev. 1.0
373
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
Bit
31
30
Name
ISNSEN
Register 20.4. EXTVREG0_CSCONTROL: Current Sense Control
ADCISNSEN
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
29
28
27
26
25
24
23
Reserved
Type
RW
RW
R
Reset
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Register ALL Access Address
EXTVREG0_CSCONTROL = 0x4004_2040
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 20.4. EXTVREG0_CSCONTROL Register Bit Descriptions
Bit
Name
31
ADCISNSEN
Function
ADC Current Sense Enable.
0: Disable ADC current sensing.
1: Enable ADC current sensing.
30
ISNSEN
External Regulator Current Sense Enable.
0: Disable external regulator current sensing.
1: Enable external regulator current sensing.
29:0
374
Reserved
Must write reset value.
Rev. 1.0
Register 20.5. EXTVREG0_CSCONFIG: Current Sense Configuration
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
0
ISINSEL
Reset
ISOGAIN
ISADCGAIN
RW
RW
RW
0
0
0
0
0
0
0
Register ALL Access Address
EXTVREG0_CSCONFIG = 0x4004_2050
Table 20.5. EXTVREG0_CSCONFIG Register Bit Descriptions
Bit
Name
Function
31:8
Reserved
Must write reset value.
7:6
ISINSEL
External Regulator Current Sense Input Select.
00: Select external regulator current sensing mode 0.
01: Select external regulator current sensing mode 1.
10: Select external regulator current sensing mode 2.
11: Reserved.
5:3
ISOGAIN
External Regulator Current Sense Gain.
000: External regulator current sensing gain is 16.
001: External regulator current sensing gain is 8.
010: External regulator current sensing gain is 4.
011: External regulator current sensing gain is 2.
100: External regulator current sensing gain is 1.
101-111: Reserved.
2:0
ISADCGAIN
ADC Current Sense Gain.
000: ADC current sensing input gain is 16.
001: ADC current sensing input gain is 8.
010: ADC current sensing input gain is 4.
011: ADC current sensing input gain is 2.
100: ADC current sensing input gain is 1.
101-111: Reserved.
Rev. 1.0
375
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
20.10. EXTVREG0 Register Memory Map
Table 20.6. EXTVREG0 Memory Map
EXTVREG0_STATUS EXTVREG0_CONFIG EXTVREG0_CONTROL Register Name
0x4004_2010
ALL Address
0x4004_2020
0x4004_2000
ALL
Access Methods
ALL
ALL | SET | CLR
Bit 31
EVREGEN
Reserved
Bit 30
Reserved
Bit 29
Bit 28
FBPINSEL
Bit 27
VOUTSEL
PNSEL
Bit 26
FBLEN
Bit 25
WPULLEN
Bit 24
Bit 23
Bit 22
Reserved
Bit 21
Bit 20
Bit 19
Bit 18
IMAX
Bit 17
Reserved
Bit 16
Reserved
Bit 15
Bit 14
FBRATE
Bit 13
Reserved
Bit 12
Reserved
Bit 11
Bit 10
FBVOSEL
Bit 9
Bit 8
Bit 7
Reserved
Bit 6
Bit 5
Bit 4
IMIN
Bit 3
Bit 2
Bit 1
IMINFINE
SAEN
FBMAXF
Bit 0
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
376
Rev. 1.0
EXTVREG0_CSCONFIG EXTVREG0_CSCONTROL Register Name
0x4004_2050
0x4004_2040
ALL Address
ALL
ALL | SET | CLR
Access Methods
ADCISNSEN
Bit 31
ISNSEN
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Reserved
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Reserved
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
ISINSEL
Bit 6
Bit 5
ISOGAIN
Bit 4
Bit 3
Bit 2
ISADCGAIN
Bit 1
Bit 0
Table 20.6. EXTVREG0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
377
External Regulator (EXTVREG0)
SiM3U1xx/SiM3C1xx
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
21. Flash Controller (FLASHCTRL0)
This section describes the flash Controller (FLASHCTRL) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the FLASHCTRL block, which is used by all device families covered in this
document.
21.1. Flash Controller Features
The flash Controller module includes the following features:
Provides
control for read timing and prefetch.
an access port for firmware to write and erase flash in system.
Buffers multiple writes to the flash and stalls the core if the buffer is full until the flash operations can
complete.
Secures the flash with a lock and key mechanism.
Allows single writes and erases or multiple writes with a single unlock operation.
Blocks modifications to flash if the Supply Monitor is not enabled as a reset source.
Provides
SiM3xxxx
Flash
RSTSRC Module
VDD Monitor
Reset Source
Enable
FLASHCTRLn
Module
Flash Controller
Status
Write/Erase
Access
Write/Erase
Security (Key)
Figure 21.1. Flash Controller Block Diagram
378
Rev. 1.0
21.2. Overview
The Flash Controller (FLASHCTRL) module provides flash read, write, and erase control. The read controller
includes the prefetch engine controls and the flash read timing settings that must be adjusted appropriately for the
AHB clock of the device. The write and erase control can be used to modify the flash contents in system. This write
and erase interface is protected by a lock and key mechanism to prevent any undesired modification of flash.
21.3. Flash Read Control
The flash read timing is controlled by the speed mode (SPMD) field and the read-store enable (RDSEN) bit. These
bits must be set appropriately for the selected AHB frequency for the system.
When read-store enable (RDSEN) is set to 1, the first flash access is stored in the read store pipeline buffer before
being passed to the AHB. Otherwise, the first flash access is passed directly to the AHB (read through).
Table 21.1. Read Timing Ranges
SPMD Wait Value
RDSEN Value
Setting
Max AHB Frequency
0
0
Non-pipelined, Latency = 0
21 MHz
0
1
Pipelined, Latency = 0
26 MHz
1
0
Non-pipelined, Latency = 1
43 MHz
1
1
Pipelined, Latency = 1
53 MHz*
2
0
Non-pipelined, Latency = 2
65 MHz*
2
1
Pipelined, Latency = 2
80 MHz*
3
0
Non-pipelined, Latency = 3
87 MHz*
3
1
Pipelined, Latency = 3
107 MHz*
*Note: Device operation beyond the maximum frequency listed in the data sheet is not guaranteed, and
should be avoided.
The flash read timing mode (FLRTMD) can also be configured to save power at slower clock frequencies. It should
be set to 1 for AHB clock frequencies above 12 MHz and cleared to 0 for AHB clock frequencies below 12 MHz.
The FLRTMD bit should only be set to 1 when RDSEN is disabled and the SPMD Wait value is zero. FLRTMD has
no effect on the flash read timing.
The flash read controller also includes prefetch engine controls. Enabling the data prefetch (DPFEN = 1) feature
allows data accesses to be stored and queued into the prefetch buffer in addition to instructions, which can help
performance if a large amount of data is accessed sequentially in flash. Firmware can also disable the prefetch
engine (PFINH = 1), which will reduce performance but improve the device’s power consumption.
Rev. 1.0
379
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
21.4. Flash Write and Erase Control
The flash write and erase interface allows firmware to modify the flash in system. This interface is protected by a
security lock and key interface to prevent inadvertent modifications of memory.
Firmware cannot modify flash through the interface when the supply monitor in the VMONn module is disabled or
disabled as a reset source (device reset source module). Any write or erase operations initiated while the supply
monitor is disabled or disabled as a reset source will be ignored.
Firmware should disable interrupts when using the interface to modify flash contents. This will ensure the flash
interface accesses are sequential in time and take the minimum time possible.
21.4.1. Security Interface
The flash interface is initially locked after a reset. The interface is unlocked by writing the initial unlock key (0xA5)
followed by one of the command keys in consecutive writes to the KEY field. Any writes to the WRDATA register
while the interface is locked or an incorrect unlock sequence will permanently lock the flash interface until the next
device reset.
The single unlock key unlocks the flash interface for one write or erase operation. The flash interface will remain
unlocked after a single unlock command if firmware writes an additional value to the KEY field before writing to the
WRDATA register.
The multiple unlock key unlocks the flash interface for write or erase operations until the multiple lock key is written
to the KEY field. The flash interface will remain unlocked if firmware writes any value other than the multiple write
lock to KEY. The multiple lock is not a permanent lock, and the interface can be unlocked again for other
operations.
Table 21.2. Flash Interface Keys
Command
KEY Value
Initial Unlock
0xA5
Single Unlock
0xF1
Multiple Unlock
0xF2
Multiple Lock
0x5A
21.4.2. Writing and Erasing Flash
Once the flash security interface is unlocked, write and erase operations occur using the write address (WRADDR)
and write data (WRDATA) indirect registers. Writes to WRDATA must be half-word aligned, and each half word may
only be written once between erase operations. For a write operation (ERASEEN = 0), the right-justified, half-word
value written to WRDATA will be written to the address specified by WRADDR. For an erase operation (ERASEEN
= 1), a write to WRDATA will initiate an erase on the flash page specified by the WRADDR field. Flash pages are
1024 bytes, and aligned at 1024-byte boundaries in the device, beginning at address 0x0000.
Firmware should write the data to the WRDATA register 16 bits at a time in right-justified format, and hardware
automatically increments the WRADDR field by two after each write operation. The data written to the WRDATA
register is first placed in the controller write buffer. When writing multiple bytes and executing from RAM, firmware
can poll on the BUFSTS flag to wait until the buffer has room before writing more data to the WRDATA register.
This allows firmware to perform other actions while the controller is modifying flash. If the buffer is full and firmware
writes another half-word to WRDATA, the flash controller will stall the AHB bus until the write operation completes,
and the buffer is no longer full. Using this method, firmware can write to WRDATA in a series of successive writes
without having to poll.
Note: For all flash write operations, firmware will stall unless operating from a memory space other than flash.
380
Rev. 1.0
The flash controller can write multiple sequential half-words to flash faster than using individual accesses if the
flash interface is unlocked for multiple byte writes and sequential writes are enabled (SQWEN = 1). Firmware using
this feature should run from a memory space other than flash. Otherwise, the flash controller switches out of
sequential mode for the flash read and back into sequential mode for the write, which causes a longer delay than
individual accesses with SQWEN cleared to 0.
The busy (BUSYF) flag indicates when the flash controller is currently executing a flash write or erase operation.
21.4.3. Writing a Single Half-Word to Flash
To write a single byte to flash:
1. Ensure the supply monitor is enabled and enabled as a reset source in the RSTSRC module.
2. Disable erase operations (ERASEEN = 0).
3. Write the destination address to WRADDR.
4. Disable interrupts.
5. Write the initial unlock value to KEY (0xA5).
6. Write the single unlock value to KEY (0xF1).
7. Write the data half-word to WRDATA in right-justified format.
8. (Optional) If executing code from a memory space other than flash, poll on the BUSYF flag until hardware
clears it to 0.
9. Enable interrupts.
21.4.4. Writing Multiple Half-Words to Sequential Flash Addresses
To write a sequential set of bytes to flash, code should execute from a memory space other than flash and
complete the following steps:
1. Ensure the supply monitor is enabled and enabled as a reset source in the RSTSRC module.
2. Disable erase operations (ERASEEN = 0).
3. Write the initial destination address to WRADDR.
4. Enable sequential writes (SQWEN = 1).
5. Disable interrupts.
6. Write the initial unlock value to KEY (0xA5).
7. Write the multiple unlock value to KEY (0xF2).
8. Write the data half-word to WRDATA in right-justified format.
9. (Optional) Poll on the BUFSTS flag until the buffer has room for more data. If code is executing from RAM,
this allows the core to perform other actions until a write operation completes and the buffer has room. The
AHB bus will automatically stall until the operation completes if firmware writes data to WRDATA when the
buffer is full.
10. Repeat steps 8 and 9 until all data is written. Hardware automatically increments the WRADDR field by 2
after each write operation.
11. (Optional) If executing code from a memory space other than flash, poll on the BUSYF flag until hardware
clears it to 0.
12. Write the multiple lock value to KEY (0x5A).
13. Enable interrupts.
21.4.5. Writing Multiple Half-Words to Non-Sequential Flash Addresses
To write multiple bytes to non-sequential addresses in flash:
1. Ensure the supply monitor is enabled and enabled as a reset source (device reset sources module).
2. Disable erase operations (ERASEEN = 0).
3. Disable interrupts.
4. Write the initial unlock value to KEY (0xA5).
Rev. 1.0
381
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
5. Write the multiple unlock value to KEY (0xF2).
6. Write the destination address to WRADDR.
7. Write the data half-word to WRDATA in right-justified format.
8. (Optional) If executing code from a memory space other than flash, poll on the BUSYF flag until hardware
clears it to 0.
9. Repeat steps 6, 7, and 8 until all data is written.
10. Write the multiple lock value to KEY (0x5A).
11. Enable interrupts.
21.4.6. Erasing a Page of Flash
To erase a page of flash:
1. Ensure the supply monitor is enabled and enabled as a reset source (device reset sources module).
2. Write the address of a byte in the flash page to WRADDR.
3. Enable erase operations (ERASEEN = 1).
4. Disable interrupts.
5. Write the initial unlock value to KEY (0xA5).
6. Write the single unlock value to KEY (0xF1).
7. Write any value to WRDATA in right-justified format to initiate the page erase.
8. (Optional) If executing code from a memory space other than flash, poll on the BUSYF flag until hardware
clears it to 0.
9. Enable interrupts.
21.4.7. Erasing Multiple Flash Pages
To erase multiple pages of flash:
1. Ensure the supply monitor is enabled and enabled as a reset source (device reset sources module).
2. Enable erase operations (ERASEEN = 1).
3. Disable interrupts.
4. Write the initial unlock value to KEY (0xA5).
5. Write the multiple unlock value to KEY (0xF2).
6. Write the address of a byte in the flash page to WRADDR.
7. Write any value to WRDATA in right-justified format to initiate the page erase.
8. (Optional) If executing code from a memory space other than flash, poll on the BUSYF flag until hardware
clears it to 0.
9. Repeat steps 6, 7, and 8 for each page.
10. Write the multiple lock value to KEY (0x5A).
11. Enable interrupts.
382
Rev. 1.0
21.5. FLASHCTRL0 Registers
This section contains the detailed register descriptions for FLASHCTRL0 registers.
Register 21.1. FLASHCTRL0_CONFIG: Controller Configuration
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
SQWEN
28
Reserved
29
ERASEEN
30
BUFSTS
31
BUSYF
Bit
Type
R
R
R
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
Reset
R
0
0
0
RW
0
0
1
1
1
RDSEN
0
Reserved
0
DPFEN
0
PFINH
Reset
Reserved
RW
RW
RW
RW
R
0
0
1
0
0
0
SPMD
RW
0
0
Register ALL Access Address
FLASHCTRL0_CONFIG = 0x4002_E000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 21.3. FLASHCTRL0_CONFIG Register Bit Descriptions
Bit
Name
31:21
Reserved
20
BUSYF
Function
Must write reset value.
Flash Operation Busy Flag.
0: The flash interface is not busy.
1: The flash interface is busy with an operation.
19
BUFSTS
Flash Buffer Status.
0: The flash controller write data buffer is empty.
1: The flash controller write data buffer is full.
18
ERASEEN
Flash Page Erase Enable.
0: Writes to the WRDATA field will initiate a write to flash at the address in the
WRADDR field.
1: Writes to the WRDATA field will initiate an erase of the flash page containing the
address in the WRADDR field.
17
Reserved
Must write reset value.
Rev. 1.0
383
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Table 21.3. FLASHCTRL0_CONFIG Register Bit Descriptions
Bit
Name
16
SQWEN
Function
Flash Write Sequence Enable.
Setting this bit will cause multiple sequential accesses to the flash interface to take
less time than individual accesses if the flash interface is unlocked for multiple byte
writes. When this bit is used, firmware should be running from a memory space
other than flash.
0: Disable sequential write mode.
1: Enable sequential write mode.
15:8
Reserved
7
PFINH
Must write reset value.
Prefetch Inhibit.
Disabling the prefetch can cause slower performance and better power consumption.
0: Any reads from flash are prefetched until the prefetch buffer is full.
1: Inhibit the prefetch engine.
6
DPFEN
Data Prefetch Enable.
Setting this bit allows data accesses to be stored and queued into the prefetch buffer, which can help performance if a large amount of data is accessed sequentially
in flash.
0: Data accesses are excluded from the prefetch buffer.
1: Data accesses are included in the prefetch buffer.
5
Reserved
4
RDSEN
Must write reset value.
Read Store Mode Enable.
When set to 1, the first flash access is stored in the prefetch (read store) before
being passed to the AHB. Otherwise, the first flash access is passed directly to the
AHB (read through).
0: Disable read store mode.
1: Enable read store mode.
3:2
Reserved
1:0
SPMD
Must write reset value.
Flash Speed Mode.
The flash speed mode must be adjusted appropriately for the system AHB frequency.
00: Read and write the flash at speed mode 0.
01: Read and write the flash at speed mode 1.
10: Read and write the flash at speed mode 2.
11: Read and write the flash at speed mode 3.
384
Rev. 1.0
Register 21.2. FLASHCTRL0_WRADDR: Flash Write Address
Bit
31
30
29
28
27
26
25
24
23
Name
WRADDR[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
WRADDR[15:0]
Type
RW
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
FLASHCTRL0_WRADDR = 0x4002_E0A0
Table 21.4. FLASHCTRL0_WRADDR Register Bit Descriptions
Bit
Name
31:0
WRADDR
Function
Flash Write Address.
The flash operation will occur at the address (write) or page (erase) specified by this
field.
Rev. 1.0
385
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Register 21.3. FLASHCTRL0_WRDATA: Flash Write Data
Bit
31
30
29
28
27
26
25
24
23
Name
WRDATA[31:16]
Type
W
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
WRDATA[15:0]
Type
W
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
FLASHCTRL0_WRDATA = 0x4002_E0B0
Table 21.5. FLASHCTRL0_WRDATA Register Bit Descriptions
Bit
Name
31:0
WRDATA
Function
Flash Write Data.
When erases are enabled, a write to this field will initiate an erase of the flash page
containing the address specified by WRADDR.
When erases are disabled, a right-justified, half-word write to this field will write the
value to the flash address specified by WRADDR. Any data written to the upper half
of WRDATA is ignored.
386
Rev. 1.0
Register 21.4. FLASHCTRL0_KEY: Flash Modification Key
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
Reserved
KEY
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
FLASHCTRL0_KEY = 0x4002_E0C0
Table 21.6. FLASHCTRL0_KEY Register Bit Descriptions
Bit
Name
31:8
Reserved
7:0
KEY
Function
Must write reset value.
Flash Key.
Writing the initial unlock key (0xA5) followed by the single unlock key (0xF1) to this
field will unlock the flash interface for single write or erase operations. The interface
will relock after the operation.
Writing the initial unlock key (0xA5) followed by the multiple unlock key (0xF2) will
unlock the flash interface for multiple write and erase operations. The interface will
remain unlocked until the multiple lock key (0x5A) is written to KEY.
All other values for the KEY field are reserved.
Rev. 1.0
387
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Register 21.5. FLASHCTRL0_TCONTROL: Flash Timing Control
Bit
31
30
29
28
27
26
25
24
Name
23
22
21
20
19
18
17
16
Reserved
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Name
Reserved
FLRTMD
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Reserved
Type
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
1
0
1
1
1
Register ALL Access Address
FLASHCTRL0_TCONTROL = 0x4002_E0D0
Table 21.7. FLASHCTRL0_TCONTROL Register Bit Descriptions
Bit
Name
Function
31:7
Reserved
Must write reset value.
6
FLRTMD
Flash Read Timing Mode.
0: Configure the flash read controller for AHB clocks below 12 MHz.
1: Configure the flash read controller for AHB clocks above 12 MHz.
5:0
388
Reserved
Must write reset value.
Rev. 1.0
21.6. FLASHCTRL0 Register Memory Map
FLASHCTRL0_WRDATA FLASHCTRL0_WRADDR FLASHCTRL0_CONFIG Register Name
ALL Address
0x4002_E0B0
0x4002_E0A0
0x4002_E000
Access Methods
ALL
ALL
ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Reserved
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
BUSYF
Bit 20
BUFSTS
Bit 19
ERASEEN
Bit 18
Reserved
Bit 17
SQWEN
Bit 16
WRDATA
WRADDR
Bit 15
Bit 14
Bit 13
Bit 12
Reserved
Bit 11
Bit 10
Bit 9
Bit 8
PFINH
Bit 7
DPFEN
Bit 6
Reserved
Bit 5
RDSEN
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
SPMD
Bit 0
Table 21.8. FLASHCTRL0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
389
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Table 21.8. FLASHCTRL0 Memory Map
FLASHCTRL0_TCONTROL FLASHCTRL0_KEY Register Name
0x4002_E0D0
0x4002_E0C0
ALL Address
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Reserved
Reserved
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
FLRTMD
Bit 6
Bit 5
Bit 4
KEY
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
Flash Controller (FLASHCTRL0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
390
Rev. 1.0
22. Inter-Integrated Circuit Bus (I2C0 and I2C1)
This section describes the I2C module, and is applicable to all products in the following device families, unless
otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the I2C block, which is used by I2C0 and I2C1 on all device families covered
in this document.
22.1. I2C Features
The I2C module includes the following features:
Standard
(up to 100 kbps) and Fast (400 kbps) transfer speeds.
operate down to APB clock divided by 32768 or up to APB clock divided by 8.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to disable all slave states.
Programmable clock high and low period.
Programmable data setup/hold times.
Spike suppression up to 2 times the APB period.
Can
I2Cn Module
TX/RX FIFO
DATA
Shift Register
Slave Address
Mask
SDA
SCL
Slave Address
APB Clock
Clock Scaler
Timer Control
32-bit Timer
Bus Control
32-bit Timer Reload
Figure 22.1. I2C Block Diagram
Rev. 1.0
391
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.2. I2C Protocol
The I2C interface is a two-wire, bi-directional serial bus. Reads and writes to the interface are byte oriented with
the I2C interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/8th of
the APB clock as a master or slave (this can be faster than allowed by the I2C specification, depending on the
clock source used). A method of extending the clock-low duration is available to accommodate devices with
different speed capabilities on the same bus.
The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/
stop control and generation.
22.2.1. Hardware Configuration
Figure 22.2 shows a typical I2C configuration. The I2C specification allows any recessive voltage between 3.0 and
5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and
SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar
circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and
SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on
the bus is limited only by the requirement that the rise and fall times on the bus not exceed 1000 ns (rise) and
300 ns (fall) for Standard mode communication and 300 ns (rise) and 300 ns (fall) for fast mode communication.
5V
3.3 V
3.6 V
5V
3.3 V
I2C Master
Device
I2C Slave
Device
I2C Master
and Slave
Device
I2C Slave
Device
SCL
SDA
Figure 22.2. I2C Hardware Configuration
A typical I2C transaction consists of a start condition followed by an address (7- or 10-bit), the Read/Write direction
bit, one or more bytes of data, and a stop condition. Address and data fields are transferred MSB first. Each byte
that is received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL. If the
receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA
during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to 1 to
indicate a read operation and cleared to 0 to indicate a write operation.
A start condition occurs when the SDA signal changes from high to low while SCL is high, and a stop condition
occurs when the SDA signal changes from low to high while SCL is high. During normal data bit transitions, the
SCL signal is low while SDA changes state.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The master
generates the start condition and then transmits the slave address and direction bit. If the transaction is a write
operation from the master to the slave, the master transmits the data a byte at a time and waits for an ACK from the
slave at the end of each byte. For read operations, the slave transmits the data and waits for an ACK from the
master at the end of each byte. At the end of the data transfer, the master generates a stop condition to terminate
the transaction and free the bus. Figure 22.3 illustrates a typical I2C 7-bit address transaction.
Both address sizes (7- and 10-bit) can be used on the same I2C bus.
392
Rev. 1.0
SCL
SDA
7-bit Address
R/W
Address Phase
START
ACK
8-bit Data
Data Phase
NACK
STOP
Time
Figure 22.3. Typical I2C 7-bit Address Transaction
22.2.2. Address Phase
The address phase consists of the 7- or 10-bit address, the read/write direction bit (R/W), and the slave’s ACK or
NACK response.
With 7-bit address transfers, the address phase consists of a single byte operation and one ACK or NACK
response from the slave. The R/W bit is the last bit transmitted before the ACK or NACK. Figure 22.4 shows the 7bit address phase.
Master
Slave
SCL
SDA
7-bit Address
Address Phase
R/W
ACK
Time
Figure 22.4. I2C 7-bit Address Phase
The 10-bit address phase consists of two bytes and two ACK or NACK responses from the slave. The first address
byte contains bits 9 and 8 of the address (fixed value of 1111 0XX, where XX are the two address bits) and the R/W
bit, which is the last bit of the byte. The rest of the address (bits 7:0) is transmitted in the second byte. All slaves
that match the first part of the address will ACK after the first address byte. The one slave that also matches the
second address byte will ACK after the second byte.
The address phase of a write operation using a 10-bit address consists of a single start followed by the two
address bytes with R/W set to 0 for a write. The address phase of a read operation using a 10-bit address consists
of a start followed by the two address bytes with R/W set to 0 for a write, followed by a repeated start with the first
address byte and R/W set to 1 for a read, and the data for the master.
Figure 22.5 shows the 10-bit address phases for both a write and a read operation.
Rev. 1.0
393
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Write Operation
Master
Slave
Master
Slave
ACK
10-bit Address (bits 7:0)
ACK
SCL
SDA
1
1
1
1
0
10-bit Address (bits 9:8)
0
R/W
Address Phase
Time
Read Operation
Master
Slave
Master
Slave
ACK
10-bit Address (bits 7:0)
ACK
Master
Slave
SCL
SDA
1
1
1
1
0
0
10-bit Address (bits 9:8)
R/W
1
Repeated
START
1
1
1
0
10-bit Address (bits 7:0)
1
R/W
ACK
Address Phase
Time
Figure 22.5. I2C 10-bit Address Phase
22.2.3. Data Phase
The data phase follows the address phase and is the same for both 7- and 10-bit address modes. The data phase
consists of a byte of data followed back an ACK or NACK. In the case of a read operation, the slave provides the
data byte and the master responds as shown in Figure 22.6. In the case of a write operation, the master provides
the data byte and the slave responds as shown in Figure 22.7.
The entire data phase for a transaction can consist of one or more bytes. The master determines the total number
of bytes sent by deciding when to send the stop condition that ends the transaction.
Slave
Master
SCL
SDA
8-bit Data
Data Phase
ACK
Time
Figure 22.6. Single Byte I2C Read Data Phase
394
Rev. 1.0
Master
Slave
SCL
SDA
8-bit Data
Data Phase
ACK
Time
Figure 22.7. Single Byte I2C Write Data Phase
Rev. 1.0
395
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.3. Clocking
The I2C module has an internal 6-bit APB clock divider that allows the module to support various APB and I2C
clock frequencies. The divided I2C clock serves as the timebase for the SCL signal, rise and fall timing, and
hardware-supported timeouts. The SCALER field in the CONFIG register sets the I2C module clock frequency
(FI2C) according to Equation 22.1.
F APB
F I2C = ---------------------------------------- 64 – SCALER 
Equation 22.1. I2C Module Clock Frequency
22.3.1. Clock Setup
When operating as an I2C master, the I2C clock high and low times (TSCL_HIGH and TSCL_LOW) are based off the
I2C module clock, and can be independently configured. The clock high time is determined by the T1RL field in the
TIMERRL register, as shown in Equation 22.2. Likewise, the clock low time is determined by the SCLL field in the
SCONFIG register, shown in Equation 22.3.
256 – T1RL
T SCL_HIGH = -----------------------------F I2C
Equation 22.2. SCL High Time
256 – SCLL
T SCL_LOW = ------------------------------F I2C
Equation 22.3. SCL Low Time
The I2C bus master controls the clock. However, slave devices have the option to extend the clock low time if
needed. When operating as an I2C slave, the SCLL field defines a period for the device to hold SCL low after
detecting a falling edge on the bus.
22.4. Operational Modes
The I2C module supports both master and slave states. Each step of the transaction process is controlled both by
hardware and firmware to provide flexibility. A typical I2C module interrupt service routine contains several states to
determine the module’s next actions in response to activity on the bus. Each state must perform actions in the
following order:
1. Set and clear bits for the next state.
2. Write or read from the DATA register.
3. Arm the transmit or receive operation.
4. Clear the pending interrupt flag.
The I2C module can send or receive multiple bytes autonomously during the data phase by setting the BC field in
the CONFIG register to a value other than 1. If the BC value is set to a value other than 1, the transmit or receive
interrupt will occur when all bytes have been sent or received (when BP is equal to BC). If multiple bytes are sent
during a transaction using a BC value other than 1, the least-significant byte in the DATA register will be sent or
received first.
The I2C module supports 7-bit addresses in hardware and can support 10-bit addresses by using firmware to
transmit and decode the second address byte.
396
Rev. 1.0
The basic software-controlled master and slave transactions are described in detail in the follow section. The
additional features of the module are described in Section 22.6 and DMA modes are described in Section 22.8.
22.4.1. Master Write Transaction
In a master write transaction, the I2C module is in master mode and sends one or more bytes of data to an
addressed slave on the bus.
The master write operation starts with firmware setting the STA bit to generate a start condition. A start interrupt
occurs after the hardware transmits a start condition. The ISR or firmware routine should then clear the start bit
(STA), set the targeted slave address and the R/W direction bit in the DATA register, set the byte count, arm the
transmission (TXARM = 1), and clear the start interrupt.
After the hardware transmits the address and direction bit, a transmit interrupt occurs. The ISR should check the
ACK bit to determine if the addressed slave acknowledged the address and is ready to receive data. If the master
received a NACK, no slaves acknowledged the address, and firmware should set the STO bit to generate a stop. If
the master received an ACK, the firmware should load the data into the DATA register, arm the transmission
(TXARM = 1), and clear the transmit interrupt. This process is identical for each byte or set of bytes in the
transmission.
For each set of bytes (determined by the BC field), the hardware generates an acknowledge interrupt if the slave
NACKs a transmission, and will not generate an interrupt if the slave ACKs. If the slave NACKs, the master can
choose to re-transmit the data or start the process over. To stop the current transmission, firmware should set the
STO bit to generate a stop condition. When the stop interrupt occurs, the transmission can be re-started by setting
the STA bit to generate a start condition.
When the hardware transmits the last data byte, a transmit interrupt occurs. The firmware can check the ACK or
NACK status and should set the STO bit to generate a stop condition and clear the transmit interrupt before exiting
the ISR. The transmission does not need to be armed in this case because an address or data isn’t being sent.
A stop interrupt occurs after the hardware transmits the stop condition. Firmware should clear the stop interrupt
and exit the ISR, completing the transaction.
Figure 22.8 shows a flow diagram of this master write transaction process.
Rev. 1.0
397
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Firmware sets the
STA bit.
SCL
SDA
1. Clear STA.
2. Set byte count (BC).
3. Write DATA with the slave address
and R/W bit.
4. Arm transmission (TXARM = 1).
5. Clear the start interrupt (STAI = 0).
START
Start Interrupt:
ISR 1st pass
SCL
SDA
7-bit Address
R/W
Master Address Phase
Handle NACK accordingly
(stop transfer, reschedule
transfer, etc.).
No
ACK?
ACK
Yes
Any bytes
remaining?
No
Yes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Transmit Interrupt:
ISR 2nd – (n-1)th pass
Transmit Interrupt:
ISR nth pass
Yes
Set BC to
remaining bytes.
1. Write DATA with the correct number
of bytes.
2. Arm transmission (TXARM = 1).
3. Clear the transmit interrupt (TXI = 0).
1. Set STO.
2. Clear the transmit
interrupt (TXI = 0).
SCL
SCL
SDA
SDA
8-bit Data
Master Data Phase
ACK
STOP
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Stop Interrupt:
ISR (n+1)th pass
Figure 22.8. Master Write Flow Diagram (7-bit Address)
398
Rev. 1.0
22.4.2. Master Read Transaction
In a master read transaction, the I2C module is in master mode and receives one or more bytes of data from an
addressed slave on the bus.
The master read operation starts the same as the master write operation with firmware setting the STA bit to
generate a start condition. A start interrupt occurs after the hardware transmits a start condition. The ISR or
firmware routine should then clear the start bit (STA), set the targeted slave address and the R/W direction bit in the
DATA register, set the byte count, arm the transmission (TXARM = 1), and clear the start interrupt.
After the hardware transmits the address and direction bit, a transmit interrupt occurs. The ISR should check the
ACK bit to determine if the addressed slave acknowledged the address and is ready to receive data. If the master
received a NACK, no slaves acknowledged the address, and firmware should set the STO bit to generate a stop. If
the master received an ACK, the firmware should arm reception (RXARM = 1), set the byte count, and clear the
transmit interrupt.
A master acknowledge interrupt occurs for each byte received from the slave (determined by the BC field). The
firmware must set the ACK bit and clear the acknowledge interrupt.
When the master receives all of the bytes of the transfer (BP is equal to BC), a receive interrupt occurs. The
firmware must read the data from the FIFO using the DATA register, set the BC field for the next reception, arm
reception (RXARM = 1), and clear the receive interrupt. If the master does not need to read any additional data
from the slave, the firmware should set the STO bit to generate a stop and clear the receive interrupt.
A stop interrupt occurs after the hardware transmits the stop condition. Firmware should clear the stop interrupt
and exit the ISR, completing the transaction.
Figure 22.9 shows a flow diagram of this master read transaction process.
Rev. 1.0
399
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Firmware sets the
STA bit.
SCL
SDA
1. Clear STA.
2. Set byte count (BC).
3. Arm transmission (TXARM = 1).
4. Clear the start interrupt (STAI = 0).
START
Start Interrupt:
ISR 1st pass
SCL
SDA
7-bit Address
R/W
Master Address Phase
Handle NACK accordingly
(stop transfer, reschedule
transfer, etc.).
No
ACK?
ACK
Yes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Transmit Interrupt:
ISR 2nd pass
Yes
Set BC to
remaining bytes.
1. Arm reception (RXARM = 1).
2. Clear the transmit interrupt (TXI = 0).
SCL
SDA
8-bit Data (from Slave)
1. ACK incoming data byte.
2. Clear the acknowledge interrupt
(ACKI = 0).
Acknowledge Interrupt:
ISR pass for each byte
SCL
SDA
IF BP = BC, hardware transitions
to the receive interrupt.
ACK
Master ACK
Read the data (BC number of
bytes) from the DATA register.
Any bytes
remaining?
No
Receive Interrupt:
ISR pass for every BC
number of bytes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Yes
Set BC to
remaining bytes.
1. Set STO.
2. Clear the receive interrupt
(RXI = 0).
1. Arm reception (RXARM = 1).
2. Clear the receive interrupt (RXI = 0).
SCL
SDA
STOP
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Stop Interrupt:
ISR nth pass
Figure 22.9. Master Read Flow Diagram (7-bit Address)
400
Rev. 1.0
22.4.3. Repeated Starts
Repeated starts are used in master transactions when slaves require a write before the master can read data. The
repeated start allows the master to maintain control of the bus even though two separate transactions take place.
The repeated start is the same as a master write transaction followed by a master read transaction where the write
ends with another start instead of a stop condition.
The repeated start operation begins with firmware setting the STA bit to generate a start condition. A start interrupt
occurs after the hardware transmits a start condition. The ISR or firmware routine should then clear the start bit
(STA), set the targeted slave address and the R/W direction bit (write) in the DATA register, set the byte count, arm
the transmission (TXARM = 1), and clear the start interrupt.
After the hardware transmits the address and direction bit, a transmit interrupt occurs. The ISR should check the
ACK bit to determine if the addressed slave acknowledged the address and is ready to receive data. If the master
received a NACK, no slaves acknowledged the address, and firmware should set the STO bit to generate a stop. If
the master received an ACK, the firmware should write the data to the DATA register, set the byte count, arm the
transmission (TXARM = 1), and clear the transmit interrupt.
The second transmit interrupt occurs after the master sends the data to the slave. The firmware should set the STA
bit again and clear the transmit interrupt to generate the repeated start.
In the second start interrupt pass, the firmware should again write the slave address and R/W direction bit (read) in
the DATA register before clearing the start bit, arming the transmission (TXARM = 1), setting the byte count, and
clearing the start interrupt.
A master acknowledge interrupt occurs for each byte received from the slave (determined by the BC field). The
firmware must set the ACK bit and clear the acknowledge interrupt.
When the master receives all of the bytes of the transfer (BP is equal to BC), a receive interrupt occurs. The
firmware must read the data from the DATA register, set the BC field for the next reception, arm reception (RXARM
= 1), and clear the receive interrupt. If the master does not need to read any additional data from the slave, the
firmware should set the STO bit to generate a stop and clear the receive interrupt.
A stop interrupt occurs after the hardware transmits the stop condition. Firmware should clear the stop interrupt
and exit the ISR, completing the transaction.
Figure 22.10 and Figure 22.11 show a flow diagram of the master repeated start process.
Rev. 1.0
401
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Firmware sets the
STA bit.
SCL
SDA
1. Clear STA.
2. Set byte count (BC).
3. Write DATA with the slave address
and R/W bit.
4. Arm transmission (TXARM = 1).
5. Clear the start interrupt (STAI = 0).
START
Start Interrupt:
ISR 1st pass
SCL
SDA
No
ACK?
7-bit Address
R/W
Master Address Phase
Handle NACK accordingly
(stop transfer, reschedule
transfer, etc.).
Yes
ACK
Transmit Interrupt:
ISR 2nd pass
1. Write DATA with the correct number
of bytes.
2. Set byte count (BC).
3. Arm transmission (TXARM = 1).
4. Clear the transmit interrupt (TXI = 0).
SCL
SDA
ACK
8-bit Data
Master Data Phase
No
ACK?
Handle NACK accordingly
(stop transfer, reschedule
transfer, etc.).
Transmit Interrupt:
ISR 3rd pass
Yes
1. Set the STA bit.
2. Clear the transmit interrupt (TXI = 0).
SCL
SDA
REPEATED
START
1. Clear STA.
2. Set byte count (BC).
3. Write DATA with the slave address
and R/W bit.
4. Arm transmission (TXARM = 1).
5. Clear the start interrupt (STAI = 0).
Start Interrupt:
ISR 4th pass
SCL
SDA
7-bit Address
R/W
Master Address Phase
ACK
A
Figure 22.10. Master Repeated Start (Write/Read) Flow Diagram (7-bit Address) (Page 1/2)
402
Rev. 1.0
A
SCL
SDA
7-bit Address
R/W
Master Address Phase
Handle NACK accordingly
(stop transfer, reschedule
transfer, etc.).
No
ACK?
ACK
Yes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Transmit Interrupt:
ISR 5th pass
Yes
Set BC to
remaining bytes.
1. Arm reception (RXARM = 1).
2. Clear the transmit interrupt (TXI = 0).
SCL
SDA
8-bit Data (from Slave)
1. ACK incoming data byte.
2. Clear the acknowledge interrupt
(ACKI = 0).
Acknowledge Interrupt:
ISR pass for each byte
SCL
SDA
IF BP = BC, hardware transitions
to the receive interrupt.
ACK
Master ACK
Read the data (BC number of
bytes) from the DATA register.
Any bytes
remaining?
No
Receive Interrupt:
ISR pass for every BC
number of bytes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Yes
Set BC to
remaining bytes.
1. Set STO.
2. Clear the receive interrupt
(RXI = 0).
1. Arm reception (RXARM = 1).
2. Clear the receive interrupt (RXI = 0).
SCL
SDA
STOP
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Stop Interrupt:
ISR nth pass
Figure 22.11. Master Repeated Start (Write/Read) Flow Diagram (7-bit Address) (Page 2/2)
Rev. 1.0
403
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.4.4. Slave Write Transaction
In a slave write transaction, the I2C module is in slave mode and receives one or more bytes of data from a master.
The slave write operation starts with a start interrupt after a master generates a start and sends the address on the
bus. The firmware should read the address and R/W direction bit from the DATA register and determine if the
address matches the slave address. If not, the slave should send a NACK by clearing the ACK bit to 0 and clear
the start interrupt. If the slave address does match, the slave should ACK the address by setting ACK to 1, set the
byte count, clear the start bit, arm reception (RXARM = 1), and clear the start interrupt.
An acknowledge interrupt occurs each time the slave receives a byte. The firmware should respond with either an
ACK or NACK and clear the acknowledge interrupt.
When the slave receives the last byte of the current packet (BP = BC), a receive interrupt occurs. The slave should
read the data from the DATA register, set the byte count for the next set of bytes, arm reception, and clear the
receive interrupt. If this is the last set of bytes the slave will receive, the slave should clear the receive interrupt.
A stop interrupt occurs after the master generates a stop condition on the bus. The firmware should clear the stop
bit and the stop interrupt.
Figure 22.12 shows a flow diagram of this slave write transaction process.
22.4.5. Slave Read Transaction
In a slave read transaction, the I2C module is in slave mode and sends one or more bytes of data to a master.
The slave read operation starts with a start interrupt after a master generates a start and sends the address on the
bus. The firmware should read the address and R/W direction bit from the DATA register and determine if the
address matches the slave address. If not, the slave should send a NACK by clearing the ACK bit to 0 and clear
the start interrupt. If the slave address does match, the slave should ACK the address by setting ACK to 1, set the
byte count, write the data to the DATA register, clear the start bit, arm transmission (TXARM = 1), and clear the
start interrupt.
A transmit interrupt occurs each time the slave sends a set of bytes (BP = BC). The firmware should check if there
are any bytes remaining for the current transfer. If so, the byte count should be set, the new data written to the
DATA register, transmission armed (TXARM = 1), and the transmit interrupt cleared. If no data remains to be sent,
the slave should clear the transmit interrupt and wait for the master to generate a stop.
A stop interrupt occurs after the master generates a stop condition on the bus. The firmware should clear the stop
bit and clear the stop interrupt.
Figure 22.13 shows a flow diagram of this slave read transaction process.
404
Rev. 1.0
Wait for a start
interrupt.
SCL
SDA
Read the address and R/W direction
bit from DATA.
7-bit Address
R/W
Master Address Phase
START
Address match?
No
Start Interrupt:
ISR 1st pass
Yes
1. Send an ACK (ACK = 1).
2. Set byte count (BC).
3. Arm reception (RXARM = 1).
4. Clear the STA bit.
5. Clear the start interrupt (STAI = 0).
1. Send a NACK (ACK = 0).
2. Clear the STA bit.
3. Clear the start interrupt
(STAI = 0).
SCL
SDA
8-bit Data (from Master)
Any bytes
remaining?
No
Send a NACK.
Yes
Acknowledge Interrupt:
ISR pass for each byte
Send an ACK.
Clear the acknowledge
interrupt (ACKI = 0).
SCL
SDA
IF BP = BC, hardware transitions
to the receive interrupt.
ACK
Slave ACK
Read the data (BC number of
bytes) from the DATA register.
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Receive Interrupt:
ISR pass for every BC
number of bytes
Yes
Set BC to
remaining bytes.
1. Arm reception (RXARM = 1).
2. Clear the receive interrupt (RXI = 0).
SCL
SDA
STOP
Stop Interrupt:
ISR nth pass
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Figure 22.12. Slave Write Flow Diagram (7-bit Address)
Rev. 1.0
405
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Wait for a start
interrupt.
SCL
SDA
Read the address and R/W direction
bit from DATA.
START
7-bit Address
R/W
Master Address Phase
Address match?
No
Start Interrupt:
ISR 1st pass
Yes
1. Send an ACK (ACK = 1).
2. Set byte count (BC).
3. Write the data to the DATA
register.
4. Arm transmission (TXARM = 1).
5. Clear the STA bit.
6. Clear the start interrupt (STAI = 0).
1. Send a NACK (ACK = 0).
2. Clear the STA bit.
3. Clear the start interrupt
(STAI = 0).
SCL
SDA
Any bytes
remaining?
No
1. Clear the transmit
interrupt.
2. Wait for a stop.
8-bit Data
Slave Data Phase
ACK
Yes
Bytes
remaining less
than maximum
BC?
No
Set BC to
maximum.
Transmit Interrupt:
ISR 2nd – (n-1)th pass
Yes
Set BC to
remaining bytes.
1. Write new data to DATA register.
2. Arm transmission (TXARM = 1).
3. Clear the transmit interrupt (TXI = 0).
SCL
SDA
STOP
Stop Interrupt:
ISR nth pass
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Figure 22.13. Slave Read Flow Diagram (7-bit Address)
406
Rev. 1.0
22.5. Error Handling
22.5.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a stop condition or after the SCL and SDA
lines remain high for a specified time. In the event that two or more devices attempt to begin a transfer at the same
time, the I2C protocol employs an arbitration scheme to force one master to give up the bus. The master devices
continue transmitting until one attempts to transmit a 1 while the other attempts to transmit a 0. Since the bus is
open-drain, the bus will be pulled low, and the master attempting to transmit the 1 will detect a low SDA signal and
lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes
a slave (if slave states are supported) and receives the rest of the transfer, if addressed. This arbitration scheme is
non-destructive: one device always wins, and no data is lost.
In the case of an arbitration lost event, the arbitration lost interrupt occurs. The read-only ARBLF flag mirrors the
state of the ARBLI interrupt flag. This interrupt can occur in both master or slave mode whenever the I2C module is
attempting to transmit data on the bus. When configured as a slave, the ARBLI interrupt flag indicates a protocol
violation on the bus. In master mode, the firmware may want to save the aborted slave target and R/W direction bit
to allow this attempt to be rescheduled after any pending slave response, if supported.
22.5.2. SMBus SCL Low Timeout
If the SCL line is held low by a device on the bus, no further communication is possible. Furthermore, the master
cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies
that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout”
condition. Devices that have detected the timeout condition must reset their communication interfaces no later than
10 ms after detecting the timeout condition.
When the I2C module is enabled (I2CEN = 1), the dedicated I2C 32-bit timer provides a counter for SCL low
timeout detection. The SCL low timeout counter is 20 bits, with Timer Byte [3: 2] providing the upper 16 bits of the
counter. The least significant bits of the timeout counter are not available to program. The timeout counter can be
set by setting the T3:T2 and T3RL:T2RL fields. The hardware automatically forces the timer to reload when SCL is
high and allows the timer to count when SCL is low.
In the event that T3:T2 matches the value in T3RL:T2RL, the timeout T3I flag will be set and an interrupt will be
generated, if enabled. If this interrupt occurs, firmware can reset the I2C module using the RESET bit.
22.5.3. Bus Free Timeout
The I2C bus is free if all previous transactions ended with a stop condition and both SCL and SDA are high. The
I2C module supports a bus free timeout that detects if SCL and SDA are high for the specified timeout period
without a stop condition appearing on the bus.
The dedicated I2C Timer Byte 0 serves as the bus free timeout counter when the module is enabled (I2CEN = 1).
The T0 field contains the timeout value and T0RL contains the counter reload value. T0 will count up if both SCL
and SDA are high, and hardware forces T0 to reload from T0RL if SCL or SDA are low. If the I2C module is waiting
for the bus to be free before starting a transfer, the module will generate the start condition after the timeout period
expires.
Rev. 1.0
407
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.6. Additional Features
22.6.1. Hardware Acknowledge and General Call Addressing
When the HACKEN bit in the CONTROL register is cleared to 0, the firmware on the device must detect incoming
slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing the ACK bit
defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received during the last
ACK cycle. ACKRQF is set each time a byte is received, indicating that an outgoing ACK value is needed. When
ACKRQF is set, firmware should write the desired outgoing value to the ACK bit before clearing the appropriate
interrupt flag. A NACK will be generated if software does not write the ACK bit before clearing the interrupt. SDA
will reflect the defined ACK value immediately following a write to the ACK bit; however, SCL will remain low until
firmware clears the interrupt. If a received slave address is not acknowledged, further slave events will be ignored
until the next start is detected.
The hardware acknowledge feature (enabled when HACKEN = 1) provides for automatic 7-bit slave address
recognition and ACK generation. The ADDRESS and MASK fields define which addresses are automatically
recognized by the hardware. A single address or range of addresses (including the General Call Address of all 0’s)
can be specified using these two registers. A 1 in a bit position of the slave address mask (MASK) enables a
comparison between the received slave address and the hardware’s slave address (ADDRESS) for those bits. A 0
in the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. Additionally,
hardware will recognize the General Call Address (all 0’s) if the GCEN bit in the CONTROL register is set to 1.
Firmware can use the SLVAF bit to determine if the slave recognized the slave address or the General Call.
Table 22.1 shows some example parameter settings and the slave addresses that will be recognized by hardware.
Table 22.1. Hardware Address Recognition Examples (HACKEN = 1)
Hardware Slave
Address
(ADDRESS)
Hardware Slave
Address Mask
(MASK)
General Call
Address
(GCEN)
Slave Addresses
Recognized by
Hardware
0x34
0x7F
Disabled
0x34
0x34
0x7F
Enabled
0x34, 0x00
0x34
0x7E
Disabled
0x34, 0x35
0x34
0x7E
Enabled
0x34, 0x35, 0x00
0x70
0x73
Disabled
0x70, 0x74, 0x78, 0x7C
During the data phases of the transfer, the I2C hardware in receiver mode will use the value currently specified by
the ACK bit to automatically respond during the ACK cycle of an incoming data byte. As a transmitter, reading the
ACK bit indicates the value received on the last ACK cycle. The ACKRQF bit is not used when hardware ACK
generation is enabled. If a received slave address is NACKed by hardware, the hardware will ignore any further
slave events until the next start is detected and will not generate a start interrupt.
When hardware acknowledge is enabled in receive mode, the last byte acknowledge enable bit (LBACKEN) can
be used to automatically NACK the last byte of a transfer, if desired.
408
Rev. 1.0
22.6.1.1. Automatic Transmit or Receive Enable
The automatic transmit or receive mode can only be used if hardware acknowledge is enabled. If the ATXRXEN bit
is set to 1, the I2C module will automatically ACK the incoming address and switch to either receive or transmit
mode depending on the R/W bit. Enabling automatic transmit or receive mode bypasses the start interrupt, so the
receive or transmit interrupt is the first interrupt triggered if ATXRXEN is set to 1.
22.6.2. SDA Setup and Hold Time Extensions
The data setup and hold times can be optionally extended using the SETUP and HOLD fields in the SCONFIG
register. I2C Timer Byte 0 determines the data setup and hold times if SETUP and HOLD are 0. If SETUP or HOLD
is set to a non-zero value, this setting overrides the I2C Timer Byte 0 count.
These extensions are based on the I2C module clock, and the equations for the additional time are provided in the
register descriptions for these fields.
22.6.3. General Purpose Timer
When the I2C is not in use (I2CEN = 0), the dedicated I2C 32-bit timer that generates SCL and SDA timing can be
used as an additional general purpose count-up timer.
This I2C timer can be configured to the following modes:
Mode
0: One 32-bit timer with auto-reload (Timer Bytes [3: 0]).
Mode 1: Two 16-bit timers with auto-reload (high timer: Timer Bytes [3: 2], low timer: Timer Bytes [1: 0]).
Mode 2: Four 8-bit timers with auto-reload (Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0).
Mode 3: One 16-bit and two 8-bit timers with auto-reload (Timer Bytes [3: 2], Timer Byte 1, and Timer Byte
0).
The mode of the timers can be controlled using the TMD field. The TxRUN bits control the timers, TxIEN bits
enable the timer interrupts, Tx fields contain the current timer value, and TxRL fields contain the reload values.
When one of the timers overflows (from all 1’s to all 0’s), the appropriate TxI interrupt flag will be set and an I2C
interrupt will occur, if enabled. The timer run bits (TxRUN) are gated by a global I2C timer enable bit (TIMEREN)
that must be set to 1 for the timers to count on the I2C module clock.
22.6.4. Noise Filtering
By default, there is a three-stage filter on both the SDA and SCL lines to help prevent noisy bus situations from
affecting the peripheral and causing bus errors. Under most conditions this filter should be left enabled. If the APB
clock frequency is relatively slow, this filter could have the side effect of filtering out the desirable bus signals. The
filter may be disabled by setting the FMD bit in the CONTROL register to 1.
22.7. Debug Mode
Firmware can set the DBGMD bit to force the I2C module to halt on a debug breakpoint. The I2C block will
complete the current byte transfer before halting. Clearing the DBGMD bit forces the module to continue operating
while the core halts in debug mode.
Rev. 1.0
409
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.8. DMA Configuration and Usage
The DMA interface to the I2C block has one channel mapped to transmit and one channel mapped to receive
operations. When DMA is enabled (DMAEN = 1), data must be transferred 4 bytes at a time. For a transfer length
which is not a multiple of 4, the extra bytes in the MSB of the final DMA transfer are ignored.
The I2C module can be programmed to transfer up to 255 bytes in a single DMA operation by setting the DMALEN
field in the I2CDMA register. For transmit operations, the DMA engine requests a word transfer to DATA whenever
the DATA register is empty and the DMALEN field is not 0. For receive operations, the DMA engine requests a
word transfer from DATA whenever the DATA register is full and the DMALEN field is not 0. The DMALEN field will
decrement by 1 when the hardware transmits or receives a byte. If the DMALEN value is less than 4, the DMA
transmits or receives the remaining bytes only. A transmit or receive interrupt occurs when DMALEN is zero.
If the hardware receives a NACK during a DMA operation, it will generate an acknowledge interrupt and stop the
remaining transaction. If the hardware detects a stop condition before DMALEN is zero, the transfer stops and a
stop interrupt occurs.
The I2C Module DMA configuration is shown in Figure 22.14.
SiM3xxxx
Address Space
DMA Module
I2Cn Transmit Data
I2Cn Module
TX/RX FIFO
DMA Channel
DATA
Shift Register
Slave Address
Mask
I2Cn Receive Data
DMA Channel
SDA
SCL
Slave Address
Clock Scaler
DMA Channel
Timer Control
32-bit Timer
Bus Control
32-bit Timer Reload
Figure 22.14. I2C Module DMA Configuration
22.8.1. Automatic Hardware DMA Options
To further automate the I2C transfer, firmware can enable Hardware Acknowledge (HACKEN = 1), Automatic
Transmit or Receive Enable (ATXRXEN = 1), or Last Byte Acknowledge Enable (LBACKEN = 1) in DMA mode. If
all of these modes are enabled, the hardware will automatically acknowledge any received bytes, automatically
switch to transmit or receive mode depending on the set direction of the R/W bit, and ACK or NACK the last byte of
the transfer, if it’s a receive operation.
410
Rev. 1.0
22.8.2. Master Write with DMA and Automatic Hardware Enabled
For a master write operation with all automatic modes enabled, the firmware should:
1. Set HACKEN and ATXRXEN to 1.
2. Write the address and R/W bit into DATA.
3. Program the DMALEN field to the appropriate value.
4. Set up the DMA transmit channel appropriately.
5. Enable the DMA mode in the I2C module (DMAEN = 1).
6. Issue a start by setting STA to 1.
If the master does not receive a NACK from the slave, the first interrupt received will be the transmit interrupt after
all bytes are transferred. The master can continue to send more bytes by setting up another transfer or issue a stop
to end the transfer. Once the stop interrupt occurs, the firmware must clear the STO bit to 0 and clear the stop
interrupt.
The DMA master write operation is shown in Figure 22.15.
1. Set HACKEN to 1.
2. Set ATXRXEN to 1.
3. Write DATA with the slave address
and R/W bit.
4. Set up the DMA transmit channel.
5. Set DMALEN.
6. Enable DMA mode (DMAEN = 1).
7. Set STA to 1.
SCL
SDA
START
Any bytes
remaining?
7-bit Address
R/W
Master Address Phase
ACK
8-bit Data
Master Data Phase
ACK
8-bit Data
Master Data Phase
ACK
No
Yes
Transmit Interrupt:
ISR 1st – (n-1)th pass
1. Set DMALEN.
2. Set up the DMA transmit channel.
3. Clear the transmit interrupt (TXI = 0).
Transmit Interrupt:
ISR nth pass
1. Set STO.
2. Clear the transmit interrupt (TXI = 0).
SCL
SDA
STOP
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Stop Interrupt:
ISR (n+1)th pass
Figure 22.15. Master Write with DMA and Automatic Hardware Flow Diagram (7-bit Address)
Rev. 1.0
411
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.8.3. Master Read with DMA and Automatic Hardware Enabled
For a master read operation with all automatic modes enabled, the firmware should:
1. Set HACKEN and ATXRXEN and to 1.
2. Write the address and R/W bit into DATA.
3. Program the DMALEN field to the appropriate value.
4. Set up the DMA receive channel appropriately.
5. Set LBACKEN to the appropriate value for the transfer.
6. Enable the DMA mode in the I2C module (DMAEN = 1).
7. Issue a start by setting STA to 1.
If the master does not receive a NACK from the slave, the first interrupt received will be the receive interrupt after
all bytes are transferred. The master can continue to receive more bytes by setting up another transfer or issue a
stop to end the transfer. Once the stop interrupt occurs, the firmware must clear the STO bit to 0 and clear the stop
interrupt.
This DMA master read operation is shown in Figure 22.16.
1. Set HACKEN to 1.
2. Set ATXRXEN to 1.
3. Write DATA with the slave address
and R/W bit.
4. Set up the DMA receive channel.
5. Set DMALEN.
6. Set LBACKEN to the appropriate
value.
7. Enable DMA mode (DMAEN = 1).
8. Set STA to 1.
SCL
SDA
START
Any bytes
remaining?
7-bit Address
R/W
Master Address Phase
ACK
8-bit Data (from Slave)
ACK
Master ACK
8-bit Data (from Slave)
ACK
Master ACK
No
Yes
1. Set DMALEN.
2. Set up the DMA receive channel.
3. Set LBACKEN to the appropriate
value.
4. Clear the receive interrupt (RXI = 0).
Receive Interrupt:
ISR 1st – (n-1)th pass
Receive Interrupt:
ISR nth pass
1. Set STO.
2. Clear the receive interrupt (RXI = 0).
SCL
SDA
STOP
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Stop Interrupt:
ISR (n+1)th pass
Figure 22.16. Master Read with DMA and Automatic Hardware Flow Diagram (7-bit Address)
412
Rev. 1.0
22.8.4. Slave Write with DMA and Automatic Hardware Enabled
The DMA slave write firmware procedure with automatic hardware enabled is as follows:
1. Program the slave address and mask in ADDRESS and MASK.
2. Set the DMALEN field.
3. Set up the DMA receive channel appropriately.
4. Enable the DMA mode in the I2C module (DMAEN = 1).
The first interrupt the slave will receive is a receive interrupt, since all the bytes are automatically acknowledged. If
more bytes should be received from the master, the firmware can set up another DMA transfer by resetting the
DMA channel, reprogramming DMALEN and clearing the receive interrupt.
When the slave receives the stop interrupt, the firmware should clear the STO bit and the stop interrupt to end the
transfer.
The DMA slave write operation is shown in Figure 22.17.
1. Set ADDRESS and MASK.
2. Set DMALEN.
3. Set up the DMA receive channel.
4. Enable DMA mode (DMAEN = 1).
SCL
SDA
7-bit Address
START
Any bytes
remaining?
No
R/W
ACK
Slave ACK
8-bit Data (from Master)
ACK
Slave ACK
8-bit Data (from Master)
ACK
Slave ACK
1. Clear the receive interrupt (RXI = 0).
2. Wait for a stop condition.
Receive Interrupt:
ISR 1st – (n-1)th pass
Yes
1. Set DMALEN.
2. Set up the DMA receive channel.
3. Clear the receive interrupt (RXI = 0).
SCL
SDA
STOP
Stop Interrupt:
ISR nth pass
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Figure 22.17. Slave Write with DMA and Automatic Hardware Flow Diagram (7-bit Address)
Rev. 1.0
413
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
22.8.5. Slave Read with DMA and Automatic Hardware Enabled
The DMA slave read firmware procedure with automatic hardware enabled is as follows:
1. Program the slave address and mask in ADDRESS and MASK.
2. Set the DMALEN field.
3. Set up the DMA transmit channel appropriately.
4. Enable the DMA mode in the I2C module (DMAEN = 1).
The first interrupt the slave will receive is a transmit interrupt after all bytes are sent to the master. If more bytes
should be sent to the master, the firmware can set up another DMA transfer by resetting the DMA channel,
reprogramming DMALEN, and clearing the transmit interrupt.
If no more data is to be sent, when the slave receives the stop interrupt, the firmware should clear the STO bit and
the stop interrupt to end the transfer.
The DMA slave read operation is shown in Figure 22.18.
1. Set ADDRESS and MASK.
2. Set DMALEN.
3. Set up the DMA transmit channel.
4. Enable DMA mode (DMAEN = 1).
SCL
SDA
7-bit Address
R/W
START
Any bytes
remaining?
No
ACK
Slave ACK
8-bit Data
Slave Data Phase
ACK
8-bit Data
Slave Data Phase
ACK
1. Clear the transmit interrupt (TXI = 0).
2. Wait for a stop condition.
Transmit Interrupt:
ISR 1st – (n-1)th pass
Yes
1. Set DMALEN.
2. Set up the DMA transmit channel.
3. Clear the transmit interrupt (TXI = 0).
SCL
SDA
STOP
Stop Interrupt:
ISR nth pass
1. Clear STO.
2. Clear the stop interrupt (STOI = 0).
Figure 22.18. Slave Read with DMA and Automatic Hardware Flow Diagram (7-bit Address)
414
Rev. 1.0
22.9. I2C0 and I2C1 Registers
This section contains the detailed register descriptions for I2C0 and I2C1 registers.
Register 22.1. I2Cn_CONTROL: Module Control
16
RW
RW
Reset
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BUSYF
RW
ACK
RW
ARBLF
R
ACKRQF
RW
STO
RW
STA
RW
TXMDF
RW
MSMDF
RW
STOI
RW
ACKI
RW
RXI
RW
TXI
RW
STAI
RW
ARBLI
RW
T0I
Type
T1I
Name
T2I
17
T3I
18
RXARM
19
TXARM
20
SLVAF
21
ATXRXEN
22
FMD
23
DBGMD
24
SMINH
25
HACKEN
26
Reserved
27
LBACKEN
28
Reserved
29
GCEN
30
RESET
31
I2CEN
Bit
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
RW
R
R
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_CONTROL = 0x4000_9000
I2C1_CONTROL = 0x4000_A000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 22.2. I2Cn_CONTROL Register Bit Descriptions
Bit
Name
31
I2CEN
Function
I2C Enable.
0: Disable the I2C module.
1: Enable the I2C module.
30
RESET
Module Soft Reset.
The following bits and fields are inaccessible while the module is in soft reset
(RESET = 1): all interrupt flags (TXI, RXI, STAI, STOI, ACKI, ARBLI, T0I, T1I, T2I,
T3I), STA, STO, TXARM, RXARM, ACK, ACKRQF, DMALEN, DATA, TIMER, and
SCLLTIMER.
0: I2C module is not in soft reset.
1: I2C module is in soft reset and firmware cannot access all bits in the module.
29
GCEN
General Call Address Enable.
0: Disable General Call address decoding.
1: Enable General Call address decoding.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
415
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Table 22.2. I2Cn_CONTROL Register Bit Descriptions
Bit
Name
Function
28
Reserved
Must write reset value.
27
LBACKEN
Last Byte Acknowledge Enable.
Automatic hardware acknowledge mode must be enabled (HACKEN = 1) for this bit
setting to have an effect.
0: NACK after the last byte is received.
1: ACK after the last byte is received.
26
Reserved
Must write reset value.
25
HACKEN
Auto Acknowledge Enable .
0: Disable automatic hardware acknowledge.
1: Enable automatic hardware acknowledge.
24
SMINH
Slave Mode Inhibit.
0: Enable Slave modes.
1: Inhibit Slave modes. The module will not respond to a Master on the bus.
23
DBGMD
I2C Debug Mode.
0: The I2C module will continue to operate while the core is halted in debug mode.
1: A debug breakpoint will cause the I2C module to halt.
22
FMD
Filter Mode.
0: Enable the input filter.
1: Disable the input filter.
21
ATXRXEN
Auto Transmit or Receive Enable.
0: Do not automatically switch to transmit or receive mode after a Start.
1: If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start.
20
SLVAF
Slave Address Type Flag.
0: Slave address detected.
1: General Call address detected.
19
TXARM
Transmit Arm.
0: Disable data and address transmission.
1: Enable the module to perform a transmit operation.
18
RXARM
Receive Arm.
0: Disable data and address reception.
1: Enable the module to perform a receive operation.
17
T3I
I2C Timer Byte 3 Interrupt Flag.
When the I2C module is enabled (I2CEN = 1), this interrupt flag will be set to 1 if an
SCL low timeout occurs. When using the I2C Timer as a stand-alone timer (when
I2C is disabled) this interrupt flag will set if an overflow occurs out of the the I2C
Timer Byte 3. Writing a 1 to this bit will manually trigger the interrupt. This flag must
be cleared by firmware.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
416
Rev. 1.0
Table 22.2. I2Cn_CONTROL Register Bit Descriptions
Bit
Name
16
T2I
Function
I2C Timer Byte 2 Interrupt Flag.
When using the I2C Timer as a stand-alone timer (when I2C is disabled) this interrupt flag will set if an overflow occurs out of the the I2C Timer Byte 2. Writing a 1 to
this bit will manually trigger the interrupt. This flag must be cleared by firmware.
15
T1I
I2C Timer Byte 1 Interrupt Flag.
When using the I2C Timer as a stand-alone timer (when I2C is disabled) this interrupt flag will set if an overflow occurs out of the I2C Timer Byte 1. Writing a 1 to this
bit will manually trigger the interrupt. This flag must be cleared by firmware.
14
T0I
I2C Timer Byte 0 Interrupt Flag.
When using the I2C Timer as a stand-alone timer (when I2C is disabled) this interrupt flag will set if an overflow occurs out of the I2C Timer Byte 0. Writing a 1 to this
bit will manually trigger the interrupt. This flag must be cleared by firmware.
13
ARBLI
Arbitration Lost Interrupt Flag.
This bit is set to 1 by hardware when an arbitration lost condition occurs. This bit
must be cleared by firmware.
12
STAI
Start Interrupt Flag.
This bit is set to 1 by hardware when a start or repeated start condition occurs. The
STO bit is also set with a repeated start to differentiate from a normal start condition.
This bit must be cleared by firmware.
11
TXI
Transmit Done Interrupt Flag.
This bit is set to 1 by hardware when a the module is transmitting data and BP is
equal to BC. This bit must be cleared by firmware.
10
RXI
Receive Done Interrupt Flag.
This bit is set to 1 by hardware when a the module is receiving data and BP is equal
to BC. This bit must be cleared by firmware.
9
ACKI
Acknowledge Interrupt Flag.
This bit is set to 1 by hardware when an acknowledge phase occurs and requires a
response. This bit must be cleared by firmware.
8
STOI
Stop Interrupt Flag.
This bit is set to 1 by hardware when a stop condition occurred or was generated.
This bit must be cleared by firmware.
7
MSMDF
Master/Slave Mode Flag.
0: Module is operating in Slave mode.
1: Module is operating in Master mode.
6
TXMDF
Transmit Mode Flag.
0: Module is in receiver mode.
1: Module is in transmitter mode.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
417
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Table 22.2. I2Cn_CONTROL Register Bit Descriptions
Bit
Name
5
STA
Function
Start.
This bit indicates whether hardware generated or detects a start on the bus. This bit
should be cleared to 0 by firmware after a start is detected. Setting this bit to 1 generates a start condition in master mode.
4
STO
Stop.
This bit indicates whether hardware generated or detects a stop on the bus. This bit
should be cleared to 0 by firmware after a stop is detected. Setting this bit to 1 generates a stop condition in master mode.
3
ACKRQF
Acknowledge Request Flag.
0: ACK has not been requested.
1: ACK requested.
2
ARBLF
Arbitration Lost Flag.
This read-only flag mirrors the state of the ARBLI interrupt flag.
0: Arbitration lost error has not occurred.
1: Arbitration lost error occurred.
1
ACK
Acknowledge.
Reading this bit returns the receive status of an ACK. Writing this bit to 1 sets the
hardware to transmit an ACK.
0
BUSYF
Busy Flag.
The BUSYF flag is set to 1 by hardware when a Start is generated or detected. This
flag is cleared to 0 when hardware generates or detects a Stop or senses a bus-free
timeout condition.
0: A transaction is not currently taking place.
1: A transaction is currently taking place.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
418
Rev. 1.0
TMD
T3RUN
T2RUN
T1RUN
R
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
13
12
11
10
9
8
7
6
5
4
3
TXIEN
RXIEN
ACKIEN
Name
Type
RW
Reset
0
0
0
Bit
15
14
Name
Type
RW
Reset
0
0
0
0
0
0
0
0
23
22
21
20
19
RW
RW
RW
RW
RW
RW
18
17
16
BP
BC
Reserved
RW
R
RW
R
RW
RW
0
0
0
2
1
0
0
0
STOIEN
28
T2IEN
24
STAIEN
29
T3IEN
25
ARBLIEN
30
T0RUN
26
Reserved
31
TIMEREN
27
T0IEN
Bit
T1IEN
Register 22.2. I2Cn_CONFIG: Module Configuration
Reserved
SCALER
RW
R
RW
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_CONFIG = 0x4000_9010
I2C1_CONFIG = 0x4000_A010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 22.3. I2Cn_CONFIG Register Bit Descriptions
Bit
Name
31
TIMEREN
Function
I2C Timer Enable.
This bit can only be set when using the I2C Timer Bytes 0-3 for general purpose
use. If I2CEN is set to 1, this bit should always be cleared to 0. If I2CEN is cleared
to 0, this bit can be set to 1 to start the timer running.
0: Disable I2C Timer.
1: Enable I2C Timer for general purpose use. This setting should not be used when
the I2C module is enabled (I2CEN = 1).
30
Reserved
29:28
TMD
Must write reset value.
I2C Timer Mode.
This setting only takes effect when using the I2C timer as a stand-alone clock
source and the I2C module is disabled (I2CEN = 0).
00: I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes
[3 : 2 : 1 : 0].
01: I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 :
2] and Timer Bytes [1 : 0].
10: I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers :
Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0.
11: I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers :
Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0.
Rev. 1.0
419
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Table 22.3. I2Cn_CONFIG Register Bit Descriptions
Bit
Name
27
T3RUN
Function
I2C Timer Byte 3 Run.
When the I2C Timer is configured for Mode 2, this bit enables the clock to the 8-bit
timer formed by Timer Byte 3. This bit has no effect if the I2C module is enabled
(I2CEN = 1).
0: Stop Timer Byte 3.
1: Start Timer Byte 3 running.
26
T2RUN
I2C Timer Byte 2 Run.
When the I2C Timer is configured for Mode 1 or 3, this bit enables the clock to the
16-bit timer formed by Timer Bytes [3 : 2]. In Mode 2, this bit enables the clock to the
8-bit timer formed by Timer Byte 2. This bit has no effect if the I2C module is
enabled (I2CEN = 1).
0: Stop Timer Byte 2.
1: Start Timer Byte 2 running.
25
T1RUN
I2C Timer Byte 1 Run.
When the I2C Timer is configured for Mode 2 or 3, this bit enables the clock to the 8bit timer formed by Timer Byte 1. This bit has no effect if the I2C module is enabled
(I2CEN = 1).
0: Stop Timer Byte 1.
1: Start Timer Byte 1 running.
24
T0RUN
I2C Timer Byte 0 Run.
When the I2C Timer is configured for Mode 1 or 3, this bit enables the clock to the
32-bit timer formed by Timer Bytes [3 : 2 : 1 : 0]. In Mode 1, this bit enables the clock
to the 16-bit timer formed by Timer Bytes [1 : 0]. In Mode 2 or 3, this bit enables the
clock to the 8-bit timer formed by Timer Byte 0. This bit has no effect if the I2C module is enabled (I2CEN = 1).
0: Stop Timer Byte 0.
1: Start Timer Byte 0 running.
23:22
BP
Transfer Byte Pointer.
This field indicates the byte of the current transfer being sent or received. This setting has no effect when using the I2C module with the DMA.
21:20
BC
Transfer Byte Count.
This field is the number of bytes to transmit or receive when using the I2C module in
software mode (DMAEN = 0). This field has no effect when DMA Mode is enabled.
19:18
Reserved
17
T3IEN
Must write reset value.
I2C Timer Byte 3 Interrupt Enable.
0: Disable the I2C Timer Byte 3 and SCL low timeout interrupt.
1: Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I).
16
T2IEN
I2C Timer Byte 2 Interrupt Enable.
0: Disable the I2C Timer Byte 2 interrupt.
1: Enable the I2C Timer Byte 2 interrupt (T2I).
420
Rev. 1.0
Table 22.3. I2Cn_CONFIG Register Bit Descriptions
Bit
Name
15
T1IEN
Function
I2C Timer Byte 1 Interrupt Enable.
0: Disable the I2C Timer Byte 1 interrupt.
1: Enable the I2C Timer Byte 1 interrupt (T1I).
14
T0IEN
I2C Timer Byte 0 Interrupt Enable.
0: Disable the I2C Timer Byte 0 interrupt.
1: Enable the I2C Timer Byte 0 interrupt (T0I).
13
ARBLIEN
Arbitration Lost Interrupt Enable.
0: Disable the arbitration lost interrupt.
1: Enable the arbitration lost interrupt (ARBLI).
12
STAIEN
Start Interrupt Enable.
0: Disable the start interrupt.
1: Enable the start interrupt (STAI).
11
TXIEN
Transmit Done Interrupt Enable.
0: Disable the transmit done interrupt.
1: Enable the transmit done interrupt (TXI).
10
RXIEN
Receive Done Interrupt Enable.
0: Disable the receive done interrupt.
1: Enable the receive done interrupt (RXI).
9
ACKIEN
Acknowledge Interrupt Enable.
0: Disable the acknowledge interrupt.
1: Enable the acknowledge interrupt (ACKI).
8
STOIEN
Stop Interrupt Enable.
0: Disable the stop interrupt.
1: Enable the stop interrupt (STOI).
7:6
Reserved
Must write reset value.
5:0
SCALER
I2C Clock Scaler.
The I2C module clock frequency is given by the equation:
F APB
F I2C = ---------------------------------------- 64 – SCALER 
Rev. 1.0
421
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Register 22.3. I2Cn_SADDRESS: Slave Address
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
Reset
R
0
0
0
RW
0
0
0
0
0
0
0
0
ADDRESS
Reserved
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
RW
R
0
0
0
0
0
Register ALL Access Addresses
I2C0_SADDRESS = 0x4000_9020
I2C1_SADDRESS = 0x4000_A020
Table 22.4. I2Cn_SADDRESS Register Bit Descriptions
Bit
Name
Function
31:8
Reserved
Must write reset value.
7:1
ADDRESS
Slave Address.
This field contains the 7-bit Slave Address. If slave modes are enabled, the slave
will respond with an ACK to any incoming address that matches ADDRESS after
being filtered by MASK.
0
422
Reserved
Must write reset value.
Rev. 1.0
Register 22.4. I2Cn_SMASK: Slave Address Mask
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
Reset
R
0
0
0
RW
0
0
0
0
0
0
0
0
MASK
Reserved
Reset
RW
R
0
0
0
0
0
Register ALL Access Addresses
I2C0_SMASK = 0x4000_9030
I2C1_SMASK = 0x4000_A030
Table 22.5. I2Cn_SMASK Register Bit Descriptions
Bit
Name
Function
31:8
Reserved
Must write reset value.
7:1
MASK
Slave Address Mask.
This field contains the 7-bit Slave Address Mask. If slave modes are enabled, the
slave will respond with an ACK to any incoming address that matches ADDRESS
after being filtered by MASK. Any bits set to 1 in MASK will result in the corresponding bit in the incoming address comparing to ADDRESS.
0
Reserved
Must write reset value.
Rev. 1.0
423
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Register 22.5. I2Cn_DATA: Data Buffer Access
Bit
31
30
29
28
27
26
25
24
23
Name
DATA[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
DATA[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_DATA = 0x4000_9040
I2C1_DATA = 0x4000_A040
Table 22.6. I2Cn_DATA Register Bit Descriptions
Bit
Name
31:0
DATA
Function
Data.
This field contains the four byte I2C transmit and receive buffer. For each transaction, the least significant byte will be sent or received first.
424
Rev. 1.0
Register 22.6. I2Cn_TIMER: Timer Data
Bit
31
30
29
28
27
26
25
24
23
22
21
20
Name
T3
T2
Type
RW
RW
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
T1
T0
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_TIMER = 0x4000_9050
I2C1_TIMER = 0x4000_A050
Table 22.7. I2Cn_TIMER Register Bit Descriptions
Bit
Name
31:24
T3
Function
Timer Byte 3.
If the I2C module is enabled (I2CEN = 1), Timer Byte 3 becomes bits [19:12] of the
SCL low timeout counter. If the I2C module is disabled (I2CEN = 0), Timer Byte 3 is
available for general purpose use and can be set to different modes using the TMD
bits.
23:16
T2
Timer Byte 2.
If the I2C module is enabled (I2CEN = 1), Timer Byte 2 becomes bits [11:4] of the
SCL low timeout counter. If the I2C module is disabled (I2CEN = 0), Timer Byte 2 is
available for general purpose use and can be set to different modes using the TMD
bits.
15:8
T1
Timer Byte 1.
If the I2C module is enabled (I2CEN = 1), Timer Byte 1 is used as the SCL clock
high or low period timer. If the I2C module is disabled (I2CEN = 0), Timer Byte 1 is
available for general purpose use and can be set to different modes using the TMD
bits.
7:0
T0
Timer Byte 0.
If the I2C module is enabled (I2CEN = 1), Timer Byte 0 is used as the SDA data
setup or hold time period and the SCL free timeout period. If the I2C module is disabled (I2CEN = 0), Timer Byte 0 is available for general purpose use and can be set
to different modes using the TMD bits. When used for I2C operations, T0 will automatically be reloaded by hardware from either the T0RL, HOLD, or SETUP fields as
necessary.
Rev. 1.0
425
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Register 22.7. I2Cn_TIMERRL: Timer Reload Values
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
Name
T3RL
T2RL
Type
RW
RW
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Name
T1RL
T0RL
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_TIMERRL = 0x4000_9060
I2C1_TIMERRL = 0x4000_A060
Table 22.8. I2Cn_TIMERRL Register Bit Descriptions
Bit
Name
31:24
T3RL
Function
Timer Byte 3 Reload / SCL Low Timeout Bits [19:12].
These bits contain the reload value for I2C Timer Byte 3. Upon a reload event, this
value will be latched into the I2C Timer Byte 3 location. When I2C is enabled, these
bits are part of the equation for SCL timeout:
2 20 –  16  [T3RL : T2RL] 
T SCL_TO = ---------------------------------------------------------------------F I2C
23:16
T2RL
Timer Byte 2 Reload / SCL Low Timeout Bits [11:4].
These bits contain the reload value for I2C Timer Byte 2. Upon a reload event, this
value will be latched into the I2C Timer Byte 2 location. When I2C is enabled, these
bits are part of the equation for SCL timeout:
2 20 –  16  [T3RL : T2RL] 
T SCL_TO = ---------------------------------------------------------------------F I2C
426
Rev. 1.0
Table 22.8. I2Cn_TIMERRL Register Bit Descriptions
Bit
Name
15:8
T1RL
Function
Timer Byte 1 Reload / SCL High Time.
These bits contain the reload value for I2C Timer Byte 1. Upon a reload event, this
value will be latched into the I2C Timer Byte 1 location. When I2C is enabled, these
bits dictate the SCL high time, according to the following equation:
256 – T1RL
T SCL_HIGH = -----------------------------F I2C
7:0
T0RL
Timer Byte 0 Reload / Bus Free Timeout.
These bits contain the reload value for I2C Timer Byte 0. Upon a reload event, this
value will be latched into the I2C Timer Byte 0 location. When I2C is enabled, these
bits dictate the bus free timeout, according to the following equation:
256 – T0RL
T BUS_FREE = -----------------------------F I2C
Rev. 1.0
427
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Register 22.8. I2Cn_SCONFIG: SCL Signal Configuration
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
SCLLTIMER
Type
R
R
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SCLL
HOLD
SETUP
Type
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_SCONFIG = 0x4000_9070
I2C1_SCONFIG = 0x4000_A070
Table 22.9. I2Cn_SCONFIG Register Bit Descriptions
Bit
Name
31:20
Reserved
19:16
SCLLTIMER
Function
Must write reset value.
SCL Low Timeout Bits [3:0].
When the I2C module is enabled (I2CEN = 1), this read-only field (bits [3:0]) combines with I2C Timer Byte 3 (bits [19:12]) and I2C Timer Byte 2 (bits [11:4]) to create
a 20-bit SCL low timeout counter.
15:8
SCLL
SCL Low Time.
This field provides the I2C Timer Byte 1 reload value used to generate the SCL low
time. This is given by the equation:
256 – SCLL
T SCL_LOW = ------------------------------F I2C
7:4
HOLD
Data Hold Time Extension.
This field provides an alternate I2C Timer Byte 0 reload value to extend the data
hold time. The additional hold time is given by the following equation:
16 – HOLD
T HOLD = ----------------------------F I2C
Note : When HOLD = 0, no additional hold time is added.
428
Rev. 1.0
Table 22.9. I2Cn_SCONFIG Register Bit Descriptions
Bit
Name
3:0
SETUP
Function
Data Setup Time Extension.
This field provides an alternate I2C Timer Byte 0 reload value to extend data setup
time. This is given by the equation:
17 – SETUP
T SETUP = -------------------------------F I2C
Note : When SETUP = 0, the setup time is reduced to a single APB clock.
Rev. 1.0
429
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Register 22.9. I2Cn_I2CDMA: DMA Configuration
Bit
31
Name
DMAEN
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
Type
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Name
Reserved
DMALEN
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
I2C0_I2CDMA = 0x4000_9080
Table 22.10. I2Cn_I2CDMA Register Bit Descriptions
Bit
Name
31
DMAEN
Function
DMA Mode Enable.
0: Disable I2C DMA data requests.
1: Enable I2C DMA data requests.
30:8
Reserved
Must write reset value.
7:0
DMALEN
DMA Transfer Length.
If DMAEN is set to 1, this field indicates the number of bytes to transfer with the I2C
module. When DMA operations are enabled, DMALEN = 0, and TXARM or RXARM
is set to 1, the module will transfer or receive data indefinitely until firmware clears
TXARM or RXARM.
430
Rev. 1.0
22.10. I2Cn Register Memory Map
I2Cn_DATA I2Cn_SMASK I2Cn_SADDRESS I2Cn_CONFIG I2Cn_CONTROL Register Name
0x20
0x40
0x30
ALL Offset
0x10
0x0
ALL
ALL
ALL
ALL | SET | CLR ALL | SET | CLR Access Methods
Bit 31
TIMEREN
I2CEN
Reserved
Bit 30
RESET
Bit 29
GCEN
TMD
Reserved
Bit 28
LBACKEN
T3RUN
Bit 27
Reserved
T2RUN
Bit 26
HACKEN
T1RUN
Bit 25
SMINH
T0RUN
Bit 24
DBGMD
Bit 23
BP
FMD
Bit 22
ATXRXEN
Bit 21
BC
SLVAF
Bit 20
Reserved
Reserved
TXARM
Bit 19
Reserved
RXARM
Bit 18
T3IEN
T3I
Bit 17
T2IEN
T2I
Bit 16
DATA
T1IEN
T1I
Bit 15
T0IEN
T0I
Bit 14
ARBLIEN
ARBLI
Bit 13
STAIEN
STAI
Bit 12
TXIEN
TXI
Bit 11
RXIEN
RXI
Bit 10
ACKIEN
ACKI
Bit 9
STOIEN
STOI
Bit 8
MSMDF
Bit 7
Reserved
TXMDF
Bit 6
STA
Bit 5
MASK
ADDRESS
STO
Bit 4
ACKRQF
Bit 3
SCALER
ARBLF
Bit 2
ACK
Bit 1
Reserved
Reserved
BUSYF
Bit 0
Table 22.11. I2Cn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: I2C0 = 0x4000_9000, I2C1 = 0x4000_A000
Rev. 1.0
431
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Table 22.11. I2Cn Memory Map
I2Cn_I2CDMA I2Cn_SCONFIG I2Cn_TIMERRL I2Cn_TIMER Register Name
0x80
0x50
ALL Offset
0x60
0x70
ALL
ALL
Access Methods
ALL
ALL
DMAEN
Bit 31
Bit 30
Bit 29
Bit 28
T3
T3RL
Bit 27
Bit 26
Reserved
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
T2
T2RL
Reserved
Bit 19
Bit 18
SCLLTIMER
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
SCLL
T1
T1RL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
HOLD
Bit 5
Bit 4
DMALEN
T0
T0RL
Bit 3
Bit 2
SETUP
Bit 1
Bit 0
Inter-Integrated Circuit Bus (I2C0 and I2C1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: I2C0 = 0x4000_9000, I2C1 = 0x4000_A000
432
Rev. 1.0
23. Integrated Interchip Sound (I2S0)
This section describes the I2S module, and is applicable to all products in the following device families, unless
otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the I2S block, which is used by all device families covered in this document.
23.1. I2S Features
The I2S module includes the following features:
Master
or slave capability.
to 12.288 MHz clock to support 48 kHz sampling with 2 32-bit channels.
Support for DMA data transfers.
Support for various data formats.
Supports Time Division Multiplexing (TDM).
The I2S module receives digital data from an external source over a data line in the standard I2S, left-justified,
right-justified, or time domain multiplexing format, de-serializes the data, and generates requests to transfer the
data using the DMA. The module also reads stereo audio samples from the DMA, serializes the data, and sends it
out of the chip on a data line in the same standard serial format for digital audio. The I2S receive interface consists
of 3 signals: SCK (bit clock), WS (word select or frame sync), and SD (data input). The block’s transmit interface
consists of 3 signals: SCK (bit clock), WS (word select or frame sync) and SD (data output).
Up
I2Sn Module
Transmit FIFO
TXFIFO
Transmit Control
FIFO Status and
Control
DFS Generator
TX_SD
TX_WS
TX_SCK
APB Clock
Clock Divisor
RX_SCK
RX_WS
Receive FIFO
RXFIFO
Receive Control
RX_SD
Figure 23.1. I2S Block Diagram
Rev. 1.0
433
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
23.2. Signal Descriptions and Protocol Overview
The I2S protocol uses three signals: clock (SCK), word select or frame sync (WS), and data (SD). Figure 23.2
shows a typical I2S transaction.
23.2.1. Clock (SCK)
Each transition of the clock corresponds to a bit of data on the data line. The clock frequency is a multiple of the
sampling frequency of the data. For example, the clock rate is 2.8224 MHz for a sampling rate of 44.1 kHz, 32-bits
of data per sample, and 2 channels (left and right).
23.2.2. Word Select or Frame Sync (WS)
The word select or frame synchronization signal determines the start of the frame and which channel is active on
the bus. The left audio data is sent on the low WS cycle, and the right audio data is sent on the high WS cycle. The
WS signal is the same frequency as the sampling rate for non time-division multiplexing systems.
23.2.3. Data (SD)
The data signal is multiplexed between multiple channels and is sent MSB first. The data transfer starts on the
second clock cycle after the frame sync transitions. Bits can be sent in varying frame sizes (between 8 and 32),
and any unused bits are ignored.
SCK
WS
SD
Dn
Dn-1
Bit n
Bit n-1
...
D2
D1
D0
Bit 2
Bit 1
Bit 0
unused
Dn
Dn-1
Bit n
Bit n-1
Channel 0
...
D2
D1
D0
Bit 2
Bit 1
Bit 0
Channel 1
2
Figure 23.2. I S Protocol Transaction
23.3. Clocking
23.3.1. Internal Clock Generator
The I2S module generates a divided version of the APB clock for internal use or to drive on the transmitter or
receiver SCK signals. The divider includes a 10-bit integer portion (INTDIV) and an 8-bit fractional portion
(FRACDIV). The integer portion creates a 50% duty cycle clock as a direct division of the APB clock. The fractional
portion can be used to further divide the input clock and create a non-50% duty cycle average clock frequency.
When using the fractional divider, the duty cycle of the clock will have some jitter as some cycles will be stretched
by half an APB clock period. Equation 23.1 describes the average I2S clock generator output frequency.
F APB
F I2S = -------------------------------------------------------FRACDIV
INTDIV + ---------------------------256
Equation 23.1. Average Clock Generator Output Frequency
The duty cycle of the clock can be inverted using the DUTYMD bit.
Firmware should set the value of the INTDIV and FRACDIV fields before setting DIVEN to enable the clock divider.
Firmware must then write to the CLKUPD bit to update these fields in the clock divider before the changes will take
effect. The CDBUSYF flag indicates when the clock divider update completes. Firmware can check the status of
the clock divider by checking the CDSTS bit.
434
Rev. 1.0
23.3.2. Transmitter and Receiver Clocking
The TXCLKSEL and RXCLKSEL bits control whether the transmitter or receiver are clocked from their SCK pins or
use the internal clock generator. If changes are made to the TXCLKSEL bit, firmware should poll the transmit clock
select ready (TXCLKSELRF) flag to determine when the update completes. Similarly, firmware should poll the
receive clock select ready (RXCLKSELRF) flag after changing the RXCLKSEL setting. The SCK frequency will be
the same for the transmitter and receiver if both use the internal clock generator. If either the transmitter or receiver
uses an incoming SCK signal as its clock, they can operate independently at different frequencies.
The TXCLKEN and RXCLKEN bits enable the clocks to the transmitter and receiver. Firmware should poll the
TXCLKENRF or RXCLKENRF flags after changing the corresponding enable bit.
23.4. Clock (SCK) Signal Formatting
The TXSCLKMD and RXSCLKMD bits in the CLKCONTROL register select whether the SCK signals are an input
or an output. The transmitter or receiver can invert the SCK signal using the SCLKINVEN bits in the TXCONTROL
and RXCONTROL registers regardless of whether the clock originates from the SCK input or the internal clock
generator.
To set up the transmitter or receiver to run from an input clock:
1. Set TXSCLKMD or RXSCLKMD to 1 to set SCK as an input.
2. Set SCLKINVEN to the desired value.
3. Set the SCK pin as a digital input in the device port configuration module.
4. Enable the transmitter (TXEN = 1) or receiver (RXEN = 1).
To set up the transmitter or receiver to output a clock:
1. Clear TXSCLKMD or RXSCLKMD to 0 to set SCK as an output.
2. Set SCLKINVEN to the desired value.
3. Set the SCK pin as a digital push-pull output in the device port configuration module.
4. Enable the transmitter (TXEN = 1) or receiver (RXEN = 1).
23.5. Word Select or Frame Sync (WS) Signal Formatting
The FSGEN bit in TXCONTROL enables the internal DFS generator shared between the transmitter and receiver.
The DFS generator can be output on the transmitter or receiver WS signals or used to synchronize with an
incoming transmitter WS signal using the FSSEN bit. The FSSRCSEL bits select the source of the frame
synchronization signal. The FSLOW and FSHIGH fields in the FSDUTY register determine the WS low and high
time.
To synchronize the internal DFS generator with an incoming WS signal on the transmitter WS pin, firmware should
set FSSEN to 1 before starting the DFS generator (FSGEN = 1). When the generator starts, the hardware waits
until a rising edge occurs on the incoming WS signal and will automatically align the internally-generated WS
waveform to the incoming signal. The FSLOW and FSHIGH fields must be properly configured so that the
generated WS waveform matches the waveform of the incoming WS signal.
The WS signal can be inverted using the FSINVEN bits in TXCONTROL and RXCONTROL regardless of whether
the signal is generated internally or input from another device.
Rev. 1.0
435
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
23.6. Basic Data (SD) Signal Formatting
When the JSEL, DDIS, and FSDEL bits in TXCONTROL and RXCONTROL and TDMEN in TXMODE and
RXMODE are in their default states, the transmitter and receiver are configured to send or receive data in standard
I2S format. The most significant bit of the left channel’s sample is sent or captured on the second rising edge of
SCK after the falling edge of WS.
23.6.1. Sample Width
The mono bit-width select (MBSEL) fields select the sample width as 8, 9, 16, 24, or 32 bits, and the transmitter
and receiver can use different selections. Any unused bit cycles during a frame will be driven to the value that is
specified by the FILLSEL field. The transmitter and receiver will always stop sending or capturing the current
sample when WS transitions, even if the WS change occurs before all bits of the specified sample size have
transferred in the frame.
23.6.2. Right-Justified Format
The JSEL bits select the data justification for the transmitter and receiver. If JSEL is cleared to 0, the data will be
sent or received one clock after the WS transition. If JSEL is set to 1, the sample is sent or received after some
delay, causing it to be aligned to the right-hand side of the defined slot. The hardware will subtract the sample width
(MBSEL) from the slot width (CYCLE) to determine the number of clock cycles to wait after a WS change before
sending the first bit of the sample. If the DDIS bit is cleared to 0, then the slot size (CYCLE) must be set as two less
than the number of clock cycles per phase of WS to account for the extra cycle of delay which occurs after WS
changes. If DDIS is set to 1, then the slot size (CYCLE) must be set as one less than the actual number of clock
cycles per phase of WS.
23.6.3. Sample Order
If the ORDER bits are set to 0, the transmitter or receiver expect the left sample first, followed by the right sample.
Setting ORDER to 1 swaps the order to the right sample first, followed by the left sample.
23.7. Left-Justified and Longer-Delay Formats
In normal I2S communications, the first bit of a sample is sent by the transmitter or captured by the receiver on the
second rising or falling edge of SCK after a change on WS. By setting the FSDEL fields to a non-zero value, the
first bit can be delayed to the cycle specified by FSDEL.
In addition, firmware can set the DDIS bits to have the transmit or receive occur on the first rising or falling edge of
SCK after WS changes state. The hardware ignores the FSDEL field when the corresponding DDIS bit is set.
When the transmitter receives WS as an input and is configured to use a left-justified format (DDIS = 1), the
transmitter must instantly drive the sample during the same cycle when WS changes state. To do this, the
transmitter should be configured to use the internal DFS generator (FSGEN and transmitter FSSRCSEL set to 1).
The transmitter hardware is then able to predict when to drive the output sample without relying on the incoming
WS signal. The data will be properly aligned if firmware synchronizes the internal DFS generator to the incoming
transmitter WS signal by setting FSSEN to 1 before starting the DFS generator. When the generator starts (FSGEN
= 1), the hardware waits until a rising edge occurs on the incoming WS signal and will automatically align the
generated WS waveform to the incoming signal. Firmware must properly configure the FSLOW and FSHIGH fields
so that the generated WS waveform matches the waveform of the incoming WS.
436
Rev. 1.0
23.8. Time-Division Multiplexing (TDM)
With time-division multiplexing, each WS cycle is split into multiple slots. Different devices on the bus can claim
different slots to send or receive samples.
The first slot (slot 0) begins after an optional preamble delay, during which the transmitter will not drive anything
onto the data line. The preamble delay is one cycle by default to readily support I 2S format and can be changed up
to 256 cycles using the FSDEL fields. The preamble can be decreased to zero cycles by setting DDIS to 1, which
may require synchronizing the internal DFS generator with an incoming WS signal as described in “23.5. Word
Select or Frame Sync (WS) Signal Formatting” .
Firmware must define the slot width using the CYCLE fields, and the maximum supported slot width is 4096 bits.
The START field in the TXMODE register contains the number of the first slot in which the transmitter will drive a
sample on SD. Similarly, the START field in the RXMODE register contains the number of the first slot the receiver
will capture a sample from the data line. The module can begin driving or capturing samples in any slot from 0 to
255. The SLOTS fields specify the number of consecutive slots in which the module will drive or capture samples.
When this field is 0, the module will drive or capture a sample in 1 slot. During the slots when the transmitter is not
actively sending a sample, it will either drive 0 (DIMD = 0) or tristate (DIMD = 1) the SD signal.
Since different sources will be driving the shared SD signal, a slot will always end with one device disabling its
drivers and another device enabling its drivers at nearly the same time. This can lead to brief conflicts if the drivers
overlap for a short time. To prevent this, firmware can define a large enough slot width to accommodate at least 1
cycle of idle time between active slots when no devices are driving the bus. By setting DEDIS to 1, the transmitter
will stop driving valid data one cycle before it’s scheduled to release the SD signal. During this cycle, the
transmitter will tristate the SD signal if DIMD is set to 1. When using this feature, the mono bit-width (MBSEL) must
be defined to be at least 1 bit smaller than the slot width (CYCLE) to accommodate the idle bus cycle.
WS
SD
optional
preamble
unused
Slot 0
Slot 1
Slot 2
Slot 3
...
Slot n
optional
preamble
Slot 0
drive left
channel
sample
Slot 1
Slot 2
Slot 3
...
Slot n
drive right
channel
sample
Figure 23.3. Time Division Multiplexing Example (START = 2, SLOTS = 0)
Rev. 1.0
437
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
23.9. Transmitter and Receiver
The I2S module transmitter and receiver operate independently. Firmware can enable the I2S module transmitter
by setting TXEN to 1. The transmitter has an 8x32-bit word FIFO that can be filled by writing left-justified data
words to the TXFIFO register. Multiple samples can be packed into a single word, depending on the enabled data
formatting options. Figure 23.4 shows several transmit FIFO formatting examples.
Transmit or Receive FIFO
Transmit or Receive FIFO
L, 24-bit
L, 16-bit
R, 16-bit
R, 24-bit
L, 16-bit
R, 16-bit
L, 24-bit
L, 16-bit
R, 16-bit
R, 24-bit
L, 16-bit
R, 16-bit
L, 24-bit
L, 16-bit
R, 16-bit
R, 24-bit
L, 16-bit
R, 16-bit
L, 24-bit
L, 16-bit
R, 16-bit
R, 24-bit
L, 16-bit
R, 16-bit
Transmit or Receive FIFO
Transmit or Receive FIFO
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
L, 9-bit
R, 9-bit
L, 8-bit
R, 8-bit
L, 8-bit
R, 8-bit
Figure 23.4. FIFO Formatting Examples
The TXFIFONUM field contains the number of words in the transmitter FIFO. The transmit FIFO watermark
(TXFIFOWM) allows firmware to receive a notification when more data can be placed in the FIFO. Hardware sets
the transmit FIFO low watermark (TXLWMI) flag and can generate an interrupt when the number of entries in the
FIFO is less than or equal to the level set by the watermark (TXFIFONUM = TXFIFOWM).
Similar to the transmitter, the receiver is enabled by setting the RXEN bit. The receiver FIFO can also contain up to
8 words, and firmware can read the FIFO by reading data words from the RXFIFO register. The hardware will pack
the input data in left-justified bytes, half-words, or words depending on the selected data formatting options.
The RXFIFONUM field describes the number of words in the receiver FIFO. Hardware sets the receive FIFO high
watermark (RXHWMI) flag when the number of words is greater than or equal to the receive FIFO watermark field
(RXFIFONUM = RXFIFOWM). An interrupt can also be generated when this watermark flag is set.
In the event of an error, the FIFOs can be emptied using the transmit FIFO flush (TXFIFOFL) and receive FIFO
flush (RXFIFOFL) bits.
438
Rev. 1.0
23.10. Interrupts and Flags
The transmit FIFO low watermark (TXLWMI) flag is set by hardware when the number of words in the transmit
FIFO is less than or equal to the TXFIFOWM field. This flag can also generate an interrupt, if enabled (TXLWMIEN
= 1).
Hardware sets the receive FIFO high watermark (RXHWMI) flag when the number of words in the receive FIFO is
greater than or equal to the RXFIFOWM field. Firmware can enable this interrupt by setting RXHWMIEN to 1.
The I2S module also includes two error interrupts. Hardware sets the transmit underrun error (TXUFI) flag when
the transmitter attempts to send a sample when the transmit FIFO is empty. The receive overflow error (RXOFI)
occurs when the receiver attempts to store more data in the receive FIFO when the FIFO is full. These interrupts
can be enabled by firmware by setting TXUFIEN or RXOFIEN to 1, respectively.
23.11. Debug Mode
Firmware can set the TXDBGHEN or RXDBGHEN bits to force the I2S transmitter or receiver to halt on a debug
breakpoint. Clearing these bits forces the module to continue operating while the core halts in debug mode.
If TXDBGMD is cleared to 0, the clock to the I2S transmitter is active in debug mode. If TXDBGMD is set to 1, the
clock divider keeps running, and the clock to the transmitter will be disabled after two samples are queued and
ready to be sent.
If RXDBGMD is cleared to 0, the clock to the I2S receiver is active in debug mode. When RXDBGMD is set to 1,
the clock divider keeps running indefinitely, and the hardware disables the receiver clock after the receiver captures
two samples.
23.12. Module Reset
To reset the I2S module:
1. Disable the clock divider (DIVEN = 0).
2. Set the CLKUPD bit to update the divider.
3. Poll on CDBUSYF to verify the divider is disabled.
4. Clear the clock divider duty mode (DUTYMD) bit to 0.
5. Set the RESET bit.
6. Poll on RESET to wait for the reset operation to complete.
7. Re-initialize the module.
Following this procedure ensures the transmitter and receiver will not output any glitches on the SCK output
signals.
Rev. 1.0
439
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
23.13. DMA Usage and Configuration
The I2S transmitter and receiver have separate DMA data requests and can be assigned to two different DMA
channels. The I2S module supports burst transfers only, but these burst transfers may be of variable size by setting
the transmitter or receiver burst mode.
When DMA is enabled to the transmitter (TXDMAEN = 1), the I2S transmitter will automatically request data from
the assigned DMA channel whenever space is available in the transmit FIFO. If burst mode is cleared to 0,
(TXDMABMD = 0), the hardware will request data when at least one word is empty in the transmit FIFO. If
TXDMABMD is set to 1, the transmitter will request data when at least four words are empty.
When DMA is enabled for the receiver (RXDMAEN = 1), the receiver will automatically request data transfers from
the DMA channel when data is present in the receive FIFO. When burst mode is cleared to 0 (RXDMABMD = 0),
the receiver will request a data transfer when at least one word is present in the FIFO. If burst mode is set to 1
(RXDMABMD = 1), the hardware will request a data transfer when data occupies at least four words of the FIFO.
Figure 23.5 shows the I2S DMA configuration.
SiM3xxxx
Address Space
I2Sn Module
Transmit FIFO
DMA Module
I2S Transmit Data
TXFIFO
DMA Channel
I2S Receive Data
FIFO Status and
Control
DFS Generator
DMA Channel
Clock Divisor
DMA Channel
Receive FIFO
RXFIFO
Figure 23.5. I2S DMA Configuration
440
Rev. 1.0
23.14. I2S0 Registers
This section contains the detailed register descriptions for I2S0 registers.
Reserved
Reserved
Type
R
RW
R
22
21
20
19
MBSEL
Reserved
FILLSEL[1]
Name
23
JSEL
27
FSINVEN
28
SCLKINVEN
29
ORDER
31
Reserved
Bit
26
25
24
18
17
16
RW
R
RW
RW
RW
R
RW
RW
0
0
0
1
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
RW
Reset
0
0
FSDEL
RW
RW
0
0
0
0
0
0
0
Reserved
FSGEN
0
FSSEN
0
DDIS
0
FSSRCSEL
Reset
FILLSEL[0]
30
TXEN
Register 23.1. I2S0_TXCONTROL: Transmit Control
RW
R
RW
RW
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_TXCONTROL = 0x4003_A000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.1. I2S0_TXCONTROL Register Bit Descriptions
Bit
Name
31:30
Reserved
29
TXEN
Function
Must write reset value.
Transmitter Enable.
0: Disable the I2S transmitter.
1: Enable the I2S transmitter.
28:27
Reserved
26:24
MBSEL
Must write reset value.
Transmit Mono Bit-Width Select.
This field specifies the number of bits per mono sample.
000: 8 bits are sent per mono sample.
001: 9 bits are sent per mono sample.
010: 16 bits are sent per mono sample.
011: 24 bits are sent per mono sample.
100: 32 bits are sent per mono sample.
101-111: Reserved.
23
Reserved
Must write reset value.
Rev. 1.0
441
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Table 23.1. I2S0_TXCONTROL Register Bit Descriptions
Bit
Name
22
ORDER
Function
Transmit Order.
This bit chooses which audio channel is sent as the first mono sample and second
mono sample in various formats.
0: Left sample transmitted first, right sample transmitted second. Use this setting for
I2S format.
1: Right sample transmitted first, left sample transmitted second.
21
SCLKINVEN
Transmit SCK Inversion Enable.
0: Do not invert the transmitter bit clock.
1: Invert the transmitter bit clock.
20
FSINVEN
Transmit WS Inversion Enable.
0: Don't invert the WS signal. Use this setting for I2S format.
1: Invert the WS signal.
19:18
Reserved
17
JSEL
Must write reset value.
Transmit Data Justification Select.
0: Use left-justified or I2S-style formats.
1: Use right-justified format.
16:15
FILLSEL
Transmit Data Fill Select.
Ths field specifies the type of data to send during unused bit cycles.
00: Send zeros during unused bit cycles.
01: Send ones during unused bit cycles.
10: Send the sign bit of the current sample (MSB-first format) or last sample (LSBfirst format) during unused bit cycles.
11: Send pseudo-random data generated by an 8-bit LFSR during unused bit
cycles.
14
FSSRCSEL
Transmit Frame Sync Source Select.
Select the source for the word select or frame sync (WS) input to the block.
0: The word select or frame sync is input from the WS pin.
1: The word select or frame sync is input from the internal DFS generator.
13:6
FSDEL
Transmit Initial Phase Delay.
This field specifies the number of cycles of initial phase delay from the frame sync
edge to the first bit of the sample (non-TDM formats) or to start the first slot (TDM
formats).
5
DDIS
Transmit Delay Disable.
Setting this bit to 1 disables the data delay after the frame sync.
0: The first data bit is sent on the second or later rising edge of SCK after WS
changes.
1: The first data bit is sent on the first rising edge of SCK after WS changes.
4:2
Reserved
1
FSSEN
Must write reset value.
DFS Synchronize Enable.
0: The internal DFS generator starts immediately when FSGEN is set to 1.
1: Synchronize the rising edge of the internally generated WS signal from the DFS
generator to the rising edge of the external WS input signal.
442
Rev. 1.0
Table 23.1. I2S0_TXCONTROL Register Bit Descriptions
Bit
Name
0
FSGEN
Function
DFS Generator Enable.
0: Disable the internal DFS generator.
1: Enable the internal DFS generator.
Rev. 1.0
443
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.2. I2S0_TXMODE: Transmit Mode
30
29
28
27
26
25
Name
Reserved
Type
R
RW
RW
24
23
22
21
20
19
18
17
DEDIS
31
DIMD
Bit
TDMEN
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
SLOTS
START[7:4]
RW
RW
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Name
START[3:0]
CYCLE
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_TXMODE = 0x4003_A010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.2. I2S0_TXMODE Register Bit Descriptions
Bit
Name
31:28
Reserved
27
TDMEN
Function
Must write reset value.
Transmit Time Division Multiplexing Enable.
0: Disable the time division multiplexing (TDM) feature.
1: Enable the time division multiplexing (TDM) feature.
26
DIMD
Transmit Drive Inactive Mode.
Defines the state to drive on the data output pins during non-active slots.
0: Drive zero on the data output pin during non-active slots.
1: Don't drive the data output pin. The data output pin is tristated.
25
DEDIS
Transmit Drive Early Disable.
0: Drive the output during every cycle of the transmitter's assigned slot(s), including
the last clock cycle.
1: Drive the output for every cycle of the transmitter's assigned slot(s), except for
the last clock cycle of the last slot.
24:20
SLOTS
Transmit Drive Select.
The number of consecutive TDM slots on which to drive data is SLOTS + 1.
19:12
START
Transmit Start Control.
This field is the first TDM slot number in which digital output will start driving data.
11:0
CYCLE
Transmit Clock Cycle Select.
If JSEL is set to 1 for the transmitter, this field should be set with the number of slots
in the frame. If DDIS is cleared to 0, the number of slots is CYCLE - 1. If DDIS is
also set to 1, the number of slots per right-justified field is CYCLE - 2.
444
Rev. 1.0
Register 23.3. I2S0_FSDUTY: Frame Sync Duty Cycle
Bit
31
30
29
28
27
26
25
24
23
Name
FSHIGH
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
FSLOW
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_FSDUTY = 0x4003_A020
Table 23.3. I2S0_FSDUTY Register Bit Descriptions
Bit
Name
31:16
FSHIGH
Function
Frame Sync High Time.
The number of bit clock cycles for the high phase of the frame sync generator is
equal to FSHIGH + 1.
15:0
FSLOW
Frame Sync Low Time.
The number of bit clock cycles for the low phase of the frame sync generator is
equal to FSLOW + 1.
Rev. 1.0
445
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
30
29
28
27
26
25
24
23
22
21
20
19
18
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
JSEL
RW
DDIS
RW
Reserved
R
FSINVEN
Type
SCLKINVEN
Reserved
16
ORDER
Reserved
17
Reserved
Name
FSSRCSEL
31
RXEN
Bit
MBSEL[2:1]
Register 23.4. I2S0_RXCONTROL: Receive Control
MBSEL[0]
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
FSDEL
Type
RW
R
RW
RW
RW
R
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_RXCONTROL = 0x4003_A030
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.4. I2S0_RXCONTROL Register Bit Descriptions
Bit
Name
31:22
Reserved
21
RXEN
Function
Must write reset value.
Receive Enable.
0: Disable the I2S receiver.
1: Enable the I2S receiver.
20
FSSRCSEL
Receive Frame Sync Source Select.
Select the source for the word select or frame sync (WS) input to the block.
0: The word select or frame sync is input from the WS pin.
1: The word select or frame sync is input from the internal DFS generator.
19:18
Reserved
17:15
MBSEL
Must write reset value.
Receive Mono Bit-Width Select.
This field specifies the number of bits per mono sample.
000: 8 bits are received per mono sample.
001: 9 bits are received per mono sample.
010: 16 bits are received per mono sample.
011: 24 bits are received per mono sample.
100: 32 bits are received per mono sample.
101-111: Reserved.
446
Rev. 1.0
Table 23.4. I2S0_RXCONTROL Register Bit Descriptions
Bit
Name
14
Reserved
13
ORDER
Function
Must write reset value.
Receive Order.
This bit chooses which audio channel is received as the first mono sample and second mono sample in various formats.
0: Left sample received first, right sample received second. Use this setting for I2S
format.
1: Right sample received first, left sample received second.
12
SCLKINVEN
Receive SCK Inversion Enable.
0: Do not invert the receiver bit clock.
1: Invert the receiver bit clock.
11
FSINVEN
Receive WS Inversion Enable.
0: Don't invert the WS signal. Use this setting for I2S format.
1: Invert the WS signal.
10
Reserved
9
DDIS
Must write reset value.
Receive Delay Disable.
Setting this bit to 1 disables the data delay after the frame sync.
0: The first data bit is captured on the second or later rising edge of SCK after WS
changes.
1: The first data bit is captured by the receiver on the first rising edge of SCK after
WS changes.
8
JSEL
Receive Data Justification.
0: Use left-justified or I2S-style formats.
1: Use right-justified format.
7:0
FSDEL
Receive Initial Phase Delay.
This field specifies the number of cycles of initial phase delay from the frame sync
edge to the first bit of the sample (non-TDM formats) or to start the first slot (TDM
formats).
Rev. 1.0
447
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.5. I2S0_RXMODE: Receive Mode
31
30
29
28
27
26
Name
Reserved
Type
R
RW
25
24
23
22
21
20
19
18
17
Reserved
Bit
TDMEN
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
SLOTS
START[7:4]
R
RW
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Name
START[3:0]
CYCLE
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_RXMODE = 0x4003_A040
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.5. I2S0_RXMODE Register Bit Descriptions
Bit
Name
31:28
Reserved
27
TDMEN
Function
Must write reset value.
Receive Time Division Multiplexing Enable.
0: Disable the time division multiplexing (TDM) feature.
1: Enable the time division multiplexing (TDM) feature.
26
Reserved
Must write reset value.
25:20
SLOTS
Receive Drive Select.
The number of consecutive TDM slots on which to accept data is equal to SLOTS +
1.
19:12
START
Receive Start Control.
This field is the first TDM slot number in which digital input will start receiving data.
11:0
CYCLE
Receive Clock Cycle Select.
If JSEL is set to 1 for the receiver, this field should be set with the number of slots in
the frame. If DDIS is cleared to 0, the number of slots is CYCLE - 1. If DDIS is also
set to 1, the number of slots per right-justified field is CYCLE - 2.
448
Rev. 1.0
Register 23.6. I2S0_CLKCONTROL: Clock Control
21
20
19
18
17
16
Name
Reserved
FRACDIV[7:6]
22
DUTYMD
23
CLKUPD
24
DIVEN
25
TXCLKSEL
26
RXCLKSEL
27
RESET
28
RXCLKEN
29
TXCLKEN
30
RXSCLKMD
31
TXSCLKMD
Bit
Type
R
RW
RW
RW
RW
W
RW
RW
RW
W
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
FRACDIV[5:0]
INTDIV
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_CLKCONTROL = 0x4003_A050
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.6. I2S0_CLKCONTROL Register Bit Descriptions
Bit
Name
Function
31:28
Reserved
Must write reset value.
27
TXSCLKMD
Transmit SCK Mode.
0: The I2S transmitter SCK signal is an output.
1: The I2S transmitter SCK signal is an input.
26
RXSCLKMD
Receive SCK Mode.
0: The I2S receiver SCK signal is an output.
1: The I2S receiver SCK signal is an input.
25
TXCLKEN
Transmit Clock Enable.
When changes are made to this bit, software should check the TXCLKENRF bit status to determine when the transmitter is ready to send data.
0: Disable the I2S transmitter clock.
1: Enable the I2S transmitter clock.
24
RXCLKEN
Receive Clock Enable.
When changes are made to this bit, software should check the RXCLKENRF bit status to determine when the receiver is ready to accept data.
0: Disable the I2S receiver clock.
1: Enable the I2S receiver clock.
23
RESET
I2S Module Reset.
Writing a 1 to this bit resets the I2S block. This bit is self-clearing when the reset is
complete and does not need to be cleared by software.
Rev. 1.0
449
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Table 23.6. I2S0_CLKCONTROL Register Bit Descriptions
Bit
Name
22
RXCLKSEL
Function
Receive Clock Select.
When changes are made to this bit, software should check the RXCLKSELRF bit
status to determine when the receiver is ready to accept data.
0: The I2S receiver is clocked from the internal clock divider.
1: The I2S receiver is clocked from the SCK pin.
21
TXCLKSEL
Transmit Clock Select.
When changes are made to this bit, software should check the TXCLKSELRF bit
status to determine when the transmitter is ready to send data.
0: The I2S transmitter is clocked from the internal clock divider.
1: The I2S transmitter is clocked from the SCK pin.
20
DIVEN
Clock Divider Enable.
0: Disable the clock divider.
1: Enable the clock divider.
19
CLKUPD
Clock Divider Update.
When this bit is set to 1, the clock divider will update with the new values of INTDIV,
FRACDIV, and DIVEN.
18
DUTYMD
Duty Cycle Adjustment Mode.
0: When the division is fractional, the clock high time will be greater than 50% (by
half of the source clock period).
1: When the division is fractional, the clock low time will be greater than 50% (by
half of the source clock period).
17:10
FRACDIV
Clock Divider Fractional Value.
This field is the fractional portion of the clock division ratio.
9:0
INTDIV
Clock Divider Integer Value.
This field is the integer portion of the clock divider.
450
Rev. 1.0
Register 23.7. I2S0_TXFIFO: Transmit Data FIFO
Bit
31
30
29
28
27
26
25
24
23
Name
TXFIFO[31:16]
Type
W
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
TXFIFO[15:0]
Type
W
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_TXFIFO = 0x4003_A060
Table 23.7. I2S0_TXFIFO Register Bit Descriptions
Bit
Name
31:0
TXFIFO
Function
Transmit Data FIFO.
A write to this register adds a word to the transmitter FIFO. This field should always
be written as a 32-bit word.
Notes:
1. Reads of this register modify the state of hardware. Debug logic should take care when reading this register.
2. The access methods for this register are restricted. Do not use half-word or byte access methods on this register.
Rev. 1.0
451
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.8. I2S0_RXFIFO: Receive Data FIFO
Bit
31
30
29
28
27
26
25
24
23
Name
RXFIFO[31:16]
Type
R
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
RXFIFO[15:0]
Type
R
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Address
I2S0_RXFIFO = 0x4003_A070
Table 23.8. I2S0_RXFIFO Register Bit Descriptions
Bit
Name
31:0
RXFIFO
Function
Receive Data FIFO.
A read from this register removes a word from the receiver FIFO. This field should
always be read as a 32-bit word.
Notes:
1. Reads of this register modify the state of hardware. Debug logic should take care when reading this register.
2. The access methods for this register are restricted. Do not use half-word or byte access methods on this register.
452
Rev. 1.0
Register 23.9. I2S0_FIFOSTATUS: FIFO Status
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
RXFIFONUM
Type
R
R
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXFIFONUM
Type
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_FIFOSTATUS = 0x4003_A080
Table 23.9. I2S0_FIFOSTATUS Register Bit Descriptions
Bit
Name
Function
31:20
Reserved
Must write reset value.
19:16
RXFIFONUM
Receive FIFO Status.
This field indicates the number of 32-bit words in the I2S receiver FIFO.
15:4
Reserved
Must write reset value.
3:0
TXFIFONUM
Transmit FIFO Status.
This field indicates the number of 32-bit words in the I2S transmitter FIFO.
Rev. 1.0
453
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.10. I2S0_FIFOCONTROL: FIFO Control
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
Reserved
31
TXFIFOFL
Bit
RXFIFOFL
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
RXFIFOWM
Type
R
W
W
R
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXFIFOWM
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_FIFOCONTROL = 0x4003_A090
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.10. I2S0_FIFOCONTROL Register Bit Descriptions
Bit
Name
Function
31:23
Reserved
Must write reset value.
22
RXFIFOFL
Receive FIFO Flush.
Writing a 1 to this bit resets the receive FIFO.
21
TXFIFOFL
Transmit FIFO Flush.
Writing a 1 to this bit resets the transmit FIFO.
20
Reserved
19:16
RXFIFOWM
Must write reset value.
Receive FIFO High Watermark.
Hardware generates an interrupt when the number of words remaining in the
receive FIFO (RXFIFONUM) is greater than or equal to the receive FIFO high
watermark (RXFIFOWM).
15:4
Reserved
3:0
TXFIFOWM
Must write reset value.
Transmit FIFO Low Watermark.
Hardware generates an interrupt when the number of words remaining in the transmit FIFO (TXFIFONUM) is less than or equal to the transmit FIFO low watermark
(TXFIFOWM).
454
Rev. 1.0
Register 23.11. I2S0_INTCONTROL: Interrupt Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXUFIEN
0
RXOFIEN
0
TXLWMIEN
0
RXHWMIEN
Reset
Type
R
RW
RW
RW
RW
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_INTCONTROL = 0x4003_A0A0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.11. I2S0_INTCONTROL Register Bit Descriptions
Bit
Name
31:4
Reserved
3
RXHWMIEN
Function
Must write reset value.
Receive FIFO High Watermark Interrupt Enable.
0: Disable the receive FIFO high watermark interrupt.
1: Enable the receive FIFO high watermark interrupt.
2
TXLWMIEN
Transmit FIFO Low Watermark Interrupt Enable.
0: Disable the transmit FIFO low watermark interrupt.
1: Enable the transmit FIFO low watermark interrupt.
1
RXOFIEN
Receive Overflow Interrupt Enable.
0: Disable the receive overflow interrupt.
1: Enable the receive overflow interrupt.
0
TXUFIEN
Transmit Underflow Interrupt Enable.
0: Disable the transmit underflow interrupt.
1: Enable the transmit underflow interrupt.
Rev. 1.0
455
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.12. I2S0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXUFI
0
RXOFI
0
TXLWMI
0
RXHWMI
0
CDBUSYF
0
CDSTS
0
TXCLKSELRF
0
RXCLKSELRF
0
TXCLKENRF
Reset
RXCLKENRF
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Type
R
R
R
R
R
R
R
R
R
RW
RW
0
0
0
0
1
0
1
1
0
0
Reset
0
0
0
0
0
0
Register ALL Access Address
I2S0_STATUS = 0x4003_A0B0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.12. I2S0_STATUS Register Bit Descriptions
Bit
Name
31:10
Reserved
9
RXCLKENRF
Function
Must write reset value.
Receive Clock Enable Ready Flag.
When changes are made to the RXCLKEN bit, software should check this bit to
determine when the receiver is ready to accept data.
0: The receive clock is not synchronized.
1: The receive clock is synchronized and the receiver is ready to accept data.
8
TXCLKENRF
Transmit Clock Enable Ready Flag.
When changes are made to the TXCLKEN bit, software should check this bit to
determine when the transmitter is ready to send data.
0: The transmit clock is not synchronized.
1: The transmit clock is synchronized and the transmitter is ready to send data.
7
RXCLKSELRF
Receive Clock Select Ready Flag.
When changes are made to the RXCLKSEL bit, software should check this bit to
determine when the receiver is ready to accept data.
0: The receive clock is not synchronized.
1: The receive clock is synchronized and the receiver is ready to accept data.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
456
Rev. 1.0
Table 23.12. I2S0_STATUS Register Bit Descriptions
Bit
Name
6
TXCLKSELRF
Function
Transmit Clock Select Ready Flag.
When changes are made to the TXCLKSEL bit, software should check this bit to
determine when the transmitter is ready to send data.
0: The transmit clock is not synchronized.
1: The transmit clock is synchronized and the transmitter is ready to send data.
5
CDSTS
Clock Divider Counter Status.
0: Divided clock output is running.
1: Divided clock output is halted.
4
CDBUSYF
Clock Divider Busy Flag.
0: The divider is not busy and an update is not pending.
1: The divider is busy and an update is pending.
3
RXHWMI
Receive FIFO High Watermark Interrupt Flag.
0: Receive FIFO level is below the high watermark.
1: Receive FIFO level is at or above the high watermark.
2
TXLWMI
Transmit FIFO Low Watermark Interrupt Flag.
0: Transmit FIFO level is above the low watermark.
1: Transmit FIFO level is at or below the low watermark.
1
RXOFI
Receive Overflow Interrupt Flag.
0: A receive overflow has not occurred.
1: A receive overflow occurred.
0
TXUFI
Transmit Underflow Interrupt Flag.
0: A transmit underflow has not occurred.
1: A transmit underflow occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
457
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Register 23.13. I2S0_DMACONTROL: DMA Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXDMAEN
0
RXDMAEN
0
TXDMABMD
Reset
RXDMABMD
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
RW
RW
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_DMACONTROL = 0x4003_A0C0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.13. I2S0_DMACONTROL Register Bit Descriptions
Bit
Name
31:4
Reserved
3
RXDMABMD
Function
Must write reset value.
Receive DMA Burst Mode.
0: The receiver receives one word at a time. Whenever there is at least one word in
the receive FIFO, a single word burst DMA request is generated.
1: The receiver receives four words at a time. Whenever the FIFO depth rises above
three, a DMA burst request is generated for four words.
2
TXDMABMD
Transmit DMA Burst Mode.
0: The transmitter transmits one word at a time. Whenever there is any room in the
transmit FIFO, a single word burst DMA data request is generated.
1: The transmitter transmits four words at a time. Whenever the FIFO depth drops
below five, a DMA burst request is generated for four words.
1
RXDMAEN
Receive DMA Enable.
When this bit is set, the receiver will send a word from the receive FIFO to the
assigned DMA channel based on the receive FIFO status.
0: Disable receiver DMA data transfer requests.
1: Enable receiver DMA data transfer requests.
0
TXDMAEN
Transmit DMA Enable.
When this bit is set, the transmitter will request a word from the assigned DMA
channel and place it in the transmitter FIFO based on the transmit FIFO status.
0: Disable transmitter DMA data requests.
1: Enable transmitter DMA data requests.
458
Rev. 1.0
Register 23.14. I2S0_DBGCONTROL: Debug Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
TXDBGHEN
0
RXDBGHEN
0
TXDBGMD
0
RXDBGMD
Reset
Type
R
RW
RW
RW
RW
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
I2S0_DBGCONTROL = 0x4003_A0D0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 23.14. I2S0_DBGCONTROL Register Bit Descriptions
Bit
Name
31:4
Reserved
3
RXDBGMD
Function
Must write reset value.
I2S Receive Debug Mode.
0: The clock to the I2S receiver is active in debug mode.
1: The clock to the I2S receiver is not active in debug mode. The clock divider keeps
running and the clock will be disabled when two samples are captured in the
receiver.
2
TXDBGMD
I2S Transmit Debug Mode.
0: The clock to the I2S transmitter is active in debug mode.
1: The clock to the I2S transmitter is not active in debug mode. The clock divider
keeps running and the clock will be disabled when two samples are ready to be sent
by the transmitter.
1
RXDBGHEN
I2S Receive DMA Debug Halt Enable.
0: Receive DMA requests continue while the core is debug mode.
1: Receive DMA requests stop while the core is debug mode.
0
TXDBGHEN
I2S Transmit DMA Debug Halt Enable.
0: Transmit DMA requests continue while the core is debug mode.
1: Transmit DMA requests stop while the core is debug mode.
Rev. 1.0
459
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
I2S0_RXMODE I2S0_RXCONTROL I2S0_FSDUTY I2S0_TXMODE I2S0_TXCONTROL Register Name
0x4003_A010
ALL Address
0x4003_A020
0x4003_A030
0x4003_A040
0x4003_A000
ALL | SET | CLR ALL | SET | CLR Access Methods
ALL
ALL | SET | CLR ALL | SET | CLR
Bit 31
Reserved
Bit 30
Reserved
Reserved
TXEN
Bit 29
Bit 28
Reserved
TDMEN
TDMEN
Bit 27
Reserved
Reserved
DIMD
Bit 26
MBSEL
DEDIS
Bit 25
Bit 24
FSHIGH
Reserved
Bit 23
SLOTS
SLOTS
ORDER
Bit 22
RXEN
SCLKINVEN
Bit 21
FSSRCSEL
FSINVEN
Bit 20
Bit 19
Reserved
Reserved
Bit 18
JSEL
Bit 17
MBSEL
Bit 16
START
START
FILLSEL
Bit 15
Reserved
FSSRCSEL
Bit 14
ORDER
Bit 13
SCLKINVEN
Bit 12
FSINVEN
Bit 11
Reserved
Bit 10
FSDEL
DDIS
Bit 9
JSEL
Bit 8
FSLOW
Bit 7
Bit 6
CYCLE
CYCLE
DDIS
Bit 5
Bit 4
FSDEL
Reserved
Bit 3
Bit 2
FSSEN
Bit 1
FSGEN
Bit 0
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
23.15. I2S0 Register Memory Map
Table 23.15. I2S0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
460
Rev. 1.0
I2S0_FIFOCONTROL I2S0_FIFOSTATUS I2S0_RXFIFO I2S0_TXFIFO I2S0_CLKCONTROL Register Name
0x4003_A090
0x4003_A050
ALL Address
0x4003_A080
0x4003_A070 0x4003_A060
ALL | SET | CLR
ALL | SET | CLR
Access Methods
ALL
ALL
ALL
Bit 31
Bit 30
Reserved
Bit 29
Bit 28
Reserved
TXSCLKMD
Bit 27
RXSCLKMD
Bit 26
Reserved
TXCLKEN
Bit 25
RXCLKEN
Bit 24
RESET
Bit 23
RXFIFOFL
RXCLKSEL
Bit 22
TXFIFOFL
TXCLKSEL
Bit 21
Reserved
DIVEN
Bit 20
CLKUPD
Bit 19
DUTYMD
Bit 18
RXFIFONUM
RXFIFOWM
Bit 17
Bit 16
RXFIFO
TXFIFO
Bit 15
Bit 14
FRACDIV
Bit 13
Bit 12
Bit 11
Bit 10
Reserved
Reserved
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
INTDIV
Bit 4
Bit 3
Bit 2
TXFIFOWM
TXFIFONUM
Bit 1
Bit 0
Table 23.15. I2S0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
461
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
I2S0_DBGCONTROL I2S0_DMACONTROL I2S0_STATUS I2S0_INTCONTROL Register Name
0x4003_A0A0
ALL Address
0x4003_A0D0
0x4003_A0B0
0x4003_A0C0
ALL | SET | CLR
ALL | SET | CLR ALL | SET | CLR Access Methods
ALL | SET | CLR
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Reserved
Bit 20
Bit 19
Bit 18
Reserved
Reserved
Reserved
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
RXCLKENRF
Bit 9
TXCLKENRF
Bit 8
RXCLKSELRF
Bit 7
TXCLKSELRF
Bit 6
CDSTS
Bit 5
CDBUSYF
Bit 4
RXDBGMD
RXDMABMD
RXHWMIEN
RXHWMI
Bit 3
TXDBGMD
TXDMABMD
TXLWMIEN
TXLWMI
Bit 2
RXDBGHEN
RXDMAEN
RXOFIEN
RXOFI
Bit 1
TXDBGHEN
TXDMAEN
TXUFIEN
TXUFI
Bit 0
Integrated Interchip Sound (I2S0)
SiM3U1xx/SiM3C1xx
Table 23.15. I2S0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
462
Rev. 1.0
24. Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
This section describes the Current Mode DAC (IDAC) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the IDAC block, which is used by both IDAC0 and IDAC1 on all device
families covered in this document.
24.1. IDAC Features
The IDAC takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module
includes the following features:
10-bit
current DAC with output update trigger source options.
to update on rising, falling, or both edge for any of the external I/O trigger sources (DACnTx).
Support for three full-scale output modes: 0.5, 1.0, and 2.0 mA.
Four-word FIFO to aid with high-speed waveform generation or DMA interactions.
FIFO supports wrapping mode, allowing the four values to be continuously cycled through to achieve 12-bit
resolution.
Individual FIFO overrun, underrun, and went-empty interrupt status sources.
Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per
word, or four 8-bit samples per word.
Support for left- and right-justified data.
Ability
IDACn Module
DACnT0
selectable
edge-based
triggers
DACnT1
DACnT2
DACnT3
DACnT4
DACnT5
DACnT6
DACnT7
DACnT8
DACnT9
DACnT10
FIFO Status and
Control
DACnT11
Data FIFO
sample 1
DATA
sample 2
sample 3
Current Mode
Digital to Analog
Converter
IDACn
sample 4
Output Control
Figure 24.1. IDAC Block Diagram
Rev. 1.0
463
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
24.2. IDAC Setup
The various IDAC features and modes are enabled using the CONTROL register. Table 24.3 summarizes the
CONTROL register settings for using the IDAC in four different modes: on-demand mode, periodic FIFO wrap
mode, periodic FIFO-only mode, and periodic DMA mode. For more detailed bit descriptions, please refer to the
IDACn_CONTROL register description.
The entire IDAC block is enabled by setting the IDACEN bit, and can be shut off completely by clearing IDACEN. In
most applications, the CONTROL register can be configured with a single write to both configure and enable the
IDAC peripheral.
24.2.1. Full Scale Output
The IDAC full scale current output is configured using the OUTMD bit field. Three selectable ranges are available.
These are nominally 2.046, 1.023 and 0.5115 mA. The resulting 10-bit LSB sizes of the IDAC in these three modes
are 2 µA, 1 µA and 500 nA, respectively.
Optionally, an on-chip load resistor can be enabled by setting the LOADEN bit. This enables an impedance path to
ground which effectively produces a voltage at the output pin. The nominal value of the load resistor is given in the
device data sheet electrical specification tables. Note that any additional load impedance on the IDAC output pin
will affect the output voltage in this mode.
This on-chip load resistor may be useful in some low-accuracy applications. The resistor exhibits a voltage
dependence that may contribute some integral non-linearity in addition to the INL of the IDAC itself. The voltage
output may also include noise or offset error due to differences in voltage between the internal ground of the
resistor and the external board ground. For these reasons, an external resistor is recommended for the generation
of an accurate ground-referenced voltage on the IDAC output.
24.2.2. Data Format
The IDAC output data can be packed into 32-bit words in three different ways, selected by the INFMT field: single
10-bit data entry, two 10-bit data entries, and four 8-bit data entries. Only single 10-bit data mode is supported
when the trigger source is set to on-demand. Note that in 8-bit mode, only the upper 8 bits of the IDAC are used.
When the packing format is configured for one of the two 10-bit options, the justification within each 16-bit half word
of the 32-bit words can be specified using the JSEL bit. Data will be interpreted as right-justified when JSEL is 0,
and left-justified when JSEL is 1. In the 8-bit packing mode, the JSEL bit has no effect. Figure 24.2 shows the data
packing mode and justification options.
DATA Register or DMA Input
31
9
0
Single 10-bit Sample, Right-Justified
INFMT = 00b, JSEL = 0
Sample 1
15
31
0
6
Single 10-bit Sample, Left-Justified
INFMT = 00b, JSEL = 1
Sample 1
31
25
16
9
0
Sample 2
31
22
15
Sample 2
31
6
0
Two 10-bit Samples, Left-Justified
INFMT = 01b, JSEL = 1
Sample 1
24 23
Sample 4
Two 10-bit Samples, Right-Justified
INFMT = 01b, JSEL = 0
Sample 1
16 15
Sample 3
8 7
Sample 2
0
Sample 1
Four 8-bit Samples
INFMT = 10b, JSEL = not used
Figure 24.2. Data Packing Modes and Data Justification
464
Rev. 1.0
24.2.3. Conversion Triggers
IDAC conversions can be triggered “on-demand” with a write to the DATA register, or periodically using one of the
internal timer options or external conversion trigger inputs. Up to eight different external pins can be used as
external trigger sources. The Sample Sync Generator (SSG) block is also selectable as an external trigger source.
Specific trigger input sources for the IDACs vary between package options, and are detailed in Table 24.1 and
Table 24.2.
Two fields in the CONTROL register configure the IDAC trigger source: OUPDT and ETRIG. The OUPDT field
selects the trigger event from internal trigger sources (DACnT8 through DACnT11), on-demand mode, or one of
three external trigger edge options. When set to an external trigger option, the IDAC can be triggered on the rising
edge, falling edge, or both edges of a trigger source specified by the ETRIG bits.
Triggering of the IDAC can be inhibited at any time from firmware by writing the TRIGINH bit to 1. Any trigger
events are ignored by the IDAC until the TRIGINH bit is cleared to 0 (except in on-demand mode, where TRIGINH
is not used).
Table 24.1. IDAC0 and IDAC1 Output Update Triggers
IDAC0
Trigger
IDAC1
Trigger
Trigger Description
Internal Signal
DAC0T8
DAC1T8
Internal Trigger Source
Timer 0 Low overflow
DAC0T9
DAC1T9
Internal Trigger Source
Timer 0 High overflow
DAC0T10
DAC1T10
Internal Trigger Source
Timer 1 Low overflow
DAC0T11
DAC1T11
Internal Trigger Source
Timer 1 High overflow
DAC0T12
DAC1T12
Internal Trigger Source
DACnT0-DACnT7 (selected by ETRIG) rising edge
DAC0T13
DAC1T13
Internal Trigger Source
DACnT0-DACnT7 (selected by ETRIG) falling edge
DAC0T14
DAC1T14
Internal Trigger Source
DACnT0-DACnT7 (selected by ETRIG) any edge
DAC0T15
DAC1T15
Internal Trigger Source
“On Demand” by writing to the DATA field
Rev. 1.0
465
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Table 24.2. IDAC0 and IDAC1 ETRIG Selections
IDAC0
Trigger
IDAC1
Trigger
Trigger Description
DAC0T0
DAC1T0
External Trigger Source
PB3.2
PB3.2
PB3.0
DAC0T1
DAC1T1
External Trigger Source
PB3.3
PB3.3
PB3.1
DAC0T2
DAC1T2
External Trigger Source
PB3.5
PB3.5
PB3.2
DAC0T3
DAC1T3
External Trigger Source
PB3.6
PB3.6
PB3.3
DAC0T4
DAC1T4
External Trigger Source
PB3.7
PB3.7
Reserved
DAC0T5
DAC1T5
External Trigger Source
PB3.8
PB3.8
Reserved
DAC0T6
DAC1T6
External Trigger Source
PB3.9
PB3.9
Reserved
DAC0T7
DAC1T7
Internal Trigger Source
466
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
Rev. 1.0
SSG0 (IDAC0 = EX2, IDAC1 = EX3)
Table 24.3. IDAC Configuration Quick-Reference
Bit Field in
CONTROL
Register
Operational Mode
On-Demand
Periodic FIFO Wrap
(no DMA)
IDACEN
Periodic FIFO-Only
(no DMA)
Periodic with DMA
1 = Enable IDAC
DMARUN
0 = Disable DMA
1 = Enable DMA
INFMT
00b = Single, 10-bit
Sample
Any Option
OUPDT
111b = Trigger OnDemand
Any Option Except 111b
LOADEN
Load resistor enable = Set to 1 if internal load path is desired
DBGMD
Debug Mode = Set to 1 to let IDAC continue running in debug halt
JSEL
Data Justification for 10-bit Input Formats: 0 = Right-justify data, 1 = Left-justify data
OUTMD
Load resistor enable = Set on/off according to application needs
WEIEN
N/A
Set to enable FIFO Went Empty Interrupt
URIEN
N/A
Set to enable FIFO Underrun Interrupt
ORIEN
N/A
Set to enable FIFO Overrun Interrupt
WRAPEN
N/A
1 = Enable Wrap
TRIGINH
N/A
Set to inhibit IDAC triggering
BUFRESET
N/A
Set to reset input FIFO
ETRIG
N/A
Selects external trigger source (if used)
Rev. 1.0
0 = Disable Wrap
467
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
24.3. Using the IDAC in On-Demand Mode
On-demand mode is useful primarily in DC applications where the IDAC output is changed infrequently. In ondemand mode, the IDAC output is taken directly from the DATA register, and any writes to the DATA register will
trigger a corresponding change in current at the IDAC output pin.
The only data input mode supported for on-demand operation is single 10-bit mode. Data writes can be left or rightjustified. The FIFO and its associated interrupts are not used in this mode.
24.4. Using the IDAC in Periodic FIFO-Only Mode
Periodic FIFO-only mode is useful in applications where the IDAC output needs to be updated at a specific time
interval, and frequent software intervention is desired. In periodic FIFO-only mode, IDAC updates are configured to
occur on the selected trigger signal, and the next output value is pulled from a four-sample FIFO buffer associated
with the IDAC. Writes to the DATA register from firmware push new data into the FIFO. It is important that the FIFO
has enough room for the sample(s) written to the data register. For example, when INFMT is configured for four 8bit samples, the entire FIFO must be empty before writing to DATA, but when INFMT is configured for single 10-bit
samples, only one FIFO entry need be free.
The number of samples currently waiting in the FIFO is reflected in the LEVEL field of the BUFSTATUS register.
The contents of the FIFO can be inspected at any time by reading the BUFFER10 and BUFFER32 registers, and
the current IDAC output can always be read from the DATA register.
All three interrupt sources can be enabled in periodic FIFO-only mode. Their meanings for this mode are detailed
below.
FIFO
Underrun Interrupt (URI): The URI interrupt flag will be set if an IDAC trigger happens and the FIFO
buffer level is zero (i.e. when there is no data to pull from the FIFO). The FIFO read pointer and IDAC
output will not be updated when an underrun error occurs.
FIFO Overrun Interrupt (ORI): The ORI interrupt flag will be set if firmware writes to DATA and there is not
enough room in the FIFO for the number of samples written. In this case, no data will be written to the
FIFO, and the FIFO write pointer will not be updated.
FIFO Went Empty Interrupt (WEI): The WEI interrupt flag will be set when an IDAC update reads the final
byte from the FIFO into the IDAC output latch, and causes the FIFO level to go to zero. This interrupt can
be used by firmware to initiate a new write to the FIFO before the next trigger occurs, and avoid an
underrun interrupt.
24.5. Using the IDAC in Periodic FIFO Wrap Mode
Periodic FIFO wrap mode is similar to periodic FIFO-only mode in all ways except for the behavior of the FIFO and
the IDAC interrupts. In this mode, the IDAC will continuously pull from the four-sample FIFO in a circular fashion,
thereby generating a repeating four sample pattern. The underrun and went empty interrupts are masked off in this
mode, and will never occur. The overrun interrupt flag is still active in this mode, but is typically not of much use.
This mode can extend the effective resolution of the DAC to 12 bits at one-fourth of the 10-bit sample rate by using
the four words in the buffer to interpolate between two adjacent 10-bit values. For example, if the FIFO includes
three words of value n and one word of value n+1, then the average output value will be n+0.25, which represents
a 12-bit quantity.
To load a new set of four samples into the FIFO, the following sequence should be followed:
1. Wait for an IDAC trigger to occur.
2. Reset the FIFO by writing 1 to the BUFRESET bit in the CONTROL register.
3. Load the FIFO with the next set of four samples. The first of these samples should be written before the
next trigger event occurs to avoid any glitches in the IDAC output.
468
Rev. 1.0
24.6. Using the IDAC in Periodic DMA Mode (on select IDAC peripherals only)
A DMA channel can be used to offload core resources and transfer data into the IDAC FIFO. When used in
periodic DMA mode, the configuration and capabilities of the IDAC are largely the same as those described in
periodic FIFO-only mode. The difference in DMA mode is how data is written into the FIFO, as well as the meaning
of the interrupt sources.
When a DMA channel is used to write the FIFO buffer, the FIFO logic will work to keep the buffer full. The FIFO
level is monitored, and when the level falls below the number of samples encoded per data word (as specified by
the INFMT field), a DMA request will be generated. The DMA request will remain pending until the FIFO no longer
has room for new transfers. When configured for a single sample per data word (INFMT = 00b), DMA requests are
generated when the LEVEL field in BUFSTATUS is less than or equal to 3. For two samples per data word (INFMT
= 01b), DMA requests are generated when LEVEL is less than or equal to two, and for four samples per data word
(INFMT = 10b), LEVEL must be 0 to initiate a DMA transfer.
For the IDAC module, the DMA should be configured as follows:
Source
size (SRCSIZE) and destination size (DSTSIZE) are 2 for a word transfer.
source address increment (SRCAIMD) is 2 for word increments.
The destination address increment (DSTAIMD) is 3 for non-incrementing mode.
The NCOUNT value is N – 1, where N is the number of 4-byte words.
RPOWER = 0 (1 word transfer per transaction).
Once the DMA is configured, writing a 1 to DMAEN will enable the DMA request from the IDAC. The FIFO will
continue to be serviced by the DMA until the specified transfer operation is complete.
The
When the DMA transfer is complete, the FIFO went empty interrupt flag will be asserted, and the DMAEN bit will be
cleared to 0 by hardware. If firmware requires continuous operation of the IDAC as this occurs, it must handle the
went empty interrupt, reconfigure the DMA and enable DMA transfers before the next trigger source occurs.
All three interrupt sources can be enabled in periodic DMA mode, and it is recommended that firmware do so. The
meanings of the interrupts for this mode are detailed below.
FIFO
Underrun Interrupt (URI): The URI interrupt flag will be set if an IDAC trigger happens and the FIFO
buffer level is zero (i.e. when there is no data to pull from the FIFO). This can occur if the configured DMA
transfer has not completed and a new trigger occurs.
FIFO Overrun Interrupt (ORI): The ORI interrupt flag will be set if a DMA transfer occurs when there is not
enough room in the FIFO for the number of samples written. In this case, no data will be written to the
FIFO, and the FIFO write pointer will not be updated. An overrun error should not occur when using the
DMA unless there is a firmware conflict with the FIFO.
FIFO Went Empty Interrupt (WEI): In DMA mode, the WEI interrupt flag is only set at the end of a DMA
transfer. This enables the WEI interrupt to be used by firmware to initiate the next DMA sequence if
needed.
24.7. Adjusting the IDAC Output Current
The output current of the IDAC is factory calibrated to provide the target current for each OUTMD setting. However,
the output current can be adjusted slightly in 32 steps using the GAINADJ field. A value of zero in this field
represents the minimum current the IDAC can output at the current OUTMD setting, and a maximum value of 31 in
this field represents the maximum current. Each step adjusts the output current by about 1.5%.
This GAINADJ field can be used to calibrate small gain errors that result when using either the internal load resistor
or a wider tolerance external load resistor. If the device has an ADC module, the IDAC can be connected internally
to the ADC if the IDAC output pin is supported on the ADC input mux or connected externally by shorting the IDAC
output and ADC input pins together. Firmware can then use the ADC to measure the resulting voltage on the IDAC
output and adjust the GAINADJ field until reaching the desired voltage on the IDAC output.
24.8. Debug Mode
Firmware can set the DBGMD bit to force the IDAC module to halt on a debug breakpoint. Clearing the DBGMD bit
forces the module to continue operating while the core halts in debug mode.
Rev. 1.0
469
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
24.9. IDAC0 and IDAC1 Registers
This section contains the detailed register descriptions for IDAC0 and IDAC1 registers.
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Reserved
BUFRESET
JSEL
DMARUN
27
26
25
24
Reserved
RW
R
RW
RW
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
INFMT
OUTMD
ETRIG
OUPDT
Type
R
RW
W
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
23
0
0
0
19
18
17
16
Reserved
WRAPEN
Name
0
28
ORIEN
29
TRIGINH
20
URIEN
30
0
21
WEIEN
31
Reset
22
DBGMD
Bit
LOADEN
Register 24.1. IDACn_CONTROL: Module Control
IDACEN
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
RW
R
RW
0
0
1
1
1
Register ALL Access Addresses
IDAC0_CONTROL = 0x4003_1000
IDAC1_CONTROL = 0x4003_2000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 24.4. IDACn_CONTROL Register Bit Descriptions
Bit
Name
31
IDACEN
Function
IDAC Enable.
0: Disable the IDAC.
1: Enable the IDAC.
30
LOADEN
Load Resistor Enable.
Enables an on-chip load resistor to ground.
0: Disable the internal load resistor.
1: Enable the internal load resistor.
29
DBGMD
IDAC Debug Mode.
0: The IDAC module will continue to operate while the core is halted in debug mode.
1: A debug breakpoint will cause the IDAC module to halt (ignore update triggers).
28:23
Reserved
22
WEIEN
Must write reset value.
FIFO Went Empty Interrupt Enable.
Enables the FIFO went empty interrupt flag (WEI) to generate an IDAC interrupt
when set to 1.
470
Rev. 1.0
Table 24.4. IDACn_CONTROL Register Bit Descriptions
Bit
Name
21
URIEN
Function
FIFO Underrun Interrupt Enable.
Enables the FIFO underrun interrupt flag (URI) to generate an IDAC interrupt when
set to 1.
20
ORIEN
FIFO Overrun Interrupt Enable.
Enables the FIFO overrun interrupt flag (ORI) to generate an IDAC interrupt when
set to 1.
19:17
Reserved
Must write reset value.
16
WRAPEN
Wrap Mode Enable.
Enables IDAC to repeatedly cycle over the FIFO contents in a circular fashion.
0: The IDAC will not wrap when it reaches the end of the data buffer.
1: The IDAC will cycle through the data buffer contents.
15:14
Reserved
Must write reset value.
13
TRIGINH
Trigger Source Inhibit.
Setting this bit to 1 will mask of any periodic trigger sources. No updates to the
IDAC will occur when this bit is set, unless the IDAC is configured for on-demand
mode. When cleared to 0, IDAC updates will resume on the next trigger source
(trigger sources are not queued).
12
BUFRESET
Data Buffer Reset.
Writing a 1 to this bit resets the data buffer. Writing a 0 has no effect, and this bit
always reads back as 0.
11
JSEL
Data Justification Select.
This bit selects the data justification in 10-bit input modes.
0: Data is right-justified.
1: Data is left-justified.
10
DMARUN
DMA Run.
Writing a 1 to this bit enables DMA transfers. This bit is automatically cleared when
DMA operations are complete.
9:8
INFMT
Data Input Format.
This field determines the interpretation of data written to the IDAC. Only single, 10bit samples are supported in on-demand mode. For periodic FIFO-only mode or
periodic FIFO wrap mode, FIFO writes occur on a write to the DATA register. In
DMA mode, FIFO writes occur on a DMA event.
00: Writes are interpreted as one 10-bit sample.
01: Writes are interpreted as two 10-bit samples.
10: Writes are interpreted as four 8-bit samples.
11: Reserved.
7:6
OUTMD
Output Mode.
This field selects the IDAC full-scale output current.
00: The full-scale output current is 0.5 mA.
01: The full-scale output current is 1 mA.
10: The full-scale output current is 2 mA.
11: Reserved.
Rev. 1.0
471
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Table 24.4. IDACn_CONTROL Register Bit Descriptions
Bit
Name
5:3
ETRIG
Function
Edge Trigger Source Select.
When OUPDT is configured for any of the edge-trigger options (100b, 101b, or
110b), this field selects the specific external trigger source.
000: Select DACnT0 as the IDAC external trigger source.
001: Select DACnT1 as the IDAC external trigger source.
010: Select DACnT2 as the IDAC external trigger source.
011: Select DACnT3 as the IDAC external trigger source.
100: Select DACnT4 as the IDAC external trigger source.
101: Select DACnT5 as the IDAC external trigger source.
110: Select DACnT6 as the IDAC external trigger source.
111: Select DACnT7 as the IDAC external trigger source.
2:0
OUPDT
Output Update Trigger.
This field selects the trigger source for IDAC output updates.
000: The IDAC output updates using the DACnT8 trigger source.
001: The IDAC output updates using the DACnT9 trigger source.
010: The IDAC output updates using the DACnT10 trigger source.
011: The IDAC output updates using the DACnT11 trigger source.
100: The IDAC output updates on the rising edge of the trigger source selected by
ETRIG.
101: The IDAC output updates on the falling edge of the trigger source selected by
ETRIG.
110: The IDAC output updates on any edge of the trigger source selected by ETRIG.
111: The IDAC output updates on write to DATA register (On Demand).
472
Rev. 1.0
Register 24.2. IDACn_DATA: Output Data
Bit
31
30
29
28
27
26
25
24
23
Name
DATA[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
DATA[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
IDAC0_DATA = 0x4003_1010
IDAC1_DATA = 0x4003_2010
Table 24.5. IDACn_DATA Register Bit Descriptions
Bit
Name
31:0
DATA
Function
Output Data.
When the OUPDT field is set to On-Demand mode, writes to this register update the
IDAC value immediately, and are assumed to contain a single 10-bit sample. For all
other trigger sources, writes to this register are pushed into the data buffer in the format specified by the INFMT field. Reads from this register always return the current
output value in the IDAC latch.
Rev. 1.0
473
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Register 24.3. IDACn_BUFSTATUS: FIFO Buffer Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
0
ORI
0
URI
Reset
WEI
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
LEVEL
Type
R
RW
RW
RW
R
R
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
IDAC0_BUFSTATUS = 0x4003_1020
IDAC1_BUFSTATUS = 0x4003_2020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 24.6. IDACn_BUFSTATUS Register Bit Descriptions
Bit
Name
31:7
Reserved
6
WEI
Function
Must write reset value.
FIFO Went Empty Interrupt Flag.
This bit is set to 1 by hardware when the last sample is transferred from the FIFO
into the IDAC output latch. This bit must be cleared by software.
5
URI
FIFO Underrun Interrupt Flag.
This bit is set to 1 by hardware when a FIFO underrun has occurred. This bit must
be cleared by software.
4
ORI
FIFO Overrun Interrupt Flag.
This bit is set to 1 by hardware when a FIFO overrun has occurred. This bit must be
cleared by software.
3
Reserved
Must write reset value.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
474
Rev. 1.0
Table 24.6. IDACn_BUFSTATUS Register Bit Descriptions
Bit
Name
2:0
LEVEL
Function
FIFO Level.
Indicates the number of words currently pending in the output data FIFO.
000: The data FIFO is empty.
001: The data FIFO contains one word.
010: The data FIFO contains two words.
011: The data FIFO contains three words.
100: The data FIFO is full and contains four words.
101-111: Reserved.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
475
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Register 24.4. IDACn_BUFFER10: FIFO Buffer Entries 0 and 1
Bit
31
30
29
28
27
26
25
24
23
Name
BUFFER1
Type
R
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
BUFFER0
Type
R
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Addresses
IDAC0_BUFFER10 = 0x4003_1030
IDAC1_BUFFER10 = 0x4003_2030
Table 24.7. IDACn_BUFFER10 Register Bit Descriptions
Bit
Name
31:16
BUFFER1
Function
FIFO Buffer Entry 1.
This field is the second pending IDAC output. It is justified according to the JSEL
selection.
15:0
BUFFER0
FIFO Buffer Entry 0.
This field is the first pending IDAC output. It is justified according to the JSEL selection.
476
Rev. 1.0
Register 24.5. IDACn_BUFFER32: FIFO Buffer Entries 2 and 3
Bit
31
30
29
28
27
26
25
24
23
Name
BUFFER3
Type
R
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
BUFFER2
Type
R
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Addresses
IDAC0_BUFFER32 = 0x4003_1040
IDAC1_BUFFER32 = 0x4003_2040
Table 24.8. IDACn_BUFFER32 Register Bit Descriptions
Bit
Name
31:16
BUFFER3
Function
FIFO Buffer Entry 3.
This field is the fourth pending IDAC output. It is justified according to the JSEL
selection.
15:0
BUFFER2
FIFO Buffer Entry 2.
This field is the third pending IDAC output. It is justified according to the JSEL selection.
Rev. 1.0
477
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Register 24.6. IDACn_GAINADJ: Output Current Gain Adjust
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
Name
Reserved
GAINADJ
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
X
X
X
Register ALL Access Addresses
IDAC0_GAINADJ = 0x4003_1050
IDAC1_GAINADJ = 0x4003_2050
Table 24.9. IDACn_GAINADJ Register Bit Descriptions
Bit
Name
Function
31:5
Reserved
Must write reset value.
4:0
GAINADJ
Output Current Gain Adjust.
This field is factory calibrated to produce the target full-scale output current for all
OUTMD settings. However, firmware can modify this field to adjust the output current of the IDAC up or down. A value of 0 represents the minimum current setting,
and a value of 31 represents the maximum current setting. Each step adjusts the
output current by about 1.5%.
478
Rev. 1.0
24.10. IDACn Register Memory Map
IDACn_BUFFER10 IDACn_BUFSTATUS IDACn_DATA IDACn_CONTROL Register Name
ALL Offset
0x30
0x20
0x10
0x0
ALL
ALL | SET | CLR
ALL
ALL | SET | CLR Access Methods
Bit 31
IDACEN
Bit 30
LOADEN
Bit 29
DBGMD
Bit 28
Bit 27
Bit 26
Reserved
Bit 25
Bit 24
BUFFER1
Bit 23
WEIEN
Bit 22
URIEN
Bit 21
ORIEN
Bit 20
Reserved
Bit 19
Reserved
Bit 18
Bit 17
WRAPEN
Bit 16
DATA
Bit 15
Reserved
Bit 14
TRIGINH
Bit 13
BUFRESET
Bit 12
JSEL
Bit 11
DMARUN
Bit 10
Bit 9
INFMT
Bit 8
BUFFER0
Bit 7
OUTMD
WEI
Bit 6
URI
Bit 5
ETRIG
ORI
Bit 4
Reserved
Bit 3
Bit 2
LEVEL
OUPDT
Bit 1
Bit 0
Table 24.10. IDACn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: IDAC0 = 0x4003_1000, IDAC1 = 0x4003_2000
Rev. 1.0
479
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Table 24.10. IDACn Memory Map
IDACn_GAINADJ IDACn_BUFFER32 Register Name
0x40
ALL Offset
0x50
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
BUFFER3
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Reserved
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
BUFFER2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GAINADJ
Bit 2
Bit 1
Bit 0
Current Mode Digital-to-Analog Converter (IDAC0 and IDAC1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: IDAC0 = 0x4003_1000, IDAC1 = 0x4003_2000
480
Rev. 1.0
25. Current-to-Voltage Converter (IVC0)
This section describes the Current-to-Voltage Converter (IVC) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the IVC block, which is used by all device families covered in this document.
25.1. IVC Features
The IVC module allows current sourced from a pin (sunk externally) to be measured by SARADCn modules on the
device. The Current-to-Voltage Converter (IVC) module includes the following features:
Two
independent channels.
input ranges.
Programmable
IVCn Module
Programmable
Input Range
IVCn.0
Current to Voltage
Converter 0
IVCnC0
IVCn.1
Current to Voltage
Converter 1
IVCnC1
Programmable
Input Range
Figure 25.1. IVC Block Diagram
Rev. 1.0
481
Current-to-Voltage Converter (IVC0)
SiM3U1xx/SiM3C1xx
Current-to-Voltage Converter (IVC0)
SiM3U1xx/SiM3C1xx
25.2. Functional Description
The IVC module consists of two channels of current-to-voltage conversion circuitry. It allows current sunk by
external circuitry to be measured by a SARADCn module on the device. The response time of the IVC circuit is fast
enough to settle full-scale current changes at the input within the SARADC’s 1 µs sampling rate. Current is sourced
from the IVC0.0 or IVC0.1 pins, creating a voltage drop at the pin and the ADC input. A simplified diagram of a
single channel of the IVC circuitry is shown in Figure 25.2.
VDD
VOUT
to
SARADCn
IVCn.x
IIN
VSS
Figure 25.2. Simplified IVC Circuit Diagram
The IVC module has selectable full-scale current ranges of 1 mA to 6 mA, configurable in 1 mA steps. The transfer
function of the IVC module is a curve that is 0 V with a 0 mA input, and 1.65 V at full scale. It is important to note
that the transfer function of the IVC module has more nonlinearity than the ADC, but the transfer function of the two
channels will tend to be reasonably well-matched on a given device. The nonlinearity of the transfer function
appears as an INL error in the ADC’s output.
Table 25.1. IVC0 Input Channels
IVC0 Input
IVC0 Input Description
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
IVC0.0
Channel 0
PB0.7
PB0.4
Reserved
IVC0.1
Channel1
PB0.8
PB0.5
Reserved
25.3. Configuration
Each of the two IVC channels are independently enabled using the C0EN and C1EN bits in the CONTROL register.
The input range for the channels are also independently selectable, using the IN0RANGE and IN1RANGE fields.
The following steps describe how to configure and use an IVC channel:
1. Select the desired IVC channel as an input in the SARADCn module.
2. Configure the input range of the IVC channel using the INxRANGE field in the CONTROL register.
3. Enable the IVC channel using the CxEN bit in the CONTROL register.
4. Begin converting data with the SARADCn module.
482
Rev. 1.0
25.4. IVC0 Registers
This section contains the detailed register descriptions for IVC0 registers.
31
30
Name
C0EN
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
Type
RW
RW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
IN1RANGE
Reserved
Bit
C1EN
Register 25.1. IVC0_CONTROL: Module Control
IN0RANGE
Type
R
RW
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
IVC0_CONTROL = 0x4004_4000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 25.2. IVC0_CONTROL Register Bit Descriptions
Bit
Name
31
C1EN
Function
Converter 1 Enable.
0: Disable IVC channel 1.
1: Enable IVC channel 1.
30
C0EN
Converter 0 Enable.
0: Disable IVC channel 0.
1: Enable IVC channel 0.
29:7
Reserved
6:4
IN1RANGE
Must write reset value.
Input 1 Range.
These bits dictate the input range for IVC channel 1. The output voltage at the fullscale input current is 1.65 V.
000: Input range is 0-6 mA.
001: Input range is 0-5 mA.
010: Input range is 0-4 mA.
011: Input range is 0-3 mA.
100: Input range is 0-2 mA.
101: Input range is 0-1 mA.
110-111: Reserved.
3
Reserved
Must write reset value.
Rev. 1.0
483
Current-to-Voltage Converter (IVC0)
SiM3U1xx/SiM3C1xx
Current-to-Voltage Converter (IVC0)
SiM3U1xx/SiM3C1xx
Table 25.2. IVC0_CONTROL Register Bit Descriptions
Bit
Name
2:0
IN0RANGE
Function
Input 0 Range.
These bits dictate the input range for IVC channel 0. The output voltage at the fullscale input current is 1.65 V.
000: Input range is 0-6 mA.
001: Input range is 0-5 mA.
010: Input range is 0-4 mA.
011: Input range is 0-3 mA.
100: Input range is 0-2 mA.
101: Input range is 0-1 mA.
110-111: Reserved.
484
Rev. 1.0
25.5. IVC0 Register Memory Map
IVC0_CONTROL Register Name
ALL Address
0x4004_4000
ALL | SET | CLR Access Methods
Bit 31
C1EN
Bit 30
C0EN
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Reserved
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
IN1RANGE
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
IN0RANGE
Bit 1
Bit 0
Table 25.3. IVC0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
485
Current-to-Voltage Converter (IVC0)
SiM3U1xx/SiM3C1xx
Low Power Oscillator (LPOSC0)
SiM3U1xx/SiM3C1xx
26. Low Power Oscillator (LPOSC0)
This section describes the Low Power Oscillator (LPOSC) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the LPOSC block, which is used by all device families covered in this
document.
26.1. Low Power Oscillator Features
The Low Power Oscillator has the following features:
20
MHz and divided 2.5 MHz frequencies available for the AHB clock.
starts and stops as needed.
Automatically
LPOSCn Module
Divided LPOSCn clock
Low Power
Oscillator
LPOSCn clock
Automatic Start/
Stop Control
Figure 26.1. Low Power Oscillator Block Diagram
486
Rev. 1.0
26.2. Operation
The Low Power Oscillator is the default AHB oscillator and enables or disables automatically, as needed. The
power consumption of this oscillator is listed in the electrical specifications of the device data sheet.
The default output frequency of this oscillator is factory calibrated to 20 MHz, and a divided 2.5 MHz version is also
available to use as an AHB clock source. More information on the clocks available to the device can be found in the
clock control description.
Rev. 1.0
487
Low Power Oscillator (LPOSC0)
SiM3U1xx/SiM3C1xx
Low Power Oscillator (LPOSC0)
SiM3U1xx/SiM3C1xx
26.3. LPOSC0 Registers
This section contains the detailed register descriptions for LPOSC0 registers.
Register 26.1. LPOSC0_OSCVAL: Low Power Oscillator Output Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
OSCVAL
Type
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
Register ALL Access Address
LPOSC0_OSCVAL = 0x4004_1000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 26.1. LPOSC0_OSCVAL Register Bit Descriptions
Bit
Name
Function
31:4
Reserved
Must write reset value.
3:0
OSCVAL
Low Power Oscillator Output Value.
This read-only field is the factory-calibrated output frequency value for the low
power oscillator.
488
Rev. 1.0
X
26.4. LPOSC0 Register Memory Map
LPOSC0_OSCVAL Register Name
ALL Address
0x4004_1000
ALL | SET | CLR Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Reserved
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OSCVAL
Bit 1
Bit 0
Table 26.2. LPOSC0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
489
Low Power Oscillator (LPOSC0)
SiM3U1xx/SiM3C1xx
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
27. Low Power Timer (LPTIMER0)
This section describes the Low Power Timer (LPTIMER) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the LPTIMER block, which is used by all device families covered in this
document.
27.1. Low Power Timer Features
The Low Power Timer includes the following features:
Runs
on RTC0TCLK or an external source (rising or falling edge).
and compare threshold-match detection, which can generate an interrupt, reset the timer, or
wake the device from low power modes.
Timer reset on threshold-match allows square-wave generation at variable output frequency.
Overflow
LPTIMERn Module
DATA
Compare
Threshold
LPTnT0
Output Control
LPTnT1
LPTnT2
Low Power Timer
LPTnT3
compare or overflow events
LPTnT15
RTCn
Module
RTC0TCLK
Figure 27.1. Low Power Timer Block Diagram
490
Rev. 1.0
LPTIMERn_OUT
27.2. Clocking
The Low Power Timer (LPTIMER) module runs from the RTC0 timer clock (RTC0TCLK), allowing the LPTIMER to
operate even if the AHB and APB clocks are disabled. When writing and reading registers, a bit or field may take 3
APB and 2 RTC0TCLK clocks to update to a written value.
The LPTIMER counter can increment using one of two clock sources: RTC0TCLK, or rising or falling edges of an
external signal.
27.2.1. Clock Input
The LPTIMER timer can use the RTC timer clock (RTC0TCLK) as its input clock. The RTC0TCLK clock is
configurable in the RTC0 module as either the RTC0 crystal oscillator (RTC0OSC), an external CMOS clock, or the
internal low frequency oscillator (LFOSC0).
27.2.2. External Signal
The LPTIMER module can select one of four external signals as its input clock using the EXTSEL field. The timer
can increment on rising, falling, or both edges of the selected external input, controlled by the CMD field. These
inputs are synchronized to RTC0TCLK, so they must be high or low for two rising RTC0TCLK edges. Figure 27.2
illustrates the external input signal timing. The external trigger sources available to the LPTIMER vary by package
and are defined in Table 27.1.
RTC0TCLK
LPT0Tx
2 rising edges
Figure 27.2. External Input Clock Synchronization Timing
Table 27.1. LPTIMER0 Triggers
LPTIMER0
Trigger
LPTIMER0 Trigger
Description
SiM3U1x7/C1x7
Pin Name
SiM3U1x6/C1x6
Pin Name
SiM3U1x4/C1x4
Pin Name
LPT0T0
External Trigger Source
PB3.2
PB3.2
PB3.0
LPT0T1
External Trigger Source
PB3.8
PB3.8
PB3.1
LPT0T2
External Trigger Source
PB3.9
PB3.9
PB3.2
LPT0T3
Internal Trigger Source
Comparator 0 output
Rev. 1.0
491
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
27.3. Configuring the Timer
The Low Power Timer is an up-counter that has a compare event and an overflow event. Firmware can access the
timer and compare values indirectly through the DATA register. Note that the RUN bit in the CONTROL register
must be set to 1 to allow writes of other bit in the LPTIMER block.
interrupt
generated
on overflow
0xFFFF
Internal Compare Threshold
interrupt
generated
on compare
Internal Timer
0x0000
Figure 27.3. Low Power Timer Operation
To write a value to the internal timer or compare thresholds:
1. Write the desired new value to DATA.
2. Set the TMRSET or CMPSET bit to set the timer or compare threshold, respectively.
3. Poll on the TMRSET or CMPSET bit to determine when the operation completes.
To read the current value of the timer or compare threshold:
1. Set the TMRCAP or CMPCAP bit to transfer the value from the internal timer or compare threshold to
DATA.
2. Poll on the TMRCAP or CMPCAP bit to determine when the operation completes.
3. Read the DATA register.
Once the LPTIMER timer is configured as desired, firmware can stop and start the timer using the RUN bit. RUN
must be set to 1 when changing any register values.
27.4. Interrupts
The LPTIMER module has two sources that can cause an interrupt: overflow and compare events. The overflow
interrupt (OVFI) flag indicates when the timer overflows and can generate an interrupt when OVFIEN is set to 1.
Hardware sets the compare interrupt (CMPI) flag when the timer value matches the value in the internal compare
threshold and can generate an interrupt if CMPIEN is set to 1.
Whenever hardware sets the OVFI and CMPI flags, firmware should clear the appropriate flag and poll until it reads
back as zero.
492
Rev. 1.0
27.5. Output
The LPTIMER module has an output (OUT) that can be toggled on an overflow or compare event. This output can
be connected to a physical pin using the device port configuration module. Table 27.2 shows a summary of the
output behavior.
Table 27.2. Low Power Timer Output Modes
OVFTMD Bit
Value
CMPTMD Bit
Value
Output Mode
0
0
never toggles
0
1
toggles on compare events only
1
0
toggles on overflow events only
1
1
toggles on both overflow and compare events
27.6. Automatic Reset
In addition to potentially generating an interrupt or toggling the LPTIMER output, the compare event can also
automatically reset the timer to zero. This automatic reset mode is enabled by setting CMPRSTEN to 1.
27.7. Debug Mode
Firmware can set the DBGMD bit to force the LPTIMER module to halt on a debug breakpoint. Clearing the
DBGMD bit forces the module to continue operating while the core halts in debug mode.
Rev. 1.0
493
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
27.8. LPTIMER0 Registers
This section contains the detailed register descriptions for LPTIMER0 registers.
Register 27.1. LPTIMER0_CONTROL: Module Control
26
Name
Type
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
17
16
RW
0
0
0
0
0
4
3
2
1
0
RW
RW
0
0
0
0
TMRSET
RW
0
18
RW
R
0
19
RW
Type
0
20
RW
Reserved
0
21
R
Name
Reset
22
RW
TMRCAP
R
23
Reserved
CMPSET
RW
24
CMPCAP
Reserved
25
OVFIEN
27
CMPIEN
28
OVFTMD
29
CMPTMD
30
CMPRSTEN
31
DBGMD
Bit
RUN
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
EXTSEL
Reserved
CMD
RW
RW
R
RW
0
0
0
0
0
0
0
0
Register ALL Access Address
LPTIMER0_CONTROL = 0x4003_8000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 27.3. LPTIMER0_CONTROL Register Bit Descriptions
Bit
Name
31
RUN
Function
Timer Run Control and Compare Threshold Enable.
This bit controls the timer operation and compare threshold. Note that this bit must
be set to 1 in order to write any LPTIMER registers.
0: Stop the timer and disable the compare threshold.
1: Start the timer running and enable the compare threshold.
30
DBGMD
Low Power Timer Debug Mode.
0: The Low Power Timer module will continue to operate while the core is halted in
debug mode.
1: A debug breakpoint will cause the Low Power Timer module to halt.
29:25
Reserved
24
CMPRSTEN
Must write reset value.
Timer Compare Event Reset Enable.
0: Timer compare events do not reset the timer.
1: Timer compare events reset the timer.
Notes:
1. When writing to any of the LPTIMER registers, the CONTROL.RUN bit must be set to 1.
2. When writing and reading registers, a bit or field may take 3 APB and 2 RTC0TCLK cycles to update to a written value.
494
Rev. 1.0
Table 27.3. LPTIMER0_CONTROL Register Bit Descriptions
Bit
Name
Function
23:20
Reserved
Must write reset value.
19
CMPTMD
Timer Compare Event Toggle Mode .
0: Timer compare events do not toggle the Low Power Timer output.
1: Timer compare events toggle the Low Power Timer output.
18
OVFTMD
Timer Overflow Toggle Mode.
0: Timer overflows do not toggle the Low Power Timer output.
1: Timer overflows toggle the Low Power Timer output.
17
CMPIEN
Timer Compare Event Interrupt Enable.
0: Disable the timer compare event interrupt.
1: Enable the timer compare event interrupt.
16
OVFIEN
Timer Overflow Interrupt Enable.
0: Disable the timer overflow interrupt.
1: Enable the timer overflow interrupt.
15:12
Reserved
Must write reset value.
11
CMPCAP
Timer Comparator Capture.
Writing a 1 to CMPCAP initiates a read of the internal comparator register into the
DATA register. This field is automatically cleared by hardware when the operation
completes and does not need to be cleared by software.
10
CMPSET
Timer Comparator Set.
Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal timer
comparator register. This field is automatically cleared by hardware when the copy
is complete and does not need to be cleared by software.
9
TMRCAP
Timer Capture.
Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA register. This field is automatically cleared by hardware when the operation completes
and does not need to be cleared by software.
8
TMRSET
Timer Set.
Writing a 1 to TMRSET initiates a copy of the value from the DATA register into the
internal timer register. This field is automatically cleared by hardware when the copy
is complete and does not need to be cleared by software.
Notes:
1. When writing to any of the LPTIMER registers, the CONTROL.RUN bit must be set to 1.
2. When writing and reading registers, a bit or field may take 3 APB and 2 RTC0TCLK cycles to update to a written value.
Rev. 1.0
495
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Table 27.3. LPTIMER0_CONTROL Register Bit Descriptions
Bit
Name
7:4
EXTSEL
Function
External Trigger Source Select.
0000: Select external trigger LPTnT0.
0001: Select external trigger LPTnT1.
0010: Select external trigger LPTnT2.
0011: Select external trigger LPTnT3.
0100: Select external trigger LPTnT4.
0101: Select external trigger LPTnT5.
0110: Select external trigger LPTnT6.
0111: Select external trigger LPTnT7.
1000: Select external trigger LPTnT8.
1001: Select external trigger LPTnT9.
1010: Select external trigger LPTnT10.
1011: Select external trigger LPTnT11.
1100: Select external trigger LPTnT12.
1101: Select external trigger LPTnT13.
1110: Select external trigger LPTnT14.
1111: Select external trigger LPTnT15.
3:2
Reserved
1:0
CMD
Must write reset value.
Count Mode.
00: The timer is free running mode on the RTC0 timer clock (RTC0TCLK).
01: The timer is incremented on the rising edges of the selected external trigger
(LPTnTx).
10: The timer is incremented on the falling edges of the selected external trigger
(LPTnTx).
11: The timer is incremented on both edges of the selected external trigger (LPTnTx).
Notes:
1. When writing to any of the LPTIMER registers, the CONTROL.RUN bit must be set to 1.
2. When writing and reading registers, a bit or field may take 3 APB and 2 RTC0TCLK cycles to update to a written value.
496
Rev. 1.0
Register 27.2. LPTIMER0_DATA: Timer and Comparator Data
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
DATA
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LPTIMER0_DATA = 0x4003_8010
Table 27.4. LPTIMER0_DATA Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
DATA
Function
Must write reset value.
Timer and Comparator Data.
This field provides read and write access to both the internal timer and compare
registers.
Notes:
1. When writing to any of the LPTIMER registers, the CONTROL.RUN bit must be set to 1.
2. When writing and reading registers, a bit or field may take 3 APB and 2 RTC0TCLK cycles to update to a written value.
Rev. 1.0
497
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Register 27.3. LPTIMER0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
OVFI
Reset
CMPI
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
LPTIMER0_STATUS = 0x4003_8020
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 27.5. LPTIMER0_STATUS Register Bit Descriptions
Bit
Name
31:2
Reserved
1
CMPI
Function
Must write reset value.
Timer Compare Event Interrupt Flag.
Hardware sets this flag to 1 when the timer equals the compare threshold. Firmware
must clear this flag and poll until it reads back as zero.
0
OVFI
Timer Overflow Interrupt Flag.
Hardware sets this flag to 1 when a timer overflow occurs. Firmware must clear this
flag and poll until it reads back as zero.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
2. When writing to any of the LPTIMER registers, the CONTROL.RUN bit must be set to 1.
3. When writing and reading registers, a bit or field may take 3 APB and 2 RTC0TCLK cycles to update to a written value.
498
Rev. 1.0
27.9. LPTIMER0 Register Memory Map
LPTIMER0_STATUS LPTIMER0_DATA LPTIMER0_CONTROL Register Name
0x4003_8020
ALL Address
0x4003_8010
0x4003_8000
ALL | SET | CLR
Access Methods
ALL
ALL | SET | CLR
Bit 31
RUN
Bit 30
DBGMD
Bit 29
Bit 28
Reserved
Bit 27
Bit 26
Bit 25
CMPRSTEN
Bit 24
Reserved
Bit 23
Bit 22
Reserved
Bit 21
Bit 20
CMPTMD
Bit 19
OVFTMD
Bit 18
CMPIEN
Bit 17
Reserved
OVFIEN
Bit 16
Bit 15
Bit 14
Reserved
Bit 13
Bit 12
CMPCAP
Bit 11
CMPSET
Bit 10
TMRCAP
Bit 9
TMRSET
Bit 8
DATA
Bit 7
Bit 6
EXTSEL
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
CMPI
Bit 1
CMD
OVFI
Bit 0
Table 27.6. LPTIMER0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
499
Low Power Timer (LPTIMER0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28. Enhanced Programmable Counter Array (EPCA0)
This section describes the Enhanced Programmable Counter Array (EPCA) module, and is applicable to all
products in the following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the EPCA block, which is used by all device families covered in this
document.
28.1. Enhanced Programmable Counter Array Features
The Enhanced PCA module is a multi-purpose counter array with features designed for motor control applications.
The EPCA module includes:
Three
sets of channel pairs (six channels total) capable of generating complementary waveforms.
and edge-aligned waveform generation.
Programmable dead times that ensure channel pairs are never both active at the same time.
Programmable clock divisor and multiple options for clock source selection.
Waveform update scheduling.
Option to function while the core is inactive.
Multiple synchronization triggers and outputs to synchronize with other blocks in the device, such as the
SARADCs.
Pulse-Width Modulation (PWM) waveform generation.
High-speed square wave generation.
Input capture mode.
DMA capability for both input capture and waveform generation.
PWM generation halt input.
Center-
500
Rev. 1.0
EPCAn Module
Counter Upper
Limit Update
synchronization
signal on overflow
Counter Upper
Limit
EPCAnT0
EPCAnT1
High Drive Port
Mapping
EPCA Counter
EPCAnT2
EPCAnT3
PB_HDKill
TIMER0 Low overflow
EXTOSCn Clock
APB Clock
CH0
XPH5
HD_CEX0
CH1
YPH5
HD_CEX1
CH2
XPH4
HD_CEX2
Channel Status
Clock
Divider
ECI
Phase X and
Phase Y Delays
DTARGET
DMA Control
Standard Port
Mapping
EPCAn_CH0 Channel
EPCAn_CH1 Channel
Channel Mode
EPCAn_CHx Channel
Channel
Mode
PWM N-Bit
Mode
Channel
Mode
Compare Value
PWM Value
N-Bit
Mode
Compare
CHx
Update
Compare Value
PWM
N-Bit
Mode
Compare
Output
ControlValue
Update
Compare Value
Compare
Value
Output
Control
Update
Channel
Input
Control
Output Control
Channel Input
XPHx
Control
Channel Input
YPHx
Control
CH0
XPH2
SD_CEX0
CH1
YPH2
SD_CEX1
CH2
XPH1
SD_CEX2
Figure 28.1. EPCA Block Diagram
Rev. 1.0
501
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.2. Module Overview
The Enhanced Programmable Counter Array (EPCA) provides flexible timer/counter functionality. The EPCA
consists of a dedicated 16-bit counter/timer and multiple (up to six) 16-bit capture/compare channels
(EPCA0_CHx). All channels trigger or capture based on the shared 16-bit counter/timer, so the channels are
inherently synchronized. The counter/timer is a 16-bit up counter with a programmable upper count limit. The
counter starts at 0 and counts continuously from zero to the upper limit. Each channel includes a data register that
can compare against the counter or capture the state of the counter based on a set of programmable conditions.
Each channel has its own associated output lines and may be configured to operate independently of the others in
one of six modes: Edge-Aligned PWM, Center-Aligned PWM, High-Frequency / Square Wave, Timer / Capture, nbit Edge-Aligned PWM, or Software Timer. The output lines may be single (one per channel, CHx) or differential (a
complimentary pair per channel, XPHx and YPHx). These signals are then mapped to the HD_CEXx and
STD_CEXx EPCA signals based on the STDOSEL and HDOSEL fields.
The RUN bit starts or stops the EPCA counter, but there are also additional controls that can halt the counter. The
counter clock is normally suspended when the core halts to save power. The DBGMD bit in the CONTROL register
controls whether the EPCA counter runs while the core is halted in debug mode. The EPCA also has an active-low
external signal input, PB_HDKill, which can be configured to enter the “safe state” on PB4 pins by setting the
SSMDEN bit in the PBHD0_PBSS register. In turn, when SSMDEN is set, the EPCA counter will halt and an
interrupt can be generated. To resume operation, the PB_HDKill signal must be de-asserted and the SSMDEN bit
must be cleared.
The EPCA additionally has up to four external trigger signals that can start the counter. The STSEL field in the
MODE register determines which of the trigger sources can start the counter. STESEL selects the active polarity of
the external signal, and setting STEN to 1 enables the external signal to start the counter. Once the counter is
running, the external trigger will not stop the counter.
Three different events can change a channel output or cause a capture. An overflow/limit event occurs when the
EPCA counter (COUNTER) is equal to the upper limit (LIMIT). A capture/compare event occurs whenever a
channel’s capture/compare register (CCAPV) matches the current EPCA counter value. An intermediate overflow
event can only occur in n-bit PWM mode and occurs when the channel’s n-bit capture/compare range matches the
EPCA counter.
To facilitate counter and channel updates while the counter continues to run, the counter upper limit register
(LIMIT) and channel compare/capture register (CCAPV) have update registers (LIMITUPD and CCAPVUPD,
respectively). Firmware can write new values to the LIMITUPD and CCAPVUPD registers without modifying the
current EPCA cycle. The hardware will load these values into the LIMIT and CCAPV registers when the next
counter overflow/limit event occurs, and the module UPDCF and channel CUPDCF flags indicate when an update
operation completes. Firmware can set the NOUPD bit to 1 to prevent updates from occurring.
502
Rev. 1.0
28.3. Clocking
The clock input for the counter/timer is selected by the CLKSEL field in the MODE register as shown in
Figure 28.2.
CLKSEL
CLKDIV
TIMER0 Low overflow
EXTOSCn
APB Clock
Clock Divider
Counter
Clock
ECI
Figure 28.2. Clock Source Selection
The selected clock is passed through a divide-by-n clock divider where n can be between 1 and 1024. The CLKDIV
field sets the clock divider for the selected clock before it drives the 16-bit counter/timer.
All non-APB clock sources must be synchronized with the APB clock, so the maximum possible operating speed
using these sources is one-half the APB frequency, if not slower.
28.3.1. APB Clock
When the APB clock signal is selected as the counter clock source, the EPCA counter clock divider will use the
APB clock source defined by the device clock control module. Selecting the APB clock provides the fastest clock
source for the module.
28.3.2. External Clock (EXTOSCn)
When the external clock is selected as the counter clock source, the counter will run from the external clock source
(EXTOSCn), regardless of the clock selection of the core. The external clock source is synchronized to the
selected core clock in this mode. In order to guarantee that the external clock transitions are recognized by the
device, the external clock signal must be high or low for at least one APB clock period. This limits the maximum
frequency of an external clock in this mode to one-half the APB clock.
28.3.3. TIMER0 Low Overflow
The EPCA module can select the TIMER0 module low timer overflows as its clock source. TIMER0 can operate in
either 32-bit or 16-bit mode and still provide the clock for the EPCA clock divider. The maximum speed for the
TIMER0 low overflows as an EPCA counter clock source is one-half the APB clock.
28.3.4. External Clock Input (ECI)
When the external clock input (ECI) is selected as the EPCA clock source, the clock divider decrements on falling
edges or both rising and falling edges of the pin. The ECI pin is synchronized to the selected AHB clock in this
mode. The maximum clock rate for the ECI external clock input is the APB divided by 4.
28.3.5. Clock Divider
The clock divider provides a flexible time base for the EPCA counter. The divider starts at one-half the CLKDIV
value and decrements to 0. Using this method, the divider counts the number of input clocks until the next counter
clock edge (either rising or falling) rather than whole counter clock periods.
The current value of the divider can be read and written using the DIV field in the MODE register. This allows
access during debugging to observe module events at the various EPCA clock edges rather than stepping through
a large number of APB clocks. Firmware should always write to the CLKDIV field to modify the divider value.
The DIVST bit displays the current output phase of the clock divider.
Rev. 1.0
503
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.4. Interrupts
The EPCA module has one interrupt vector and multiple interrupt sources within the module.
The module has two interrupt sources: a counter overflow/limit and the halt input. The OVFIEN bit enables the
counter overflow/limit interrupt, which occurs when counter (COUNTER) equals the upper limit (LIMIT) and resets
to 0. The OVFI interrupt flag indicates when an counter overflow/limit event occurs. The halt input, PB_HDKill, must
be enabled (HALTEN = 1) and enabled as an interrupt source (HALTIEN = 1) in order to generate an interrupt. The
HALTI interrupt flag indicates that an external signal input interrupt has occurred. The flag is cleared after a reset
and set following the assertion of the halt input, if enabled.
Each channel (CHx) has a compare/capture interrupt flag (CxCCI) and an intermediate overflow flag (CxIOVFI).
These interrupts can be enabled in the channel registers (CCIEN for capture/compare, CIOVFIEN for intermediate
overflow).
Firmware can check the source of the EPCA interrupt by checking the appropriate flags in the interrupt service
routine.
28.5. Outputs
The EPCA module has up to six module outputs (CEXx) that can be routed to physical pins by configuring the
device port configuration module.
Each EPCA capture/compare channel has two independent output modes: single and differential. In single output
mode, the channel has one CHx output. In differential mode, the channel has two XPHx and YPHx outputs. The
mapping of these channel outputs to the EPCA module outputs (HD_CEXx and STD_CEXx) is determined by the
HDOSEL and STDOSEL fields.
The HDOSEL field determines the output mapping for high drive ports, and the STDOSEL field determines the
mapping for standard port banks. The mappings are selected such that all six potential channels can operate in
differential mode at the same time: three (0, 1, and 2) are available for the standard port banks, and three (3, 4, and
5) are available for the high drive ports.
Table 28.1 shows the output mapping for the high drive ports, and shows the output mapping for standard ports.
Table 28.1. High Drive Output Mapping
EPCA Output
504
HDOSEL Value
0
1
2
3
HD_CEX0
XPH3
CH2
CH1
CH0
HD_CEX1
YPH3
CH3
CH2
CH1
HD_CEX2
XPH4
XPH4
CH3
CH2
HD_CEX3
YPH4
YPH4
CH4
CH3
HD_CEX4
XPH5
XPH5
XPH5
CH4
HD_CEX5
YPH5
YPH5
YPH5
CH5
Rev. 1.0
Table 28.2. Standard Output Mapping
EPCA Output
STDOSEL Value
0
1
2
3
STD_CEX0
CH0
CH0
CH0
XPH0
STD_CEX1
CH1
CH1
CH1
YPH0
STD_CEX2
CH2
CH2
XPH1
XPH1
STD_CEX3
CH3
CH3
YPH1
YPH1
STD_CEX4
CH4
XPH2
XPH2
XPH2
STD_CEX5
CH5
YPH2
YPH2
YPH2
Note: The COUTST (and optionally XPHST, YPHST, and ACTIVEPH) bit determines the starting state of the channel output. If
the starting state is active, this means the channel could be sitting in an active state for some time while firmware finishes initializing the module and starts the counter. If the output is connected to a transistor where this behavior is undesireable, firmware can initialize the counter to a mid-range value and the outputs with an inactive value. This will ensure
that any sensitive external circuits will not be damaged.
28.5.1. Single Output Mode
When a channel operates in single output mode, the COUTST bit in the EPCA channels determines the polarity of
the output. This value should be set when the counter is not running to ensure predictable operation. Hardware
sets the COUTST bit on the rising edges of the APB clock to reflect the current output state of the channel.
Figure 28.3 shows an EPCA channel single output timing diagram.
EPCA Clock
COUNTER
0x0002
0x0003
0x0000
0x0001
LIMIT
0x0003
CCAPV
0x0006
0x0002
0x0003
0x0000
CHx
COUTST
Figure 28.3. Example Channel Single Output Timing Diagram (Toggle Mode)
The CHx output can toggle, set, or clear on an overflow/limit, compare, or intermediate overflow event. In addition,
the output can ignore these events and stay at its previous value. The COSEL field in the channel MODE register
determines the CHx output behavior. This field allows firmware to modify the behavior of the CHx output without
changing the configuration of the channel, interrupting the counter, or changing the port configuration.
28.5.2. Differential Output Mode
A channel additionally generates two synchronous outputs when operating in differential mode (DIFGEN = 1).
The YPHST and XPHST bits in the EPCA channels determine the polarity of the outputs. These values should be
set when the counter is not running to ensure predictable operation. These bits can be read at any time to
determine the current states of the outputs.
Rev. 1.0
505
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
In addition, the differential outputs have programmable dead-time delays (AHB clocks) that prevent both channels
from being active at the same time. The X delay time (DTIMEX) starts when the XPHx output switches to its
inactive state. The YPHx output then switches to its active state when the time expires, and the Y delay time
(DTIMEY) behaves similarly. These delay times are global for all channels.
The channel ACTIVEPH bit indicates which output is currently active. The active channel can be asserted or
deasserted pending the dead time delay timeout.
Figure 28.4 shows an EPCA channel differential output timing diagram.
EPCA Clock
COUNTER
0x0006
0x0007
0x0000
0x0001
LIMIT
0x0007
CCAPV
0x0006
0x0002
0x0003
0x0004
CHx
XPHx
YPHx
TDTIMEX
ACTIVEPH
X active
TDTIMEY
Y active
X active
Figure 28.4. Example Channel Differential Output Timing Diagram
The output behavior of the XPHx and YPHx outputs depends on the behavior of the CHx output. These phase
outputs will toggle as long as CHx is toggling. If the COSEL field is set such that the CHx output is no longer
toggling (set, clear, or ignore), the XPHx and YPHx outputs will not change state. As long as the hardware control
of the CHx output remains static, firmware can manually stimulate the XPHx and YPHx outputs by writing COUTST
to different states and directly controlling the CHx output.
28.5.3. Synchronization Signal
In addition to the CHx, XPHx, and YPHx outputs, the EPCA module can generate a synchronization signal for use
by other modules on the device (SARADC0, SARADC1, TIMER0, and TIMER1). This signal can pulse when a
counter overflow/limit (OVFSEN = 1), channel intermediate overflow (CIOVFSEN = 1), or channel capture/compare
(CCSEN = 1) event occurs.
506
Rev. 1.0
28.6. Triggers
The EPCA supports four trigger sources. The selections for the trigger are made in the STSEL, STESEL and STEN
fields of the CONTROL register, The trigger sources for SiM3U1xx/SiM3C1xx devices are defined in Table 28.3.
Table 28.3. EPCA0 Triggers
EPCA0
Trigger
EPCA0 Trigger Description
Internal Signal
EPCA0T0
Internal Trigger Source
Comparator 0 output
EPCA0T1
Internal Trigger Source
Comparator 1 output
EPCA0T2
Internal Trigger Source
Timer 0 High Overflow output
EPCA0T3
Internal Trigger Source
Timer 1 High Overflow output
To use a trigger:
1. Set up the desired trigger source module or channel.
2. Select the trigger source using the STSEL field.
3. Set the polarity of the trigger using the STESEL bit.
4. Enable the trigger (STEN = 1).
5. Set up the desired EPCA counter and channel settings.
6. Start the EPCA counter by setting RUN to 1.
The EPCA counter will start running when the selected trigger source meets the criteria set by the STESEL polarity.
The counter will then continue to run regardless of the state of the trigger source.
Rev. 1.0
507
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.7. Operational Modes
The EPCA module has six operational modes that each channel can independently select: Edge-Aligned PWM,
Center-Aligned PWM, High-Frequency/Square Wave, Timer/Capture, n-bit Edge-Aligned PWM, and Software
Timer modes. The CMD bits select the channel operational mode.
The EPCA counter is 16 bits and counts in full EPCA clock cycles. The channel CCAPV registers are 18 bits and
represent half EPCA clock cycles. To match an counter value, the CCAPV field should be written with double the
counter value. The CCAPV LSB provides timing resolution to one half-clock counter cycle. The additional 18th bit
of the CCAPV register allows the channel outputs to create 0-100% duty cycles (0x00000 is 0% and 0x20000 is
100% duty cycle).
COUNTER
CCAPV
allows for 100% duty
cycle
counts half
clocks
Figure 28.5. EPCA Counter and Channel Compare/Capture Registers
This section discusses the channel behavior in each of these modes in detail.
508
Rev. 1.0
28.7.1. Edge-Aligned Pulse Width Modulation (PWM) Mode
In edge-aligned PWM mode (CMD = 0), the 18-bit capture/compare register (CCAPV) defines the number of EPCA
half clocks for the inactive time of the PWM signal. A capture/compare event occurs when the counter matches the
register contents, and the output will change from the initial state set by COUTST depending on the selected
COSEL value (typically 00b for toggle). An overflow/limit event occurs when the counter reaches the LIMIT value
and resets to 0, and CHx will again change depending on the COSEL value. To output a varying duty cycle,
firmware can write to the CCAPVUPD register, which hardware will automatically load into the channel’s CCAPV
register on the next counter overflow/limit if the module register update inhibit (NOUPD) is cleared to 0.
Assuming that the inactive and initial state of the output is low and COSEL is set to toggle, the CHx output duty
cycle in edge-aligned PWM mode is shown in Equation 28.1. No output pulse is generated if CCAPV is 0, and
100% duty cycle results from CCAPV set to 0x20000. The resulting XPHx and YPHx timing also depends on the
dead-time delay values.
Figure 28.6 shows an example edge-aligned PWM timing diagram.
  LIMIT + 1   2  – CCAPV
Duty Cycle = ------------------------------------------------------------------------ LIMIT + 1   2
Equation 28.1. Edge-Aligned PWM Duty Cycle
Because CCAPV is given in half clocks, an odd CCAPV value results in the CHx output changing state at the midcycle edge of the EPCA clock.
EPCA Clock
COUNTER
0x0003
0x0000
0x0001
0x0002
LIMIT
0x0003
CCAPV
0x00003
capture/compare
CHx
0x0003
0x0000
0x0001
overflow/limit
PWM waveform
XPHx
YPHx
TDTIMEX
ACTIVEPH
X active
TDTIMEY
Y active
X active
Y active
Figure 28.6. Example Edge-Aligned PWM Timing Diagram
Rev. 1.0
509
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.7.2. Center-Aligned Pulse Width Modulation (PWM) Mode
In center-aligned PWM mode (CMD = 1), a channel generates a PWM waveform symmetric about the counter’s
overflow/limit event defined by the LIMIT field. Multiple channels in an array configured in this mode will each have
PWM waveforms which are all symmetric about the same center-pulse points (counter equal to zero).
LIMIT
COUNTER
CH0
CH1
CH2
CCAPV
2
LIMIT –
CCAPV
2
Figure 28.7. Multiple Center-Aligned PWM Channels
The channel 18-bit capture/compare register (CCAPV) is used to generate two capture/compare events in one
counter cycle (0 to LIMIT). The first event occurs when the counter is equal to CCAPV divided by 2. The second
event occurs when the counter is equal to LIMIT minus CCAPV divided by 2. In the event of an odd value in
CCAPV, the hardware adds the extra half cycle to the capture/compare event following the counter overflow/limit
event.
Firmware can write to the channel’s CCAPVUPD register to update the waveform. Hardware will update the
CCAPV field with the CCAPVUPD value when the counter overflows from the upper limit to zero as long as the
update inhibit bit (NOUPD) is cleared to 0.
The COUTST (and optionally XPHST, YPHST, and ACTIVEPH) bit determines the starting state of the channel
output and should be set before starting the counter. If the starting state is active, this means the channel could be
sitting in an active state for some time while firmware finishes initializing the module and starts the counter. If the
output is connected to a transistor where this behavior is undesireable, firmware can initialize the counter to a midrange value and the outputs with an inactive value. This will ensure that any sensitive external circuits will not be
damaged.
Assuming that the active and initial state of the output is high and COSEL is set to toggle, the CHx output duty
cycle in center-aligned PWM mode is shown in Equation 28.2. No output pulse is generated if CCAPV is 0, and
100% duty cycle results when CCAPV (in half clocks) is set to a number of full clocks equal to or greater than
LIMIT. The resulting XPHx and YPHx timing also depends on the dead-time delay values.
Figure 28.8 shows an example center-aligned PWM timing diagram.
 LIMIT  2  – CCAPV
Duty Cycle = ----------------------------------------------------------LIMIT  2
Equation 28.2. Center-Aligned PWM Duty Cycle
510
Rev. 1.0
overflow/limit
capture/
compare
capture/
compare
EPCA Clock
COUNTER
0x0003
0x0000
0x0001
0x0002
LIMIT
0x0003
CCAPV
0x00003
CHx
0x0003
0x0000
0x0001
PWM waveform
XPHx
YPHx
TDTIMEX
ACTIVEPH
TDTIMEY
X active
Y active
X active
Figure 28.8. Example Center-Aligned PWM Timing Diagram
Rev. 1.0
511
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.7.3. High-Frequency / Square Wave Mode
High-frequency square-wave mode (CMD = 2) produces a 50% duty cycle waveform of programmable period on
the channel's CHx output. This mode provides a flexible way of creating square waves with a fast period. Each
half-period of the generated output clock can be as short as one counter clock period (two CCAPV half clocks) and
as long as 128 counter clock periods, programmable in half clock steps.
Bits [15:8] of the channel capture/compare register (CCAPV) contain the waveform half period in the number of half
EPCA clocks. The lower byte (bits [7:0]) is the calculated value compared to the counter. When a match occurs
between the lower byte and the counter, the hardware triggers a capture/compare event and automatically adds
the match value of the counter to the CCAPV[15:8] value to create a new compare value for the lower byte. An
overflow/limit event occurs when the counter reaches the upper limit defined by the LIMIT field. Firmware should
program the upper limit register to reset the counter at a (multiple of 128) - 1 to avoid undesired waveform edges.
Figure 28.9 shows how the hardware creates the waveform.
COUNTER
6
5
4
3
2
1
0
capture/compare event
comparator
phase comparator
CCAPV
7
6
5
4
3
2
1
FCLKIN
enable
Figure 28.9. High-Frequency Square Wave Waveform Generation
Firmware can update the frequency of the output by writing to the CCAPVUPD register. Hardware will
automatically load bits [15:8] of this register to the CCAPV register at the next counter overflow/limit event, if
possible (NOUPD = 0). The rest of the CCAPVUPD register (bits [17:16] and [7:0]) are ignored.
Assuming that the COSEL field for the channel is set to toggle, the resulting CHx output frequency in highfrequency square-wave mode is shown in Equation 28.3. A CCAPV[15:8] value of 1 is not valid, and a
CCAPV[15:8] value of 0 results in an output waveform half period of 128 counter clocks. The resulting XPHx and
YPHx timing also depends on the dead-time delay values.
Figure 28.10 shows an example high-frequency square wave mode timing diagram.
F EPCA
F CHx = ----------------------------------CCAPV[15:8]
Equation 28.3. High-Frequency Square Wave Output Frequency
512
Rev. 1.0
EPCA Clock
COUNTER
0x0002
0x0003
0x0004
0x0005
LIMIT
0x0006
0x0007
0x0008
0x007F
CCAPV
0x00306
CHx
0x0309
0x030C
0x030F
square waveform
XPHx
YPHx
TDTIMEX
ACTIVEPH
X active
TDTIMEY
Y active
X active
Y active
X active
Figure 28.10. Example High-Frequency Square Wave Mode Timing Diagram
Rev. 1.0
513
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.7.4. Timer / Capture Mode
In timer/capture mode (CMD = 3), the channel uses the CEXn line as an input signal that triggers a capture/
compare event and stores the counter state in the channel capture/compare register (CCAPV) in half clocks.
Firmware can configure the event to trigger on rising, falling, or both edges using the channel CPCAPEN and
CNCAPEN bits. Table 28.4 shows the capture edge configuration options.
Table 28.4. Capture Edge Configuration Options
CPCAPEN
CNCAPEN
Selected Edge
0
0
Capture disabled.
0
1
Capture on the falling edge.
1
0
Capture on the rising edge.
1
1
Capture on both edges.
The input CEXn signal must remain high or low for at least two APB clocks to be recognized by the hardware. The
capture occurs at the next EPCA clock edge.
Figure 28.11 shows an example timer/capture mode timing diagram.
EPCA Clock
COUNTER 0x013C
0x013D
0x013E
0x013F
LIMIT
CCAPV
0x0000
0x0001
0x013F
0x0005C
0x0027A
CEXx*
falling edge capture
*Note: CEXx must be high or low for 2 APB clock cycles.
Figure 28.11. Example Timer / Capture Mode Timing Diagram
514
Rev. 1.0
0x0002
28.7.5. N-bit Edge-Aligned Pulse Width Modulation (PWM) Mode
The n-bit edge-aligned PWM modes allow each channel to be independently configured to generate edge-aligned
PWM waveforms with a faster duty cycle than the counter. In n-bit edge-aligned PWM mode (CMD = 4), the leastsignificant n bits (set by PWMMD) of the counter define the number of full clocks of the PWM waveform. The
channel’s capture/compare register (CCAPV) defines the number of EPCA half clocks for the inactive time of the
PWM signal, and the higher order unused bits of CCAPV are ignored. A capture/compare event occurs when the nbit counter is equal to the number of half clocks defined by the CCAPV field. An intermediate overflow event occurs
when the counter overflows the n-bit range. A counter overflow/limit event occurs when the counter reaches the
upper limit (LIMIT) within the full 16-bit range. If one of the channels operates in n-bit mode, firmware should set
the counter’s upper limit as an even multiple of the n-bit boundary to ensure the channel’s output does not have
any irregular edges from the overflow/limit events.
intermediate
overflow
capture/
compare
overflow/limit and
intermediate
overflow
LIMIT
COUNTER
CH0
(n-bit mode)
CH1
(edge aligned
mode)
Figure 28.12. Multiple Edge-Aligned PWM Channels (N-bit and Edge Aligned)
Table 28.5 provides a list of the intermediate overflow, recommended upper limit values, and 100% duty cycle
values for each n-bit setting.
Rev. 1.0
515
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Table 28.5. N-bit Intermediate Overflow Values
PWMMD Value
N-bit PWM
Mode
Counter Intermediate
Overflow Value
(full clocks)
Recommended
Counter Upper Limit
(full clocks)
CCAPV 100% Duty
Cycle Value
(half clocks)
0
0-bit
0
any value
2
1
1-bit
1
(multiple of 2) - 1
4
2
2-bit
3
(multiple of 4) - 1
8
3
3-bit
7
(multiple of 8) - 1
16
4
4-bit
15
(multiple of 16) - 1
32
5
5-bit
31
(multiple of 32) - 1
64
6
6-bit
63
(multiple of 64) - 1
128
7
7-bit
127
(multiple of 128) - 1
256
8
8-bit
255
(multiple of 256) - 1
512
9
9-bit
511
(multiple of 512) - 1
1024
10
10-bit
1023
(multiple of 1024) - 1
2048
11
11-bit
2047
(multiple of 2048) - 1
4096
12
12-bit
4095
(multiple of 4096) - 1
8192
13
13-bit
8191
(multiple of 8192) - 1
16334
14
14-bit
16333
(multiple of 16334) - 1
32768
15
15-bit
32767
(multiple of 32768) - 1
65536
Firmware can write to the CCAPVUPD register to update the duty cycle, which hardware will automatically load
into the channel’s CCAPV register on the next counter overflow/limit event if the module register update inhibit
(NOUPD) is cleared to 0.
Assuming that the inactive and initial state of the output is low, COSEL is set to toggle, and the upper limit is set to
an even multiple, the CHx output duty cycle in n-bit edge-aligned PWM mode is shown in Equation 28.4. No output
pulse is generated if CCAPV is 0. The resulting XPHx and YPHx timing also depends on the dead-time delay
values.
Figure 28.13 shows an example n-bit edge-aligned PWM timing diagram.
n
 2  2  – CCAPV
Duty Cycle = ----------------------------------------------n
2 2
Equation 28.4. N-bit Edge-Aligned PWM Duty Cycle
Because CCAPV is given in half clocks, an odd CCAPV value results in the CHx output changing state at the midcycle edge of the EPCA clock.
516
Rev. 1.0
EPCA Clock
COUNTER
0x0005
0x0000
0x0001
0x0002
LIMIT
0x0005
CCAPV
0x00001
CHx
channel in 1-bit mode
0x0003
0x0004
0x0005
PWM waveform
XPHx
YPHx
TDTIMEX
ACTIVEPH
X active
TDTIMEY
Y
X active
Y
X active
Y
X active
Figure 28.13. Example N-bit Edge-Aligned PWM Timing Diagram
Rev. 1.0
517
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.7.6. Software Timer Mode
Software timer mode is a free-running mode with the CHx output unaffected by the counter or channel state.
Setting the COSEL field to 3 (output ignore events) enters software timer mode, regardless of the CMD field
setting. The counter overflow/limit, intermediate overflow, and capture/compare events can still be used to
generate interrupts, even though the channel output is disabled.
Figure 28.14 shows an example software timer mode timing diagram.
EPCA Clock
COUNTER 0x008F
LIMIT
CCAPV
0x0090
0x0091
0x0092
0x0000
0x0001
0x0002
0x0092
0x0007C
overflow/limit event
CHx
channel output is unaffected
Figure 28.14. Example Software Timer Mode Timing Diagram
518
Rev. 1.0
28.8. DMA Configuration and Usage
The EPCA supports two DMA channels: control and capture. The control requests move data from memory into the
counter and channel update registers to autonomously set up new waveform generation. Capture requests move
the counter capture data from the channel CCAPV register to memory.
The hardware can generate a DMA transfer request with a counter overflow/limit (OVFDEN = 1), channel
intermediate overflow (CIOVFDEN = 1), or channel capture event (CCDEN = 1). When these events are enabled
as a source for a DMA transfer, hardware automatically clears the flags associated with the request after the
transfer completes. A DMA transfer to service a control request will not clear a flag for a pending capture service
request.
The EPCA Module DMA configuration is shown in Figure 28.15.
SiM3xxxx
Address Space
EPCAn Module
DMA Module
EPCA Control Data
EPCA Counter
Counter Upper
Limit Update
DMA Channel
DTARGET
Counter Upper
Limit
DMA Control
EPCA Capture Data
EPCAn_CH0 Channel
DMA Channel
EPCAn_CH1 Channel
Channel Mode
EPCAn_CHx Channel
Channel
Mode
PWM N-Bit
Mode
Channel
Mode
Compare Value
PWM Value
N-Bit
Mode
Compare
CHx
Update
PWM Value
N-Bit Mode Compare Value
Compare
Output Control
Update
Compare Value
Compare
Value
Output
Control
Update
Channel Input
Control
Output
Control
Channel
Input
XPHx
Control
Channel Input
YPHx
Control
DMA Channel
Figure 28.15. EPCA Module DMA Configuration
Rev. 1.0
519
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.8.1. Control DMA Transfers
In a control transfer, the DMA should be configured to transfer one word at a time to the DTARGET location in nonincrementing mode. The module MODE register contains three pointers for use with a control transfer: DSTART,
DEND, and DPTR. These pointers control the transfer of data from the DTARGET register to the module and
channel update registers (LIMITUPD and CCAPVUPD). The DSTART pointer indicates the starting register in a
new DMA write transfer, DEND indicates the ending register in the transfer, and DPTR is a circular pointer to the
next register a DMA write to DTARGET will update.
Table 28.6. DMA Control Transfer Pointer Slots
DSTART, DEND, or
DPTR Value
Register
0
LIMITUPD
1
Channel 0 CCAPVUPD
2
Channel 1 CCAPVUPD
3
Channel 2 CCAPVUPD
4
Channel 3 CCAPVUPD
5
Channel 4 CCAPVUPD
6
Channel 5 CCAPVUPD
7
empty
Slot 7 is not normally written unless DEND is set to 7, DSTART is set to 0, and the DMA uses 8-word transfers. In
this case, the 8th data write is discarded.
A transfer starting at slot 5 (Channel 4 CCAPVUPD) can wrap around to end at an earlier slot. Any wraps ignore
slot 7, so the sequence for a 4 DMA word transfers would be: slot 5, slot 6, slot 0, slot 1.
Firmware should not modify these fields while a DMA transfer is in progress, indicated by the DBUSYF flag.
28.8.2. Software DMA Transfers
Software DMA requests can be directly generated by two different software mechanisms:
1. Configure the EPCA for a DMA control request without enabling the DMA channel in the controller.
Software can then write to the update registers by writing directly the DTARGET field.
2. Completely configure the DMA transfer (including the controller channel) and trigger DMA transfers by
writing to the associated event interrupt flag.
520
Rev. 1.0
28.9. EPCA0 Registers
This section contains the detailed register descriptions for EPCA0 registers.
Register 28.1. EPCA0_MODE: Module Operating Mode
Name
Reserved
Type
R
29
28
27
26
25
24
23
22
DBUSYF
30
Reserved
31
STDOSEL
Bit
DSTART
RW
R
RW
RW
21
20
19
18
17
DPTR
DEND
RW
RW
16
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
HDOSEL
Type
RW
0
0
0
0
Reset
0
0
Reserved
Reset
CLKSEL
CLKDIV
R
RW
RW
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_MODE = 0x4000_E180
Table 28.7. EPCA0_MODE Register Bit Descriptions
Bit
Name
Function
31:29
Reserved
Must write reset value.
28:27
STDOSEL
Standard Port Bank Output Select.
00: Select the non-differential channel outputs (Channels 0-5) for the standard PB
pins.
01: Select the differential output from Channel 2 and non-differential outputs from
Channels 0, 1, 3, and 4 for the standard PB pins.
10: Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 3 for the standard PB pins.
11: Select three differential outputs from Channels 0, 1, and 2 for the standard PB
pins.
26
Reserved
Must write reset value.
25
DBUSYF
DMA Busy Flag.
0: The DMA channel is not servicing an EPCA control transfer.
1: The DMA channel is busy servicing an EPCA control transfer.
Rev. 1.0
521
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Table 28.7. EPCA0_MODE Register Bit Descriptions
Bit
Name
24:22
DSTART
Function
DMA Target Start Index.
This field is the first register to be accessed in a new DMA write transfer set to
DTARGET. This field should be written by software before the start of the DMA
transfer.
000: Set the first register in a DMA write transfer to LIMITUPD.
001: Set the first register in a DMA write transfer to Channel 0 CCAPVUPD.
010: Set the first register in a DMA write transfer to Channel 1 CCAPVUPD.
011: Set the first register in a DMA write transfer to Channel 2 CCAPVUPD.
100: Set the first register in a DMA write transfer to Channel 3 CCAPVUPD.
101: Set the first register in a DMA write transfer to Channel 4 CCAPVUPD.
110: Set the first register in a DMA write transfer to Channel 5 CCAPVUPD.
111: Empty slot.
21:19
DPTR
DMA Write Transfer Pointer.
This field is the current target of the DMA. The next word written to DTARGET will
be transferred to the register selected by DPTR. This field is set by hardware and
should not be modified by software.
000: The DMA channel will write to LIMITUPD next.
001: The DMA channel will write to Channel 0 CCAPVUPD next.
010: The DMA channel will write to Channel 1 CCAPVUPD next.
011: The DMA channel will write to Channel 2 CCAPVUPD next.
100: The DMA channel will write to Channel 3 CCAPVUPD next.
101: The DMA channel will write to Channel 4 CCAPVUPD next.
110: The DMA channel will write to Channel 5 CCAPVUPD next.
111: Empty slot.
18:16
DEND
DMA Write End Index.
This field is the last register to be accessed in a DMA write transfer set. This field
should be written by software before the start of the DMA transfer.
000: Set the last register in a DMA write transfer to LIMITUPD.
001: Set the last register in a DMA write transfer to Channel 0 CCAPVUPD.
010: Set the last register in a DMA write transfer to Channel 1 CCAPVUPD.
011: Set the last register in a DMA write transfer to Channel 2 CCAPVUPD.
100: Set the last register in a DMA write transfer to Channel 3 CCAPVUPD.
101: Set the last register in a DMA write transfer to Channel 4 CCAPVUPD.
110: Set the last register in a DMA write transfer to Channel 5 CCAPVUPD.
111: Empty slot.
15:14
HDOSEL
High Drive Port Bank Output Select.
00: Select three differential outputs from Channels 3, 4, and 5 for the High Drive
pins.
01: Select the differential outputs from Channels 4 and 5 and non-differential outputs from Channels 2 and 3 for the High Drive pins.
10: Select the differential output from Channel 5 and non-differential outputs from
Channels 1-4 for the High Drive pins.
11: Select the non-differential channel outputs (Channels 0-5) for the High Drive
pins.
13
522
Reserved
Must write reset value.
Rev. 1.0
Table 28.7. EPCA0_MODE Register Bit Descriptions
Bit
Name
12:10
CLKSEL
Function
Input Clock (FCLKIN) Select.
000: Set the APB as the input clock (FCLKIN).
001: Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).
010: Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).
011: Set the external oscillator module output (EXTOSCn) divided by 2 as the input
clock (FCLKIN).
100: Set ECI transitions divided by 2 as the input clock (FCLKIN).
101-111: Reserved.
9:0
CLKDIV
Input Clock Divider.
The EPCA module clock is given by the equation:
F CLKIN
F EPCA = ------------------------------CLKDIV + 1
Where the input clock (CLKIN) is determined by the CLKSEL bits.
Rev. 1.0
523
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.2. EPCA0_CONTROL: Module Control
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Type
RW
RW
R
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
STSEL
Type
R
RW
RW
RW
R
Reset
0
0
0
0
0
0
0
Reserved
OVFIEN
0
OVFDEN
0
OVFSEN
0
HALTIEN
0
NOUPD
0
Reserved
0
DBGMD
0
HALTEN
Reset
Reserved
Reserved
16
STESEL
DIV
17
STEN
Name
DIVST
Bit
Reserved
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
RW
R
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_CONTROL = 0x4000_E190
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 28.8. EPCA0_CONTROL Register Bit Descriptions
Bit
Name
31:22
DIV
Function
Current Clock Divider Count.
This field is the current value of the internal EPCA clock divider. The clock divider is
a counter that starts at CLKDIV / 2 and counts down to zero.
21
DIVST
Clock Divider Output State.
0: The clock divider is currently in the first half-cycle.
1: The clock divider is currently in the second half-cycle.
20:15
Reserved
14
STEN
Must write reset value.
Synchronous Input Trigger Enable.
0: Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run
if the RUN bit is set regardless of the value on the input trigger.
1: Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer
will start running when the selected input trigger (STSEL) meets the criteria set by
STESEL. It will not stop running if the criteria is no longer met.
13
STESEL
Synchronous Input Trigger Edge Select.
0: A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer.
1: A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer.
Notes:
1. Because hardware updates the DIV and DIVST fields, the SET and CLR addresses are the only safe way to access the
other fields in this register while the EPCA is running.
524
Rev. 1.0
Table 28.8. EPCA0_CONTROL Register Bit Descriptions
Bit
Name
12:11
STSEL
Function
Synchronous Input Trigger Select.
00: Select input trigger 0, Comparator0 output.
01: Select input trigger 1, Comparator1 output.
10: Select input trigger 2, Timer 0 high overflow.
11: Select input trigger 3, Timer 1 high overflow.
10
Reserved
Must write reset value.
9
HALTEN
Halt Input Enable.
0: The Halt input (PB_HDKill) does not affect the EPCA counter/timer.
1: An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer.
8:7
Reserved
Must write reset value.
6
DBGMD
EPCA Debug Mode.
0: A debug breakpoint will stop the EPCA counter/timer.
1: The EPCA will continue to operate while the core is halted in debug mode.
5
Reserved
4
NOUPD
Must write reset value.
Internal Register Update Inhibit.
0: The EPCA registers will automatically load any new update values after an overflow/limit event occurs.
1: The EPCA registers will not load any new update values after an overflow/limit
event occurs.
3
HALTIEN
EPCA Halt Input Interrupt Enable.
0: Do not generate an interrupt if the EPCA halt input is high.
1: Generate an interrupt if the EPCA halt input is high.
2
OVFSEN
EPCA Counter Overflow/Limit Synchronization Signal Enable.
The sychronization signal generated by the EPCA module can be used as an input
by other modules to synchronize with a particular EPCA event or state.
0: Do not send a synchronization signal when a EPCA counter overflow/limit event
occurs.
1: Send a synchronization signal when a EPCA counter overflow/limit event occurs.
1
OVFDEN
EPCA Counter Overflow/Limit DMA Request Enable.
0: Do not request DMA data when a EPCA counter overflow/limit event occurs.
1: Request DMA data when a EPCA counter overflow/limit event occurs.
0
OVFIEN
EPCA Counter Overflow/Limit Interrupt Enable.
0: Disable the EPCA counter overflow/limit event interrupt.
1: Enable the EPCA counter overflow/limit event interrupt.
Notes:
1. Because hardware updates the DIV and DIVST fields, the SET and CLR addresses are the only safe way to access the
other fields in this register while the EPCA is running.
Rev. 1.0
525
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.3. EPCA0_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
C0CCI
0
C1CCI
0
C2CCI
0
C3CCI
0
C4CCI
0
C5CCI
0
RUN
0
OVFI
0
UPDCF
0
HALTI
0
C0IOVFI
0
C1IOVFI
0
C2IOVFI
0
C3IOVFI
0
C4IOVFI
Reset
C5IOVFI
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_STATUS = 0x4000_E1A0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 28.9. EPCA0_STATUS Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15
C5IOVFI
Channel 5 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 5 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 5 did not count past the channel n-bit mode limit.
1: Channel 5 counted past the channel n-bit mode limit.
14
C4IOVFI
Channel 4 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 4 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 4 did not count past the channel n-bit mode limit.
1: Channel 4 counted past the channel n-bit mode limit.
13
C3IOVFI
Channel 3 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 3 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 3 did not count past the channel n-bit mode limit.
1: Channel 3 counted past the channel n-bit mode limit.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
526
Rev. 1.0
Table 28.9. EPCA0_STATUS Register Bit Descriptions
Bit
Name
12
C2IOVFI
Function
Channel 2 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 2 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 2 did not count past the channel n-bit mode limit.
1: Channel 2 counted past the channel n-bit mode limit.
11
C1IOVFI
Channel 1 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 1 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 1 did not count past the channel n-bit mode limit.
1: Channel 1 counted past the channel n-bit mode limit.
10
C0IOVFI
Channel 0 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 0 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 0 did not count past the channel n-bit mode limit.
1: Channel 0 counted past the channel n-bit mode limit.
9
HALTI
Halt Input Interrupt Flag.
This bit is set by hardware when the halt input is asserted. This bit must be cleared
by firmware.
0: The Halt input (PB_HDKill) was not asserted.
1: The Halt input (PB_HDKill) was asserted.
8
UPDCF
Register Update Complete Flag.
0: An EPCA register update completed or is not pending.
1: An EPCA register update has not completed and is still pending.
7
OVFI
Counter/Timer Overflow/Limit Interrupt Flag.
This bit is set by hardware when the counter reaches the value in LIMIT and overflows to zero. This bit must be cleared by firmware.
0: An EPCA Counter/Timer overflow/limit event did not occur.
1: An EPCA Counter/Timer overflow/limit event occurred.
6
RUN
Counter/Timer Run.
0: Stop the EPCA Counter/Timer.
1: Start the EPCA Counter/Timer.
5
C5CCI
Channel 5 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 5. This bit
must be cleared by firmware.
0: A Channel 5 match or capture event did not occur.
1: A Channel 5 match or capture event occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
527
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Table 28.9. EPCA0_STATUS Register Bit Descriptions
Bit
Name
Function
4
C4CCI
Channel 4 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 4. This bit
must be cleared by firmware.
0: A Channel 4 match or capture event did not occur.
1: A Channel 4 match or capture event occurred.
3
C3CCI
Channel 3 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 3. This bit
must be cleared by firmware.
0: A Channel 3 match or capture event did not occur.
1: A Channel 3 match or capture event occurred.
2
C2CCI
Channel 2 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 2. This bit
must be cleared by firmware.
0: A Channel 2 match or capture event did not occur.
1: A Channel 2 match or capture event occurred.
1
C1CCI
Channel 1 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 1. This bit
must be cleared by firmware.
0: A Channel 1 match or capture event did not occur.
1: A Channel 1 match or capture event occurred.
0
C0CCI
Channel 0 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 0. This bit
must be cleared by firmware.
0: A Channel 0 match or capture event did not occur.
1: A Channel 0 match or capture event occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
528
Rev. 1.0
Register 28.4. EPCA0_COUNTER: Module Counter/Timer
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
COUNTER
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_COUNTER = 0x4000_E1B0
Table 28.10. EPCA0_COUNTER Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
COUNTER
Function
Must write reset value.
Counter/Timer.
This field is the current value of EPCA counter/timer.
Rev. 1.0
529
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.5. EPCA0_LIMIT: Module Upper Limit
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
LIMIT
Type
RW
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Address
EPCA0_LIMIT = 0x4000_E1C0
Table 28.11. EPCA0_LIMIT Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
LIMIT
Function
Must write reset value.
Upper Limit.
The EPCA Counter/Timer counts from 0 to the upper limit represented by this field.
530
Rev. 1.0
Register 28.6. EPCA0_LIMITUPD: Module Upper Limit Update Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
LIMITUPD
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_LIMITUPD = 0x4000_E1D0
Table 28.12. EPCA0_LIMITUPD Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:0
LIMITUPD
Module Upper Limit Update Value.
This field will be transferred to the LIMIT field when a EPCA counter/timer overflow/
limit event occurs if updates are allowed (NOUPD = 0). The UPDCF bit will be set to
1 by hardware when the transfer operation is complete.
Rev. 1.0
531
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.7. EPCA0_DTIME: Phase Delay Time
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Name
DTIMEY
DTIMEX
Type
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_DTIME = 0x4000_E1E0
Table 28.13. EPCA0_DTIME Register Bit Descriptions
Bit
Name
Function
31:16
Reserved
Must write reset value.
15:8
DTIMEY
Y Phase Delay Time.
This field is the amount of time in AHB clock cycles after the differential Y Phase
output de-asserts before the X Phase output can assert. This is a global setting for
all channels in the EPCA module.
7:0
DTIMEX
X Phase Delay Time.
This field is the amount of time in AHB clock cycles after the differential X Phase
output de-asserts before the Y Phase output can assert. This is a global setting for
all channels in the EPCA module.
532
Rev. 1.0
Register 28.8. EPCA0_DTARGET: DMA Transfer Target
Bit
31
30
29
28
27
26
25
24
23
22
Name
DTARGET[31:16]
Type
W
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
DTARGET[15:0]
Type
W
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
EPCA0_DTARGET = 0x4000_E200
Table 28.14. EPCA0_DTARGET Register Bit Descriptions
Bit
Name
31:0
DTARGET
Function
DMA Transfer Target.
Writes to this field will be written to the EPCA register selected by the DPTR field.
Notes:
1. The access methods for this register are restricted. Do not use half-word or byte access methods on this register.
Rev. 1.0
533
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
EPCA0_LIMIT EPCA0_COUNTER EPCA0_STATUS EPCA0_CONTROL EPCA0_MODE Register Name
0x4000_E1C0
ALL Address
0x4000_E1A0
0x4000_E190
0x4000_E1B0
0x4000_E180
ALL
Access Methods
ALL | SET | CLR ALL | SET | CLR
ALL
ALL
Bit 31
Reserved
Bit 30
Bit 29
Bit 28
STDOSEL
Bit 27
DIV
Reserved
Bit 26
DBUSYF
Bit 25
Bit 24
Reserved
Reserved
Reserved
DSTART
Bit 23
Bit 22
DIVST
Bit 21
DPTR
Bit 20
Bit 19
Bit 18
Reserved
DEND
Bit 17
Bit 16
C5IOVFI
Bit 15
HDOSEL
STEN
C4IOVFI
Bit 14
STESEL
Reserved
C3IOVFI
Bit 13
C2IOVFI
Bit 12
STSEL
CLKSEL
C1IOVFI
Bit 11
Reserved
C0IOVFI
Bit 10
HALTEN
HALTI
Bit 9
UPDCF
Bit 8
LIMIT
COUNTER
Reserved
OVFI
Bit 7
DBGMD
RUN
Bit 6
Reserved
C5CCI
Bit 5
CLKDIV
NOUPD
C4CCI
Bit 4
HALTIEN
C3CCI
Bit 3
OVFSEN
C2CCI
Bit 2
OVFDEN
C1CCI
Bit 1
OVFIEN
C0CCI
Bit 0
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.10. EPCA0 Register Memory Map
Table 28.15. EPCA0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
534
Rev. 1.0
EPCA0_DTARGET EPCA0_DTIME EPCA0_LIMITUPD Register Name
0x4000_E1E0
0x4000_E1D0
ALL Address
0x4000_E200
ALL
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
DTARGET
Bit 15
Bit 14
Bit 13
Bit 12
DTIMEY
Bit 11
Bit 10
Bit 9
Bit 8
LIMITUPD
Bit 7
Bit 6
Bit 5
Bit 4
DTIMEX
Bit 3
Bit 2
Bit 1
Bit 0
Table 28.15. EPCA0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
535
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.11. EPCA0_CH0-5 Registers
This section contains the detailed register descriptions for EPCA0_CH0, EPCA0_CH1, EPCA0_CH2,
EPCA0_CH3, EPCA0_CH4 and EPCA0_CH5 registers.
Register 28.9. EPCAn_CHx_MODE: Channel Capture/Compare Mode
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CMD
Type
R
RW
R
0
0
Reset
0
0
0
0
0
0
0
0
DIFGEN
Name
Reserved
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
PWMMD
COSEL
RW
RW
RW
0
0
0
0
0
0
Register ALL Access Addresses
EPCA0_CH0_MODE = 0x4000_E000
EPCA0_CH1_MODE = 0x4000_E040
EPCA0_CH2_MODE = 0x4000_E080
EPCA0_CH3_MODE = 0x4000_E0C0
EPCA0_CH4_MODE = 0x4000_E100
EPCA0_CH5_MODE = 0x4000_E140
Table 28.16. EPCAn_CHx_MODE Register Bit Descriptions
Bit
Name
31:11
Reserved
10:8
CMD
Function
Must write reset value.
Channel Operating Mode.
000: Configure the channel for edge-aligned PWM mode.
001: Configure the channel for center-aligned PWM mode.
010: Configure the channel for high-frequency/square-wave mode.
011: Configure the channel for timer/capture mode.
100: Configure the channel for n-bit edge-aligned PWM mode.
101-111: Reserved.
7
Reserved
Must write reset value.
6
DIFGEN
Differential Signal Generator Enable.
0: Disable the differential signal generator. The channel will output a single non-differential output.
1: Enable the differential signal generator. The channel will output two differential
outputs: X Phase (XPH) and Y Phase (YPH).
536
Rev. 1.0
Table 28.16. EPCAn_CHx_MODE Register Bit Descriptions
Bit
Name
5:2
PWMMD
Function
PWM N-Bit Mode.
This field represents the n-bit PWM for this channel. When in n-bit PWM mode, the
channel will behave as if the EPCA Counter/Timer is only n bits wide.
1:0
COSEL
Channel Output Function Select.
00: Toggle the channel output at the next capture/compare, overflow, or intermediate event.
01: Set the channel output at the next capture/compare, overflow, or intermediate
event.
10: Clear the output at the next capture/compare, overflow, or intermediate event.
11: Capture/Compare, overflow, or intermediate events do not control the output
state.
Rev. 1.0
537
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.10. EPCAn_CHx_CONTROL: Channel Capture/Compare Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
COUTST
0
CPCAPEN
0
CNCAPEN
0
CUPDCF
0
Reserved
0
YPHST
0
ACTIVEPH
0
XPHST
0
CCIEN
0
CCDEN
0
CCSEN
0
CIOVFIEN
0
CIOVFDEN
Reset
CIOVFSEN
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
Register ALL Access Addresses
EPCA0_CH0_CONTROL = 0x4000_E010
EPCA0_CH1_CONTROL = 0x4000_E050
EPCA0_CH2_CONTROL = 0x4000_E090
EPCA0_CH3_CONTROL = 0x4000_E0D0
EPCA0_CH4_CONTROL = 0x4000_E110
EPCA0_CH5_CONTROL = 0x4000_E150
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 28.17. EPCAn_CHx_CONTROL Register Bit Descriptions
Bit
Name
31:14
Reserved
13
CIOVFSEN
Function
Must write reset value.
Intermediate Overflow Synchronization Signal Enable.
0: Do not send a synchronization signal when a channel intermediate overflow
event occurs.
1: Send a synchronization signal when a channel intermediate overflow occurs.
12
CIOVFDEN
Intermediate Overflow DMA Request Enable.
0: Do not request DMA data when a channel intermediate overflow event occurs.
1: Request DMA data when a channel intermediate overflow event occurs.
11
CIOVFIEN
Intermediate Overflow Interrupt Enable.
0: Disable the channel intermediate overflow interrupt.
1: Enable the channel intermediate overflow interrupt.
10
CCSEN
Capture/Compare Synchronization Signal Enable.
0: Do not send a synchronization signal when a channel capture/compare event
occurs.
1: Send a synchronization signal when a channel capture/compare event occurs.
538
Rev. 1.0
Table 28.17. EPCAn_CHx_CONTROL Register Bit Descriptions
Bit
Name
9
CCDEN
Function
Capture/Compare DMA Request Enable.
0: Do not request DMA data when a channel capture/compare event occurs.
1: Request DMA data when a channel capture/compare event occurs.
8
CCIEN
Capture/Compare Interrupt Enable.
0: Disable the channel capture/compare interrupt.
1: Enable the channel capture/compare interrupt.
7
XPHST
Differential X Phase State.
0: Set the X Phase output state to low.
1: Set the X Phase output state to high.
6
ACTIVEPH
Active Channel Select.
This bit indicates which phase logic is currently controlling the differential outputs.
0: The Y Phase is active and X Phase is inactive.
1: The X Phase is active and Y Phase is inactive.
5
YPHST
Differential Y Phase State.
0: Set the Y Phase output state to low.
1: Set the Y Phase output state to high.
4
Reserved
Must write reset value.
3
CUPDCF
Channel Register Update Complete Flag.
0: A EPCA channel register update completed or is not pending.
1: A EPCA channel register update has not completed and is still pending.
2
CNCAPEN
Negative Edge Input Capture Enable.
0: Disable negative-edge input capture.
1: Enable negative-edge input capture.
1
CPCAPEN
Positive Edge Input Capture Enable.
0: Disable positive-edge input capture.
1: Enable positive-edge input capture.
0
COUTST
Channel Output State.
0: The channel output state is low.
1: The channel output state is high.
Rev. 1.0
539
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Register 28.11. EPCAn_CHx_CCAPV: Channel Compare Value
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
CCAPV[17:16]
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
CCAPV[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
EPCA0_CH0_CCAPV = 0x4000_E020
EPCA0_CH1_CCAPV = 0x4000_E060
EPCA0_CH2_CCAPV = 0x4000_E0A0
EPCA0_CH3_CCAPV = 0x4000_E0E0
EPCA0_CH4_CCAPV = 0x4000_E120
EPCA0_CH5_CCAPV = 0x4000_E160
Table 28.18. EPCAn_CHx_CCAPV Register Bit Descriptions
Bit
Name
31:18
Reserved
17:0
CCAPV
Function
Must write reset value.
Channel Compare Value.
This field holds the channel compare value for comparator functions or the channel
capture data from timer functions. The LSB represents 1/2 PCA clock period.
540
Rev. 1.0
Register 28.12. EPCAn_CHx_CCAPVUPD: Channel Compare Update Value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
CCAPVUPD[17:16]
Bit
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
CCAPVUPD[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
EPCA0_CH0_CCAPVUPD = 0x4000_E030
EPCA0_CH1_CCAPVUPD = 0x4000_E070
EPCA0_CH2_CCAPVUPD = 0x4000_E0B0
EPCA0_CH3_CCAPVUPD = 0x4000_E0F0
EPCA0_CH4_CCAPVUPD = 0x4000_E130
EPCA0_CH5_CCAPVUPD = 0x4000_E170
Table 28.19. EPCAn_CHx_CCAPVUPD Register Bit Descriptions
Bit
Name
31:18
Reserved
17:0
CCAPVUPD
Function
Must write reset value.
Channel Compare Update Value.
This field will be transferred to the CCAPV field when a EPCA counter/timer overflow occurs if updates are allowed (NOUPD = 0). The CUPDCF bit will be set to 1 by
hardware when the transfer operation is complete.
Rev. 1.0
541
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
28.12. EPCAn_CHx Register Memory Map
Table 28.20. EPCAn_CHx Memory Map
EPCAn_CHx_CONTROL EPCAn_CHx_MODE Register Name
ALL Offset
0x10
0x0
Access Methods
ALL | SET | CLR
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Reserved
Bit 22
Reserved
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
CIOVFSEN
Bit 13
CIOVFDEN
Bit 12
CIOVFIEN
Bit 11
CCSEN
Bit 10
CMD
CCDEN
Bit 9
CCIEN
Bit 8
Reserved
XPHST
Bit 7
DIFGEN
ACTIVEPH
Bit 6
YPHST
Bit 5
Reserved
Bit 4
PWMMD
CUPDCF
Bit 3
CNCAPEN
Bit 2
CPCAPEN
Bit 1
COSEL
COUTST
Bit 0
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: EPCA0_CH0 = 0x4000_E000, EPCA0_CH1 = 0x4000_E040,
EPCA0_CH2 = 0x4000_E080, EPCA0_CH3 = 0x4000_E0C0, EPCA0_CH4 = 0x4000_E100, EPCA0_CH5 =
0x4000_E140
542
Rev. 1.0
EPCAn_CHx_CCAPVUPD EPCAn_CHx_CCAPV Register Name
0x30
0x20
ALL Offset
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
Reserved
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CCAPVUPD
CCAPV
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 28.20. EPCAn_CHx Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: EPCA0_CH0 = 0x4000_E000, EPCA0_CH1 = 0x4000_E040,
EPCA0_CH2 = 0x4000_E080, EPCA0_CH3 = 0x4000_E0C0, EPCA0_CH4 = 0x4000_E100, EPCA0_CH5 =
0x4000_E140
Rev. 1.0
543
Enhanced Programmable Counter Array (EPCA0)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29. Programmable Counter Array (PCA0 and PCA1)
This section describes the Programmable Counter Array (PCA) module, and is applicable to all products in the
following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the PCA block, which is used by both PCA0 and PCA1 on all device families
covered in this document.
29.1. Programmable Counter Array Features
The PCA module includes the following features:
Independent
channels.
and edge-aligned waveform generation.
Programmable clock divisor and multiple options for clock source selection.
Pulse-Width Modulation waveform generation.
Center-
PCAn Module
Counter Upper
Limit
PCA Counter
TIMER0 overflow
EXTOSCn Clock
APB Clock
Clock
Divisor
Channel Status
ECI
PCAn_CH0 Channel
PCAn_CH1 Channel
Channel Mode
Channel
Mode
PWM N-Bit
Mode
PWM Value
N-Bit Mode Compare Value
Compare
Update
Compare Value
Compare
Output
ControlValue
Update
Output
Control
Channel
Input
Control
Channel Input
Control
Figure 29.1. PCA Block Diagram
544
Rev. 1.0
CEX0
CEX1
29.2. Module Overview
The Programmable Counter Array (PCA) provides flexible timer/counter functionality. The PCA consists of a
dedicated 16-bit counter/timer and multiple (up to two) 16-bit capture/compare channels (PCAn_CHx). All channels
trigger or capture based on the shared 16-bit counter/timer, so the channels are inherently synchronized. The
counter/timer is a 16-bit up counter with a programmable upper count limit. The counter starts at 0 and counts
continuously from zero to the upper limit. Each channel includes a data register that can compare against the
counter or capture the state of the counter based on a set of programmable conditions.
Each channel has its own associated output lines and may be configured to operate independently of the others in
one of six modes: Edge-Aligned PWM, Center-Aligned PWM, High-Frequency / Square Wave, Timer / Capture, nbit Edge-Aligned PWM, or Software Timer. Each channel has a single output (CHx).
The RUN bit starts or stops the PCA counter. The DBGMD bit in the CONTROL register controls whether the PCA
counter runs while the core is halted in debug mode.
Three different events can change a channel output or cause a capture. An overflow/limit event occurs when the
PCA counter (COUNTER) is equal to the upper limit (LIMIT). A capture/compare event occurs whenever a
channel’s capture/compare register (CCAPV) matches the current PCA counter value. An intermediate overflow
event can only occur in n-bit PWM mode and occurs when the channel’s n-bit capture/compare range matches the
PCA counter.
To facilitate counter and channel updates while the counter continues to run, the channel compare/capture register
(CCAPV) has an update register (CCAPVUPD). Firmware can write a new value to the CCAPVUPD register
without modifying the current PCA cycle. The hardware will load these values into the CCAPV register when the
next counter overflow/limit event occurs, and the channel CUPDCF flag indicates when an update operation
completes.
Rev. 1.0
545
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.3. Clocking
The clock input for the counter/timer is selected by the CLKSEL field in the MODE register as shown in
Figure 29.2.
CLKSEL
CLKDIV
TIMER0 Low overflow
EXTOSCn
APB Clock
Clock Divider
Counter
Clock
ECI
Figure 29.2. Clock Source Selection
The selected clock is passed through a divide-by-n clock divider where n can be between 1 and 1024. The CLKDIV
field sets the clock divider for the selected clock before it drives the 16-bit counter/timer.
All non-APB clock sources must be synchronized with the APB clock, so the maximum possible operating speed
using these sources is one-half the APB frequency, if not slower.
29.3.1. APB Clock
When the APB clock signal is selected as the counter clock source, the PCA counter clock divider will use the APB
clock source defined by the device clock control module. Selecting the APB clock provides the fastest clock source
for the module.
29.3.2. External Clock (EXTOSCn)
When the external clock is selected as the counter clock source, the counter will run from the external clock source
(EXTOSCn), regardless of the clock selection of the core. The external clock source is synchronized to the
selected core clock in this mode. In order to guarantee that the external clock transitions are recognized by the
device, the external clock signal must be high or low for at least one APB clock period. This limits the maximum
frequency of an external clock in this mode to one-half the APB clock.
29.3.3. TIMER0 Low Overflow
The PCA module can select the TIMER0 module low timer overflows as its clock source. TIMER0 can operate in
either 32-bit or 16-bit mode and still provide the clock for the PCA clock divider. The maximum speed for the
TIMER0 low overflows as an PCA counter clock source is one-half the APB clock.
29.3.4. External Clock Input (ECI)
When the external clock input (ECI) is selected as the PCA clock source, the clock divider decrements on falling
edges or both rising and falling edges of the pin. The ECI pin is synchronized to the selected AHB clock in this
mode. The maximum clock rate for the ECI external clock input is the APB divided by 4.
29.3.5. Clock Divider
The clock divider provides a flexible time base for the PCA counter. The divider starts at one-half the CLKDIV value
and decrements to 0. Using this method, the divider counts the number of input clocks until the next counter clock
edge (either rising or falling) rather than whole counter clock periods.
The current value of the divider can be read and written using the DIV field in the MODE register. This allows
access during debugging to observe module events at the various PCA clock edges rather than stepping through a
large number of APB clocks. Firmware should always write to the CLKDIV field to modify the divider value.
The DIVST bit displays the current output phase of the clock divider.
546
Rev. 1.0
29.4. Interrupts
The PCA module has one interrupt vector and multiple interrupt sources within the module.
The module has one counter overflow/limit interrupt source. The OVFIEN bit enables the counter overflow/limit
interrupt, which occurs when counter (COUNTER) equals the upper limit (LIMIT) and resets to 0. The OVFI
interrupt flag indicates when an counter overflow/limit event occurs.
Each channel (CHx) has a compare/capture interrupt flag (CxCCI) and an intermediate overflow flag (CxIOVFI).
These interrupts can be enabled in the channel registers (CCIEN for capture/compare, CIOVFIEN for intermediate
overflow).
Firmware can check the source of the PCA interrupt by checking the appropriate flags in the interrupt service
routine.
29.5. Outputs
The PCA module has up to two module outputs (CEXx) that can be routed to physical pins by configuring the
device port configuration module. Each PCA capture/compare channel has a single CHx output.
The COUTST bit in the PCA channels determines the polarity of the output. This value should be set when the
counter is not running to ensure predictable operation. Hardware sets the COUTST bit on the rising edges of the
APB clock to reflect the current output state of the channel.
Note: The COUTST bit determines the starting state of the channel output. If the starting state is active, this means the channel
could be sitting in an active state for some time while firmware finishes initializing the module and starts the counter. If
the output is connected to a transistor where this behavior is undesirable, firmware can initialize the counter to a midrange value and the outputs with an inactive value. This will ensure that any sensitive external circuits will not be damaged.
Figure 29.3 shows a PCA channel single output timing diagram.
PCA Clock
COUNTER
0x0002
0x0003
0x0000
0x0001
LIMIT
0x0003
CCAPV
0x0006
0x0002
0x0003
0x0000
CHx
COUTST
Figure 29.3. Example Channel Single Output Timing Diagram (Toggle Mode)
The CHx output can toggle, set, or clear on an overflow/limit, compare, or intermediate overflow event. In addition,
the output can ignore these events and stay at its previous value. The COSEL field in the channel MODE register
determines the CHx output behavior. This field allows firmware to modify the behavior of the CHx output without
changing the configuration of the channel, interrupting the counter, or changing the port configuration.
Rev. 1.0
547
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.6. Operational Modes
The PCA module has six operational modes that each channel can independently select: Edge-Aligned PWM,
Center-Aligned PWM, High-Frequency/Square Wave, Timer/Capture, n-bit Edge-Aligned PWM, and Software
Timer modes. The CMD bits select the channel operational mode.
The PCA counter is 16 bits and counts in full PCA clock cycles. The channel CCAPV registers are 18 bits and
represent half PCA clock cycles. To match an counter value, the CCAPV field should be written with double the
counter value. The CCAPV LSB provides timing resolution to one half-clock counter cycle. The additional 18th bit
of the CCAPV register allows the channel outputs to create 0-100% duty cycles (0x00000 is 0% and 0x20000 is
100% duty cycle).
COUNTER
CCAPV
allows for 100% duty
cycle
counts half
clocks
Figure 29.4. PCA Counter and Channel Compare/Capture Registers
This section discusses the channel behavior in each of these modes in detail.
548
Rev. 1.0
29.6.1. Edge-Aligned Pulse Width Modulation (PWM) Mode
In edge-aligned PWM mode (CMD = 0), the 18-bit capture/compare register (CCAPV) defines the number of PCA
half clocks for the inactive time of the PWM signal. A capture/compare event occurs when the counter matches the
register contents, and the output will change from the initial state set by COUTST depending on the selected
COSEL value (typically 00b for toggle). An overflow/limit event occurs when the counter reaches the LIMIT value
and resets to 0, and CHx will again change depending on the COSEL value. To output a varying duty cycle,
firmware can write to the CCAPVUPD register, which hardware will automatically load into the channel’s CCAPV
register on the next counter overflow/limit if the module register update inhibit (NOUPD) is cleared to 0.
Assuming that the inactive and initial state of the output is low and COSEL is set to toggle, the CHx output duty
cycle in edge-aligned PWM mode is shown in Equation 29.1. No output pulse is generated if CCAPV is 0, and
100% duty cycle results from CCAPV set to 0x20000.
Figure 29.5 shows an example edge-aligned PWM timing diagram.
 LIMIT  2  – CCAPV
Duty Cycle = ----------------------------------------------------------LIMIT  2
Equation 29.1. Edge-Aligned PWM Duty Cycle
Because CCAPV is given in half clocks, an odd CCAPV value results in the CHx output changing state at the midcycle edge of the PCA clock.
PCA Clock
COUNTER
0x0003
0x0000
0x0001
0x0002
LIMIT
0x0003
CCAPV
0x00003
0x0003
capture/compare
CHx
0x0000
0x0001
overflow/limit
PWM waveform
capture/compare
overflow/limit
COUTST
Figure 29.5. Example Edge-Aligned PWM Timing Diagram
Rev. 1.0
549
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.6.2. Center-Aligned Pulse Width Modulation (PWM) Mode
In center-aligned PWM mode (CMD = 1), a channel generates a PWM waveform symmetric about the counter’s
overflow/limit event defined by the LIMIT field. Multiple channels in an array configured in this mode will each have
PWM waveforms which are all symmetric about the same center-pulse points (counter equal to zero).
LIMIT
COUNTER
CH0
CH1
CCAPV
2
LIMIT –
CCAPV
2
Figure 29.6. Multiple Center-Aligned PWM Channels
The channel 18-bit capture/compare register (CCAPV) is used to generate two capture/compare events in one
counter cycle (0 to LIMIT). The first event occurs when the counter is equal to CCAPV divided by 2. The second
event occurs when the counter is equal to LIMIT minus CCAPV divided by 2. In the event of an odd value in
CCAPV, the hardware adds the extra half cycle to the capture/compare event following the counter overflow/limit
event.
Firmware can write to the channel’s CCAPVUPD register to update the waveform. Hardware will update the
CCAPV field with the CCAPVUPD value when the counter overflows from the upper limit to zero as long as the
update inhibit bit (NOUPD) is cleared to 0.
The COUTST bit determines the starting state of the channel output and should be set before starting the counter.
If the starting state is active, this means the channel could be sitting in an active state for some time while firmware
finishes initializing the module and starts the counter. If the output is connected to a transistor where this behavior
is undesirable, firmware can initialize the counter to a mid-range value and the outputs with an inactive value. This
will ensure that any sensitive external circuits will not be damaged.
Assuming that the active and initial state of the output is high and COSEL is set to toggle, the CHx output duty
cycle in center-aligned PWM mode is shown in Equation 29.2. No output pulse is generated if CCAPV is 0, and
100% duty cycle results when CCAPV (in half clocks) is set to a number of full clocks equal to or greater than
LIMIT.
Figure 29.7 shows an example center-aligned PWM timing diagram.
 LIMIT  2  – CCAPV
Duty Cycle = ----------------------------------------------------------LIMIT  2
Equation 29.2. Center-Aligned PWM Duty Cycle
550
Rev. 1.0
overflow/limit
capture/
compare
capture/
compare
PCA Clock
COUNTER
0x0003
0x0000
0x0001
0x0002
LIMIT
0x0003
CCAPV
0x00003
CHx
0x0003
0x0000
0x0001
PWM waveform
COUTST
Figure 29.7. Example Center-Aligned PWM Timing Diagram
Rev. 1.0
551
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.6.3. High-Frequency / Square Wave Mode
High-frequency square-wave mode (CMD = 2) produces a 50% duty cycle waveform of programmable period on
the channel's CHx output. This mode provides a flexible way of creating square waves with a fast period. Each
half-period of the generated output clock can be as short as one counter clock period (two CCAPV half clocks) and
as long as 128 counter clock periods, programmable in half clock steps.
Bits [15:8] of the channel capture/compare register (CCAPV) contain the waveform half period in the number of half
PCA clocks. The lower byte (bits [7:0]) is the calculated value compared to the counter. When a match occurs
between the lower byte and the counter, the hardware triggers a capture/compare event and automatically adds
the match value of the counter to the CCAPV[15:8] value to create a new compare value for the lower byte. An
overflow/limit event occurs when the counter reaches the upper limit defined by the LIMIT field. Firmware should
program the upper limit register to reset the counter at a (multiple of 128) - 1 to avoid undesired waveform edges.
Figure 29.8 shows how the hardware creates the waveform.
COUNTER
6
5
4
3
2
1
0
capture/compare event
comparator
phase comparator
CCAPV
7
6
5
4
3
2
1
FCLKIN
enable
Figure 29.8. High-Frequency Square Wave Waveform Generation
Firmware can update the frequency of the output by writing to the CCAPVUPD register. Hardware will
automatically load bits [15:8] of this register to the CCAPV register at the next counter overflow/limit event, if
possible (NOUPD = 0). The rest of the CCAPVUPD register (bits [17:16] and [7:0]) are ignored.
Assuming that the COSEL field for the channel is set to toggle, the resulting CHx output frequency in highfrequency square-wave mode is shown in Equation 29.3. A CCAPV[15:8] value of 1 is not valid, and a
CCAPV[15:8] value of 0 results in an output waveform half period of 128 counter clocks.
Figure 29.9 shows an example high-frequency square wave mode timing diagram.
F PCA
F CHx = ----------------------------------CCAPV[15:8]
Equation 29.3. High-Frequency Square Wave Output Frequency
552
Rev. 1.0
PCA Clock
COUNTER
0x0002
0x0003
0x0004
0x0005
LIMIT
CCAPV
CHx
0x0006
0x0007
0x0008
0x007F
0x00306
0x0309
0x030C
0x030F
square waveform
COUTST
Figure 29.9. Example High-Frequency Square Wave Mode Timing Diagram
Rev. 1.0
553
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.6.4. Timer/Capture Mode
In timer/capture mode (CMD = 3), the channel uses the CEXn line as an input signal that triggers a capture/
compare event and stores the counter state in the channel capture/compare register (CCAPV) in half clocks.
Firmware can configure the event to trigger on rising, falling, or both edges using the channel CPCAPEN and
CNCAPEN bits. Table 29.1 shows the capture edge configuration options.
Table 29.1. Capture Edge Configuration Options
CPCAPEN
CNCAPEN
Selected Edge
0
0
Capture disabled.
0
1
Capture on the falling edge.
1
0
Capture on the rising edge.
1
1
Capture on both edges.
The input CEXn signal must remain high or low for at least two APB clocks to be recognized by the hardware. The
capture occurs at the next PCA clock edge.
Figure 29.10 shows an example timer/capture mode timing diagram.
PCA Clock
COUNTER 0x013C
0x013D
0x013E
0x013F
LIMIT
CCAPV
0x0000
0x0001
0x013F
0x0005C
0x0027A
CEXx*
falling edge capture
*Note: CEXx must be high or low for 2 APB clock cycles.
Figure 29.10. Example Timer / Capture Mode Timing Diagram
554
Rev. 1.0
0x0002
29.6.5. N-bit Edge-Aligned Pulse Width Modulation (PWM) Mode
The n-bit edge-aligned PWM modes allow each channel to be independently configured to generate edge-aligned
PWM waveforms with a faster duty cycle than the counter. In n-bit edge-aligned PWM mode (CMD = 4), the leastsignificant n bits (set by PWMMD) of the counter define the number of full clocks of the PWM waveform. The
channel’s capture/compare register (CCAPV) defines the number of PCA half clocks for the inactive time of the
PWM signal, and the higher order unused bits of CCAPV are ignored. A capture/compare event occurs when the nbit counter is equal to the number of half clocks defined by the CCAPV field. An intermediate overflow event occurs
when the counter overflows the n-bit range. A counter overflow/limit event occurs when the counter reaches the
upper limit (LIMIT) within the full 16-bit range. If one of the channels operates in n-bit mode, firmware should set
the counter’s upper limit as an even multiple of the n-bit boundary to ensure the channel’s output does not have
any irregular edges from the overflow/limit events.
intermediate
overflow
capture/
compare
overflow/limit and
intermediate
overflow
LIMIT
COUNTER
CH0
(n-bit mode)
CH1
(edge aligned
mode)
Figure 29.11. Multiple Edge-Aligned PWM Channels (N-bit and Edge Aligned)
Table 29.2 provides a list of the intermediate overflow, recommended upper limit values, and 100% duty cycle
values for each n-bit setting.
Rev. 1.0
555
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Table 29.2. N-bit Intermediate Overflow Values
PWMMD Value
N-bit PWM
Mode
Counter Intermediate
Overflow Value
(full clocks)
Recommended
Counter Upper Limit
(full clocks)
CCAPV 100% Duty
Cycle Value
(half clocks)
0
0-bit
0
any value
2
1
1-bit
1
(multiple of 2) - 1
4
2
2-bit
3
(multiple of 4) - 1
8
3
3-bit
7
(multiple of 8) - 1
16
4
4-bit
15
(multiple of 16) - 1
32
5
5-bit
31
(multiple of 32) - 1
64
6
6-bit
63
(multiple of 64) - 1
128
7
7-bit
127
(multiple of 128) - 1
256
8
8-bit
255
(multiple of 256) - 1
512
9
9-bit
511
(multiple of 512) - 1
1024
10
10-bit
1023
(multiple of 1024) - 1
2048
11
11-bit
2047
(multiple of 2048) - 1
4096
12
12-bit
4095
(multiple of 4096) - 1
8192
13
13-bit
8191
(multiple of 8192) - 1
16334
14
14-bit
16333
(multiple of 16334) - 1
32768
15
15-bit
32767
(multiple of 32768) - 1
65536
Firmware can write to the CCAPVUPD register to update the duty cycle, which hardware will automatically load
into the channel’s CCAPV register on the next counter overflow/limit event if the module register update inhibit
(NOUPD) is cleared to 0.
Assuming that the inactive and initial state of the output is low, COSEL is set to toggle, and the upper limit is set to
an even multiple, the CHx output duty cycle in n-bit edge-aligned PWM mode is shown in Equation 29.4. No output
pulse is generated if CCAPV is 0.
Figure 29.12 shows an example n-bit edge-aligned PWM timing diagram.
n
 2  2  – CCAPV
Duty Cycle = ----------------------------------------------n
2 2
Equation 29.4. N-bit Edge-Aligned PWM Duty Cycle
Because CCAPV is given in half clocks, an odd CCAPV value results in the CHx output changing state at the midcycle edge of the PCA clock.
556
Rev. 1.0
PCA Clock
COUNTER
0x0005
0x0000
0x0001
0x0002
LIMIT
0x0005
CCAPV
0x00001
CHx
channel in 1-bit mode
0x0003
0x0004
0x0005
PWM waveform
COUTST
Figure 29.12. Example N-bit Edge-Aligned PWM Timing Diagram
Rev. 1.0
557
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.6.6. Software Timer Mode
Software timer mode is a free-running mode with the CHx output unaffected by the counter or channel state.
Setting the COSEL field to 3 (output ignore events) enters software timer mode, regardless of the CMD field
setting. The counter overflow/limit, intermediate overflow, and capture/compare events can still be used to
generate interrupts, even though the channel output is disabled.
Figure 29.13 shows an example software timer mode timing diagram.
PCA Clock
COUNTER 0x008F
LIMIT
CCAPV
0x0090
0x0091
0x0092
0x0000
0x0001
0x0002
0x0092
0x0007C
overflow/limit event
CHx
channel output is unaffected
Figure 29.13. Example Software Timer Mode Timing Diagram
558
Rev. 1.0
29.7. PCA0 and PCA1 Registers
This section contains the detailed register descriptions for PCA0 and PCA1 registers.
Register 29.1. PCAn_MODE: Module Operating Mode
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Name
Reserved
CLKSEL
CLKDIV
Type
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_MODE = 0x4000_F180
PCA1_MODE = 0x4001_0180
Table 29.3. PCAn_MODE Register Bit Descriptions
Bit
Name
Function
31:13
Reserved
Must write reset value.
12:10
CLKSEL
Input Clock (FCLKIN) Select.
000: Set the APB as the input clock (FCLKIN).
001: Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).
010: Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).
011: Set the external oscillator module output (EXTOSCn) divided by 2 as the input
clock (FCLKIN).
100: Set ECI transitions divided by 2 as the input clock (FCLKIN).
101-111: Reserved.
9:0
CLKDIV
Input Clock Divisor.
The PCA module clock is given by the equation:
F CLKIN
F PCA = ------------------------------CLKDIV + 1
Where the input clock (CLKIN) is determined by the CLKSEL bits.
Rev. 1.0
559
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Register 29.2. PCAn_CONTROL: Module Control
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Name
DIV
DIVST
Bit
Reserved
Type
RW
RW
R
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
0
Reserved
OVFIEN
Reset
DBGMD
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
RW
R
RW
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_CONTROL = 0x4000_F190
PCA1_CONTROL = 0x4001_0190
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 29.4. PCAn_CONTROL Register Bit Descriptions
Bit
Name
31:22
DIV
Function
Current Clock Divider Count.
This field is the current value of the internal PCA clock divider. The clock divider is a
counter that starts at CLKDIV / 2 and counts down to zero.
21
DIVST
Clock Divider Output State.
0: The clock divider is currently in the first half-cycle.
1: The clock divider is currently in the second half-cycle.
20:7
Reserved
Must write reset value.
6
DBGMD
PCA Debug Mode.
0: A debug breakpoint will cause the PCA to halt.
1: The PCA will continue to operate while the core is halted in debug mode.
5:1
Reserved
Must write reset value.
0
OVFIEN
PCA Counter Overflow/Limit Interrupt Enable.
0: Disable the PCA counter overflow/limit event interrupt.
1: Enable the PCA counter overflow/limit event interrupt.
Notes:
1. Because hardware updates the DIV and DIVST fields, the SET and CLR addresses are the only safe way to access the
other fields in this register while the PCA is running.
560
Rev. 1.0
Register 29.3. PCAn_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Reserved
Type
R
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
0
Name
Reserved
Reserved
Type
R
RW
RW
R
0
0
Reset
0
0
0
0
0
0
Reserved
C0CCI
0
C1CCI
0
RUN
0
C0IOVFI
0
C1IOVFI
Reset
OVFI
Name
22
RW
R
RW
RW
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_STATUS = 0x4000_F1A0
PCA1_STATUS = 0x4001_01A0
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 29.5. PCAn_STATUS Register Bit Descriptions
Bit
Name
Function
31:12
Reserved
Must write reset value.
11
C1IOVFI
Channel 1 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 1 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 1 did not count past the channel n-bit mode limit.
1: Channel 1 counted past the channel n-bit mode limit.
10
C0IOVFI
Channel 0 Intermediate Overflow Interrupt Flag.
This bit is set by hardware when a counter overflows the n-bit range in Channel 0 nbit PWM mode. This bit must be cleared by firmware.
0: Channel 0 did not count past the channel n-bit mode limit.
1: Channel 0 counted past the channel n-bit mode limit.
9:8
Reserved
7
OVFI
Must write reset value.
Counter/Timer Overflow/Limit Interrupt Flag.
This bit is set by hardware when the counter reaches the value in LIMIT and overflows to zero. This bit must be cleared by firmware.
0: A PCA Counter/Timer overflow/limit event did not occur.
1: A PCA Counter/Timer overflow/limit event occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
561
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Table 29.5. PCAn_STATUS Register Bit Descriptions
Bit
Name
6
RUN
Function
Counter/Timer Run.
0: Stop the PCA Counter/Timer.
1: Start the PCA Counter/Timer.
5:2
Reserved
1
C1CCI
Must write reset value.
Channel 1 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 1. This bit
must be cleared by firmware.
0: A Channel 1 match or capture event did not occur.
1: A Channel 1 match or capture event occurred.
0
C0CCI
Channel 0 Capture/Compare Interrupt Flag.
This bit is set by hardware when a match or capture occurs in Channel 0. This bit
must be cleared by firmware.
0: A Channel 0 match or capture event did not occur.
1: A Channel 0 match or capture event occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
562
Rev. 1.0
Register 29.4. PCAn_COUNTER: Module Counter/Timer
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
COUNTER
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_COUNTER = 0x4000_F1B0
PCA1_COUNTER = 0x4001_01B0
Table 29.6. PCAn_COUNTER Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
COUNTER
Function
Must write reset value.
Counter/Timer.
This field is the current value of PCA counter/timer.
Rev. 1.0
563
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Register 29.5. PCAn_LIMIT: Module Counter/Timer Upper Limit
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Name
LIMIT
Type
RW
Reset
1
1
1
1
1
1
1
1
1
Register ALL Access Addresses
PCA0_LIMIT = 0x4000_F1C0
PCA1_LIMIT = 0x4001_01C0
Table 29.7. PCAn_LIMIT Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
LIMIT
Function
Must write reset value.
Upper Limit.
The PCA Counter/Timer counts from 0 to the upper limit represented by this field.
564
Rev. 1.0
29.8. PCAn Register Memory Map
PCAn_LIMIT PCAn_COUNTER PCAn_STATUS PCAn_CONTROL PCAn_MODE Register Name
0x40
0x20
0x30
0x10
ALL Offset
0x0
ALL
ALL | SET | CLR ALL | SET | CLR
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
DIV
Bit 26
Bit 25
Bit 24
Reserved
Reserved
Bit 23
Reserved
Bit 22
Reserved
DIVST
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Reserved
Bit 13
Bit 12
CLKSEL
C1IOVFI
Bit 11
C0IOVFI
Bit 10
Bit 9
Reserved
Bit 8
LIMIT
COUNTER
OVFI
Bit 7
DBGMD
RUN
Bit 6
Bit 5
CLKDIV
Bit 4
Reserved
Reserved
Bit 3
Bit 2
C1CCI
Bit 1
OVFIEN
C0CCI
Bit 0
Table 29.8. PCAn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PCA0 = 0x4000_F180, PCA1 = 0x4001_0180
Rev. 1.0
565
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.9. PCA0_CH0-1 and PCA1_CH0-1 Registers
This section contains the detailed register descriptions for PCA0_CH0, PCA0_CH1, PCA1_CH0 and PCA1_CH1
registers.
Register 29.6. PCAn_CHx_MODE: Channel Capture/Compare Mode
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
CMD
Reserved
PWMMD
COSEL
Type
R
RW
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_CH0_MODE = 0x4000_F000
PCA0_CH1_MODE = 0x4000_F040
PCA1_CH0_MODE = 0x4001_0000
PCA1_CH1_MODE = 0x4001_0040
Table 29.9. PCAn_CHx_MODE Register Bit Descriptions
Bit
Name
31:11
Reserved
10:8
CMD
Function
Must write reset value.
Channel Operating Mode.
000: Configure the channel for edge-aligned PWM mode.
001: Configure the channel for center-aligned PWM mode.
010: Configure the channel for high-frequency/square-wave mode.
011: Configure the channel for timer/capture mode.
100: Configure the channel for n-bit edge-aligned PWM mode.
101-111: Reserved.
7:6
Reserved
Must write reset value.
5:2
PWMMD
PWM N-Bit Mode.
This field represents the n-bit PWM for this channel. When in n-bit PWM mode, the
channel will behave as if the PCA Counter/Timer is only n bits wide.
566
Rev. 1.0
Table 29.9. PCAn_CHx_MODE Register Bit Descriptions
Bit
Name
1:0
COSEL
Function
Channel Output Function Select.
00: Toggle the channel output at the next capture/compare, overflow, or intermediate event.
01: Set the channel output at the next capture/compare, overflow, or intermediate
event.
10: Clear the output at the next capture/compare, overflow, or intermediate event.
11: Capture/Compare, overflow, or intermediate events do not control the output
state.
Rev. 1.0
567
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Register 29.7. PCAn_CHx_CONTROL: Channel Capture/Compare Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Type
R
RW
R
Reset
0
0
0
0
0
0
0
Reserved
COUTST
0
CPCAPEN
0
CNCAPEN
0
CUPDCF
0
CCIEN
Reset
CIOVFIEN
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
RW
R
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_CH0_CONTROL = 0x4000_F010
PCA0_CH1_CONTROL = 0x4000_F050
PCA1_CH0_CONTROL = 0x4001_0010
PCA1_CH1_CONTROL = 0x4001_0050
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 29.10. PCAn_CHx_CONTROL Register Bit Descriptions
Bit
Name
Function
31:12
Reserved
Must write reset value.
11
CIOVFIEN
Intermediate Overflow Interrupt Enable.
0: Disable the channel intermediate overflow interrupt.
1: Enable the channel intermediate overflow interrupt.
10:9
Reserved
8
CCIEN
Must write reset value.
Capture/Compare Interrupt Enable.
0: Disable the channel capture/compare interrupt.
1: Enable the channel capture/compare interrupt.
7:4
Reserved
Must write reset value.
3
CUPDCF
Channel Register Update Complete Flag.
0: A PCA channel register update completed or is not pending.
1: A PCA channel register update has not completed and is still pending.
2
CNCAPEN
Negative Edge Input Capture Enable.
0: Disable negative-edge input capture.
1: Enable negative-edge input capture.
568
Rev. 1.0
Table 29.10. PCAn_CHx_CONTROL Register Bit Descriptions
Bit
Name
1
CPCAPEN
Function
Positive Edge Input Capture Enable.
0: Disable positive-edge input capture.
1: Enable positive-edge input capture.
0
COUTST
Channel Output State.
0: The channel output state is low.
1: The channel output state is high.
Rev. 1.0
569
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Register 29.8. PCAn_CHx_CCAPV: Channel Compare Value
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
CCAPV[17:16]
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
CCAPV[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_CH0_CCAPV = 0x4000_F020
PCA0_CH1_CCAPV = 0x4000_F060
PCA1_CH0_CCAPV = 0x4001_0020
PCA1_CH1_CCAPV = 0x4001_0060
Table 29.11. PCAn_CHx_CCAPV Register Bit Descriptions
Bit
Name
31:18
Reserved
17:0
CCAPV
Function
Must write reset value.
Channel Compare Value.
This field holds the channel compare value for comparator functions or the channel
capture data from timer functions.
570
Rev. 1.0
Register 29.9. PCAn_CHx_CCAPVUPD: Channel Compare Update Value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Reserved
CCAPVUPD[17:16]
Bit
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
CCAPVUPD[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
PCA0_CH0_CCAPVUPD = 0x4000_F030
PCA0_CH1_CCAPVUPD = 0x4000_F070
PCA1_CH0_CCAPVUPD = 0x4001_0030
PCA1_CH1_CCAPVUPD = 0x4001_0070
Table 29.12. PCAn_CHx_CCAPVUPD Register Bit Descriptions
Bit
Name
31:18
Reserved
17:0
CCAPVUPD
Function
Must write reset value.
Channel Compare Update Value.
This field will be transferred to the CCAPV field when a PCA counter/timer overflow
occurs if updates are allowed (NOUPD = 0). The CUPDCF bit will be set to 1 by
hardware when the transfer operation is complete.
Rev. 1.0
571
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
29.10. PCAn_CHx Register Memory Map
Table 29.13. PCAn_CHx Memory Map
PCAn_CHx_CONTROL PCAn_CHx_MODE Register Name
ALL Offset
0x10
0x0
Access Methods
ALL | SET | CLR
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Reserved
Reserved
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
CIOVFIEN
Bit 11
Bit 10
Reserved
CMD
Bit 9
CCIEN
Bit 8
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Bit 4
PWMMD
CUPDCF
Bit 3
CNCAPEN
Bit 2
CPCAPEN
Bit 1
COSEL
COUTST
Bit 0
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PCA0_CH0 = 0x4000_F000, PCA0_CH1 = 0x4000_F040, PCA1_CH0
= 0x4001_0000, PCA1_CH1 = 0x4001_0040
572
Rev. 1.0
PCAn_CHx_CCAPVUPD PCAn_CHx_CCAPV Register Name
0x30
0x20
ALL Offset
ALL
ALL
Access Methods
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Reserved
Reserved
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CCAPVUPD
CCAPV
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 29.13. PCAn_CHx Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: PCA0_CH0 = 0x4000_F000, PCA0_CH1 = 0x4000_F040, PCA1_CH0
= 0x4001_0000, PCA1_CH1 = 0x4001_0040
Rev. 1.0
573
Programmable Counter Array (PCA0 and PCA1)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
30. Phase-Locked Loop (PLL0)
This section describes the phase-locked loop (PLL) module, and is applicable to all products in the following device
families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the PLL block, which is used by all device families covered in this document.
Note that features related to the USB oscillator are only available on the SiM3U1xx device family.
30.1. PLL Features
The PLL module includes the following features:
Five
output ranges with output frequencies ranging from 23 to 80 MHz (can also be divided by up to 128 to
provide lower system clock speeds).
Multiple reference frequency inputs.
Three output modes: free-running DCO, frequency-locked, and phase-locked.
Ability to sense the rising edge or falling edge of the reference source.
DCO frequency LSB dithering to provide finer average output frequencies.
Spectrum spreading to reduce generated system noise.
Low jitter and fast lock times.
Ability to suspend all output frequency updates (including dithering and spectrum spreading) using the
STALL bit during jitter-sensitive measurements.
PLLn Module
RTCn Oscillator
Divided Low Power Oscillator
EXTOSCn Clock
USBn Oscillator
Reference
Frequency
(FREF)
N+1
M+1
Phase and
Frequency Adjuster
OUTMD
CAL
DITHER
RANGE
Digitally-Controlled
Oscillator (DCO)
Figure 30.1. PLL Block Diagram
574
Rev. 1.0
Spectrum
Spreading
Output
Frequency
(FDCO)
30.2. Overview
The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in free-running
DCO mode without a reference frequency, frequency-locked mode with a reference frequency, or phase-locked
mode with a reference frequency. The reference frequency for frequency-lock and phase-lock modes can be
sourced from multiple sources (including a dedicated USB oscillator or external oscillator) to provide maximum
flexibility for different application needs. Because the PLL module generates its own clock, the DCO can be locked
to a particular reference frequency and then moved to free-running mode to reduce system power or noise.
30.3. Interrupts
A PLL interrupt can be generated whenever the PLL module locks to or unlocks from the reference frequency in
either frequency-lock or phase-lock mode. The LCKI flag indicates the locked state of the module, and the
LCKSEN bit configures whether the hardware setting (“is locked”) or clearing (“is unlocked”) the LCKI bit causes
the interrupt, if enabled (LCKIEN = 1). A PLL interrupt can also be generated whenever the module is trying to lock
but saturates (high or low) the DCO period, which indicates that the range should be adjusted. This “is saturated”
interrupt is indicated by the HLMT and LLMT flags and is automatically disabled when the module is locked (LCKI
= 1). It will automatically become active again if locked status is lost for any reason (LCKI = 0). The LCKI interrupt
is level sensitive, and the HLMT and LLMT interrupts are edge sensitive. All three flags (LCKI, HLMT, and LLMT)
can be cleared by setting OUTMD to 00b or 01b.
30.4. Output Modes
The PLL module has three available output modes: free-running DCO, frequency-lock, and phase-lock.
30.4.1. Free-Running DCO Mode
The PLL module includes its own Digitally-Controlled Oscillator (DCO) and does not need a reference frequency to
generate a clock output. Using the module in this matter is called free-running DCO mode and is enabled by setting
OUTMD to 01b.
When in free-running DCO mode, the output frequency of the DCO is determined by the RANGE, CAL, and
DITHER settings. The spectrum spreading feature is also available in free-running DCO mode.
The output frequency of the DCO in free-running DCO mode is given by Equation 30.1:
1
F DCOavg = --------------------------------------------------------------------------------------DITHER
T(RANGE) + T(CAL + ------------------------)
16
Equation 30.1. Average DCO Output Frequency
TDCO
FDCO
Figure 30.2. Free-Running DCO Mode
More information on dithering and spectrum spreading can be found in Section 30.5.1 and Section 30.5.2.
30.4.1.1. Free-Running DCO PLL Setup
To set up the PLL for free-running DCO mode:
1. If the output of the DCO will be used as the AHB clock and the AHB clock will be increasing in frequency,
program the flash read timing bits to the appropriate value for the new clock rate.
2. Program the CAL field to the maximum value.
Rev. 1.0
575
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
3. Program the desired output range by setting the RANGE field.
4. Program the desired output frequency by setting the CAL field.
5. (Optional) Enable dithering by setting DITHER to a non-zero value.
6. (Optional) Enable spectrum spreading by writing a non-zero value to SSAMP.
7. Set OUTMD to 01b.
8. Switch the AHB clock source to the DCO output using the device’s clock control module.
9. If the output of the DCO will be used as the AHB clock and the AHB clock will be decreasing in frequency,
program the flash read timing bits to the appropriate value for the new clock rate.
If the CAL, DITHER, or SSAMP DCO settings need to be changed when the output frequency running, the settings
can be modified directly even when using the DCO output as the AHB clock. Any changes to RANGE should be
made while the DCO output is off (OUTMD = 00b).
30.4.2. Frequency-Lock Mode
In frequency-lock mode, the PLL module will ensure the frequency of the DCO output (FDCO) is derived from the
reference frequency (FREF) correctly based on the values of N and M, but the phase of the output frequency may
not necessarily match the reference source. Any changes in frequency on the reference will propagate through to
the DCO output frequency. frequency-lock mode is enabled by setting OUTMD to 10b.
N+1
F DCO = F REF  -------------M+1
Equation 30.2. PLL Output Frequency
TREF
FREF
TDCO
FDCO
Figure 30.3. Frequency-Lock Mode
The hardware will take the firmware-set RANGE, N, and M values and automatically adjust CAL to match the
reference frequency. Additionally, finer frequency matching can be achieved by enabling automatic dithering
(DITHEN = 1), and generated noise can be reduced by enabling spectrum spreading.
576
Rev. 1.0
30.4.3. Phase-Lock Mode
Phase-Lock mode matches the phase and frequency of the DCO output (FDCO) to the reference frequency (FREF)
based on the values of N and M. Any drift or changes in phase and frequency on the reference will propagate
through to the DCO output phase and frequency. Phase-Lock mode is enabled by setting OUTMD to 11b.
N+1
F DCO = F REF  -------------M+1
TREF
FREF
TDCO
FDCO
Figure 30.4. Phase-Lock Mode
The hardware will take the firmware-set RANGE, N, and M values and automatically adjust CAL to match the
reference phase and frequency. Additionally, finer frequency matching can be achieved by enabling automatic
dithering (DITHEN = 1), and generated noise can be reduced by enabling spectrum spreading.
30.4.4. Frequency-Lock and Phase-Lock Differences
In frequency-lock mode, the frequency error is bounded by definition, but this error will not necessarily approach
zero over time. phase-lock mode guarantees the average frequency error approaches zero over time. As a result,
the PLL module may need to make DCO output period corrections more often in phase-lock mode, resulting in
higher output jitter. Additionally, frequency-lock mode generates less overshoot and undershoot compared to
phase-lock mode, resulting in a better transient response.
frequency-lock mode is sufficient for most applications that require a specific output frequency.
Rev. 1.0
577
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
30.4.5. Selecting N and M Values
In frequency-lock and phase-lock modes, the output jitter and lock time of the PLL module are dependent upon the
N and M factors and the DCO output frequency. Larger values of N and M increase lock time but decrease output
jitter. This relationship is shown in Figure 30.5. Longer DCO output periods (slower frequencies) increase lock time.
Equation 30.3 gives the approximate equation for DCO output jitter in frequency-lock or phase-lock modes.
1
1
t   t DCO   -------------- + -------------
 N + 1 2500
Equation 30.3. Output Jitter
Equation 30.4 and Equation 30.5 approximate the maximum DCO lock time in frequency-lock or phase-lock modes
(the PLL may lock faster). In the equations, tREF is the period of the reference clock, tDCO is the period of the DCO
output, and tINIT is the period of the DCO before enabling the PLL.
t lock  t REF   M + 1  + 2  t REF + 32  t INIT
Equation 30.4. DCO Lock Time with LOCKTH = 0
t lock  t REF   M + 1    LOCKTH + 1  + 2  t REF + 32  t DCO
Equation 30.5. DCO Lock Time with LOCKTH > 0
N = 128
Jitter ( T)
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
N = 600
N = 1800
N = 3000
N = 1200
N = 2400
N = 3600
Lock Time (tlock)
Figure 30.5. Jitter vs. Lock Time for Values of N
578
Rev. 1.0
The value of M and N should be selected such that the lock time and jitter requirements of the system are met.
Alternatively, a small value of N can be used initially to speed the locking process, and then a larger value of N (and
consequently M) can be re-written to the registers to reduce output jitter once the module is locked to the
reference. Once N is selected, the desired output frequency dictates the corresponding value of M. This method is
discussed in detail in Section 30.6.2. The process for updating the PLL register values when the DCO is running is
discussed in Section 30.4.5.1.
30.4.5.1. Initial Frequency-Lock and Phase-Lock PLL Setup
To set up the PLL for frequency-lock or phase-lock mode:
1. Ensure that the reference clock to be used (internal or external) is running and stable.
2. If the output of the PLL will be used as the AHB clock and the AHB clock will be increasing in frequency,
program the flash read timing bits to the appropriate value for the new clock rate.
3. Set the REFSEL bits to select the desired reference clock for the PLL DCO.
4. Program the CAL field to the maximum value.
5. Program the desired output range by setting the RANGE field.
6. Program the appropriate N and M values to achieve the desired output frequency.
7. Select the edge (rising or falling) of the reference frequency the DCO output should lock to using the
EDGSEL bit.
8. (Recommended) Enable dithering by setting DITHEN.
9. (Optional) Enable spectrum spreading by writing a non-zero value to SSAMP.
10. (Optional) Enable CAL saturation interrupts by setting LMTIEN to 1.
11. (Optional) Enable PLL interrupts and set LCKSEN to 1 to enable the “is locked” interrupt when the
hardware sets the LCKI flag to 1.
12. Set OUTMD to 10b for frequency-lock mode or 11b for phase-lock mode.
13. Wait for the LCKI interrupt (if interrupts are enabled) or poll on LCKI until it changes from 0 to 1. If RANGE
is set to the proper value, the HLMT and LLMT saturation interrupts should not occur. If these interrupts are
enabled and trigger, this indicates that the RANGE setting is too low or high for the desired output
frequency. The RANGE setting can be adjusted by writing OUTMD to 00b, writing RANGE with the new
value, and setting OUTMD back to 10b for frequency-lock mode or 11b for phase-lock mode.
14. (Optional) Switch the value of LCKSEN to 0 to enable interrupts if the PLL module loses lock on the
reference frequency.BBREN
15. Switch the AHB clock source to the DCO output using the CONTROL register in the CLKCTRL module.
16. If the output of the PLL will be used as the AHB clock and the AHB clock will be decreasing in frequency,
program the flash read timing bits to the appropriate value for the new clock rate.
30.4.5.2. Modifying the RANGE Setting while the PLL is Locked and Running
If the PLL RANGE setting needs to be changed when the output frequency is locked and running, implement the
following procedure:
1. Switch the AHB clock to another clock source that is running and stable.
2. Set the OUTMD bits to 00b.
3. Program the CAL field to the maximum value.
4. Modify the RANGE setting as desired.
5. If interrupts are enabled, set LCKSEN to 1 to enable the “is locked” interrupt when the LCKI flag is set to 1.
6. Set the OUTMD bits to 10b for frequency-lock mode or 11b for phase-lock mode. The PLL module will
relock to the reference frequency using the new settings.
7. Wait for the LCKI interrupt (if interrupts are enabled) or poll on LCKI until it changes from 0 to 1. If RANGE
is set to the proper value, the HLMT and LLMT saturation interrupts should not occur.
8. (Optional) Switch the value of LCKSEN to 0 to enable interrupts if the PLL module loses lock.
Rev. 1.0
579
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
9. Switch the AHB clock source to the DCO output using the CONTROL register in the CLKCTRL module.
30.4.5.3. Modifying PLL Settings (other than RANGE) while the PLL is Locked and Running
If the other PLL settings need to be changed when the output frequency is locked and running, the following
procedure should be implemented:
1. Set the OUTMD bits to 01.
2. Modify the settings as desired.
3. If interrupts are enabled, set LCKSEN to 1 to enable the “is locked” interrupt when the LCKI flag is set to 1.
4. Set the OUTMD bits to 10b for frequency-lock mode or 11b for phase-lock mode. The PLL module will
relock to the reference frequency using the new settings.
5. Wait for the LCKI interrupt (if interrupts are enabled) or poll on LCKI until it changes from 0 to 1. If RANGE
is set to the proper value, the HLMT and LLMT saturation interrupts should not occur.
6. (Optional) Switch the value of LCKSEN to 0 to enable interrupts if the PLL module loses lock.
If a sensitive analog measurement needs to be taken, the automatic DCO output frequency adjustment (including
dithering and spectrum spreading) can be temporarily halted by setting the STALL bit. The module will not resume
the output updates until STALL has been cleared to 0 by firmware.
30.5. Additional Features
In addition to three output modes, the PLL module has the additional features of output frequency dithering and
spectrum spreading.
30.5.1. Output Frequency Dithering
The CAL field provides 12 bits of frequency steps within a particular output range, determined by RANGE. The
output frequency dithering feature allows an average frequency of finer resolution than CAL alone can provide,
though the instantaneous frequency will not be equal to the average frequency at a particular moment in time. The
dithering setting controls how often a 1 is added to CAL to achieve the desired average frequency. The DITHER
value acts like fractional bits of CAL.
In free-running DCO mode (OUTMD set to 01b), firmware can set the dithering to a particular setting by writing the
desired value to DITHER. Dithering can be disabled by writing 0’s to DITHER.
In frequency-lock or phase-lock modes (OUTMD set to 10b or 11b), automatic dithering is enabled by setting
DITHEN to 1 and will cause the hardware to automatically set these dithering bits to achieve average frequencies
the CAL setting would normally not be able to achieve. Disabling automatic dithering causes the hardware to
always set DITHER to 0 when in frequency-lock or phase-lock mode.
Setting the STALL bit to 1 will disable dithering until STALL is written with a 0.
TDCO
FDCO(CAL)
FDCO(CAL) + 50% dither
= FDCO(CAL + ½)
FDCO(CAL + 1)
TDCO+1
Figure 30.6. Dithering Timing Example
580
Rev. 1.0
The average DCO output frequency when dithering is enabled is given by Equation 30.1. Dithering is available in
any output mode.
30.5.2. Output Frequency Spectrum Spreading
Spectrum spreading adds intentional noise to the DCO output period to improve system noise performance.
Spectrum spreading is a signed random number of uniform distribution added to the DCO output period to slightly
vary the resulting clock output. This random number has an adjustable amplitude based on the SSAMP field and
an adjustable update rate based on the SSUINV field. Setting the STALL bit to 1 will disable spectrum spreading
until STALL is written with a 0.
Note: The added noise from spectrum spreading is centered about the DCO output period. As a result, the peak frequencies
may exceed the maximum allowable frequency for the AHB clock. As a result, the desired output frequency created by
RANGE, N, and M should be programmed below the maximum allowable frequency to allow some headroom for spectrum spreading.
TDCO
TDCO(SSAMP = 1, SSUINV = 0)
TDCO(SSAMP = 2, SSUINV = 0)
TDCO(SSAMP = 2, SSUINV = 31)
Figure 30.7. Spectrum Spreading Example
The spectrum spreading amplitude has fixed settings of approximately ± 0.1%, ± 0.2%, ± 0.4%, ± 0.8%, or ± 1.6%
of the DCO output period. Equation 30.6 describes the spectrum spreading update rate.
UpdateRate = 4  T DCO   SSUINV + 1 
Equation 30.6. Spectrum Spreading Update Rate
Rev. 1.0
581
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
30.6. Advanced Setup Examples
This section discusses advanced uses of the PLL module to save power or reduce the external components
required by a system.
30.6.1. Temporarily Using a Reference
The PLL module can temporarily use a reference to tune the DCO to a frequency. Once the DCO is locked to the
reference, the PLL can be switched to free-running DCO mode and the reference source can be disabled. This
enables the system to operate at the desired frequency without providing power to the reference source. The DCO
output created in this manner will remain stable at the correct frequency, but may not have tolerances as tight as
the original reference source. The reference can periodically be enabled and the DCO allowed to relock to improve
tolerances, if desired.
To use the PLL module in this manner, follow the procedure in Section 30.4.5.1 for frequency-lock mode and then
set OUTMD to 01b for free-running DCO mode. The hardware-tuned CAL and DITHER settings will remain until
overwritten by either firmware or hardware (OUTMD set to 10b or 11b).
30.6.2. Obtaining Fast Lock Times and Low Output Jitter
As discussed in Section 30.4.4, the value of N affects both the lock time and the output jitter of the DCO output
frequency. To obtain both a fast lock time and low output jitter, a small value of N can be used initially to speed the
locking process, and then a larger value of N can be re-written to the registers to reduce output jitter once the
module is locked to the reference.
For example, a DCO output frequency of approximately 70 MHz is desired using a reference clock of 48 MHz.
Using Equation 30.2, if N is 500, the corresponding value of M is 342 for a desired output frequency of 70 MHz. If N
is 3000, the corresponding value of M is 2056.
To obtain a fast lock time and a long-term low output jitter:
1. Follow the procedure in Section 30.4.5.1 for frequency-lock or phase-lock mode, setting N to 128 and M to
87.
2. Once the DCO output is LCKI, set OUTMD to 01b for free-running DCO mode.
3. Change N to 3000 and M to 2056.
4. Set OUTMD back to 10b for frequency-lock mode or 11b for phase-lock mode.
582
Rev. 1.0
30.7. PLL0 Registers
This section contains the detailed register descriptions for PLL0 registers.
Register 30.1. PLL0_DIVIDER: Reference Divider Setting
Bit
31
30
29
28
27
26
25
24
23
22
Name
Reserved
N
Type
R
RW
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Name
Reserved
M
Type
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PLL0_DIVIDER = 0x4003_B000
Table 30.1. PLL0_DIVIDER Register Bit Descriptions
Bit
Name
31:28
Reserved
27:16
N
Function
Must write reset value.
N Divider Value.
Selects the reference clock multiplier. Valid values include 32 to 4095 (values below
31 are invalid and may cause incorrect behavior). The frequency-lock or phase-lock
output frequency is the result of the equation:
N+1
F DCO = F REF  -------------M+1
15:12
Reserved
Must write reset value.
Notes:
1. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
Rev. 1.0
583
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Table 30.1. PLL0_DIVIDER Register Bit Descriptions
Bit
Name
11:0
M
Function
M Divider Value.
Selects the reference clock divider. Valid values include the entire 12-bit range of M
(0 to 4095). The frequency-lock or phase-lock output frequency is the result of the
equation:
N+1
F DCO = F REF  -------------M+1
Notes:
1. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
584
Rev. 1.0
29
28
27
26
Name
OUTMD
DITHEN
Reserved
Type
RW
RW
RW
RW
25
24
23
22
21
20
19
18
17
16
LOCKTH
Reserved
REFSEL
RW
R
RW
R
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
0
0
0
Name
Reserved
LMTIEN
0
LCKIEN
0
LCKPOL
Reset
LLMTF
Reserved
HLMTF
31
LCKI
Bit
STALL
30
EDGSEL
Register 30.2. PLL0_CONTROL: Module Control
Reserved
Type
R
RW
RW
RW
R
1
0
0
Reset
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PLL0_CONTROL = 0x4003_B010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 30.2. PLL0_CONTROL Register Bit Descriptions
Bit
Name
31:30
OUTMD
Function
PLL Output Mode.
Sets the DCO output mode.
All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static
while OUTMD is set to frequency-lock or phase-lock modes. If RANGE setting
changes are required, turn off the DCO output, write the maximum value to CAL,
write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting the module in Free-Running Mode, writing to the
registers, and re-enabling frequency-lock or phase-lock mode.
00: DCO output is off.
01: DCO output is in Free-Running DCO mode.
10: DCO output is in frequency-lock mode (reference source required).
11: DCO output is in phase-lock mode (reference source required).
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
2. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
Rev. 1.0
585
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Table 30.2. PLL0_CONTROL Register Bit Descriptions
Bit
Name
29
EDGSEL
Function
Edge Lock Select.
Selects between locking on the rising edge or falling edge of the reference frequency in frequency-lock and phase-lock modes. The setting of this bit has no effect
in Free-Running DCO mode.
0: Lock DCO output frequency to the falling edge of the reference frequency.
1: Lock DCO output frequency to the rising edge of the reference frequency.
28
DITHEN
Dithering Enable.
Enables automatic dithering on the DCO output period in frequency-lock and phaselock modes.
The DITHER field is used to generate a 1-bit dither of the DCO output frequency.
This provides better performance and generally reduces the overall jitter in frequency-lock and phase-lock modes. Automatic dithering can be disabled by clearing DITHEN to 0, which forces the hardware to always generate DITHER values of
0. When OUTMD is set to 01b, firmware can write a non-zero value to the DITHER
bits to enable dithering, even if DITHEN is 0. Setting DITHEN to 1 in Free-Running
DCO mode will have no effect.
0: Automatic DCO output dithering disabled.
1: Automatic DCO output dithering enabled.
27
Reserved
26
STALL
Must write reset value.
DCO Output Updates Stall.
When STALL is set to 1, the phase-lock and frequency-lock modes are temporarily
disabled. Spectrum spreading and dithering are also disabled. This is useful for providing the quietest environment possible for sensitive analog measurements. The
phase-lock and frequency-lock modes, spectrum spreading, and dithering, are reenabled when STALL is cleared to 0.
0: In phase-lock and frequency-lock modes, spectrum spreading, and dithering
operate normally, if enabled.
1: In phase-lock and frequency-lock modes, spectrum spreading, and dithering are
prevented from updating the output of the DCO.
25:22
Reserved
Must write reset value.
21:20
LOCKTH
Lock Threshold Control.
Lock is deterministic based on the number of (M+1)xTREF cycles over which the
algorithm has operated. Assuming lock is possible given the present RANGE setting, phase lock is guaranteed after one (M+1)xTREF cycle. The value of LOCKTH
sets the number of extra (M+1)xTREF cycles to wait before declaring lock. It is recommended to set the LOCKTH field to 1 if the PLL will be switched to free-running
mode immediately after lock.
19:18
Reserved
Must write reset value.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
2. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
586
Rev. 1.0
Table 30.2. PLL0_CONTROL Register Bit Descriptions
Bit
Name
17:16
REFSEL
Function
Reference Clock Selection Control.
00: PLL reference clock (FREF) is the RTC0 oscillator (RTC0OSC).
01: PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0).
10: PLL reference clock (FREF) is the external oscillator output (EXTOSC0).
11: PLL reference clock (FREF) is the USB0 oscillator (USB0OSC).
15:12
Reserved
Must write reset value.
11
LCKPOL
Lock Interrupt Polarity.
Sets the state of LCKI that causes the PLL lock state interrupt to occur, if enabled.
0: The lock state PLL interrupt will occur when LCKI is 0.
1: The lock state PLL interrupt will occur when LCKI is 1.
10
LCKIEN
Locked Interrupt Enable.
0: The PLL locking does not cause an interrupt
1: An interrupt is generated if LCKI matches the state selected by LCKPOL.
9
LMTIEN
Limit Interrupt Enable.
Enables interrupt generation if the DCO output frequency saturates high or low, preventing the DCO from reliably locking to the reference frequency or phase. This
interrupt will not be generated while the DCO is locked (LCKI = 1).
0: Saturation (high and low) interrupt disabled.
1: Saturation (high and low) interrupt enabled.
8:3
Reserved
2
LCKI
Must write reset value.
Phase-Lock and Frequency-Lock Locked Interrupt Flag.
Indicates when the PLL module DCO is locked to the reference clock. In phase-lock
mode, this indicates that the DCO is phase-locked with the reference clock. In frequency-lock mode, this indicates that the DCO is frequency-locked (not necessarily
phase-locked) with the reference clock. This bit will also assert the level-sensitive
lock state interrupt, if enabled. This bit is automatically set and cleared by hardware,
but can also be manually cleared by writing 00b or 01b to OUTMD.
0: DCO is disabled or not locked.
1: DCO is enabled and locked.
1
HLMTF
CAL Saturation (High) Flag.
Indicates when the DCO output period is saturated high and the DCO cannot lock
reliably, so the RANGE value should be decreased. This flag is not automatically
cleared by hardware and must be cleared by software by writing 00b or 01b to
OUTMD.
0: DCO period is not saturated high.
1: DCO period is saturated high.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
2. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
Rev. 1.0
587
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Table 30.2. PLL0_CONTROL Register Bit Descriptions
Bit
Name
0
LLMTF
Function
CAL Saturation (Low) Flag.
Indicates when the DCO output period is saturated low and the DCO cannot lock
reliably, so the RANGE value should be increased. This flag is not automatically
cleared by hardware and must be cleared by software by writing 00b or 01b to
OUTMD.
0: DCO period is not saturated low.
1: DCO period is saturated low.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
2. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
588
Rev. 1.0
Register 30.3. PLL0_SSPR: Spectrum Spreading Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
SSUINV
Reserved
SSAMP
Type
R
RW
R
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
PLL0_SSPR = 0x4003_B020
Table 30.3. PLL0_SSPR Register Bit Descriptions
Bit
Name
Function
31:13
Reserved
Must write reset value.
12:8
SSUINV
Spectrum Spreading Update Interval.
The update interval is given by the following equation:
UpdateInterval = 4  T DCO   SSUINV + 1 
7:3
Reserved
2:0
SSAMP
Must write reset value.
Spectrum Spreading Amplitude.
000: Disable Spectrum Spreading.
001: Spectrum Spreading set to approximately + 0.1% of TDCO.
010: Spectrum Spreading set to approximately + 0.2% of TDCO.
011: Spectrum Spreading set to approximately + 0.4% of TDCO.
100: Spectrum Spreading set to approximately + 0.8% of TDCO.
101: Spectrum Spreading set to approximately + 1.6% of TDCO.
110-111: Reserved.
Notes:
1. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
Rev. 1.0
589
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Register 30.4. PLL0_CALCONFIG: Calibration Configuration
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Name
Reserved
RANGE
Type
R
RW
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CAL
DITHER
Type
RW
RW
Reset
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
Register ALL Access Address
PLL0_CALCONFIG = 0x4003_B030
Table 30.4. PLL0_CALCONFIG Register Bit Descriptions
Bit
Name
31:19
Reserved
18:16
RANGE
Function
Must write reset value.
DCO Range.
Determines the output frequency range of the DCO.
000: DCO operates from 23 to 37 MHz.
001: DCO operates from 33 to 54 MHz.
010: DCO operates from 45 to 71 MHz.
011: DCO operates from 53 to 80 MHz.
100: DCO operates from 73 to 80 MHz.
101-111: Reserved.
15:4
CAL
DCO Calibration Value.
This value adjusts the output period of the PLL module DCO in fine steps. Increasing CAL increases the DCO output period and decreases the DCO output frequency.
Notes:
1. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
590
Rev. 1.0
Table 30.4. PLL0_CALCONFIG Register Bit Descriptions
Bit
Name
3:0
DITHER
Function
DCO Dither Setting.
The DITHER bits control how often a 1 is added to CAL to create an average frequency in between the two CAL settings (CAL and CAL + 1). The DITHER value
acts like fractional bits of CAL.
In Free-Running DCO mode, firmware can write these bits to select a specific dithering setting. Writing 0's to this field disables dithering. The value of DITHEN has no
effect in this mode.
When DITHEN is set to 1 in frequency-lock or phase-lock modes, the hardware will
automatically adjust the DITHER bits. If DITHEN is set to 0 in these modes, the
hardware will force the DITHER bits to 0.
Notes:
1. All PLL register fields except LCKPOL, LMTIEN, and STALL must remain static while OUTMD is set to frequency-lock
or phase-lock modes. If RANGE setting changes are required, turn off the DCO output, write the maximum value to
CAL, write to RANGE, and re-enable frequency-lock or phase-lock mode. All other settings can be changed by putting
the module in Free-Running Mode, writing to the registers, and re-enabling frequency-lock or phase-lock mode.
Rev. 1.0
591
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
30.8. PLL0 Register Memory Map
Table 30.5. PLL0 Memory Map
PLL0_CALCONFIG PLL0_SSPR PLL0_CONTROL PLL0_DIVIDER Register Name
ALL Address
0x4003_B030
0x4003_B020 0x4003_B010
0x4003_B000
Access Methods
ALL
ALL
ALL | SET | CLR
ALL
Bit 31
OUTMD
Bit 30
Reserved
Bit 29
EDGSEL
Bit 28
DITHEN
Reserved
Bit 27
STALL
Bit 26
Reserved
Bit 25
Bit 24
Reserved
Bit 23
Reserved
Bit 22
N
Bit 21
LOCKTH
Bit 20
Bit 19
Reserved
Bit 18
RANGE
Bit 17
REFSEL
Bit 16
Bit 15
Bit 14
Reserved
Reserved
Bit 13
Bit 12
LCKPOL
Bit 11
SSUINV
LCKIEN
Bit 10
CAL
LMTIEN
Bit 9
Bit 8
Bit 7
Bit 6
Reserved
M
Reserved
Bit 5
Bit 4
Bit 3
LCKI
Bit 2
DITHER
SSAMP
HLMTF
Bit 1
LLMTF
Bit 0
Phase-Locked Loop (PLL0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
592
Rev. 1.0
31. Real Time Clock and Low Frequency Oscillator (RTC0)
This section describes the Real Time Clock and Low Frequency Oscillator (RTC) module, and is applicable to all
products in the following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the RTC block, which is used by all device families covered in this document.
31.1. RTC Features
The RTC module includes the following features:
32-bit
timer (supports up to 36 hours) with three separate alarms.
for one alarm to automatically reset the RTC timer.
Missing clock detector.
Can be used with the internal low frequency oscillator (LFOSC0), an external 32.768 kHz crystal (no
additional resistors or capacitors necessary), or with an external CMOS clock.
Programmable internal loading capacitors support a wide range of external 32.768 kHz crystals.
Operates directly from VDD and remains operational even when the device goes into its lowest power
down mode.
Two buffered outputs provide an accurate, low frequency clock to other devices:
Option
RTC0TCLK_OUT:
This output connects via the crossbar to an IO pin. Because the crossbar is powered down in
the sleep mode, this output is not suitable for applications requiring the RTC clock output in sleep mode.
RTC0OSC_OUT; This output connects directly to an IO pin (consult data sheet pin definition) and does not pass
through the crossbar. This output should be used for applications requiring the RTC clock output in sleep mode."
External CMOS Clock
RTCn Module
LFOSCn clock
RTC1
To CLKCTRLn
To WDTIMERn
Crossbar
RTCnTCLK_OUT
External Crystal
RTCnTCLK
RTC1
32.768
kHz
Alarm 2 Compare
Low
Frequency
Oscillator
RTC2
Alarm 1 Compare
Alarm 0 Compare
LFOSCADJ
RTC1
RTC2
RTC External
Oscillator
Control
1
Auto
Reset
RTC Timer
0
CLKSEL
Load
Capacitance
To CLKCTRLn
To LPTIMERn
To PLLn
SETCAP
Missing Clock
Detector
OSCFI
RTCnOSC_OUT
RTCOEN
Figure 31.1. RTC Block Diagram
Rev. 1.0
593
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
31.2. Overview
The RTC module allows a maximum of 36 hour 32-bit independent time-keeping when used with a 32.768 kHz
watch crystal. The RTC provides three alarm events in addition to a missing clock event, which can also function as
an interrupt, reset or wakeup source.
The RTC module includes internal loading capacitors that are programmable to 16 discrete levels, allowing
compatibility with a wide range of crystals.
The RTCnOSC output can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to
other devices while the core is in its lowest power down mode. The module also includes a low power internal low
frequency oscillator that reduces sleep mode current and is available for other modules to use as a clock source.
31.3. Clocking
The RTC module clocks from its own timebase independent of the AHB clock. This timebase can be derived from
an external CMOS clock, an external 32.768 kHz crystal, or an internal low frequency oscillator.
31.3.1. Crystal Mode
When using crystal mode, a 32.768 kHz crystal should be connected between RTC1 and RTC2. No other external
components are required. The following steps show how to start the RTC crystal oscillator in firmware:
1. Configure the RTC1 and RTC2 pins as analog inputs using the device port configuration module.
2. Disable automatic gain control (AGCEN = 0) and enable bias doubling (BDEN = 1).
3. Program the RTCLC field.
4. Enable automatic load capacitance stepping (ASEN = 1).
5. Select the RTC oscillator (CLKSEL = 0).
6. Enable the crystal oscillator (CRYSEN = 1).
7. Wait 20 ms.
8. Poll the clock valid (CLKVF) until the crystal oscillator stabilizes.
9. Poll the load capacitance ready (LRDYF) flag until the load capacitance reaches its programmed value.
10. Enable automatic gain control (AGCEN = 1) and disable bias doubling (BDEN = 0) for maximum power
savings.
11. Enable the missing clock detector (MCLKEN = 1).
12. Wait 2 ms.
13. Clear OSCFI.
14. If serving as a wake up source from a low-power mode, clear the wake-up source flags in the device
power management module.
Figure 31.2 shows the hardware configuration for crystal mode.
594
Rev. 1.0
SiM3xxxx
Load Capacitance
32.768
kHz
RTC External
Oscillator Control
RTC1
RTC2
Figure 31.2. Crystal Mode Hardware Configuration
Rev. 1.0
595
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
31.3.2. External CMOS Clock Mode
The RTC oscillator may also be driven by an external CMOS clock. The CMOS clock should be applied to RTC1,
and RTC2 should be left floating. In this mode, the external CMOS clock should have a minimum voltage swing of
400 mV without exceeding VDD or dropping below VSS. Bias levels closer to VDD will result in lower I/O power
consumption because the RTC1 pin has a built-in weak pull-up.
To use the module with an external CMOS clock:
1. Configure the RTC1 as an analog input using the device port configuration module. RTC2 may be left
floating or used for other functions.
2. Disable automatic gain control (AGCEN = 0) and disable bias doubling (BDEN = 0).
3. Select the lowest bias setting (RTCLC = 0).
4. Select the RTC oscillator (CLKSEL = 0).
5. Enable the crystal oscillator (CRYSEN = 1).
6. Wait 2 ms.
7. Enable the missing clock detector (MCLKEN = 1).
8. Wait 2 ms.
9. Check the OSCFI flag to ensure a valid clock is present on RTC1.
10. If serving as a wake up source from a low-power mode, clear the wake-up source flags in the device
power management module.
The CLKVF bit is indeterminate when using a CMOS clock with the RTC module.
Figure 31.3 shows the hardware configuration for external CMOS clock mode.
SiM3xxxx
Load Capacitance
RTC1
RTC External
Oscillator Control
RTC2
Figure 31.3. External CMOS Clock Mode Hardware Configuration
31.3.3. Low Frequency Oscillator
The low frequency oscillator (LFOSC0) provides a low power internal clock source for the RTC timer. No external
components are required to use the low frequency oscillator and the RTC1 and RTC2 pins do not need to be
shorted together. The typical oscillation frequency of the oscillator is 16.4 kHz, but may vary depending on supply
voltage, temperature and process. Consult the electrical characteristics tables in the device data sheet for more
information.
To use the low frequency oscillator with the RTC module:
1. Enable the low frequency oscillator (LFOSCEN = 1). The oscillator starts oscillating instantaneously.
2. Select the low frequency oscillator as the RTC timer clock source (CLKSEL = 1).
3. Disable the crystal oscillator (CRYSEN = 0).
596
Rev. 1.0
4. If serving as a wake up source from a low-power mode, clear the wake-up source flags in the device power
management module.
When using the low frequency oscillator as its clock source, the RTC module increments bit 1 of the 32-bit timer
instead of bit 0, effectively multiplying the oscillator frequency by 2.
31.3.4. RTC Timer Clock Selection
The RTC timer clock (RTCnTCLK) is configured by the Clock Select (CLKSEL) bits to be either the RTC Crystal
Oscillator (RTCnOSC), an external CMOS clock, or the low frequency oscillator (LFOSCn).
31.3.5. RTC Clock Outputs
31.3.5.1. RTC0OSC_OUT
If the RTC oscillator output is enabled (RTCOEN = 1), the RTCnOSC clock is buffered and output to the
RTCnOSC_OUT pin for use by external modules. This output may still be enabled in sleep mode. Consult data
sheet pin definition for location of the RTCnOSC_OUT function
31.3.5.2. RTC0TCLK_OUT
If the RTC0TCLK_OUT is enabled in the crossbar, the RTC timer clock is output onto the RTC0TCLK_OUT pin.
Depending on the CLKSEL configuration, the RTC timer clock can be either the Low Frequency Oscillator
(LFOOSC) or the RTC External Oscillator (RTCOSC). This output cannot be enabled in sleep mode.
31.3.6. Programmable Load Capacitance
The programmable load capacitance has 16 values to support a wide range of crystal oscillators. If automatic load
capacitance stepping is enabled (ASEN = 1), the crystal load capacitors start at the smallest setting to allow a fast
startup time, then increase the capacitance until reaching the final programmed value in the RTCLC field. The
RTCLC setting specifies the amount of internal load capacitance and does not include any stray PCB capacitance.
Once the final programmed loading capacitance value is reached, the hardware will set the load ready (LRDYF)
flag to 1.
Table 31.1 shows the equivalent crystal load capacitance for RTCLC settings.
Table 31.1. Load Capacitance Settings
RTCLC Value
Crystal Load Capacitance
Equivalent Capacitance seen
on RTC1 and RTC2
0
4.0 pF
8.0 pF
1
4.5 pF
9.0 pF
2
5.0 pF
10.0 pF
3
5.5 pF
11.0 pF
4
6.0 pF
12.0 pF
5
6.5 pF
13.0 pF
6
7.0 pF
14.0 pF
7
7.5 pF
15.0 pF
8
8.0 pF
16.0 pF
9
8.5 pF
17.0 pF
10
9.0 pF
18.0 pF
11
9.5 pF
19.0 pF
Rev. 1.0
597
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Table 31.1. Load Capacitance Settings
598
RTCLC Value
Crystal Load Capacitance
Equivalent Capacitance seen
on RTC1 and RTC2
12
10.5 pF
21.0 pF
13
11.5 pF
23.0 pF
14
12.5 pF
25.0 pF
15
13.5 pF
27.0 pF
Rev. 1.0
31.3.7. Automatic Gain Control (Crystal Mode Only) and Bias Doubling
Automatic gain control (AGC) allows the RTC oscillator to trim the oscillation amplitude of a crystal in order to
achieve the lowest possible power consumption. Automatic gain control automatically detects when the oscillation
amplitude has reached a point where it safe to reduce the drive current, and it may be enabled during crystal
startup. It is recommended to enable AGC in most systems that use the RTC oscillator in crystal mode. The
following are recommended crystal specifications and operating conditions when enabling AGC:
ESR
< 50 k
capacitance < 10 pF
Supply voltage < 3.0 V
Temperature > –20 °C
The chosen crystal should undergo an oscillation robustness test to ensure it will oscillate under the worst case
condition to which the system will be exposed. This worst case condition will occur at the following system
conditions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, bias doubling disabled).
Load
To perform the oscillation robustness test, the RTC oscillator output should be routed to a port pin configured as a
push-pull digital output using the device port configuration module. The positive duty cycle of the output clock can
be used as an indicator of oscillation robustness.
As shown in Figure 31.4, duty cycles less than the low threshold indicate a robust oscillation. As the duty cycle
approaches the high threshold, oscillation becomes less reliable and the risk of clock failure increases. Increasing
the bias current by disabling AGC will always improve oscillation robustness and will reduce the output clock’s duty
cycle. This test should be performed at the worst case system conditions, as results at very low temperatures or
high supply voltage will vary from results taken at room temperature or low supply voltage. Consult the device data
sheet for information on the robust duty cycle range specifications.
Safe Operating Zone
25%
Low Risk of Clock
Failure
low threshold
High Risk of Clock
Failure
high threshold
RTCn Oscillator (RTCnOSC)
Duty Cycle
Figure 31.4. Interpreting Oscillation Robustness (Duty Cycle) Test Results
AGC may be disabled at the cost of increased power consumption. Disabling Automatic Gain Control will provide
the crystal oscillator with higher immunity against the external factors that may cause clock failure.
The bias doubling feature can increase the self-oscillation frequency and allow a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor environmental
conditions, including excessive moisture. The bias doubler should always be enabled during oscillator startup.
Note that when the bias doubler is disabled, the RTC External Oscillator Valid Flag (CLKVF) is disabled and will
always read 0.
Table 31.2 shows a summary of the oscillator AGC and bias doubling settings.
Rev. 1.0
599
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Table 31.2. RTC Bias Settings
Bias Doubling (BDEN)
Setting
AGC (AGCEN) Setting
Power Consumption
off (0)
on (1)
lowest
off (0)
off (0)
low
on (1)
on (1)
high
on (1)
off (0)
highest
31.3.8. Missing Clock Detector
The missing clock detector (MCD) is a one-shot circuit enabled by setting MCLKEN to 1. When the MCD is
enabled, hardware sets the oscillator fail (OSCFI) flag if the RTC oscillator (RTCnOSC) frequency drops below the
missing clock detector trigger frequency given in the device data sheet.
The missing clock detector can only be used for the external crystal oscillator or external CMOS clock modes, and
should be disabled if using the low frequency oscillator clock as the RTC timer clock.
An MCD timeout can trigger an interrupt, wake the device from a low power mode, or reset the device. This feature
should be disabled when making changes to the oscillator settings to avoid undesired interrupts or resets.
31.3.9. Oscillator Crystal Valid Detector
The RTC oscillator crystal valid detector is an oscillation amplitude detector circuit used during crystal startup to
determine when oscillation is nearly stable. Firmware can read the output of this detector using the clock valid
(CLKVF) flag in the CONTROL register. The output of CLKVF is not valid for the first 2 ms after turning on the
crystal oscillator. The CLKVF bit is always low when bias doubling is disabled (BDEN = 0).Therefore, the bias
doubler should be enabled during crystal startup.
The crystal valid detector is not intended for detecting an oscillator failure - once set, the CLKVF will not be reset
unless the external oscillator is disabled. To determine if the oscillator has failed, firmware should use the missing
clock detector and OSCFI flag.
31.4. Accessing the Timer
The RTC timer is a 32-bit counter that increments every RTC oscillator cycle.
Firmware can set the value of the timer by writing a 32-bit value to the SETCAP register and setting the TMRSET.
Hardware will automatically clear TMRSET when the set operation completes.
Firmware can read the current value of the timer by setting the TMRCAP bit. Hardware will automatically clear
TMRCAP when the capture operation completes, and firmware can then read the SETCAP register.
If the AHB clock is greater than 4X the RTC clock, the RTC High Speed Mode Enable bit (HSMDEN) must be set to
allow the timer value to be written or captured.
31.5. Alarms
The RTC timer has three alarm functions that can be set to generate an interrupt, wake the device from a low
power mode, or reset the device at a specific time.
The alarms can be set using the ALARM0, ALARM1, and ALARM2 registers. These 32-bit fields are compared
directly to the 32-bit timer value. Hardware sets the ALM0I, ALM1I, and ALM2I when the corresponding ALARMx
value matches the timer, generating an interrupt, if enabled.
The alarms and the alarm interrupts are enabled setting the ALM0EN, ALM1EN, and ALM2EN bits. Note that there
is not a separate interrupt enable bit for the alarms.
31.5.1. Automatic Timer Reset
The RTC timer includes an automatic reset feature that resets the timer to zero when alarm 0 triggers.
600
Rev. 1.0
When using this auto-reset feature, the alarm match value should always be set to 2 counts less than the desired
match value to account for delays. When using the low frequency oscillator in combination with auto-reset, the
right-justified alarm 0 value should be set to 4 counts less than the desired match value.
The auto-reset feature can be enabled by writing a 1 to ALM0AREN and writing a 1 to ALRM0EN.
Rev. 1.0
601
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
31.6. Interrupts
The RTC module has interrupts for each of the alarms and the missing clock detector. The ALM0I, ALM1I, and
ALM2I flags can cause an interrupt if the corresponding alarm is enabled (ALM0EN, ALM1EN, or ALM2EN set to
1). Hardware sets the oscillator fail (OSCFI) flag to 1 when a missing clock detector event triggers, causing an
interrupt.
31.7. Usage Models
The RTC timer and alarms have two operating modes to suit varying applications.
31.7.1. Usage Mode 1
The first mode uses the RTC timer as a perpetual timebase that is never reset to zero. Every 36 hours, the timer is
allowed to overflow without being stopped or disrupted. Firmware manages the alarm intervals and adds the
intervals to the expired value in the ALARMx registers after each alarm. This allows the alarm match value to
always stay ahead of the timer by one firmware-managed interval. If firmware uses 32-bit unsigned addition to
increment the alarm match values, then it does not need to handle overflows since both the timer and the alarm
match values will overflow in the same manner.
This mode is ideal for applications using a long alarm interval (24 or 36 hours) or have a need for a perpetual
timebase, which is useful in situations where the wake-up interval is constantly changing. For these applications,
firmware can keep track of the number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to
a 48-bit (272 year) perpetual timebase.
31.7.2. Usage Mode 2
The second mode uses the RTC timer as a general purpose up-counter that is auto-reset to zero by hardware after
each alarm 0 event. Hardware manages the alarm intervals in the ALARMx registers, and firmware only needs to
set the alarm intervals once during device initialization. After each alarm 0 event, firmware should keep a count of
the number of alarms that have occurred in order to keep track of time. Alarm 1 and alarm 2 events do not trigger
the timer auto-reset.
This mode is ideal for applications that require minimal firmware intervention or have a fixed alarm interval. This
mode is the most power-efficient since it requires less core processing time per alarm.
602
Rev. 1.0
31.8. RTC0 Registers
This section contains the detailed register descriptions for RTC0 registers.
28
27
26
25
24
Name
CLKSEL
RTCOEN
Reserved
ALM2EN
ALM1EN
23
22
21
20
Type
RW
RW
RW
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
RW
RW
0
0
0
0
3
2
1
0
Name
Reserved
RTCLC
ALM0AREN
RW
RUN
R
MCLKEN
RW
ASEN
Reserved
BDEN
29
CRYSEN
30
AGCEN
31
ALM0EN
Bit
RTCEN
Register 31.1. RTC0_CONFIG: RTC Configuration
Type
R
RW
RW
RW
RW
RW
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_CONFIG = 0x4002_9000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 31.3. RTC0_CONFIG Register Bit Descriptions
Bit
Name
31
RTCEN
Function
RTC Timer Enable.
0: Disable the RTC timer.
1: Enable the RTC timer.
30
CLKSEL
RTC Timer Clock Select.
0: Select the External Crystal or External CMOS Clock as the RTC Timer clock
(RTCnTCLK) source.
1: Select the Low Frequency Oscillator as the RTC Timer clock (RTCnTCLK)
source.
29
RTCOEN
RTC0 External Output Enable.
Setting this bit to 1 allows the RTC module to drive the RTCnOSC on an external
pin.
0: Disable the external RTCnOSC output.
1: Enable the external RTCnOSC output.
28:27
Reserved
Must write reset value.
Rev. 1.0
603
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Table 31.3. RTC0_CONFIG Register Bit Descriptions
Bit
Name
26
ALM2EN
Function
Alarm 2 Enable.
0: Disable RTC Alarm 2.
1: Enable RTC Alarm 2 and Alarm 2 Interrupt.
25
ALM1EN
Alarm 1 Enable.
0: Disable RTC Alarm 1.
1: Enable RTC Alarm 1 and Alarm 1 Interrupt.
24
ALM0EN
Alarm 0 Enable.
0: Disable RTC Alarm 0.
1: Enable RTC Alarm 0 and Alarm 0 Interrupt.
23:19
Reserved
18
AGCEN
Must write reset value.
Automatic Gain Control Enable.
0: Disable automatic gain control.
1: Enable automatic gain control, saving power.
17
CRYSEN
Crystal Oscillator Enable.
0: Disable the crystal oscillator circuitry.
1: Enable the crystal oscillator circuitry.
16
BDEN
Bias Doubler Enable.
The bias doubler should always be enabled at startup in External Crystal Mode.
When the bias doubler is disabled (BDEN=0), the RTC External Oscillator Valid Flag
(CLKVF) is also disabled and will always read 0.
0: Disable the bias doubler, saving power.
1: Enable the bias doubler.
15:8
Reserved
7:4
RTCLC
Must write reset value.
Load Capacitance Value.
This field is the load capacitance value. This field will be automatically set by hardware if automatic load capacitance stepping is enabled (ASEN = 1).
3
ASEN
Automatic Crystal Load Capacitance Stepping Enable.
0: Disable automatic load capacitance stepping.
1: Enable automatic load capacitance stepping.
2
MCLKEN
Missing Clock Detector Enable.
0: Disable the missing clock detector.
1: Enable the missing clock detector. If the missing clock detector triggers, it will
generate an RTC Fail event.
1
RUN
RTC Timer Run Control.
0: Stop the RTC timer.
1: Start the RTC timer running.
604
Rev. 1.0
Table 31.3. RTC0_CONFIG Register Bit Descriptions
Bit
Name
0
ALM0AREN
Function
Alarm 0 Automatic Reset Enable.
Setting this bit to 1 will automatically reset the RTC timer when a Alarm 0 event
occurs. Note that Alarm 0 must be enabled (ALM0EN=1) to use the Automatic
Reset feature.
0: Disable the Alarm 0 automatic reset.
1: Enable the Alarm 0 automatic reset.
Rev. 1.0
605
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Register 31.2. RTC0_CONTROL: RTC Control
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
ALM0I
0
ALM1I
0
ALM2I
0
TMRCAP
0
TMRSET
0
CLKVF
0
OSCFI
0
HSMDEN
Reset
LRDYF
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Type
R
R
RW
RW
R
RW
RW
RW
RW
RW
X
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_CONTROL = 0x4002_9010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 31.4. RTC0_CONTROL Register Bit Descriptions
Bit
Name
31:9
Reserved
8
LRDYF
Function
Must write reset value.
RTC Load Capacitance Ready Flag.
This bit is set by hardware when the load capacitance matches the programmed
value.
0: The load capacitance is currently stepping.
1: The load capacitance has reached its programmed value.
7
HSMDEN
RTC High Speed Mode Enable.
This bit should be set to 1 by firmware if the AHB clock is greater than or equal to 4x
the RTC Timer Clock (RTCnTCLK) frequency.
0: Disable high speed mode. (AHBCLK < 4x RTCnTCLK)
1: Enable high speed mode. (AHBCLK >= 4x RTCnTCLK)
6
OSCFI
RTC Oscillator Fail Interrupt Flag.
This bit is set by hardware when a missing clock detector timeout occurs. This bit
must be cleared by software.
0: Oscillator is running.
1: Oscillator has failed.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
606
Rev. 1.0
Table 31.4. RTC0_CONTROL Register Bit Descriptions
Bit
Name
5
CLKVF
Function
RTC External Oscillator Valid Flag.
Note that the Bias Double must be enabled(BDEN=1) to use this flag. When the
BDEN=0, CLKVF always reads 0.
0: External oscillator is not valid.
1: External oscillator is valid.
4
TMRSET
RTC Timer Set.
Set this bit to 1 to initiate an RTC timer set operation, which copies the value in
SETCAP to the RTC timer. The timer must be running (RUN = 1) in order to set the
timer value. This bit is cleared by hardware when the transfer operation is done.
0: RTC timer set operation is complete.
1: Start the RTC timer set.
3
TMRCAP
RTC Timer Capture.
Set this bit to 1 to initiate an RTC timer capture operation, which copies the current
RTC timer value to SETCAP. This bit is cleared by hardware when the transfer operation is done.
0: RTC timer capture operation is complete.
1: Start the RTC timer capture.
2
ALM2I
Alarm 2 Interrupt Flag.
0: Alarm 2 event has not occurred.
1: Alarm 2 event occurred.
1
ALM1I
Alarm 1 Interrupt Flag.
0: Alarm 1 event has not occurred.
1: Alarm 1 event occurred.
0
ALM0I
Alarm 0 Interrupt Flag.
0: Alarm 0 event has not occurred.
1: Alarm 0 event occurred.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
Rev. 1.0
607
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Register 31.3. RTC0_ALARM0: RTC Alarm 0
Bit
31
30
29
28
27
26
25
24
23
Name
ALARM0[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
ALARM0[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_ALARM0 = 0x4002_9020
Table 31.5. RTC0_ALARM0 Register Bit Descriptions
Bit
Name
31:0
ALARM0
Function
RTC Alarm 0.
The RTC Alarm 0 event will occur when ALARM0 matches the RTC timer value.
608
Rev. 1.0
Register 31.4. RTC0_ALARM1: RTC Alarm 1
Bit
31
30
29
28
27
26
25
24
23
Name
ALARM1[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
ALARM1[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_ALARM1 = 0x4002_9030
Table 31.6. RTC0_ALARM1 Register Bit Descriptions
Bit
Name
31:0
ALARM1
Function
RTC Alarm 1.
The RTC Alarm 1 event will occur when ALARM1 matches the RTC timer value.
Rev. 1.0
609
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Register 31.5. RTC0_ALARM2: RTC Alarm 2
Bit
31
30
29
28
27
26
25
24
23
Name
ALARM2[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
ALARM2[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_ALARM2 = 0x4002_9040
Table 31.7. RTC0_ALARM2 Register Bit Descriptions
Bit
Name
31:0
ALARM2
Function
RTC Alarm 2.
The RTC Alarm 2 event will occur when ALARM2 matches the RTC timer value.
610
Rev. 1.0
Register 31.6. RTC0_SETCAP: RTC Timer Set/Capture Value
Bit
31
30
29
28
27
26
25
24
23
Name
SETCAP[31:16]
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
SETCAP[15:0]
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_SETCAP = 0x4002_9050
Table 31.8. RTC0_SETCAP Register Bit Descriptions
Bit
Name
31:0
SETCAP
Function
RTC Timer Set/Capture Value.
The value in SETCAP will be written to the RTC timer when TMRSET is set to 1.
The operation will be complete when TMRSET is cleared to 0 by the hardware.
The value of the RTC timer will be copied to SETCAP when TMRCAP is set to 1.
The operation will be complete when TMRCAP is cleared to 0 by the hardware.
Rev. 1.0
611
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Register 31.7. RTC0_LFOCONTROL: LFOSC Control
Bit
31
Name
LFOSCEN
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
Type
RW
R
Reset
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
Reserved
Type
R
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Address
RTC0_LFOCONTROL = 0x4002_9060
Table 31.9. RTC0_LFOCONTROL Register Bit Descriptions
Bit
Name
31
LFOSCEN
Function
Low Frequency Oscillator Enable.
0: Disable the Low Frequency Oscillator (LFOSCn).
1: Enable the Low Frequency Oscillator (LFOSCn).
30:0
612
Reserved
Must write reset value.
Rev. 1.0
31.9. RTC0 Register Memory Map
RTC0_ALARM2 RTC0_ALARM1 RTC0_ALARM0 RTC0_CONTROL RTC0_CONFIG Register Name
ALL Address
0x4002_9010
0x4002_9040
0x4002_9030
0x4002_9020
0x4002_9000
ALL | SET | CLR ALL | SET | CLR Access Methods
ALL
ALL
ALL
Bit 31
RTCEN
Bit 30
CLKSEL
Bit 29
RTCOEN
Bit 28
Reserved
Bit 27
ALM2EN
Bit 26
ALM1EN
Bit 25
ALM0EN
Bit 24
Bit 23
Bit 22
Reserved
Bit 21
Reserved
Bit 20
Bit 19
AGCEN
Bit 18
CRYSEN
Bit 17
BDEN
Bit 16
ALARM2
ALARM1
ALARM0
Bit 15
Bit 14
Bit 13
Bit 12
Reserved
Bit 11
Bit 10
Bit 9
LRDYF
Bit 8
HSMDEN
Bit 7
OSCFI
Bit 6
RTCLC
CLKVF
Bit 5
TMRSET
Bit 4
ASEN
TMRCAP
Bit 3
MCLKEN
ALM2I
Bit 2
RUN
ALM1I
Bit 1
ALM0AREN
ALM0I
Bit 0
Table 31.10. RTC0 Memory Map
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
Rev. 1.0
613
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Table 31.10. RTC0 Memory Map
RTC0_LFOCONTROL RTC0_SETCAP Register Name
0x4002_9060
0x4002_9050
ALL Address
ALL
ALL
Access Methods
LFOSCEN
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
SETCAP
Reserved
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Real Time Clock and Low Frequency Oscillator (RTC0)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Address" refers to the absolute address of the ALL access method for a register. A register may also support
SET, CLR, and MSK access methods, as indicated by the "Access Methods" column. SET, CLR and MSK addresses
are offset from the ALL address by 4, 8 and 12 bytes, respectively. For example, a register whose ALL address is
located at 0x4001_00A0 in the address map may have a SET address at 0x4001_00A4, a CLR address at
0x4001_00A8, and a MSK address at 0x4001_00AC.
614
Rev. 1.0
32. SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
This section describes the SAR Analog to Digital Converter (SARADC) module, and is applicable to all products in
the following device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the SARADC block, which is used by both SARADC0 and SARADC1 on all
device families covered in this document.
32.1. SARADC Features
The SARADC module includes the following features:
Single-ended
10-bit or 12-bit operation.
in low power modes at lower conversion speeds.
Can be synchronized to the EPCA0 synchronization output, to take samples at precise times in the PWM
waveform.
Selectable asynchronous hardware conversion trigger with hardware channel select.
Output data window comparator allows automatic range checking.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with
programmable power-on settling and tracking time.
Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts
supported.
Flexible output data formatting.
Sequencer allows up to 8 sources to be automatically scanned using one of four channel characteristic
profiles without software intervention.
Eight-word conversion data FIFO for DMA operations.
SARADC0 and SARADC1 can work together synchronously or by interleaving samples.
Operation
Rev. 1.0
615
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SARADCn Module
ADCnT0
ADCnT1
Master Control
ADCnT2
SSGn signal
ADCnT3
Less Than
Greater
Than
Comparator
ADCnT15
Burst
Mode
SAR Analog to
Digital Converter
0.5x – 1x
gain
Channel
Sequencer
Clock
Divisor
Sampling
Edge Select
ADCn.0
Accumulator
Left Shift
ADCn.1
ADCn.2
ADCn.3
Data FIFO
ADCn.21
APB Clock
Low Power Oscillator
DATA
FIFO Status and
Control
Burst Mode clock
SSGn phase
Dedicated
SARADCn
VREF
Internal LDO
VDD
VREF
Internal VREF
Device Ground
VREFGND
+
-
ADC
Reference
Conversion Characteristic 0
Conversion Characteristic 1
Conversion Characteristic 2
Conversion Characteristic 3
Figure 32.1. SARADC Block Diagram
616
Rev. 1.0
32.2. Tracking and Conversion Time
A single ADC conversion consists of two phases; the tracking phase, and the conversion phase. During the
tracking phase, the ADC's sampling capacitor connects to the selected multiplexer channel and charges to the
voltage present at that node. During the conversion phase, the sampling capacitor disconnects from the multiplexer
channel and connects to the SAR converter circuitry.
32.2.1. Input Settling Time
It is important for the application to allow enough settling time at the ADC input during the tracking phase. This will
depend largely on the external source impedance and the desired accuracy level. The input to the SARADC is
shown in Figure 32.2. The sample switch is closed during the tracking phase and open during the conversion
phase. Values for CIN, CSAR, and RMUX are different depending on the type of input channel and the gain range.
These values can be found in the device data sheet electrical specifications tables. The system designer should
assume that the capacitor CSAR is discharged between every conversion.
Sample Switch
Input Pin
RMUX
CIN
CSAR
Figure 32.2. SARADC Input Model
32.2.2. SAR Clock Generation
The SAR clock speed dictates the timing of the conversion phase, which lasts for 13 SAR clock cycles. The SAR
clock speed is programmable as a divided version of the APB clock using the CLKDIV field in the CONFIG register.
The SAR clock should be configured to be as fast as possible according to the electrical specifications in the
device data sheet. Faster SAR clock speeds allow the converter more time in the tracking phase and reduce the
amount of time the converter is actively converting, thereby reducing system power.
32.2.3. Tracking Mode (Non-Burst Operation)
When the ADC operates in non-burst mode, two tracking options are available and are selected by the TRKMD bit
in the CONTROL register: normal tracking and delayed tracking. In normal tracking mode, the ADC tracks any time
a conversion is not taking place, and the start-of-conversion event triggers the beginning of the conversion phase.
The ADC returns to tracking immediately after a conversion finishes. The tracking time in this mode is therefore
determined by the sample rate minus the conversion time.
In delayed tracking mode, the start-of-conversion event will trigger the ADC to track for three SAR clock cycles,
followed by the conversion phase. Upon completion of a conversion, the ADC will go into an idle state, waiting for
the next start-of-conversion trigger. Timing for the two tracking modes is shown in Figure 32.3.
Rev. 1.0
617
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Start of conversion
trigger
SAR clock
Normal tracking
Tracking
Converting
Tracking
tCNV
Delayed tracking
Tracking
Tracking
Converting
Tracking
tCNV
Figure 32.3. Non-Burst Tracking and Conversion Timing
32.2.4. Start-of-Conversion Source
Conversions can be initiated by several different internal and external trigger sources, which vary between device
families. The SCSEL field in the CONTROL register selects the start-of-conversion source to be used by the ADC.
In "on-demand" trigger mode, conversions are initiated when firmware sets the ADBUSY bit in the CONTROL
register to 1. In all other conversion modes, the selected start-of-conversion trigger (timer overflow, external pin
transition, SSG, etc.) will begin a conversion. The frequency of the selected start-of-conversion trigger determines
the sampling rate of the ADC and should not exceed the maximum listed in the electrical specification for the
device. SARADC0 and SARADC1 start of conversion sources vary by package, and are shown in Table 32.1 and
Table 32.2.
Table 32.1. SARADC0 Start of Conversion Sources
618
Trigger
External Convert Start
Description
SiM3U1x7/C1x7
Pin Name
ADC0T0
Internal Convert Start
“On Demand” by writing 1 to ADBUSY
ADC0T1
Internal Convert Start
Timer 0 Low overflow
ADC0T2
Internal Convert Start
Timer 0 High overflow
ADC0T3
Internal Convert Start
Timer 1 Low overflow
ADC0T4
Internal Convert Start
Timer 1 High overflow
ADC0T5
Internal Convert Start
EPCA0 synchronization pulse
ADC0T6
Internal Convert Start
I2C0 Timer overflow
ADC0T7
Internal Convert Start
I2C1 Timer overflow
ADC0T8
Internal Convert Start
SSG phase defined by ADSP bits (cannot be used in
Burst Mode).
ADC0T15
External Convert Start
PB1.13
Rev. 1.0
SiM3U1x6/C1x6
Pin Name
PB1.6
SiM3U1x4/C1x4
Pin Name
PB0.12
Table 32.2. SARADC1 Start of Conversion Sources
Trigger
External Convert Start
Description
SiM3U1x7/C1x7
Pin Name
ADC1T0
Internal Convert Start
“On Demand” by writing 1 to ADBUSY
ADC1T1
Internal Convert Start
Timer 0 Low overflow
ADC1T2
Internal Convert Start
Timer 0 High overflow
ADC1T3
Internal Convert Start
Timer 1 Low overflow
ADC1T4
Internal Convert Start
Timer 1 High overflow
ADC1T5
Internal Convert Start
EPCA0 synchronization pulse
ADC1T6
Internal Convert Start
I2C0 Timer overflow
ADC1T7
Internal Convert Start
I2C1 Timer overflow
ADC1T8
Internal Convert Start
SSG phase defined by ADSP bits (cannot be used in
Burst Mode).
ADC1T15
External Convert Start
PB1.14
Rev. 1.0
SiM3U1x6/C1x6
Pin Name
PB1.7
SiM3U1x4/C1x4
Pin Name
PB0.13
619
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
32.2.5. 12-bit Mode
The ADC normally operates as a 10-bit converter, and achieves its highest sampling rate in the 10-bit mode. A 12bit mode is available, which increases the resolution of the converter to 12 bits at the expense of conversion speed.
This 12-bit mode is a special condition of burst mode operation. When operating the converter in 12-bit mode, the
BURSTEN bit in the CONTROL register must be set to 1. One input sample and four conversion cycles are
required per 12-bit conversion word, and the set of four conversions will be initiated by the start-of-conversion
trigger. The converter uses a patented technique to increase the resolution and linearity of the converter by two bits
using only four conversion cycles, whereas a traditional straight average operation would require 16 samples to
increase noise resolution by 2 bits, and would have no effect on linearity. Additionally, when used to sample DC
input signals, the converter can be configured to resample the input four times per 12-bit conversion, which can
provide additional filtering of Gaussian noise present at the input. The AD12BSSEL field on the CONTROL register
is used to configure whether four separate input samples or a single input sample is used for the 12-bit result.
Figure 32.4 shows the difference in timing between these two options.
Note: When using single-sampling (AD12BSSEL = 1), the TRKMD bit should be cleared to 0 to ensure proper signal tracking.
start of conversion
trigger
AD12BSSEL = 0
Tracking
Converting
new data
available
Tracking
Converting
Tracking
Converting
Tracking
start of conversion
trigger
AD12BSSEL = 1
Tracking
Converting
Tracking
new data
available
Idle
Converting
Idle
Converting
Idle
Figure 32.4. 12-Bit Sampling Options
620
Converting
Rev. 1.0
Converting
Tracking
32.3. Burst Mode
The ADC implements a "burst mode" feature which enables lower power operation of the system. When a
conversion trigger event occurs, the ADC will power on (if needed), track for a selected period of time, perform one
or more conversions, and then return to the idle or powered-down state. The repeat counter (CHRxRPT) dictates
the number of conversions performed for the channel being converted. Burst mode is enabled by setting the
BURSTEN bit in the CONTROL register to 1.
In burst mode, the ADCEN bit controls the power consumption of the ADC between conversions. When ADCEN is
cleared to 0, the ADC is powered down after each burst. If ADCEN is set to 1, the ADC will remain powered on
between bursts.
In burst mode, the ADC can use a high-speed, low-power oscillator for conversion timing, enabling the system
designer to run the core from a slow clock source or put the core in a low-power state to conserve power. Burst
mode can also be configured to use the APB clock as a source. The clock used for burst mode is selected using
the BCLKSEL bit in the CONFIG register.
32.3.1. Data Accumulation
When burst mode is enabled, ADC samples can automatically be accumulated by the converter as they are taken.
The accumulation mode is controlled by the ACCMD bit in the CONTROL register. This bit should be cleared to 0
to enable accumulation. Firmware must write the initial value (typically zero) to the ACC register prior to a
conversion being taken or a scan sequence being initiated. The number of conversions accumulated is determined
by the repeat counter field of the selected conversion characteristic register. For example, if CHxRPT is set to
sample four times, four conversions will be accumulated.
When using the ADC’s scan function, the accumulator will automatically be cleared to zero before the sequencer
moves to the next selected channel. In other modes, this does not occur, and firmware must clear the ACC register,
as necessary. Note that the ACC register should not be written while conversions are in progress, and its contents
cannot be read.
32.3.2. Burst Mode Tracking
Tracking time in burst mode is different than non-burst mode operation of the ADC. For the first conversion, the
tracking time is determined by the power-on time selected by the PWRTIME field in the CONTROL register. For all
subsequent conversions during an ADC burst, the tracking time is dictated by the setting of the BMTK and the
TRKMD bits. This timing is described in the BMTK bit description in the CONTROL register. Figure 32.5 illustrates
the burst mode tracking timing when ADCEN is cleared to 0 (power down between conversions), the burst clock is
the low power oscillator, and the APB clock is operating at a low frequency.
APB clock
Start of conversion
trigger
Normal tracking
powered down
power up
and track
Delayed tracking
powered down
power up
and track
C
D
T
C
C
T
T
D
C
C
T
T
C
D
power up
and track
powered down
C
T
D
C
powered
down
power up
and track
C – converting
T – burst mode tracking time (BMTK)
D – delay time (TRKMD) (3 SAR clocks)
Figure 32.5. Burst Mode Tracking and Conversion Timing (Four Samples)
Rev. 1.0
621
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
32.4. Channel Sequencer
The channel sequencer allows the user to define up to eight different combinations of ADC configurations and
multiplexer channels, then scan through them with an ADC scan operation, relieving software of the overhead
necessary to change multiplexer channels and other parameters.
32.4.1. Multiplexer Input Settings
Each ADC module (SARADC0, SARADC1) can select between multiple external inputs (up to 16 are available,
depending on the package type) and internal inputs. These inputs become the positive inputs to the single-ended
SARADC0 or SARADC1 module. The possible input selections for SARADC0 and SARADC1 are shown in
Table 32.3 and Table 32.4. Note that for some selections, other device circuitry must be enabled.
32.4.2. Timeslot Settings
The Channel Sequencer Time Slot Setup registers SQ7654 and SQ3210 configure the eight channel sequencer
time slots each ADC. Each time slot defines the multiplexer channel to be converted, as well as which conversion
characteristic to use for the conversion.
If the TSnMUX field in a time slot is set to the terminate scan value (0x1F), this indicates that no conversion is to be
performed on this channel. When the sequencer encounters an 0x1F value in the time slot mux selection or
converts the final time slot, it will either halt (single scan mode) or wrap back to time slot 0 (continuous scan mode).
The scan done interrupt flag (SDI in the STATUS register) will be set to 1 when a single scan operation is complete
or when firmware clears SCANEN. Figure 32.6 shows a typical setup for a single scan using three sequencer time
slots.
32.4.3. Conversion Characteristic Settings
The Conversion Characteristic Setup registers CHAR10 and CHAR32 define some of the characteristics of how
the SARADC conversions will be performed. Each register defines two conversion characteristics (for example,
CHAR10 defines conversion characteristic 1 and 0). The conversion characteristics select the gain, accumulation
levels, post-conversion shifting, number of data bits, and whether to use the window comparator hardware. See the
CHAR10 and CHAR32 register descriptions for more details on the selectable options.
32.4.4. Channel Scan Mode
The ADC implements channel sequencer logic which is capable of "scanning" through one or more ADC
configurations automatically. When SCANEN is set to 1, the channel sequencer is active. The sequencer begins
with time slot 0, and continues scanning through all eight time slots in sequence until it reaches the last channel or
the final time slot or the terminate scan value (0x1F).
32.4.4.1. Single Scan Mode
If the SCANMD field in the CONFIG register is set to 0, the ADC performs a single scan through the channels.
When using single-scan mode, each scan must be initiated by a 0-to-1 transition of the SCANEN bit in the CONFIG
register. The scan will begin on the next conversion trigger event and end when the final channel in the sequencer
has been converted. Note that a conversion trigger event is required for each channel in the scan, and the length of
time between each conversion trigger event needs to be greater than or equal to the time required for the longest
conversion. SCANEN will return to 0 upon completion of a scan in the single scan mode.
32.4.4.2. Continuous Scan Mode
If the SCANMD field in the CONFIG register is set to 1, the ADC will continue to wrap through all channels of the
sequencer indefinitely. The continuous scan operation must be initiated by a 0-to-1 transition of the SCANEN bit in
the CONFIG register. When the channel sequencer reaches the end of the sequence or the terminate scan value
(0x1F), the ADC will begin again with the first channel. The scans will continue until firmware clears the SCANEN
bit to 0.
32.4.4.3. Important notes on the use of Scan Mode
Note the following important restrictions on the use of Scan Mode:
1. Scan should not be used if interleaved or simultaneous modes are enabled.
2. Burst mode should be enabled (BURSTEN = 1) if using scan.
3. A start-of-conversion trigger is required for each time slot in the sequence. Each trigger needs to be
622
Rev. 1.0
spaced farther apart in time than the amount of time required for the longest conversion in the sequence.
For example, if one time slot uses a 64-sample accumulation, the length of time between each conversion
needs to be longer than the time required for one 64-sample accumulation.
Data FIFO
TS0 Sample
SAR Analog to Digital
Converter
Accumulator
DATA
TS1 Sample
TS2 Sample
TS0MUX
0 / ADCn.0
TS0CHR
0
TS1MUX
10 / ADCn.10
TS1CHR
1
TS2MUX
3 / ADCn.3
TS2CHR
0
TS3MUX
0x1F / END
TS3CHR
TS4MUX
TS4CHR
TS5MUX
TS5CHR
TS6MUX
TS6CHR
TS7MUX
TS7CHR
Conversion Characteristic 0
Conversion Characteristic 1
Conversion Characteristic 2
(unused)
Conversion Characteristic 3
(unused)
Sequencer
Figure 32.6. Channel Scan Setup and Timing
32.4.5. Single Channel Mode
When SCANEN is cleared to 0, the channel sequencer is not active. In this mode, time slot 0 is used for all
conversions performed by the ADC. Any of the conversion characteristic setup registers can be used to define the
conversion parameters in single configuration mode. The single conversion complete interrupt flag (SCCI in the
STATUS register) will be set to 1 after each conversion is complete.
Setting the TSnMUX to 0x1F will terminate the scan at that time slot.
Table 32.3. SARADC0 Input Channels
SARADC0
Input
SARADC0 Input Description
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
ADC0.0
Normal Input
PB0.0
Reserved
PB0.6
ADC0.1
Normal Input
PB0.1
Reserved
PB0.7
ADC0.2
Normal Input
PB0.2
PB0.0
Reserved
ADC0.3
Normal Input
PB0.3
PB0.1
Reserved
ADC0.4
Normal Input
PB0.4
PB0.2
Reserved
ADC0.5
Normal Input
PB0.5
PB0.3
Reserved
ADC0.6
Normal Input
PB0.7
PB0.4
Reserved
Rev. 1.0
623
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.3. SARADC0 Input Channels (Continued)
SARADC0
Input
SARADC0 Input Description
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
ADC0.7
Normal Input
PB0.8
PB0.5
Reserved
ADC0.8
Normal Input
PB0.9
PB0.6
PB0.0
ADC0.9
Normal Input
PB0.11
PB0.8
PB0.2
ADC0.10
Normal Input
PB0.12
PB0.9
PB0.3
ADC0.11
Normal Input
PB1.1
Reserved
Reserved
ADC0.12
High Quality Input
PB1.3
PB0.14
Reserved
ADC0.13
High Quality Input
PB1.4
PB0.15
Reserved
ADC0.14
High Quality Input
PB1.5
PB1.0
PB0.8
ADC0.15
High Quality Input
PB1.6
PB1.1
PB0.9
ADC0.16
Internal Channel
IVC0.0 Output (IVC0C0)
ADC0.17
Internal Channel
VSS
ADC0.18
Internal Channel
1.8 V Output of LDO
ADC0.19
Internal Channel
VDD
ADC0.20
Internal Channel
Temperature Sensor Output
ADC0.21
Internal Channel
Voltage at VIOHD / 4 (1)
Notes:
1. The VIOHD/4 option requires the VIOHD divider to be enabled within the PBHD block
(PBHD4_PBDRV.PBVTRKEN).
Table 32.4. SARADC1 Input Channels
624
SARADC1
Input
SARADC1 Input Description
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
ADC1.0
Normal Input
PB2.2
PB1.11
PB1.1
ADC1.1
Normal Input
PB2.1
PB1.10
PB1.0
ADC1.2
Normal Input
PB2.0
PB1.9
PB0.15
ADC1.3
Normal Input
PB1.15
PB1.8
PB0.14
ADC1.4
Normal Input
PB1.14
PB1.7
PB0.13
ADC1.5
Normal Input
PB1.13
PB1.6
PB0.12
ADC1.6
Normal Input
PB1.12
PB0.10
PB0.4
ADC1.7
Normal Input
PB1.11
PB1.5
PB0.11
Rev. 1.0
Table 32.4. SARADC1 Input Channels
SARADC1
Input
SARADC1 Input Description
SiM3U1x7/C1x7 SiM3U1x6/C1x6 SiM3U1x4/C1x4
Pin Name
Pin Name
Pin Name
ADC1.8
Normal Input
PB1.10
PB1.4
PB0.10
ADC1.9
Normal Input
PB1.9
Reserved
Reserved
ADC1.10
Normal Input
PB1.8
PB1.3
Reserved
ADC1.11
Normal Input
PB1.7
PB1.2
Reserved
ADC1.12
High Quality Input
PB1.3
PB0.14
Reserved
ADC1.13
High Quality Input
PB1.4
PB0.15
Reserved
ADC1.14
High Quality Input
PB1.5
PB1.0
PB0.8
ADC1.15
High Quality Input
PB1.6
PB1.1
PB0.9
ADC1.16
Internal Channel
IVC0.1 Output (IVC0C1)
ADC1.17
Internal Channel
Voltage at VREGIN / 4 (1)
ADC1.18
Internal Channel
EXTVREG0 Current Sense (2)
ADC1.19
Internal Channel
VIO
ADC1.20
Internal Channel
Temperature Sensor Output
ADC1.21
Internal Channel
Voltage at VIOHD / 4 (3)
Notes:
1. The VREGIN/4 option requires the VREGIN sense circuitry to be enabled within the VREG0 block
(VREG0_CONTROL.SENSEEN).
2. The EXTVREG0 Current Sense option requires the current sense circuit in the EXTVREG0 block to be enabled
(EXTVREG0_CSCONTROL.ADCISNSEN).
3. The VIOHD/4 option requires the VIOHD divider to be enabled within the PBHD block
(PBHD4_PBDRV.PBVTRKEN).
Rev. 1.0
625
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
32.5. Sample Sync Generator
The Sample Sync Generator (SSG) module can be used to synchronize sampling of multiple ADC modules with
other external and internal events, as well as IDAC conversions. The SSG module synchronizes everything,
including its own output signals, with the SAR clock of an ADC. Note that when using the SSG module, SARADC0
will always be the master ADC and SARADC1 will always be the slave ADC.
32.5.1. Sampling Phase Selection
When using the SSG, the ADC sampling rate will be 1/16th the SAR clock frequency, and the ADC must be
configured for 10-bit operation. The ADC can sample on any of sixteen different phases within the conversion time.
These phases are spaced according to the speed of the ADC's SAR clock. By default, the ADC will sample at
phase 0 of the SSG module. To sample on a different phase, firmware should set the SPEN bit in the CONFIG to 1
and select the desired phase using the SPSEL field. Figure 32.7 shows the relationship between the SAR clock,
and the SSG phases.
SAR Clock
Phase
0
Phase
1
Phase
2
Phase
3
Multiple ADCs sample on the
same phase in simultaneous
mode
Phase
4
Phase
5
...
Phase
14
Phase
15
Multiple ADCs configured to sample
180 degrees apart in interleaved
mode (master at phase 0, slave at
phase 8, for example)
Figure 32.7. ADC Sample Timing And SSG Phase Relationship
32.5.2. Dual ADC Operation
On device families with more than one ADC module, the SSG can be used to synchronize the operation of multiple
ADCs. This can be useful for sampling two different channels simultaneously (simultaneous mode) or for
interleaving two ADCs on the same channel to obtain a faster throughput (interleaved mode). To synchronize two
ADCs, the SSG module must be enabled and configured. Note that scan should not be used if interleaved or
simultaneous modes are enabled.
When using the SSG module, SARADC0 will always be the master and SARADC1 will always be the slave. The
SPSEL field in the CONFIG register of both the master and slave is used to select the desired sampling phase, as
detailed in “32.5.1. Sampling Phase Selection” . Both ADCs should have the SSG module selected as their start-ofconversion triggers. On both master and slave ADCs, the SSGEN bit in the CONFIG register should be set to
enable generation of conversion triggers from the SSG module. Note that when enabling the ADCs, the SSGEN bit
for the master must be set first, followed by the slave ADC’s SSGEN bit. When disabling the ADCs, the reverse is
true: the slave ADC’s SSGEN must be cleared first, followed by the master’s SSGEN bit.
32.5.2.1. Simultaneous Mode
To operate two ADCs simultaneously, their respective SPSEL fields should be set to the same value. This
configures the ADCs to sample at the same time. If it is necessary that the ADC data from both ADCs be packed
into a single 32-bit data word, the SIMCEN bit in the CONFIG register should also be set to 1 on the master ADC,
and the desired sample order should be configured using the PACKMD field. Only the options for two samples per
32-bit word are valid if SIMCEN is set, and the master ADC's configuration for PACKMD determines the order (the
slave ADC’s PACKMD setting doesn’t matter). If SIMCEN is cleared to 0 on the master ADC, samples from the
slave will not be packed into the same data word as the master samples and will be available in the slave ADC
FIFO.
626
Rev. 1.0
32.5.2.2. Interleaved Mode
To operate two ADCs in interleaved mode, their respective SPSEL fields are most commonly set to values 8
phases apart. This configures the ADCs to sample at regular intervals between one another. If it is necessary that
the ADC data from both ADCs be packed into a single 32-bit data word, the INTLVEN bit in the CONFIG register
should also be set to 1 on the master ADC, and the desired sample order should be configured using the master
ADC’s PACKMD field (the slave’s PACKMD setting doesn’t matter). Any selection of PACKMD is valid when
INTLVEN is set; the order in which samples are taken will determine the order they appear in the FIFO. If INTLVEN
is cleared to 0 on the master ADC, samples from the slave will not be packed into the same data word as the
master samples and will be available in the slave ADC FIFO.
32.5.2.3. Important notes on the use of the SSG
Note the following important restrictions on the use of the SSG:
1. Scan should be disabled if interleaved or simultaneous modes are enabled.
2. SARADC0 will always be the master and SARADC1 will always be the slave.
3. 12-bit conversions are not supported.
4. When enabling SSG mode, SSGEN must be set first on the Master ADC, then can be set on the Slave
ADC. The reverse is true when disabling SSG mode.
32.5.2.4. Dual ADC + SSG Configuration Sequence
The following steps show the configuration of dual SARADCs with the SSG. If using only a single ADC with the
SSG, the slave ADC configuration steps may be omitted.
1. Configure all clock source, clock divider and voltage reference settings for each ADC.
2. Clear the scan mode enable (SCANEN) bit to disable scan mode for each ADC.
3. Set the Sampling Phase Enable (SPEN) bit for each ADC.
4. Configure the desired sampling phase in the Sample Phase Select (SPSEL) for each ADC.
5. Set the start of conversion source (SCEL) in each ADC to use the SSG.
6. If desired, configure the master ADC’s output packing mode (PACKMD) bit field to enable packing data
from the slave ADCs into the master ADC data register.
7. For each ADC, configure the Conversion Characteristic 0 Repeat Counter (CHR0PFT) to 0 to accumulate
a single sample.
8. For each ADC, set the Conversion Characteristic 0 Resolution Selection (CHR0RSEL) bit to 0 to select 10bit mode.
9. If using Interleaved mode, set the Interleaved Conversion Packing Enable (INTLVEN) bit on the master
ADC, and clear the INTLVEN bit on the slave ADC.
10. Alternately, if using Simultaneous mode, set the Simultaneous Conversion Packing Enable (SIMCEN) bit
on the master ADC, and clear the SIMCEN bit on the slave ADC
11. Set the Synchronous Sample Generator Enable (SSGEN) bit for the master ADC. Note that the slave
ADC’s SSGEN bit must be set after the master’s SSGEN bit is set.
12. Set the Synchronous Sample Generator Enable (SSGEN) bit for the slave ADC.
13. If desired, configure and enable DMA for the ADC. If the slave ADC’s data is packed into the master’s
ADC’s data register, DMA only needs to be enabled for the master ADC.
14. Configure and enable the SSG module as described in the SSGn chapter.
32.6. Voltage Reference Configuration
The ADC has the option to use several voltage reference sources: the on-chip VREF module, an external voltage
reference, a dedicated internal reference for the SARADC block, an internal 1.8V LDO regulator, or the VDD
voltage supply. The VREFSEL field in the CONTROL register selects the voltage reference for the ADC. The
dedicated SARADC reference will be automatically enabled if it is selected. Optionally, when using the external
VREF pin as the reference source, the reference ground is selectable between an internal ground node tied to VSS
Rev. 1.0
627
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
and the external VREFGND pin. The REFGNDSEL bit in the CONTROL register determines which option is used.
When REFGNDSEL is set to use VREFGND and an external input is being measured, the VREFGND pin signal is
also used as the ADC’s signal ground reference. Using the external VREFGND can provide for cleaner ADC
conversions with an external reference source. The various VREF configuration options are shown in Figure 32.8.
VREFSEL
VDD
Dedicated
SARADCn
Reference
Reference
External VREF
VREF
SAR Analog to
Digital Converter
VREFn Module
Reference ground
REFGNDSEL
VREFGND
VSS
Figure 32.8. Voltage Reference Options
32.7. Power Configuration
When the ADC is disabled, it will remain in a powered-down, inactive state. The ADC is enabled by setting the
ADCEN bit in the CONTROL register to 1, and there are several fields in the CONTROL register to reduce
operational power when the ADC is enabled. The MREFLPEN bit can be used to reduce the power to the internal
buffers when the SAR clock is operated at a slower speed. Additionally, the BIASSEL field has four selectable
power levels that can scale power in regards to the SAR clock speed. The LPMDEN bit is used to reduce the
current required during the tracking phase. If the application allows for longer tracking times, LPMDEN can be set
to 1.
628
Rev. 1.0
32.8. Data Output
The ADC allows for several different configurations and post-processing options on the output data. In the basic
configuration, individual samples are written into a FIFO at the end of each conversion, and can be read through
the DATA register or transferred to RAM using the DMA. The FIFOLVL field in the FIFOSTATUS register indicates
the number of 32-bit words currently available in the FIFO. Each data word may contain one or two ADC samples.
The order and number of the data words is selected by the PACKMD field in the CONFIG register. When the MSB
of PACKMD is 0, only one sample is written per word, and the LSB of the PACKMD field determines whether the
sample is written to the upper half or lower half of the 32-bit word. When the MSB of PACKMD is 1, two samples
are packed into each output word. The order in which the samples are packed is determined by the LSB of
PACKMD. The DPSTS bit in the FIFOSTATUS register indicates the target for the next sample within a data word
(upper half or lower half). Figure 32.9 and Figure 32.10 show the data packing options.
Output Conversion Half Word Sample
15
0
10-bit sample, right-justified
CHRxLS = 0, CHRxRSEL = 0
Sample
15
0
10-bit sample, left-justified
CHRxLS = 6, CHRxRSEL = 0
Sample
15
0
12-bit sample, right-justified
CHRxLS = 0, CHRxRSEL = 1
Sample
15
0
12-bit sample, left-justified
CHRxLS = 4, CHRxRSEL = 1
Sample
15
0
12-bit sample, middle of half-word
CHRxLS = 2, CHRxRSEL = 1
Sample
Figure 32.9. Sample Formatting
Rev. 1.0
629
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
DATA Register
31
0
single sample half-word
PACKMD = 0
Sample 1
0x0000
0x0000
Sample 1
Sample 1
Sample 2
Sample 2
Sample 1
Master Sample
Slave Sample
31
0
single sample half-word
PACKMD = 1
31
0
two sample half-words
PACKMD = 2
31
0
two sample half-words
PACKMD = 3
31
0
31
two sample half-words
PACKMD = 2
0
Slave Sample
Master Sample
Sample 1
Sample 2
31
Dual ADCs
(SIMCEN = 1)
two sample half-words
PACKMD = 3
0
31
two sample half-words
PACKMD = 2
0
Sample 2
two sample half-words
PACKMD = 3
Sample 1
Figure 32.10. ADC Output Data Packing Options
630
Single ADC
(SIMCEN = 0,
INTLVEN = 0)
Rev. 1.0
Dual ADCs
(INTLVEN = 1)
32.8.1. Output Data Window Comparator
The ADC includes an output data window comparator. Using the window comparator, the ADC output data can be
automatically compared against a specified upper and lower limit and trigger an interrupt, when desired. The
window comparator limits are set by the WCLIMITS register. The WCGT field in WCLIMITS sets a "greater than"
comparison limit, and the WCLT field sets a "less than" comparison limit. These two limit values are always
compared against a right-justified output after any accumulation has been performed on the data. The window
comparator is enabled for individual channel characteristics as detailed in “32.4. Channel Sequencer” .
The window comparator limits work together to determine when an interrupt will be triggered. Firmware can
configure the ADC to generate an interrupt when the output is within the two limits or outside of the limits. To
generate an interrupt within the two limits, WCLT should be programmed to a higher value than WCGT. To
generate an interrupt outside of the two limits, WCGT should be programmed to a higher value than WCLT.
Figure 32.11, Figure 32.12, Figure 32.13, and Figure 32.14 show examples of configuring the window comparator
limits for different situations.
0xFFFF
no interrupt
WCLT
interrupt
generated
WCGT
no interrupt
0x0000
Figure 32.11. Example Window Comparator Limits for Inside Range (WCGT < WCLT)
0xFFFF
interrupt
generated
WCGT
no interrupt
WCLT
interrupt
generated
0x0000
Figure 32.12. Example Window Comparator Limits for Outside Range (WCGT > WCLT)
Rev. 1.0
631
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
0xFFFF
interrupt
generated
WCGT
no interrupt
WCLT = 0x0000
Figure 32.13. Example Window Comparator Limits for Above Value (WCGT = Value, WCLT = 0)
WCGT = 0xFFFF
no interrupt
WCLT
interrupt
generated
0x0000
Figure 32.14. Example Window Comparator Limits for Below Value (WCLT = Value, WCGT = Full
Scale)
32.9. Interrupts
The ADC interrupt can be triggered by five different, independently maskable interrupt sources. Two of these
interrupts indicate error conditions, while the other three are primarily used for non-DMA operation. All interrupt
status flags are located in the STATUS register and must be cleared by software. Descriptions of each interrupt
condition are below:
FURI:
The FIFO underrun interrupt flag is set when a read from the DATA register is initiated while the
FIFO is empty (FIFOLVL = 0). The read of the DATA register in this event will return the previous ADC
result.
FORI: The FIFO overrun interrupt flag is set when a new ADC data word (containing one or two samples)
is to be written to the FIFO and the FIFO is full. If a FIFO overrun occurs, the data word that triggered the
overrun will be lost.
632
Rev. 1.0
SDI:
The scan done interrupt flag is set when scan mode is enabled and a channel scan sequence
completes a single scan operation. In continuous scan mode, the SDI flag will be set when firmware exits
scan.
SCCI: The single conversion complete interrupt flag is set at the end of every conversion or accumulated
conversion (when accumulation is enabled).
WCI: The window comparator interrupt is set when a window comparison event happens and the current
sequencer channel has enabled the interrupt.
Rev. 1.0
633
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
32.10. DMA Configuration and Usage
DMA can be used to pipe the ADC data out of the FIFO into RAM, allowing more bandwidth for the core to perform
other tasks. Note that the DMA will only start a transfer when there are 4 elements in the FIFO. For the SARADC
module, the DMA should be configured as follows:
Source
size (SRCSIZE) and destination size (DSTSIZE) are 2 for a word transfer.
The source address increment (SRCAIMD) is 3 for non-incrementing mode.
The destination address increment (DSTAIMD) is 2 for word increments.
(where NCOUNT+1 is the number of 4-byte words) and RPOWER (where 2RPOWER is the
number of data transfers) set as described below. Note that RPOWER > 2 is not valid setting.
NCOUNT
RPOWER
= 0 and NCOUNT = 0. As soon as the FIFO reaches 4 words, the first word will be transferred using the
DMA. In this configuration, there will always be 3 lagging elements in the FIFO.
RPOWER = 1 and NCOUNT = 1. As soon as the FIFO reaches 4 words, the first two words will be transferred
using the DMA. In this configuration, there will always be 2 lagging elements in the FIFO.
RPOWER = 2 and NCOUNT = 3. As soon as the FIFO reaches 4 words, all elements in the FIFO will be
transferred using the DMA. In this configuration, there will be no lagging elements in the FIFO.
Once the DMA is configured, writing a 1 to DMAEN in the CONFIG register will enable the DMA transfers from the
ADC. The FIFO will continue to be serviced by the DMA until the specified transfer operation is complete.
SiM3xxxx
Address Space
SARADCn Module
Master Control
DMA Module
SARADC Sample Data
Less Than
Greater
Than
DMA Channel
Comparator
SAR Analog to
Digital Converter
Accumulator
Left Shift
Data FIFO
Channel
Sequencer
DMA Channel
DATA
FIFO Status and
Control
DMA Channel
Conversion Characteristic 0
Conversion Characteristic 1
Conversion Characteristic 2
Conversion Characteristic 3
Figure 32.15. SAR ADC DMA Configuration
634
Rev. 1.0
32.11. SARADC0 and SARADC1 Registers
This section contains the detailed register descriptions for SARADC0 and SARADC1 registers.
29
28
27
Name
FURIEN
FORIEN
SDIEN
SCCIEN
CLKDIV
Type
R
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
Name
Reserved
SCANMD
Reserved
SCANEN
INTLVEN
20
19
18
17
16
0
0
0
0
0
0
5
4
3
2
1
0
PACKMD
SPEN
30
DMAEN
25
SSGEN
31
Reserved
26
SIMCEN
Bit
BCLKSEL
Register 32.1. SARADCn_CONFIG: Module Configuration
24
23
SPSEL
Type
RW
RW
R
RW
R
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
22
21
0
0
0
0
0
Register ALL Access Addresses
SARADC0_CONFIG = 0x4001_A000
SARADC1_CONFIG = 0x4001_B000
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 32.5. SARADCn_CONFIG Register Bit Descriptions
Bit
Name
Function
31
Reserved
Must write reset value.
30
FURIEN
FIFO Underrun Interrupt Enable.
0: Disable the data FIFO underrun interrupt.
1: Enable the data FIFO underrun interrupt.
29
FORIEN
FIFO Overrun Interrupt Enable.
0: Disable the data FIFO overrun interrupt.
1: Enable the data FIFO overrun interrupt.
28
SDIEN
Scan Done Interrupt Enable.
This bit enables the generation of an interrupt when the channel sequencer has
cycled through all of the specified time slots.
0: Disable the ADC scan complete interrupt.
1: Enable the ADC scan complete interrupt.
27
SCCIEN
Single Conversion Complete Interrupt Enable.
0: Disable the ADC single data conversion complete interrupt.
1: Enable the ADC single data conversion complete interrupt.
Rev. 1.0
635
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.5. SARADCn_CONFIG Register Bit Descriptions
Bit
Name
26:16
CLKDIV
Function
SAR Clock Divider.
This field sets the ADC clock divider value. It should be configured to be as close to
the maximum SAR clock speed as the datasheet will allow.
When CLKDIV < 3, the APB clock is used as the SAR clock.
When CLKDIV > 3, the SAR clock frequency is given by the following equation:
2  F APB
F CLKSAR = ------------------------------CLKDIV + 1
15
BCLKSEL
Burst Mode Clock Select.
0: Burst mode uses the Low Power Oscillator.
1: Burst mode uses the APB clock.
14
DMAEN
DMA Interface Enable .
0: Disable the ADC module DMA interface.
1: Enable the ADC module DMA interface.
13
Reserved
Must write reset value.
12
SCANMD
Scan Mode Select.
0: The channel sequencer will cycle through all of the specified time slots once.
1: The channel sequencer will cycle through all of the specified time slots in a loop
until SCANEN is cleared to 0.
11
Reserved
Must write reset value.
10
SCANEN
Scan Mode Enable.
Setting this bit to 1 enables the ADC to scan through the specified time slots in the
channel sequencer. The sequence begins on a 0-to-1 transition of this bit, so it must
be 0 before a write to 1 to have any effect.
0: Disable ADC scan mode.
1: Enable ADC scan mode. The ADC will scan through the defined time slots in
sequence on every start of conversion.
9
INTLVEN
Interleaved Conversion Packing Enable.
This bit enables packing of the conversions from two ADCs in interleaved mode. It
should be set to 1 on the master ADC if dual ADC sample packing is desired. This
bit should always be set to 0 on the slave ADC.
0: Disable interleaved mode conversion packing.
1: Enable interleaved mode conversion packing.
8
SIMCEN
Simultaneous Conversion Packing Enable.
This bit enables packing of the conversions from two ADCs in simultaneous mode. It
should be set to 1 on the master ADC if dual ADC sample packing is desired. This
bit should always be set to 0 on the slave ADC.
0: Disable simultaneous mode conversion packing.
1: Enable simultaneous mode conversion packing.
636
Rev. 1.0
Table 32.5. SARADCn_CONFIG Register Bit Descriptions
Bit
Name
7:6
PACKMD
Function
Output Packing Mode.
This field specifies how the ADC output data will be packed into the data registers.
00: Data is written to the upper half-word and the lower half-word is filled with 0's.
An SCI interrupt is triggered when data is written, if enabled.
01: Data is written to the lower half-word, and the upper half-word is filled with 0's.
An SCI interrupt is triggered when data is written, if enabled.
10: Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN
is set to 1, the upper half-word represents data from the master ADC and the lower
half-word represents data from the slave ADC. The ADC write to the lower half-word
will trigger the SCI interrupt, if enabled.
11: Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN
is set to 1, the lower half-word represents data from the master ADC and the upper
half-word represents data from the slave ADC. The ADC write to the upper halfword will trigger the SCI interrupt, if enabled.
5
SSGEN
Synchronous Sample Generator Enable.
This bit enables the ADC to create a conversion trigger based on the SSG module
phase output signal. In dual ADC modes, SSGEN must be set to 1 for both ADCs.
Note that when enabling SSG mode, the master's SSGEN must be set first, followed by the slave's SSGEN. When disabling SSG mode, the slave's SSGEN must
be cleared first, followed by the master's SSGEN.
0: Disables conversion trigger generation from the SSG module phase output.
1: Enables conversion trigger generation from the SSG module phase output.
4
SPEN
Sampling Phase Enable.
0: Disable Phase Select. The ADC will always sample on the start-of-conversion
trigger selected by the SCSEL field.
1: Enable Phase Select. The ADC will sample according to the phase selected by
the SPSEL field.
Rev. 1.0
637
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.5. SARADCn_CONFIG Register Bit Descriptions
Bit
Name
3:0
SPSEL
Function
Sampling Phase Select.
Allows the ADC to delay sampling from the start-of-conversion source to one of 16
different phases. This feature can only be used in conjunction with the sample sync
generator (SSG).
0000: The ADC samples at SSG phase 0.
0001: The ADC samples at SSG phase 1.
0010: The ADC samples at SSG phase 2.
0011: The ADC samples at SSG phase 3.
0100: The ADC samples at SSG phase 4.
0101: The ADC samples at SSG phase 5.
0110: The ADC samples at SSG phase 6.
0111: The ADC samples at SSG phase 7.
1000: The ADC samples at SSG phase 8.
1001: The ADC samples at SSG phase 9.
1010: The ADC samples at SSG phase 10.
1011: The ADC samples at SSG phase 11.
1100: The ADC samples at SSG phase 12.
1101: The ADC samples at SSG phase 13.
1110: The ADC samples at SSG phase 14.
1111: The ADC samples at SSG phase 15.
638
Rev. 1.0
Register 32.2. SARADCn_CONTROL: Measurement Control
RW
20
19
18
17
16
BURSTEN
RW
21
ADCEN
RW
22
AD12BSSEL
RW
23
VCMEN
Reserved
24
Reserved
25
ACCMD
26
TRKMD
27
ADBUSY
28
BIASSEL
29
LPMDEN
Type
30
MREFLPEN
Name
31
VREFSEL
Bit
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PWRTIME
SCSEL
BMTK
REFGNDSEL
0
CLKESEL
Reset
Type
RW
RW
RW
RW
RW
0
0
Reset
1
1
1
1
0
0
0
0
0
1
1
1
1
0
Register ALL Access Addresses
SARADC0_CONTROL = 0x4001_A010
SARADC1_CONTROL = 0x4001_B010
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 32.6. SARADCn_CONTROL Register Bit Descriptions
Bit
Name
31:30
VREFSEL
Function
Voltage Reference Select.
00: Select the internal, dedicated SARADC voltage reference as the ADC reference.
01: Select the VDD pin as the ADC reference.
10: Select the output of the internal LDO regulator (~1.8 V) as the ADC reference.
11: Select the VREF pin as the ADC reference. This option is used for either an
external VREF or the on-chip VREF driving out to the VREF pin.
29:28
Reserved
27
MREFLPEN
Must write reset value.
MUX and VREF Low Power Enable.
This bit is used to limit the power of the internal buffers used on the reference and
the mux. It can be set to 1 to reduce power consumption when the SAR clock is
slowed down.
0: Disable low power mode.
1: Enable low power mode (SAR clock < 4 MHz).
Rev. 1.0
639
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.6. SARADCn_CONTROL Register Bit Descriptions
Bit
Name
26
LPMDEN
Function
Low Power Mode Enable.
This bit can be used to reduce power to one of the ADC's internal nodes. It can be
set to 1 to reduce power when tracking times in the application are longer (slower
sample rates).
0: Disable low power mode.
1: Enable low power mode (requires extended tracking time).
25:24
BIASSEL
Bias Power Select.
This field can be used to adjust the ADC's power consumption based on the conversion speed. Higher bias currents allow for faster conversion times.
00: Select bias current mode 0. Recommended to use modes 1, 2, or 3.
01: Select bias current mode 1 (SARCLK = 16 MHz).
10: Select bias current mode 2.
11: Select bias current mode 3 (SARCLK = 4 MHz).
23
ADBUSY
ADC Busy.
This bit indicates that the ADC is currently converting (not tracking). Writing 1 to this
bit in "On Demand" trigger mode initiates a conversion.
22
TRKMD
ADC Tracking Mode.
0: Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal.
1: Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR
clock cycles following the start-of-conversion signal. The ADC is allowed to track
during this time.
21
ACCMD
Accumulation Mode.
This bit is used to enable or disable accumulation when burst mode is enabled
(BURSTEN = 1).
0: Conversions will be accumulated for the specified number of cycles in burst mode
according to the channel configuration.
1: Conversions will not be accumulated in burst mode.
20
Reserved
19
VCMEN
Must write reset value.
Common Mode Buffer Enable.
0: Disable the common mode buffer.
1: Enable the common mode buffer.
18
AD12BSSEL
12-Bit Mode Sample Select.
This bit defines how the ADC samples the analog input in 12-bit mode.
0: The ADC re-samples the input before each of the four conversions.
1: The ADC samples once before the first conversion and converts four times.
17
ADCEN
ADC Enable.
0: Disable the ADC (low-power shutdown).
1: Enable the ADC (active and ready for data conversions).
16
640
BURSTEN
Burst Mode Enable.
Rev. 1.0
Table 32.6. SARADCn_CONTROL Register Bit Descriptions
Bit
Name
15:12
PWRTIME
Function
Burst Mode Power Up Time.
This field sets the time delay required for ADC to power up from a low power state.
8  PWRTIME
T PWRTIME = -------------------------------------F APB
11:8
SCSEL
Start-Of-Conversion Source Select.
This field specifies the event used to initiate conversions.
0000: An ADC conversion triggers from the ADCnT0 trigger source.
0001: An ADC conversion triggers from the ADCnT1 trigger source.
0010: An ADC conversion triggers from the ADCnT2 trigger source.
0011: An ADC conversion triggers from the ADCnT3 trigger source.
0100: An ADC conversion triggers from the ADCnT4 trigger source.
0101: An ADC conversion triggers from the ADCnT5 trigger source.
0110: An ADC conversion triggers from the ADCnT6 trigger source.
0111: An ADC conversion triggers from the ADCnT7 trigger source.
1000: An ADC conversion triggers from the ADCnT8 trigger source.
1001: An ADC conversion triggers from the ADCnT9 trigger source.
1010: An ADC conversion triggers from the ADCnT10 trigger source.
1011: An ADC conversion triggers from the ADCnT11 trigger source.
1100: An ADC conversion triggers from the ADCnT12 trigger source.
1101: An ADC conversion triggers from the ADCnT13 trigger source.
1110: An ADC conversion triggers from the ADCnT14 trigger source.
1111: An ADC conversion triggers from the ADCnT15 trigger source.
7:2
BMTK
Burst Mode Tracking Time.
This field Sets the time delay between consecutive conversions performed in Burst
Mode.
64 – BMTK +  3  TRKMD 
T BMTK = ----------------------------------------------------------------------F APB
Note: The Burst Mode track delay is not inserted prior to the first conversion. The
required tracking time for the first conversion should be defined with the ADPWM
field.
1
CLKESEL
Sampling Clock Edge Select.
This bit selects which edge of the APB clock is used during sampling. Note that if
the core is halted and a conversion completes while this bit is set to 1, the SCCI bit
will not set. It is recommended to leave this bit at 0 when debugging SAR-related
firmware.
0: Select the rising edge of the APB clock.
1: Select the falling edge of the APB clock.
Rev. 1.0
641
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.6. SARADCn_CONTROL Register Bit Descriptions
Bit
Name
0
REFGNDSEL
Function
Reference Ground Select.
This bit selects the reference ground for ADC conversions. The internal ground is
always used for temperature sensor measurements.
0: The internal device ground is used as the ground reference for ADC conversions.
1: The VREFGND pin is used as the ground reference for ADC conversions.
642
Rev. 1.0
31
23
Name
TS7MUX
TS7CHR
Type
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
TS5MUX
TS5CHR
Type
R
RW
RW
Reset
0
0
29
0
28
0
27
0
26
0
25
0
0
22
21
20
19
18
17
16
TS6MUX
TS6CHR
R
RW
RW
Reserved
30
Reserved
24
Reserved
Bit
Reserved
Register 32.3. SARADCn_SQ7654: Channel Sequencer Time Slots 4-7 Setup
TS4MUX
TS4CHR
R
RW
RW
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_SQ7654 = 0x4001_A020
SARADC1_SQ7654 = 0x4001_B020
Table 32.7. SARADCn_SQ7654 Register Bit Descriptions
Bit
Name
Function
31
Reserved
Must write reset value.
30:26
TS7MUX
Time Slot 7 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
25:24
TS7CHR
Time Slot 7 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 7.
01: Select conversion characteristic 1 for time slot 7.
10: Select conversion characteristic 2 for time slot 7.
11: Select conversion characteristic 3 for time slot 7.
23
Reserved
Must write reset value.
22:18
TS6MUX
Time Slot 6 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
Rev. 1.0
643
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.7. SARADCn_SQ7654 Register Bit Descriptions
Bit
Name
17:16
TS6CHR
Function
Time Slot 6 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 6.
01: Select conversion characteristic 1 for time slot 6.
10: Select conversion characteristic 2 for time slot 6.
11: Select conversion characteristic 3 for time slot 6.
15
Reserved
Must write reset value.
14:10
TS5MUX
Time Slot 5 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
9:8
TS5CHR
Time Slot 5 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 5.
01: Select conversion characteristic 1 for time slot 5.
10: Select conversion characteristic 2 for time slot 5.
11: Select conversion characteristic 3 for time slot 5.
7
Reserved
Must write reset value.
6:2
TS4MUX
Time Slot 4 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
1:0
TS4CHR
Time Slot 4 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 4.
01: Select conversion characteristic 1 for time slot 4.
10: Select conversion characteristic 2 for time slot 4.
11: Select conversion characteristic 3 for time slot 4.
644
Rev. 1.0
31
23
Name
TS3MUX
TS3CHR
Type
R
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
TS1MUX
TS1CHR
Type
R
RW
RW
Reset
0
0
29
0
28
0
27
0
26
0
25
0
0
22
21
20
19
18
17
16
TS2MUX
TS2CHR
R
RW
RW
Reserved
30
Reserved
24
Reserved
Bit
Reserved
Register 32.4. SARADCn_SQ3210: Channel Sequencer Time Slots 0-3 Setup
TS0MUX
TS0CHR
R
RW
RW
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_SQ3210 = 0x4001_A030
SARADC1_SQ3210 = 0x4001_B030
Table 32.8. SARADCn_SQ3210 Register Bit Descriptions
Bit
Name
Function
31
Reserved
Must write reset value.
30:26
TS3MUX
Time Slot 3 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
25:24
TS3CHR
Time Slot 3 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 3.
01: Select conversion characteristic 1 for time slot 3.
10: Select conversion characteristic 2 for time slot 3.
11: Select conversion characteristic 3 for time slot 3.
23
Reserved
Must write reset value.
22:18
TS2MUX
Time Slot 2 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
Rev. 1.0
645
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.8. SARADCn_SQ3210 Register Bit Descriptions
Bit
Name
17:16
TS2CHR
Function
Time Slot 2 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 2.
01: Select conversion characteristic 1 for time slot 2.
10: Select conversion characteristic 2 for time slot 2.
11: Select conversion characteristic 3 for time slot 2.
15
Reserved
Must write reset value.
14:10
TS1MUX
Time Slot 1 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
9:8
TS1CHR
Time Slot 1 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 1.
01: Select conversion characteristic 1 for time slot 1.
10: Select conversion characteristic 2 for time slot 1.
11: Select conversion characteristic 3 for time slot 1.
7
Reserved
Must write reset value.
6:2
TS0MUX
Time Slot 0 Input Channel.
A value of x in this field selects the ADCn.x channel as the ADCn input during this
time slot. Set this field to 0x1F to terminate the scan at this slot.
Time Slot 0 is also used to specify the parameters for single (non-scan mode) conversions.
1:0
TS0CHR
Time Slot 0 Conversion Characteristic.
Selects which of the conversion characteristic settings is used for this time slot.
00: Select conversion characteristic 0 for time slot 0.
01: Select conversion characteristic 1 for time slot 0.
10: Select conversion characteristic 2 for time slot 0.
11: Select conversion characteristic 3 for time slot 0.
646
Rev. 1.0
Register 32.5. SARADCn_CHAR32: Conversion Characteristic 2 and 3 Setup
29
28
27
26
25
24
23
Name
Reserved
Type
R
RW
22
21
20
19
18
17
16
CHR3LS
CHR3RPT
CHR3GN
30
CHR3RSEL
31
CHR3WCIEN
Bit
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
RW
0
0
Reset
0
0
0
0
0
0
0
CHR2LS
CHR2RPT
CHR2GN
Reserved
CHR2RSEL
Name
CHR2WCIEN
Reset
RW
RW
RW
RW
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_CHAR32 = 0x4001_A040
SARADC1_CHAR32 = 0x4001_B040
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 32.9. SARADCn_CHAR32 Register Bit Descriptions
Bit
Name
31:25
Reserved
24
CHR3WCIEN
Function
Must write reset value.
Conversion Characteristic 3 Window Comparator Interrupt Enable.
Enable window comparison interrupts for this channel.
0: Disable window comparison interrupts.
1: Enabled window comparison interrupts. The window comparator will be used to
check the ADC result on channels that use this characteristic.
23
CHR3RSEL
Conversion Characteristic 3 Resolution Selection.
Select between 10- and 12-bit mode.
0: Select 10-bit Mode.
1: Select 12-bit Mode (burst mode must be enabled).
22:20
CHR3LS
Conversion Characteristic 3 Left-Shift Bits.
This field specifies the number of bits to shift the result left at conversion completion. A zero value produces a fully right-justified result.
Rev. 1.0
647
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.9. SARADCn_CHAR32 Register Bit Descriptions
Bit
Name
19:17
CHR3RPT
Function
Conversion Characteristic 3 Repeat Counter.
This field determines the number of samples the converter will accumulate in burst
mode when the accumulation option is enabled.
000: Accumulate one sample.
001: Accumulate four samples.
010: Accumulate eight samples.
011: Accumulate sixteen samples.
100: Accumulate thirty-two samples (10-bit mode only).
101: Accumulate sixty-four samples (10-bit mode only).
110-111: Reserved.
16
CHR3GN
Conversion Characteristic 3 Gain.
0: The on-chip PGA gain is 1.
1: The on-chip PGA gain is 0.5.
15:9
Reserved
8
CHR2WCIEN
Must write reset value.
Conversion Characteristic 2 Window Comparator Interrupt Enable.
Enable window comparison interrupts for this channel.
0: Disable window comparison interrupts.
1: Enabled window comparison interrupts. The window comparator will be used to
check the ADC result on channels that use this characteristic.
7
CHR2RSEL
Conversion Characteristic 2 Resolution Selection.
Select between 10- and 12-bit mode.
0: Select 10-bit Mode.
1: Select 12-bit Mode (burst mode must be enabled).
6:4
CHR2LS
Conversion Characteristic 2 Left-Shift Bits.
This field specifies the number of bits to shift the result left at conversion completion. A zero value produces a fully right-justified result.
3:1
CHR2RPT
Conversion Characteristic 2 Repeat Counter.
This field determines the number of samples the converter will accumulate in burst
mode when the accumulation option is enabled.
000: Accumulate one sample.
001: Accumulate four samples.
010: Accumulate eight samples.
011: Accumulate sixteen samples.
100: Accumulate thirty-two samples (10-bit mode only).
101: Accumulate sixty-four samples (10-bit mode only).
110-111: Reserved.
0
CHR2GN
Conversion Characteristic 2 Gain.
0: The on-chip PGA gain is 1.
1: The on-chip PGA gain is 0.5.
648
Rev. 1.0
Register 32.6. SARADCn_CHAR10: Conversion Characteristic 0 and 1 Setup
29
28
27
26
25
24
23
Name
Reserved
Type
R
RW
22
21
20
19
18
17
16
CHR1LS
CHR1RPT
CHR1GN
30
CHR1RSEL
31
CHR1WCIEN
Bit
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
RW
0
0
Reset
0
0
0
0
0
0
0
CHR0LS
CHR0RPT
CHR0GN
Reserved
CHR0RSEL
Name
CHR0WCIEN
Reset
RW
RW
RW
RW
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_CHAR10 = 0x4001_A050
SARADC1_CHAR10 = 0x4001_B050
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 32.10. SARADCn_CHAR10 Register Bit Descriptions
Bit
Name
31:25
Reserved
24
CHR1WCIEN
Function
Must write reset value.
Conversion Characteristic 1 Window Comparator Interrupt Enable.
Enable window comparison interrupts for this channel.
0: Disable window comparison interrupts.
1: Enabled window comparison interrupts. The window comparator will be used to
check the ADC result on channels that use this characteristic.
23
CHR1RSEL
Conversion Characteristic 1 Resolution Selection.
Select between 10- and 12-bit mode.
0: Select 10-bit Mode.
1: Select 12-bit Mode (burst mode must be enabled).
22:20
CHR1LS
Conversion Characteristic 1 Left-Shift Bits.
This field specifies the number of bits to shift the result left at conversion completion. A zero value produces a fully right-justified result.
Rev. 1.0
649
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.10. SARADCn_CHAR10 Register Bit Descriptions
Bit
Name
19:17
CHR1RPT
Function
Conversion Characteristic 1 Repeat Counter.
This field determines the number of samples the converter will accumulate in burst
mode when the accumulation option is enabled.
000: Accumulate one sample.
001: Accumulate four samples.
010: Accumulate eight samples.
011: Accumulate sixteen samples.
100: Accumulate thirty-two samples (10-bit mode only).
101: Accumulate sixty-four samples (10-bit mode only).
110-111: Reserved.
16
CHR1GN
Conversion Characteristic 1 Gain.
0: The on-chip PGA gain is 1.
1: The on-chip PGA gain is 0.5.
15:9
Reserved
8
CHR0WCIEN
Must write reset value.
Conversion Characteristic 0 Window Comparator Interrupt Enable.
Enable window comparison interrupts for this channel.
0: Disable window comparison interrupts.
1: Enabled window comparison interrupts. The window comparator will be used to
check the ADC result on channels that use this characteristic.
7
CHR0RSEL
Conversion Characteristic 0 Resolution Selection.
Select between 10- and 12-bit mode.
0: Select 10-bit Mode.
1: Select 12-bit Mode (burst mode must be enabled).
6:4
CHR0LS
Conversion Characteristic 0 Left-Shift Bits.
This field specifies the number of bits to shift the result left at conversion completion. A zero value produces a fully right-justified result.
3:1
CHR0RPT
Conversion Characteristic 0 Repeat Counter.
This field determines the number of samples the converter will accumulate in burst
mode when the accumulation option is enabled.
000: Accumulate one sample.
001: Accumulate four samples.
010: Accumulate eight samples.
011: Accumulate sixteen samples.
100: Accumulate thirty-two samples (10-bit mode only).
101: Accumulate sixty-four samples (10-bit mode only).
110-111: Reserved.
0
CHR0GN
Conversion Characteristic 0 Gain.
0: The on-chip PGA gain is 1.
1: The on-chip PGA gain is 0.5.
650
Rev. 1.0
Register 32.7. SARADCn_DATA: Output Data Word
Bit
31
30
29
28
27
26
25
24
23
Name
DATA[31:16]
Type
R
22
21
20
19
18
17
16
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Name
DATA[15:0]
Type
R
Reset
X
X
X
X
X
X
X
X
X
Register ALL Access Addresses
SARADC0_DATA = 0x4001_A060
SARADC1_DATA = 0x4001_B060
Table 32.11. SARADCn_DATA Register Bit Descriptions
Bit
Name
31:0
DATA
Function
Output Data Word.
The DATA register represents the oldest information available in the FIFO. When
DATA is read, FIFOLVL decrements by one, and the FIFO pointer will point to the
next value in the FIFO. Data is packed according to the PACKMD field.
Rev. 1.0
651
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Register 32.8. SARADCn_WCLIMITS: Window Comparator Limits
Bit
31
30
29
28
27
26
25
24
23
Name
WCGT
Type
RW
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Name
WCLT
Type
RW
Reset
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_WCLIMITS = 0x4001_A070
SARADC1_WCLIMITS = 0x4001_B070
Table 32.12. SARADCn_WCLIMITS Register Bit Descriptions
Bit
Name
31:16
WCGT
Function
Greater-Than Window Comparator Limit.
This field is the right-justified "greater than" parameter for the window comparator.
ADC output data will be compared against this value when it is available.
When WCLT is greater than WCGT, an ADC result between the two limits will cause
a window compare interrupt, if enabled. When WCLT is less than WCGT, an ADC
result above or below the two limits (but not in between) will cause a window compare interrupt, if enabled.
15:0
WCLT
Less-Than Window Comparator Limit.
This field is the right-justified "less than" parameter for the window comparator. ADC
output data will be compared against this value when it is available.
When WCLT is greater than WCGT, an ADC result between the two limits will cause
a window compare interrupt, if enabled. When WCLT is less than WCGT, an ADC
result above or below the two limits (but not in between) will cause a window compare interrupt, if enabled.
652
Rev. 1.0
Register 32.9. SARADCn_ACC: Accumulator Initial Value
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Name
ACC
Type
W
Reset
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_ACC = 0x4001_A080
SARADC1_ACC = 0x4001_B080
Table 32.13. SARADCn_ACC Register Bit Descriptions
Bit
Name
31:16
Reserved
15:0
ACC
Function
Must write reset value.
Accumulator Initial Value.
This write-only field is used to set the accumulator to an initial value. In most cases,
this field should be written to zero before beginning a conversion or a scan
sequence when accumulation is enabled (ACCMD = 0).
Rev. 1.0
653
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Register 32.10. SARADCn_STATUS: Module Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
WCI
0
SCCI
0
SDI
0
FORI
Reset
FURI
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Type
R
RW
RW
RW
RW
RW
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_STATUS = 0x4001_A090
SARADC1_STATUS = 0x4001_B090
This register also supports SET access at (ALL+0x4) and CLR access at (ALL+0x8)
Table 32.14. SARADCn_STATUS Register Bit Descriptions
Bit
Name
31:5
Reserved
4
FURI
Function
Must write reset value.
FIFO Underrun Interrupt Flag.
This bit is set to 1 by hardware when a FIFO underrun event has occurred, and can
be used to trigger an interrupt if enabled. This bit must be cleared by software.
3
FORI
FIFO Overrun Interrupt Flag.
This bit is set to 1 by hardware when a FIFO overrun event has occurred, and can
be used to trigger an interrupt if enabled. This bit must be cleared by software.
2
SDI
Scan Done Interrupt Flag.
This bit is set to 1 by hardware when a scan operation is complete, and can be used
to trigger an interrupt if enabled. This bit must be cleared by software.
1
SCCI
Single Conversion Complete Interrupt Flag.
This bit is set to 1 by hardware at the end of each conversion, and can be used to
trigger an interrupt if enabled. This bit must be cleared by software.
0
WCI
Window Compare Interrupt Flag.
This bit is set to 1 by hardware when a window comparator event has occurred, and
can be used to trigger an interrupt if enabled. This bit must be cleared by software.
Notes:
1. This register contains interrupt flags. Firmware should only use the SET and CLR addresses when modifying interrupt
flags to avoid conflicts with hardware.
654
Rev. 1.0
Register 32.11. SARADCn_FIFOSTATUS: FIFO Status
Bit
31
30
29
28
27
26
25
24
23
Name
Reserved
Type
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
DPSTS
0
DRDYF
Reset
FIFOLVL
Type
R
R
R
R
0
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register ALL Access Addresses
SARADC0_FIFOSTATUS = 0x4001_A0A0
SARADC1_FIFOSTATUS = 0x4001_B0A0
Table 32.15. SARADCn_FIFOSTATUS Register Bit Descriptions
Bit
Name
31:6
Reserved
5
DRDYF
Function
Must write reset value.
Data Ready Flag.
This bit indicates that new data is ready to be written into the FIFO. It is set after the
data conversion is complete and cleared by any new conversion start trigger.
0: New data is not produced yet.
1: New data is ready.
4
DPSTS
Data Packing Status.
This is a read only status bit indicating to which half-word the hardware will write the
next ADC output data.
0: The next ADC conversion will be written to the lower half-word.
1: The next ADC conversion will be written to the upper half-word.
3:0
FIFOLVL
FIFO Level.
This is the number of ADC words in the FIFO. Each word may contain one or two
samples depending on the packing mode (PACKMD).
Rev. 1.0
655
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
32.12. SARADCn Register Memory Map
Table 32.16. SARADCn Memory Map
SARADCn_SQ3210 SARADCn_SQ7654 SARADCn_CONTROL SARADCn_CONFIG Register Name
0x10
0x30
ALL Offset
0x20
0x0
ALL | SET | CLR
ALL
Access Methods
ALL
ALL | SET | CLR
Reserved
Reserved
Reserved
Bit 31
VREFSEL
FURIEN
Bit 30
FORIEN
Bit 29
Reserved
TS3MUX
TS7MUX
SDIEN
Bit 28
MREFLPEN
SCCIEN
Bit 27
LPMDEN
Bit 26
Bit 25
TS3CHR
TS7CHR
BIASSEL
Bit 24
Reserved
Reserved
ADBUSY
Bit 23
TRKMD
Bit 22
CLKDIV
ACCMD
Bit 21
TS2MUX
TS6MUX
Reserved
Bit 20
VCMEN
Bit 19
AD12BSSEL
Bit 18
ADCEN
Bit 17
TS2CHR
TS6CHR
BURSTEN
Bit 16
Reserved
Reserved
BCLKSEL
Bit 15
DMAEN
Bit 14
PWRTIME
Reserved
Bit 13
TS1MUX
TS5MUX
SCANMD
Bit 12
Reserved
Bit 11
SCANEN
Bit 10
SCSEL
INTLVEN
Bit 9
TS1CHR
TS5CHR
SIMCEN
Bit 8
Reserved
Reserved
Bit 7
PACKMD
Bit 6
SSGEN
Bit 5
BMTK
TS0MUX
TS4MUX
SPEN
Bit 4
Bit 3
Bit 2
SPSEL
CLKESEL
Bit 1
TS0CHR
TS4CHR
REFGNDSEL
Bit 0
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: SARADC0 = 0x4001_A000, SARADC1 = 0x4001_B000
656
Rev. 1.0
SARADCn_WCLIMITS SARADCn_DATA SARADCn_CHAR10 SARADCn_CHAR32 Register Name
0x70
0x60
0x50
0x40
ALL Offset
ALL
ALL
ALL | SET | CLR
ALL | SET | CLR
Access Methods
Bit 31
Bit 30
Bit 29
Reserved
Reserved
Bit 28
Bit 27
Bit 26
Bit 25
CHR1WCIEN
CHR3WCIEN
Bit 24
WCGT
CHR1RSEL
CHR3RSEL
Bit 23
Bit 22
CHR1LS
CHR3LS
Bit 21
Bit 20
Bit 19
CHR1RPT
CHR3RPT
Bit 18
Bit 17
CHR1GN
CHR3GN
Bit 16
DATA
Bit 15
Bit 14
Bit 13
Reserved
Reserved
Bit 12
Bit 11
Bit 10
Bit 9
CHR0WCIEN
CHR2WCIEN
Bit 8
WCLT
CHR0RSEL
CHR2RSEL
Bit 7
Bit 6
CHR0LS
CHR2LS
Bit 5
Bit 4
Bit 3
CHR0RPT
CHR2RPT
Bit 2
Bit 1
CHR0GN
CHR2GN
Bit 0
Table 32.16. SARADCn Memory Map
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: SARADC0 = 0x4001_A000, SARADC1 = 0x4001_B000
Rev. 1.0
657
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Table 32.16. SARADCn Memory Map
SARADCn_FIFOSTATUS SARADCn_STATUS SARADCn_ACC Register Name
0x90
0x80
ALL Offset
0xA0
ALL | SET | CLR
ALL
Access Methods
ALL
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Reserved
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Reserved
Reserved
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ACC
Bit 7
Bit 6
DRDYF
Bit 5
FURI
DPSTS
Bit 4
FORI
Bit 3
SDI
Bit 2
FIFOLVL
SCCI
Bit 1
WCI
Bit 0
SAR Analog-to-Digital Converter (SARADC0 and SARADC1)
SiM3U1xx/SiM3C1xx
Notes:
1. The "ALL Offset" refers to the address offset of the ALL access method for a register, this offset should be referenced
to the base address for the block. For example, if a register block has a base address of 0x4001_0000 and the ALL
offset is specified to be 0xA4, the register's absolute ALL access address is located at 0x4001_00A0 in the address
map. A register may also support SET, CLR, and MSK access methods, as indicated by the "Access Methods" column.
SET, CLR and MSK addresses are offset from the ALL address by 4, 8 and 12 bytes, respectively. The register with
ALL access at 0x4001_00A0 may have a SET address at 0x4001_00A4, a CLR address at 0x4001_00A8, and a MSK
address at 0x4001_00AC.
2. The base addresses for this register block are: SARADC0 = 0x4001_A000, SARADC1 = 0x4001_B000
658
Rev. 1.0
33. Serial Peripheral Interface (SPI0, SPI1 and SPI2)
This section describes the Serial Peripheral Interface (SPI) module, and is applicable to all products in the following
device families, unless otherwise stated:
SiM3U1xx
SiM3C1xx
This section describes version “A” of the SPI block, which is used by SPI0, SPI1 and SPI2 on all device families
covered in this document.
33.1. SPI Features
The SPI module includes the following features:
Supports
3- or 4-wire master or slave modes.
up to 10 MHz clock in master mode and one-tenth of the APB clock in slave mode.
Support for all clock phase polarity and slave select (NSS) polarity modes.
16-bit programmable clock rate.
Programmable MSB-first or LSB-first shifting.
8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers.
Programmable FIFO threshold level to request data service for DMA transfers.
Support for multiple masters on the same data lines.
Supports
SPIn Module
NSS Polarity
Data Direction
SCK Phase
Master or Slave
SCK Polarity
Data Size
SCK
APB Clock
Clock Rate
Bus Control
NSS
MISO
DATA
Shift Register
TX FIFO
MOSI
RX FIFO
FIFO Status and
Control
Figure 33.1. SPI Block Diagram
Rev. 1.0
659
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
33.2. Signal Descriptions
The four signals used by the SPI module are MOSI, MISO, SCK, NSS. Figure 33.2 shows a typical SPI transfer.
33.2.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to the slave devices on the
bus. It is used to serially transfer data from the master to the slaves. This MOSI pin is an output when the module
operates as a master and an input when operating as a slave.
33.2.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is
used to serially transfer data from the slave to the master. The MISO pin is an input when the SPI module operates
as a master and an output when operating as a slave. The hardware places the MISO pin in a high-impedance
state when the module is disabled or when the module operates in 4-wire mode as a slave that is not selected.
33.2.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to the slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO pins. The SCK pin is an
output driving the clock when operating as a master and an input receiving the clock when operating as a slave.
33.2.4. Slave Select (NSS)
The slave select (NSS) signal can be an output from a master device (in 4-wire single master mode), an input to a
master device (in 4-wire multiple master), an input to a slave device (in 4-wire slave mode), or unused/
unconnected (in 3-wire master or 3-wire slave mode). The slave select mode (NSSMD) field in the CONFIG
register configures the NSS pin for the desired mode.
If NSS is used as either an output or input, the pin should have an external pull-up resistor to VIO.
The NSS signal may be optionally connected to a physical pin. The device port configuration module has more
information.
SCK
MOSI
MDn
MDn-1
MD4
MD3
MD2
MD1
MD0
MISO
SDn
SDn-1
SD4
SD3
SD2
SD1
SD0
Bit n
Bit n-1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS
...
Figure 33.2. 4-Wire SPI Transfer
660
Rev. 1.0
33.3. Clocking
The APB clock is the clock source for the SPI module. The SCK output clock in master mode is a divided version of
this clock. In both master and slave modes, the clock signal present on the SCK pin determines when data is
shifted out of or into the data shift register.
33.3.1. Master Mode Clocking
In master mode, an internal clock rate generator is used to divide down the APB clock to produce the desired SCK
rate, and the hardware drives the SCK pin as an output from the device. The 16-bit clock divider (CLKDIV) field in
the CLKRATE register sets the SCK frequency as a fraction of the APB clock. The CLKDIV bit description
describes the equation for the SCK frequency as a function of the APB clock.
33.3.2. Slave Mode Clocking
The CLKDIV field is not used in slave mode, and the SCK pin becomes an input to the device. A different device
should be configured as the SPI bus master and is expected to drive the SCK input at the desired frequency. The
maximum input SCK rate in slave mode is equal to the APB clock frequency divided by 10.
33.4. Signal Format
The SPI module has flexible data formatting options. The data length, clock phase, clock polarity, shift direction,
and NSS polarity are all selectable via fields in the CONFIG register.
33.4.1. Data Size and Shift Direction
The data size (DSIZE) field configures the transfer data length to be between 1 and 16 bits. DSIZE should be set to
one less than the desired data length; for an 8-bit data length, firmware should set DSIZE to 7.
The data direction select (DDIRSEL) field configures the data shift direction for both transmitted and received data.
The hardware can shift data MSB first (DDIRSEL = 0) or LSB first (DDIRSEL = 1).
33.4.2. Slave Select Polarity
The slave select polarity (NSSPOL) bit determines the polarity of the NSS pin for both master mode where NSS is
an output and for slave mode where NSS is an input. The pin can be active low (NSSPOL = 0) or active high
(NSSPOL = 1).
33.4.3. Clock Phase and Polarity Configuration
The CLKPHA and CLKPOL bits configure the SCK pin phase and polarity, respectively. Clearing CLKPHA to 0
places the SCK edge at the center of the data bit, and setting CLKPHA to 1 places the SCK edge at the data bit
transition edge. The clock can also be idle low (CLKPOL = 0) or idle high (CLKPOL = 1).
The CLKPHA and CLKPOL bits must be set in both master and slave modes. In master mode, these bits determine
the characteristics of the clock driven on of the SCK output. In slave mode, these bits set the characteristics of the
clock that the module expects to receive on the SCK input. The clock phase and polarity settings determine when
the data transitions take place with respect to the SCK phase.
Figure 33.3 illustrates all clock polarity and phase combinations when DDIRSEL is cleared to 0. Figure 33.4
illustrates all clock polarity and phase combinations when DDIRSEL is set to 1.
Rev. 1.0
661
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
CLKPHA = 0
CLKPOL = 0
SCK
MOSI
Dn
Dn-1
Bit n
Bit n-1
Dn
Dn-1
Bit n
Bit n-1
Dn
Dn-1
Bit n
Bit n-1
Dn
Dn-1
Bit n
Bit n-1
...
D4
D3
D2
D1
D0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D4
D3
D2
D1
D0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D4
D3
D2
D1
D0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D4
D3
D2
D1
D0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKPHA = 0
CLKPOL = 1
SCK
MOSI
...
CLKPHA = 1
CLKPOL = 0
SCK
MOSI
...
CLKPHA = 1
CLKPOL = 1
SCK
MOSI
...
Figure 33.3. SPI Clock Polarity and Phase Combinations (DDIRSEL = 0, Master Mode)
662
Rev. 1.0
CLKPHA = 0
CLKPOL = 0
SCK
MOSI
D0
D1
D2
D3
D4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
D0
D1
D2
D3
D4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
D0
D1
D2
D3
D4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
D0
D1
D2
D3
D4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
...
Dn-1
Dn
Bit n-1
Bit n
Dn-1
Dn
Bit n-1
Bit n
Dn-1
Dn
Bit n-1
Bit n
Dn-1
Dn
Bit n-1
Bit n
CLKPHA = 0
CLKPOL = 1
SCK
MOSI
...
CLKPHA = 1
CLKPOL = 0
SCK
MOSI
...
CLKPHA = 1
CLKPOL = 1
SCK
MOSI
...
Figure 33.4. SPI Clock Polarity and Phase Combinations (DDIRSEL = 1, Master Mode)
Rev. 1.0
663
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
33.5. Master Mode Configurations and Data Transfer
Firmware can set the MSTEN bit to 1 to configure the module as a master. The module supports three different
options of master mode operation.
33.5.1. 3-Wire Single Master Mode
In 3-wire single master mode (NSSMD = 0), the slave select (NSS) pin is not required and may not be connected to
port pins by the device port configuration module. In this mode, the device should be connected to a single slave
device that either doesn't support an NSS input or has its NSS input tied low. To support multiple slaves in 3-wire
single master mode, each slave device must have an NSS input, the NSS inputs must be connected to a unique
port pin on the master device, and each pin must be controlled from firmware (bit-banged).
Figure 33.5 illustrates the master-slave connection diagram for 3-wire single master mode.
Master Device
Slave Device
SCK
SCK
SPIn
Module
MISO
MISO
MOSI
MOSI
NSS
Figure 33.5. 3-Wire Single Master Mode Connection Diagram
33.5.2. 4-Wire Single Master Mode
In 4-wire single master mode (NSSMD = 2 or 3), the slave select (NSS) pin is configured as an output and should
be connected to the NSS input of the first slave device. An additional slave device added on the SPI bus should
have its NSS input driven by a firmware-controlled port pin output from the master device. The least-significant bit
of NSSMD determines the state of the master’s NSS pin in this mode.
Figure 33.6 shows the master-slave connection diagram for 4-wire single master mode.
Master Device
Slave Device
SCK
SCK
SPIn
Module
MISO
MISO
MOSI
MOSI
NSS
NSS
Figure 33.6. 4-Wire Single Master Mode Connection Diagram
664
Rev. 1.0
33.5.3. 4-Wire Multiple Master Mode
Set the NSSMD (Slave Select Mode) field to 0x01 to configure the NSS pin for 4-wire slave / multi master mode.
In 4-wire multiple master mode (NSSMD = 1), the slave select (NSS) pin is configured as an input and is used to
disable the SPI module while another SPI master accesses the bus. When the NSS input is driven low by the bus
master, two events occur:
1. Hardware clears the master mode enable (MSTEN) and SPI enable (SPIEN) bits to disable the SPI
module. The module must be manually re-enabled by firmware.
2. Hardware sets the mode fault interrupt (MDFI) flag. This will generate an interrupt if the mode fault interrupt
is enabled (MDFIEN = 1).
Slave devices on the SPI bus should have their NSS inputs driven by a firmware-controlled port pin output from the
master devices.
Figure 33.7 illustrates the connection diagram for 4-wire multiple master mode.
Master Device 1
Slave Device
SCK
SCK
SPIn
Module
MISO
MISO
MOSI
MOSI
NSS
NSS
port pin
Master Device 2
NSS
MOSI
MISO
SCK
port pin
Figure 33.7. 4-Wire Multiple Master Mode Connection Diagram
33.5.4. Master Mode Data Transfer
A master device initiates all data transfers on a SPI bus. When the SPI module is first enabled by setting the SPIEN
bit to 1, the transmit and receive FIFOs are empty. The hardware sets the transmit FIFO write request interrupt
(TFRQI) flag when the number of empty slots in the transmit FIFO is at or above the transmit FIFO threshold
(TFTH), which causes an interrupt, if enabled (TFRQIEN = 1). Firmware can then write to the DATA register in
right-justified bytes, half-words, or full words to transfer data to the transmit FIFO.
When the shift register is empty, the hardware retrieves data from the transmit FIFO and begins a transmission.
The module immediately shifts the data out serially on the MOSI line while driving the serial clock on SCK. When
both the transmit FIFO and the shift register are empty, the hardware sets the underrun interrupt (URI) flag,
resulting in an interrupt if the underrun interrupt is enabled (URIEN = 1).
Rev. 1.0
665
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
The SPI bus is full-duplex, so the addressed SPI slave device may also be simultaneously transferring the contents
of its shift register back to the SPI master using the MISO line as the master transfers data to a slave using MOSI.
The shift register empty interrupt (SREI) flag serves as both a transmit-complete flag and receive-data-ready flag.
When a received byte is fully transferred into the shift register, the hardware automatically moves it into the receive
FIFO where it may be accessed by reading the DATA register.
33.6. Slave Mode Configurations and Data Transfer
Clearing the master mode enable (MSTEN) bit configures the SPI module for slave mode. Firmware should first
fully configure the module (data length, clock polarity and phase, and slave mode) before setting the SPIEN bit to
initiate SPI operations.
33.6.1. 3-Wire Slave Mode
In 3-wire slave mode (NSSMD = 0), the slave select (NSS) pin is not required and may not be connected to
physical pins by the device’s port configuration module. Because there is no means to uniquely address multiple
slave devices in this mode, the device’s SPI module should be the only slave device present on the bus in 3-wire
slave mode. In addition, the master’s pins should be in an idle state before enabling the module in 3-wire slave
mode, since any unexpected transitions on SCK can cause erroneous bits to be shifted into the shift register
without the NSS signal to gate the clock on SCK.
Figure 33.8 illustrates the connection diagram for 3-wire slave mode.
Master Device
Slave Device
SCK
SCK
MISO
MISO
MOSI
SPIn
Module
MOSI
NSS
Figure 33.8. 3-Wire Single Slave Mode Connection Diagram
33.6.1.1. 4-Wire Slave Mode
In 4-wire slave mode (NSSMD = 2), the slave select (NSS) pin is configured as an input and should be connected
to the NSS output of the master device. Any additional slaves should have their NSS pins be connected to one of
the master’s general purpose port pins controlled by firmware.
Asserting the NSS signal enables the SPI module, and deasserting NSS disables the module. The polarity of the
NSS input can be set using the NSSPOL bit. The NSS signal must be asserted for at least two APB clocks before
the first active edge of SCK for each byte transfer.
Figure 33.9 shows the connection diagram for 4-wire slave mode.
666
Rev. 1.0
Master Device
Slave Device 1
SCK
SCK
MISO
SPIn
Module
MISO
MOSI
MOSI
NSS
NSS
port pin
Slave Device 2
SCK
MISO
MOSI
NSS
Figure 33.9. 4-Wire Slave Mode Connection Diagram
33.6.2. Slave Mode Data Transfer
In a SPI slave device, the master-generated clock input on the slave’s SCK signal drives the data bytes received
on MOSI and transmitted out through MISO. The hardware copies the data into the receive FIFO after receiving the
number of bits specified by the DSIZE field. When the number of filled slots in the receive FIFO reaches or exceeds
the programmed receive FIFO threshold (RFTH), hardware sets the receive FIFO read request interrupt (RFRQI)
flag and generates an interrupt if RFRQIEN is set to 1. Firmware can read from the DATA register in right-justified
bytes, half-words, or full words to pop data from the receive FIFO.
A slave device cannot initiate transfers and should pre-load the data into the transmit FIFO by writing to the DATA
register before the master begins a transfer. If the shift register is empty, the hardware moves the first data in the
transmit FIFO to the shift register in preparation for the data transfer.
Rev. 1.0
667
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
Serial Peripheral Interface (SPI0, SPI1 and SPI2)
SiM3U1xx/SiM3C1xx
33.7. Interrupts
The SPI module has several interrupt sources that can generate a SPI interrupt. All sources can be enabled or
disabled by a corresponding interrupt enable bit except for the illegal FIFO access interrupts (TFILI and RFILI),
which are always enabled.
33.7.1. Transmit Interrupts
The transmit FIFO write request (TFRQI) flag indicates that the FIFO has more room for data. Hardware sets this
flag when the number of empty slots in the transmit FIFO is greater than or equal to the number of slots specified in
the TFTH field. If DMA operations are enabled, a DMA request will be generated when hardware sets the flag. This
flag can also generate an interrupt if the TFRQIEN bit is set to 1 until the number of empty slots in the transmit
FIFO level drops below the TFTH setting.
33.7.2. Receive Interrupts
This receive FIFO read request interrupt (RFRQI) flag indicates that the receive FIFO has data available to be read
by firmware. Hardware sets this bit when the number of filled slots in the receive FIFO is greater than or equal to
the number of slots specified in the RFTH field. A DMA request will be generated if DMA is enabled (DMAEN = 1).
If the receive FIFO read request interrupt is enabled (RFRQIEN = 1), an interrupt will also be generated until the
number of filled slots in the receive FIFO drops below the RFTH setting.
33.7.3. Other Interrupts
The slave sele