SiM3U1xx High-Performance, Low-Power, 32-Bit Precision32™ USB MCU Family with up to 256 kB of Flash 32-bit ARM® Cortex™-M3 CPU - 80 MHz maximum frequency - Single-cycle multiplication, hardware division support - Nested vectored interrupt control (NVIC) with 16 levels of interrupt priority Memory - 32–256 kB Flash, in-system programmable - 8–32 kB SRAM (including 4 kB retention SRAM) - External bus interface supports up to 16 MB of external memory and a parallel LCD interface with QVGA resolution Power Management - Low drop-out (LDO) regulator - Power-on reset circuit and brownout detectors - 5-to-3.3 V voltage regulator supports up to 150 mA to drive the - device directly from USB; no off-chip regulator required Programmable external regulator supports up to 3.6 V, 1000 mA Multiple power modes supported for low power optimization Clock Sources - Internal oscillator with PLL: Fine frequency resolution up to - 80 MHz; spread-spectrum mode for reduced EMI USB internal 48 MHz oscillator supports crystal-less operation Low power internal oscillator: 20 MHz and 2.5 MHz modes Low frequency internal oscillator: 16.4 kHz External oscillators: Crystal, RC, C, CMOS and RTC Crystal Flexible clock divider: Reduce frequency by up to 128x from any clock source 128/192/256-bit Hardware AES Encryption - Hardware-supported Electronic Codebook (ECB), Cipher-Block Chaining (CBC) and Counter (CTR) algorithms - All cipher operations can be performed without any firmware intervention for a set of 4-word blocks (up to 32 kB) 16/32-bit CRC - Hardware support for common 32-bit and 16-bit polynomials Timers/Counters - 2 x 32-bit or 4 x 16-bit timers with capture/compare - 2 x 16-bit, 2-channel counters with capture/compare/PWM - 16-bit, 6-channel counter with capture/compare/PWM and dead-time controller with differential outputs - 16-bit low power timer/pulse counter operational in the lowest power mode - 32-bit real time clock (RTC) with multiple alarms - Watchdog timer Current-to-Voltage Converter - Supports up to 6 mA input range Supply Voltage - 2.7 to 5.5 V (regulator enabled) - 1.8 to 3.6 V (regulator disabled) Preliminary Rev. 0.8 2/12 Low Power Features - 85 nA current mode with voltage supply monitor enabled - 350 nA current mode with RTC (internal oscillator) - 620 nA current mode with RTC (external oscillator) - 10 µs wakeup (lowest power mode); 1.5 µs analog setting time - 275 µA/MHz active current - Clocks can be gated off from unused peripherals to save power 2 x 12-Bit Analog-to-Digital Converters - Up to 28 input channels - Up to 250 ksps 12-bit mode or 1 Msps 10-bit mode - Single, simultaneous, and interleaving modes supported - Channel sequencer enables automatic multiplexing of multiple channels without firmware intervention - Internal VREF or external VREF supported 2 x 10-Bit Digital-to-Analog Converters - DMA support for waveform generation - Four-word circular buffer to enable 12-bit mode 16-Channel Capacitance-to-Digital Converter - Supports buttons, sliders, wheels, and capacitive proximity - Fast conversion time; <1 µA wake-on-touch average current Two Low-Current Comparators - Integrated 6-bit programmable reference voltage - 400 nA current consumption in low power mode 16-Channel DMA Controller - Supports ADC, DAC, USB, I2C, I2S, SPI, USART, AES, EPCA, capacitive sensing, external triggers, and timers Up to 65 Flexible I/O - Up to 59 contiguous GPIO with two priority crossbars providing flexibility in pin assignments; 12 x 5 V tolerant GPIO - Up to 6 programmable high drive capable (5–300 mA, 1.8–6 V) I/O can drive LEDs, power MOSFETs, buzzers, etc. Communication Interfaces - USB 2.0-compliant full speed with 10 endpoints, 2 kB buffer, oscillator with automatic frequency correction, and transceiver; no external components needed 2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard - 3 x SPIs, 2 x I2C, I2S (receive and transmit) On-Chip Debugging - Serial wire debug (SWD) and JTAG allow for full-speed, nonintrusive debug - Serial wire viewer (SWV) available in 64 / 80 / 92-pin packages - Cortex-M3 embedded trace macrocell (ETM) in 80 / 92-pin packages Temperature Range: –40 to +85 °C Package Options - QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm) - TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm) - LGA option: 92-pin (7 x 7 mm) Copyright © 2012 by Silicon Laboratories SiM3U1xx This information applies to a product under development. Its characteristics and specifications are subject to change without notice. SiM3U1xx 2 Preliminary Rev. 0.8 SiM3U1xx Ta ble of Contents 1. Related Documents and Conventions ...............................................................................5 1.1. Related Documents........................................................................................................5 1.1.1. SiM3U1xx/SiM3C1xx Reference Manual...............................................................5 1.1.2. Hardware Access Layer (HAL) API Description ....................................................5 1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5 1.2. Conventions ...................................................................................................................5 2. Typical Connection Diagrams ............................................................................................6 2.1. Power .............................................................................................................................6 3. Electrical Specifications......................................................................................................9 3.1. Electrical Characteristics ................................................................................................9 3.2. Thermal Conditions ...................................................................................................... 33 3.3. Absolute Maximum Ratings..........................................................................................33 4. Precision32™ SiM3U1xx System Overview .................................................................... 35 4.1. Power ........................................................................................................................... 37 4.1.1. LDO and Voltage Regulator (VREG0) ................................................................. 37 4.1.2. Voltage Supply Monitor (VMON0) ....................................................................... 37 4.1.3. External Regulator (EXTVREG0) ........................................................................ 37 4.1.4. Power Management Unit (PMU).......................................................................... 37 4.1.5. Device Power Modes........................................................................................... 38 4.2. I/O................................................................................................................................. 40 4.2.1. General Features.................................................................................................40 4.2.2. High Drive Pins (PB4)..........................................................................................40 4.2.3. 5 V Tolerant Pins (PB3) ....................................................................................... 40 4.2.4. Crossbars ............................................................................................................ 40 4.3. Clocking........................................................................................................................ 41 4.3.1. PLL (PLL0)........................................................................................................... 42 4.3.2. Low Power Oscillator (LPOSC0) ......................................................................... 42 4.3.3. Low Frequency Oscillator (LFOSC0)................................................................... 42 4.3.4. External Oscillators (EXTOSC0).......................................................................... 42 4.4. Data Peripherals...........................................................................................................43 4.4.1. 16-Channel DMA Controller................................................................................. 43 4.4.2. 128/192/256-bit Hardware AES Encryption (AES0) ............................................ 43 4.4.3. 16/32-bit CRC (CRC0)......................................................................................... 43 4.5. Counters/Timers and PWM ..........................................................................................44 4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1)........................................ 44 4.5.2. 32-bit Timer (TIMER0, TIMER1).......................................................................... 44 4.5.3. Real-Time Clock (RTC0) ..................................................................................... 45 4.5.4. Low Power Timer (LPTIMER0)............................................................................45 4.5.5. Watchdog Timer (WDTIMER0)............................................................................45 4.6. Communications Peripherals ....................................................................................... 46 4.6.1. External Memory Interface (EMIF0).....................................................................46 4.6.2. USB0 .................................................................................................................. 46 4.6.3. USART (USART0, USART1)............................................................................... 46 4.6.4. UART (UART0, UART1) ...................................................................................... 47 Preliminary Rev. 0.8 3 SiM3U1xx 4.6.5. SPI (SPI0, SPI1) .................................................................................................. 47 4.6.6. I2C (I2C0, I2C1)................................................................................................... 47 4.6.7. I2S (I2S0)............................................................................................................. 48 4.7. Analog .......................................................................................................................... 49 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1).............................. 49 4.7.2. Sample Sync Generator (SSG0) ......................................................................... 49 4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................ 49 4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) ............................ 50 4.7.5. Low Current Comparators (CMP0, CMP1) .......................................................... 50 4.7.6. Current-to-Voltage Converter (IVC0) ................................................................... 50 4.8. Reset Sources..............................................................................................................51 4.9. Security ........................................................................................................................ 52 4.10.On-Chip Debugging ..................................................................................................... 52 5. Pin Definitions and Packaging Information.....................................................................53 5.1. SiM3U1x7 Pin Definitions............................................................................................. 53 5.2. SiM3U1x6 Pin Definitions............................................................................................. 61 5.3. SiM3U1x4 Pin Definitions............................................................................................. 68 6. Ordering Information .........................................................................................................72 6.1. LGA-92 Package Specifications...................................................................................74 6.1.1. LGA-92 Solder Mask Design ............................................................................... 76 6.1.2. LGA-92 Stencil Design ........................................................................................ 76 6.1.3. LGA-92 Card Assembly ....................................................................................... 76 6.2. TQFP-80 Package Specifications ................................................................................ 77 6.2.1. TQFP-80 Solder Mask Design............................................................................. 80 6.2.2. TQFP-80 Stencil Design ...................................................................................... 80 6.2.3. TQFP-80 Card Assembly..................................................................................... 80 6.3. QFN-64 Package Specifications .................................................................................. 81 6.3.1. QFN-64 Solder Mask Design............................................................................... 83 6.3.2. QFN-64 Stencil Design ........................................................................................ 83 6.3.3. QFN-64 Card Assembly....................................................................................... 83 6.4. TQFP-64 Package Specifications ................................................................................ 84 6.4.1. TQFP-64 Solder Mask Design............................................................................. 87 6.4.2. TQFP-64 Stencil Design ...................................................................................... 87 6.4.3. TQFP-64 Card Assembly..................................................................................... 87 6.5. QFN-40 Package Specifications .................................................................................. 88 6.5.1. QFN-40 Solder Mask Design............................................................................... 90 6.5.2. QFN-40 Stencil Design ........................................................................................ 90 6.5.3. QFN-40 Card Assembly....................................................................................... 90 7. Revision Specific Behavior............................................................................................... 91 7.1. Revision Identification .................................................................................................. 91 7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)...................... 92 7.2.1. Problem ...............................................................................................................92 7.2.2. Impacts ................................................................................................................ 92 7.2.3. Workaround ......................................................................................................... 92 7.2.4. Resolution............................................................................................................ 92 Contact Information ................................................................................................................ 94 4 Preliminary Rev. 0.8 SiM3U1xx 1. Related Documents and Conventions 1.1. Related Documents This data sheet accompanies several documents to provide the complete description of the SiM3U1xx device family. 1.1.1. SiM3U1xx/SiM3C1xx Reference Manual The Silicon Laboratories SiM3U1xx/SiM3C1xx Reference Manual provides detailed functional descriptions for the SiM3U1xx devices. 1.1.2. Hardware Access Layer (HAL) API Description The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read each bit in the SiM3U1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual. 1.1.3. ARM Cortex-M3 Reference Manual The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3 reference documentation. The online reference manual can be found here: http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3. 1.2. Conventions The block diagrams in this document use the following formatting conventions: Internal Module Other Internal Peripheral Block External Memory Block DMA Block Memory Block Input_Pin External to MCU Block Output_Pin Functional Block Internal_Input_Signal Internal_Output_Signal REGn_NAME / BIT_NAME Figure 1.1. Block Diagram Conventions Preliminary Rev. 0.8 5 SiM3U1xx 2. Typical Connection Diagrams This section provides typical connection diagrams for SiM3U1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator is in use and USB is not used. SiM3U1xx Device 5 V (in) VBUS VREGn 3.3 V (out) 1 uF and 0.1 uF bypass capacitors required for each power pin placed as close to the pins as possible. VREGIN VIOHD VDD VIO VSS VSSHD Figure 2.1. Connection Diagram with Voltage Regulator Used and No USB Figure 2.2 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator and USB are not used. SiM3U1xx Device 1.8-3.6 V (in) VBUS VREGn VREGIN VIOHD 1 uF and 0.1 uF bypass capacitors required for each power pin placed as close to the pins as possible. VDD VIO VSS VSSHD Figure 2.2. Connection Diagram with Voltage Regulator Not Used and No USB Figure 2.3 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used and USB is connected (bus-powered). 6 Preliminary Rev. 0.8 SiM3U1xx SiM3U1xx Device USB 5 V (in) VBUS VREGn 3.3 V (out) 1 uF and 0.1 uF bypass capacitors required for each power pin placed as close to the pins as possible. VREGIN VIOHD VDD VIO VSS VSSHD Figure 2.3. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) Figure 2.4 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used and USB is connected (self-powered). The VBUS signal is used to detect when USB is connected to a host device. USB 5 V (sense) SiM3U1xx Device 3.6-5.5 V (in) VBUS VREGn 1 uF and 0.1 uF bypass capacitors required for each power pin placed as close to the pins as possible. 3.3 V (out) VREGIN VIOHD VDD VIO VSS VSSHD Figure 2.4. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) Figure 2.5 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used, USB is connected (bus-powered), and the VIO and VIOHD pins are sourced from separate supplies. Preliminary Rev. 0.8 7 SiM3U1xx SiM3U1xx Device USB 5 V (in) VBUS 3.3-6 V (in) VREGn VREGIN 1 uF and 0.1 uF bypass capacitors required for each power pin placed as close to the pins as possible. 3.3 V (out) VIOHD 1.8-3.3 V (in) VDD VIO VSS VSSHD Figure 2.5. Connection Diagram with Voltage Regulator Used, USB Connected (Bus-Powered), and I/O Powered Separately 8 Preliminary Rev. 0.8 SiM3U1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Operating Supply Voltage on VDD Operating Supply Voltage on VREGIN Operating Supply Voltage on VIO Operating Supply Voltage on VIOHD Symbol Conditions Min Typ Max Units 1.8 — 3.6 V EXTVREG0 Not Used 4 — 5.5 V EXTVREG0 Used 3.0 — 3.6 V 1.8 — VDD V HV Mode (default) 2.7 — 6.0 V LV Mode 1.8 — 3.6 V VSS — VIO V SiM3U1x7 PB3.0–PB3.7 and RESET VSS — VIO+2.0 V SiM3U1x7 PB3.8 - PB3.11 VSS — Lowest of VIO+2.0 or VREGIN V SiM3U1x6 PB3.0–PB3.5 and RESET VSS — VIO+2.0 V SiM3U1x6 PB3.6–PB3.9 VSS — Lowest of VIO+2.0 or VREGIN V SiM3U1x4 RESET VSS — VIO+2.0 V SiM3U1x4 PB3.0–PB3.3 VSS — Lowest of VIO+2.0 or VREGIN V VDD VREGIN VIO VIOHD Voltage on I/O pins, Port Bank 0, 1 and 2 I/O VIN Voltage on I/O pins, Port Bank 3 I/O and RESET VIN Voltage on I/O pins, Port Bank 4 I/O VIN VSSHD — VIOHD V System Clock Frequency (AHB) fAHB 0 — 80 MHz Peripheral Clock Frequency (APB) fAPB 0 — 50 MHz Operating Ambient Temperature TA –40 — 85 °C Operating Junction Temperature TJ –40 — 105 °C Note: All voltages with respect to VSS. Preliminary Rev. 0.8 9 SiM3U1xx Table 3.2. Power Consumption Parameter Symbol Conditions Min Typ Max Units IDD FAHB = 80 MHz, FAPB = 40 MHz — 33 36.5 mA FAHB = FAPB = 48 MHz — 28.5 31 mA FAHB = FAPB = 20 MHz — 10.5 13.3 mA FAHB = FAPB = 2.5 MHz — 2.0 3.8 mA FAHB = 80 MHz, FAPB = 40 MHz — 22 24.9 mA FAHB = FAPB = 48 MHz — 14.5 17.2 mA FAHB = FAPB = 20 MHz — 7.8 10 mA FAHB = FAPB = 2.5 MHz — 1.2 3 mA FAHB = 80 MHz, FAPB = 40 MHz — 30.5 35.5 mA FAHB = FAPB = 48 MHz — 26.8 29.5 mA FAHB = FAPB = 20 MHz — 8.5 10 mA FAHB = FAPB = 2.5 MHz — 1.7 3.5 mA FAHB = 80 MHz, FAPB = 40 MHz — 20 23 mA FAHB = FAPB = 48 MHz — 13 15.3 mA FAHB = FAPB = 20 MHz — 5.3 7.3 mA FAHB = FAPB = 2.5 MHz — 1.0 2.8 mA FAHB = 80 MHz, FAPB = 40 MHz — 19 22 mA FAHB = FAPB = 48 MHz — 19 21.5 mA FAHB = FAPB = 20 MHz — 7.8 9.7 mA FAHB = FAPB = 2.5 MHz — 1.3 3 mA Digital Core Supply Current Normal Mode2,3,4,5—Full speed with code executing from Flash, peripheral clocks ON 2,3,4,5 Normal Mode —Full speed with code executing from Flash, peripheral clocks OFF Power Mode 12,3,4,6—Full speed with code executing from RAM, peripheral clocks ON Power Mode 12,3,4,6—Full speed with code executing from RAM, peripheral clocks OFF Power Mode 22,3,4—Core halted with peripheral clocks ON IDD IDD IDD IDD Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 3. Includes all peripherals that cannot have clocks gated in the Clock Control module. 4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz). 5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less. 6. RAM execution numbers use 0 wait states for all frequencies. 7. IDAC output current and IVC input current not included. 8. Bias current only. Does not include dynamic current from oscillator running at speed. 10 Preliminary Rev. 0.8 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Power Mode 32,3 Power Mode 92,3—Low Power Shutdown with VREG0 disabled, powered through VDD and VIO Power Mode 92,3—Low Power Shutdown with VREG0 in lowpower mode, VDD and VIO powered through VREG0 (Includes VREG0 current) VIOHD Current (High-drive I/O disabled) Symbol Conditions Min Typ Max Units IDD VDD = 1.8 V, TA = 25 °C — 175 — µA VDD = 3.0 V, TA = 25 °C — 250 — µA RTC Disabled, VDD = 1.8 V, TA = 25 °C — 85 — nA RTC w/ 16.4 kHz LFO, VDD = 1.8 V, TA = 25 °C — 350 — nA RTC w/ 32.768 kHz Crystal, VDD = 1.8 V, TA = 25 °C — 620 — nA RTC Disabled, VDD = 3.0 V, TA = 25 °C — 145 — nA RTC w/ 16.4 kHz LFO, VDD = 3.0 V, TA = 25 °C — 500 — nA RTC w/ 32.768 kHz Crystal, VDD = 3.0 V, TA = 25 °C — 800 — nA RTC Disabled, VREGIN = 5 V, TA = 25 °C — 300 — nA RTC w/ 16.4 kHz LFO, VREGIN = 5 V, TA = 25 °C — 650 — nA RTC w/ 32.768 kHz Crystal, VREGIN = 5 V, TA = 25 °C — 950 — nA HV Mode (default) — 2.5 5 µA LV Mode — 2 — nA IDD IVREGIN IVIOHD Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 3. Includes all peripherals that cannot have clocks gated in the Clock Control module. 4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz). 5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less. 6. RAM execution numbers use 0 wait states for all frequencies. 7. IDAC output current and IVC input current not included. 8. Bias current only. Does not include dynamic current from oscillator running at speed. Preliminary Rev. 0.8 11 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Min Typ Max Units IVREGIN Normal Mode, TA = 25 °C BGDIS = 0, SUSEN = 0 — 300 — µA Normal Mode, TA = 85 °C BGDIS = 0, SUSEN = 0 — — 650 µA Suspend Mode, TA = 25 °C BGDIS = 0, SUSEN = 1 — 75 — µA Suspend Mode, TA = 85 °C BGDIS = 0, SUSEN = 1 — — 115 µA Sleep Mode, TA = 25 °C BGDIS = 1, SUSEN = X — 90 — nA Sleep Mode, TA = 85 °C BGDIS = 1, SUSEN = X — — 500 nA Regulator — 215 250 µA Current Sensor — 7 — µA Analog Peripheral Supply Currents Voltage Regulator (VREG0) External Regulator (EXTVREG0) IEXTVREG PLL0 Oscillator (PLL0OSC) IPLLOSC Operating at 80 MHz — 1.75 1.86 mA USB0 Oscillator (USB0OSC) IUSBOSC Operating at 48 MHz — 770 830 µA ILPOSC Operating at 20 MHz — 190 — µA Operating at 2.5 MHz — 40 — µA Operating at 16.4 kHz, TA = 25 °C — 215 — nA Operating at 16.4 kHz, TA = 85 °C — — 500 nA Low-Power Oscillator (LPOSC0) Low-Frequency Oscillator (LFOSC0) ILFOSC Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 3. Includes all peripherals that cannot have clocks gated in the Clock Control module. 4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz). 5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less. 6. RAM execution numbers use 0 wait states for all frequencies. 7. IDAC output current and IVC input current not included. 8. Bias current only. Does not include dynamic current from oscillator running at speed. 12 Preliminary Rev. 0.8 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter External Oscillator (EXTOSC0)8 SARADC0, SARADC1 Temperature Sensor Internal SAR Reference Symbol Conditions Min Typ Max Units IEXTOSC FREQCN = 111 — 3.8 4.7 mA FREQCN = 110 — 840 950 µA FREQCN = 101 — 185 220 µA FREQCN = 100 — 65 80 µA FREQCN = 011 — 25 30 µA FREQCN = 010 — 10 15 µA FREQCN = 001 — 5 10 µA FREQCN = 000 — 3 8 µA Sampling at 1 Msps, highest power mode settings. — 1.2 1.5 mA Sampling at 250 ksps, lowest power mode settings. — 390 510 µA — 75 105 µA Normal Power Mode — 680 750 µA Low Power Mode — 160 190 µA — 75 100 µA CMPMD = 11 — 0.5 — µA CMPMD = 10 — 3 — µA CMPMD = 01 — 10 — µA CMPMD = 00 — 25 — µA Continuous Conversions — 55 80 µA — 75 90 µA — 1.5 1.9 µA — 15 25 µA ISARADC ITSENSE IREFFS VREF0 IREFP Comparator 0 (CMP0), Comparator 1 (CMP1) ICMP Capacitive Sensing (CAPSENSE0) ICS IDAC07, IDAC17 IIDAC IVC07 IIVC Voltage Supply Monitor (VMON0) IIN = 0 IVMON Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 3. Includes all peripherals that cannot have clocks gated in the Clock Control module. 4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz). 5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less. 6. RAM execution numbers use 0 wait states for all frequencies. 7. IDAC output current and IVC input current not included. 8. Bias current only. Does not include dynamic current from oscillator running at speed. Preliminary Rev. 0.8 13 SiM3U1xx Table 3.2. Power Consumption (Continued) Parameter Symbol Conditions Min Typ Max Units Flash Current on VDD Write Operation IFLASH-W — — 8 mA Erase Operation IFLASH-E — — 15 mA Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 3. Includes all peripherals that cannot have clocks gated in the Clock Control module. 4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz). 5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less. 6. RAM execution numbers use 0 wait states for all frequencies. 7. IDAC output current and IVC input current not included. 8. Bias current only. Does not include dynamic current from oscillator running at speed. Table 3.3. Power Mode Wake Up Times Parameter Min Typ Max Units tPM3FW — 425 — µs Power Mode 3 Wake Time tPM3 — 1.35 — ms Power Mode 9 Wake Time tPM9 — 12 — µs Power Mode 3 Fast Wake Time 14 Symbol Conditions Preliminary Rev. 0.8 SiM3U1xx Table 3.4. Reset and Supply Monitor Parameter Symbol Conditions Min Typ Max Units VDD High Supply Monitor Threshold (VDDHITHEN = 1) VVDDMH Early Warning 2.10 2.20 2.30 V Reset 1.95 2.05 2.1 V VDD Low Supply Monitor Threshold (VDDHITHEN = 0) VVDDML Early Warning 1.81 1.85 1.88 V Reset 1.70 1.74 1.77 V VREGIN Supply Monitor Threshold VVREGM Early Warning 4.2 4.4 4.6 V Power-On Reset (POR) Threshold VPOR Rising Voltage on VDD — 1.4 — V Falling Voltage on VDD 0.8 1 1.3 V VDD Ramp Time tRMP Time to VDD > 1.8 V 10 — 3000 µs Reset Delay from POR tPOR Relative to VDD > VPOR 3 — 100 ms Reset Delay from non-POR source tRST Time between release of reset source and code execution — 10 — µs RESET Low Time to Generate Reset tRSTL 50 — — ns Missing Clock Detector Response Time (final rising edge to reset) tMCD — 0.4 1 ms Missing Clock Detector Trigger Frequency FMCD — 7.5 13 kHz VDD Supply Monitor Turn-On Time tMON — 2 — µs FAHB > 1 MHz Preliminary Rev. 0.8 15 SiM3U1xx Table 3.5. On-Chip Regulators Parameter Symbol Conditions Min Typ Max Units 4 < VREGIN < 5.5 BGDIS = 0, SUSEN = 0 3.2 3.3 3.4 V 4 < VREGIN < 5.5 BGDIS = 0, SUSEN = 1 3.2 3.3 3.4 V 4 < VREGIN < 5.5 BGDIS = 1, SUSEN = X IDDOUT = 500 µA 2.3 2.8 3.6 V 4 < VREGIN < 5.5 BGDIS = 1, SUSEN = X IDDOUT = 5 mA 2.1 2.65 3.3 V 4 < VREGIN < 5.5 BGDIS = 0, SUSEN = X — — 150 mA 4 < VREGIN < 5.5 BGDIS = 1, SUSEN = X — — 5 mA BGDIS = 0 — 0.1 1 mV/mA 1 — 10 µF 3.3 V Regulator Characteristics (VREG0, Supplied from VREGIN Pin) Output Voltage (at VDD pin) Output Current (at VDD pin)* VDDOUT IDDOUT Output Load Regulation VDDLR Output Capacitance CVDD *Note: Total current VREG0 is capable of providing. Any current consumed by the SiM3U1xx reduces the current available to external devices powered from VDD. 16 Preliminary Rev. 0.8 SiM3U1xx Table 3.6. External Regulator Parameter Symbol Input Voltage Range (at VREGIN) VREGIN Conditions Min Typ Max Units 3.0 — 3.6 V Output Voltage (at EXREGOUT) VEXREGOUT Programmable in 100 mV steps 1.8 — 3.6 V NPN Current Drive INPN 400 mV Dropout 12 — — mA PNP Current Drive IPNP VEXREGBD > VREGIN1.5 V –6 — — mA VEXREGBD VREGIN >= 3.5 V VREGIN – 2.0 — — V VREGIN < 3.5 V 1.5 — — V 400mV Dropout — — 11.5 mA EXREGBD Voltage (PNP Mode) Standalone Mode Output Current IEXTREGBD External Capacitance with External BJT CBJT 4.7 — — µF Standalone Mode Load Regulation LRSTAND- — 1 — mV/mA Standalone Mode External Capacitance CSTAND- 47 — — nF 10 — 720 mA Current Limit Accuracy — — 10 % Foldback Limit Accuracy — — 20 % RSENSE — — 1 Internal Pull-Down RPD — 10 — k Internal Pull-Up RPU — 5 — k Current Limit Range Current Sense Resistor ALONE ALONE ILIMIT 1 Sense Resistor Current Sensor Sensing Pin Voltage VEXTREGSP VEXTREGSN Measured at EXTREGSP or EXTREGSN pin 2.2 — VREGIN V Differential Sensing Voltage VDIFF (VEXTREGSP VEXTREGSN) 10 — 1600 mV Current at EXTREGSN Pin IEXTREGSN — 8 — A Current at EXTREGSP Pin IEXTREGSP — VDIFF x 200 + 12 — A Preliminary Rev. 0.8 17 SiM3U1xx Table 3.7. Flash Memory Parameter Write Time 1 Erase Time1 Symbol Conditions Min Typ Max Units tWRITE One 16-bit Half Word 20 21 22 µs tERASE One Page 20 21 22 ms tERALL Full Device 20 21 22 ms VDD Voltage During Programming VPROG 1.8 — 3.6 V Endurance (Write/Erase Cycles) NWE 20k TBD — Cycles Retention2 tRET TBD TBD — Years TA = 85 °C, 1k Cycles Notes: 1. Does not include sequencing time before and after the write/erase operation, which may be multiple AHB clock cycles. 2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report. Table 3.8. Internal Oscillators Parameter Symbol Conditions Min Typ Max Units fUSB0OSC No Clock Recovery, Full Temperature and Supply Range 47.3 48 48.7 MHz No Clock Recovery, TA = 25 °C, VDD = 3.3 V 47.8 48 48.2 MHz USB Active with Clock Recovery, Full Temperature and Supply Range 47.88 48 48.12 MHz USB Oscillator (USB0OSC) Oscillator Frequency Power Supply Sensitivity PSSUSB0OSC TA = 25 °C — 175 — ppm/V Temperature Sensitivity TSUSB0OSC VDD = 3.3 V — 45 — ppm/°C fPLL0OSC Full Temperature and Supply Range 77 79 80 MHz Power Supply Sensitivity* PSSPLL0OSC TA = 25 °C, Fout = 79 MHz — 430 — ppm/V Temperature Sensitivity* TSPLL0OSC VDD = 3.3 V, Fout = 79 MHz — 95 — ppm/°C 23 — 80 MHz Phase-Locked Loop (PLL0OSC) Calibrated Output Frequency* Adjustable Output Frequency Range 18 fPLL0OSC Preliminary Rev. 0.8 SiM3U1xx Table 3.8. Internal Oscillators (Continued) Parameter Lock Time Symbol Conditions Min Typ Max Units tPLL0LOCK fREF = 48 MHz, fPLL0OSC = 80 MHz, M=59, N= 99, LOCKTH = 0 — 1.7 — µs fREF = 20 MHz, fPLL0OSC = 80 MHz, M=24, N=99, LOCKTH = 0 — 1.7 — µs fREF = 32 kHz, fPLL0OSC = 80 MHz, M=0, N=2440, LOCKTH = 0 — 91 — µs Preliminary Rev. 0.8 19 SiM3U1xx Table 3.8. Internal Oscillators (Continued) Parameter Symbol Conditions Min Typ Max Units fLPOSC Full Temperature and Supply Range 19 20 21 MHz TA = 25 °C, VDD = 3.3 V 19.6 20 20.4 MHz fLPOSCD Full Temperature and Supply Range 2.375 2.5 2.625 MHz Power Supply Sensitivity PSSLPOSC TA = 25 °C — 0.5 — %/V Temperature Sensitivity TSLPOSC VDD = 3.3 V — 55 — ppm/°C Full Temperature and Supply Range 13.4 16.4 19.7 kHz TA = 25 °C, VDD = 3.3 V 15.8 16.4 17.3 kHz Low Power Oscillator (LPOSC0) Oscillator Frequency Divided Oscillator Frequency Low Frequency Oscillator (LFOSC0) Oscillator Frequency fLFOSC Power Supply Sensitivity PSSLFOSC TA = 25 °C — 2.4 — %/V Temperature Sensitivity TSLFOSC VDD = 3.3 V — 0.2 — %/°C RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger Frequency fRTCMCD — 8 15 kHz RTC Robust Duty Cycle Range DCRTC 25 — 55 % Min Typ Max Units *Note: PLL0OSC in free-running oscillator mode Table 3.9. External Oscillator Parameter Symbol Conditions External Input CMOS Clock Frequency fCMOS 0 — 50 MHz External Input CMOS Clock High Time tCMOSH 9 — — ns External Input CMOS Clock Low Time tCMOSL 9 — — ns 20 Preliminary Rev. 0.8 SiM3U1xx Table 3.10. SAR ADC Parameter Resolution Supply Voltage Requirements (VDD) Symbol Conditions Nbits 12 Bit Mode 12 Bits 10 Bit Mode 10 Bits VADC Throughput Rate (High Speed Mode) fS Throughput Rate (Low Power Mode) fS Tracking Time SAR Clock Frequency tTRK fSAR Min Typ Max Units High Speed Mode 2.2 — 3.6 V Low Power Mode 1.8 — 3.6 V 12 Bit Mode — — 250 ksps 10 Bit Mode — — 1 Msps 12 Bit Mode — — 62.5 ksps 10 Bit Mode — — 250 ksps High Speed Mode 230 — — ns Low Power Mode 450 — — ns High Speed Mode — — 16.24 MHz Low Power Mode — — 4 MHz Conversion Time tCNV 10-Bit Conversion, SAR Clock = 16 MHz, APB Clock = 40 MHz. Sample/Hold Capacitor CSAR Gain = 1 — 5 — pF Gain = 0.5 — 2.5 — pF High Quality Inputs — 18 — pF Normal Inputs — 20 — pF High Quality Inputs — 300 — Normal Inputs — 550 — 1 — VDD V Gain = 1 0 — VREF V Gain = 0.5 0 — 2xVREF V — 70 — dB 12 Bit Mode — ±1 ±1.9 LSB 10 Bit Mode — ±0.2 ±0.5 LSB 12 Bit Mode –1 ±0.7 1.8 LSB 10 Bit Mode — ±0.2 ±0.5 LSB Input Pin Capacitance Input Mux Impedance Voltage Reference Range Input Voltage Range* Power Supply Rejection Ratio CIN RMUX VREF VIN PSRRADC 762.5 ns DC Performance Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) INL DNL *Note: Absolute input pin voltage is limited by the lower of the supply at VDD and VIO. Preliminary Rev. 0.8 21 SiM3U1xx Table 3.10. SAR ADC (Continued) Parameter Offset Error (using AGND) Offset Temperatue Coefficient Slope Error Symbol Conditions Min Typ Max Units EOFF 12 Bit Mode, VREF =2.4 V –2 0 2 LSB 10 Bit Mode, VREF =2.4 V –1 0 1 LSB — 0.004 — LSB/°C –0.07 –0.02 0.02 % TCOFF EM 12 Bit Mode Dynamic Performance with External Reference or Internal Reference in High Speed Mode, 10 kHz Sine Wave Input 1dB below full scale, Max throughput Signal-to-Noise Signal-to-Noise Plus Distortion SNR SNDR Total Harmonic Distortion (Up to 5th Harmonic) THD Spurious-Free Dynamic Range SFDR 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB 12 Bit Mode 62 66 — dB 10 Bit Mode 58 60 — dB 12 Bit Mode — 78 — dB 10 Bit Mode — 77 — dB 12 Bit Mode — –79 — dB 10 Bit Mode — –74 — dB Dynamic Performance with Internal Reference in Low Power Mode, 10 kHz Sine Wave Input 1dB below full scale, Max throughput Signal-to-Noise Signal-to-Noise Plus Distortion SNR SNDR Total Harmonic Distortion (Up to 5th Harmonic) THD Spurious-Free Dynamic Range SFDR 12 Bit Mode TBD 66 — dB 10 Bit Mode TBD 60 — dB 12 Bit Mode TBD 66 — dB 10 Bit Mode TBD 60 — dB 12 Bit Mode — 78 — dB 10 Bit Mode — 77 — dB 12 Bit Mode — –72 — dB 10 Bit Mode — –71 — dB *Note: Absolute input pin voltage is limited by the lower of the supply at VDD and VIO. 22 Preliminary Rev. 0.8 SiM3U1xx Table 3.11. IDAC Parameter Symbol Conditions Min Typ Max Units Static Performance Resolution Nbits 10 Integral Nonlinearity INL — ±0.5 ±2 LSB Differential Nonlinearity (Guaranteed Monotonic) DNL — ±0.5 ±1 LSB Output Compliance Range VOCR — — VDD – 1.0 V Full Scale Output Current IOUT 2 mA Range 2.0 2.046 2.10 mA 1 mA Range 1.00 1.023 1.05 mA 0.5 mA Range 495 511.5 525 µA — 250 — nA 2 mA Range — 100 — ppm/°C 2 mA Range — -220 — ppm/V — 1 — k — 1.2 — µs — 3 — µs Offset Error EOFF Full Scale Error Tempco TCFS VDD Power Supply Rejection Ratio Test Load Impedance (to VSS) RTEST Bits Dynamic Performance Output Settling Time to 1/2 LSB min output to max output Startup Time Preliminary Rev. 0.8 23 SiM3U1xx Table 3.12. Capacitive Sense Parameter Symbol Conditions Min Typ Max Units tsingle 12-bit Mode — 25 — µs 13-bit Mode — 27 — µs 14-bit Mode — 29 — µs 16-bit Mode — 33 — µs Highest Gain Setting (default) — 45 — pF Lowest Gain Setting — 500 — pF Highest Gain Setting (default) — 50 — k Min Typ Max Units VDDIVC 2.2 — 3.6 V Input Pin Voltage VIN 2.2 — VDD V Minimum Input Current (source) IIN 100 — — µA INLIVC –0.6 — 0.6 % VIVCOUT — 1.65 — V Input Range 1 mA (INxRANGE = 101) 1.62 1.66 1.73 V/mA Input Range 2 mA (INxRANGE = 100) 810 830 855 mV/mA Input Range 3 mA (INxRANGE = 011) 540 550 565 mV/mA Input Range 4 mA (INxRANGE = 010) 400 415 425 mV/mA Input Range 5 mA (INxRANGE = 001) 320 330 340 mV/mA Input Range 6 mA (INxRANGE = 000) 265 275 285 mV/mA — — 500 ns Single Conversion Time (Default Configuration) Maximum External Capacitive Load Maximum External Series Impedance CL CL Table 3.13. Current-to-Voltage Converter (IVC) Parameter Supply Voltage (VDD) Integral Nonlinearity Full Scale Output Slope Settling Time to 0.1% 24 Symbol MIVC Conditions VIVCOUT Preliminary Rev. 0.8 SiM3U1xx Table 3.14. Voltage Reference Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Symbol Conditions Min Typ Max Units VREFFS –40 to +85 °C, VDD = 1.8–3.6 V 1.62 1.65 1.68 V TCREFFS — 50 — ppm/°C tREFFS — — 1.5 µs PSRRREFFS — 400 — ppm/V VREF2X = 0 1.8 — 3.6 V VREF2X = 1 2.7 — 3.6 V 25 °C ambient, VREF2X = 0 1.195 1.2 1.205 V 25 °C ambient, VREF2X = 1 2.39 2.4 2.41 V ISC — — 10 mA Temperature Coefficient TCVREFP — 25 — ppm/°C Load Regulation LRVREFP Load = 0 to 200 µA to VREFGND — 4.5 — ppm/µA Load Capacitor CVREFP Load = 0 to 200 µA to VREFGND 0.1 — — µF tVREFPON 4.7 µF tantalum, 0.1 µF ceramic bypass — 3.8 — ms 0.1 µF ceramic bypass — 200 — µs VREF2X = 0 — 320 — ppm/V VREF2X = 1 — 560 — ppm/V Sample Rate = 250 ksps; VREF = 3.0 V — 5.25 — µA Internal Fast Settling Reference Output Voltage Temperature Coefficient Turn-on Time Power Supply Rejection On-Chip Precision Reference (VREF0) Valid Supply Range Output Voltage Short-Circuit Current Turn-on Time Power Supply Rejection VDD VREFP PSRRVREFP External Reference Input Current IEXTREF Preliminary Rev. 0.8 25 SiM3U1xx Table 3.15. Temperature Sensor Parameter Symbol Conditions Min Typ Max Units Offset VOFF TA = 0 °C — 760 — mV Offset Error* EOFF TA = 0 °C — ±14 — mV Slope M — 2.8 — mV/°C Slope Error* EM — TBD — µV/°C Linearity — 1 — °C Turn-on Time — 1.8 — µs *Note: Represents one standard deviation from the mean. 26 Preliminary Rev. 0.8 SiM3U1xx Table 3.16. Comparator Parameter Symbol Conditions Min Typ Max Units Response Time, CMPMD = 00 (Highest Speed) tRESP0 +100 mV Differential — 100 — ns –100 mV Differential — 150 — ns Response Time, CMPMD = 11 (Lowest Power) tRESP3 +100 mV Differential — 1.4 — µs –100 mV Differential — 3.5 — µs CMPHYP = 00 — 0.37 — mV CMPHYP = 01 — 7.9 — mV CMPHYP = 10 — 16.7 — mV CMPHYP = 11 — 32.8 — mV CMPHYN = 00 — 0.37 — mV CMPHYN = 01 — –7.9 — mV CMPHYN = 10 — –16.1 — mV CMPHYN = 11 — –32.7 — mV CMPHYP = 00 — 0.47 — mV CMPHYP = 01 — 5.85 — mV CMPHYP = 10 — 12 — mV CMPHYP = 11 — 24.4 — mV CMPHYN = 00 — 0.47 — mV CMPHYN = 01 — –6.0 — mV CMPHYN = 10 — –12.1 — mV CMPHYN = 11 — –24.6 — mV CMPHYP = 00 — 0.66 — mV CMPHYP = 01 — 4.55 — mV CMPHYP = 10 — 9.3 — mV CMPHYP = 11 — 19 — mV CMPHYN = 00 — 0.6 — mV CMPHYN = 01 — –4.5 — mV CMPHYN = 10 — –9.5 — mV CMPHYN = 11 — –19 — mV Positive Hysterisis Mode 0 (CPMD = 00) Negative Hysterisis Mode 0 (CPMD = 00) Positive Hysterisis Mode 1 (CPMD = 01) Negative Hysterisis Mode 1 (CPMD = 01) Positive Hysterisis Mode 2 (CPMD = 10) Negative Hysterisis Mode 2 (CPMD = 10) HYSCP+ HYSCP- HYSCP+ HYSCP- HYSCP+ HYSCP- Preliminary Rev. 0.8 27 SiM3U1xx Table 3.16. Comparator (Continued) Parameter Positive Hysterisis Mode 3 (CPMD = 11) Negative Hysterisis Mode 3 (CPMD = 11) Symbol Conditions Min Typ Max Units HYSCP+ CMPHYP = 00 — 1.37 — mV CMPHYP = 01 — 3.8 — mV CMPHYP = 10 — 7.8 — mV CMPHYP = 11 — 15.6 — mV CMPHYN = 00 — 1.37 — mV CMPHYN = 01 — –3.9 — mV CMPHYN = 10 — –7.9 — mV CMPHYN = 11 — –16 — mV -0.25 — VDD+0.2 5 V PB2 Pins — 7.5 — pF PB3 Pins — 10.5 — pF HYSCP- Input Range (CP+ or CP–) VIN Input Pin Capacitance CCP Common-Mode Rejection Ratio CMRRCP — 75 — dB Power Supply Rejection Ratio PSRRCP — 72 — dB -5 0 5 mV — 3.5 — µV/°C Input Offset Voltage VOFF Input Offset Tempco TCOFF Reference DAC Resolution 28 TA = 25 °C NBits 6 Preliminary Rev. 0.8 bits SiM3U1xx Table 3.17. USB Transciever Parameter Valid Supply Range (for USB Compliance) VBUS Pull-Down Leakage Current Symbol Conditions VDD IVBUSL VBUS = 5 V, VIO = 3.3 V Min Typ Max Units 3.0 — 3.6 V — 10 — µA Transmitter Output High Voltage VOH 2.8 — — V Output Low Voltage VOL — — 0.8 V Output Crossover Point VCRS 1.3 — 2.0 V Output Impedance ZDRV Driving High Driving Low — — 38 38 — — Pull-up Resistance RPU Full Speed (D+ Pull-up) Low Speed (D– Pull-up) 1.425 1.5 1.575 k Output Rise Time tR Low Speed Full Speed 75 4 — — 300 20 ns Output Fall Time tF Low Speed Full Speed 75 4 — — 300 20 ns Differential Input Sensitivity VDI | (D+) – (D–) | 0.2 — — V Differential Input Common Mode Range VCM 0.8 — 2.5 V — <1.0 — µA Receiver Input Leakage Current IL Pullups Disabled Note: Refer to the USB Specification for timing diagrams and symbol definitions Preliminary Rev. 0.8 29 SiM3U1xx Table 3.18. Port I/O Parameter Symbol Conditions Min Typ Max Units Low Drive, IOH = –2 mA VIO – 0.7 — — V High Drive, IOH = –5 mA VIO – 0.7 — — V Low Drive, IOL = 3 mA — — 0.6 V High Drive, IOL = 12.5 mA — — 0.6 V Standard I/O (PB0, PB1, and PB2) and 5 V Tolerant I/O (PB3) Output High Voltage Output Low Voltage VOH VOL Output Rise Time tR C = TBD TBD — TBD ns Output Fall Time tF C = TBD TBD — TBD ns VIH 1.8 <= VIO <= 2.0 0.7 x VIO — — V 2.0 <= VIO <= 3.6 VIO – 0.6 — — V — — 0.6 V PB0, PB1 and PB2 Pins — 4 — pF PB3 Pins — 7 — pF VIO = 1.8 –6 –3.5 –2 µA VIO = 3.6 –30 –20 –10 µA Input High Voltage Input Low Voltage VIL Pin Capacitance CIO Weak Pull-Up Current (VIN = 0 V) IPU Input Leakage (Pullups off or Analog) ILK 0 < VIN < VIO –1 — 1 µA Input Leakage Current of Port Bank 3 I/O, VIN above VIO IL VIO < VIN < VIO+2.0 V (pins without EXREG functions) 0 5 150 µA VIO < VIN < VREGIN (pins with EXREG functions) 0 5 150 µA Standard Mode, Low Drive, IOH = -3mA VIOHD – 0.7 — — V Standard Mode, High Drive, IOH = -10mA VIOHD – 0.7 — — V Standard Mode, Low Drive, IOH = 3mA — — 0.6 V Standard Mode, High Drive, IOH = 12.5mA — — 0.6 V Slew Rate Mode 0, VIOHD = 5V — 50 — ns Slew Rate Mode 1, VIOHD = 5V — 300 — ns Slew Rate Mode 2, VIOHD = 5V — 1 — µs Slew Rate Mode 3, VIOHD = 5V — 3 — µs High Drive I/O (PB4) Output High Voltage Output Low Voltage Output Rise Time 30 VOH VOL tR Preliminary Rev. 0.8 SiM3U1xx Table 3.18. Port I/O (Continued) Parameter Output Fall Time Input High Voltage Symbol Conditions Min Typ Max Units tF Slew Rate Mode 0, VIOHD = 5V — 50 — ns Slew Rate Mode 1, VIOHD = 5V — 300 — ns Slew Rate Mode 2, VIOHD = 5V — 1 — µs Slew Rate Mode 3, VIOHD = 5V — 3 — µs — — V VIOHD – 0.6 — — V — — 0.6 V Mode 0 — 1.76 — mA Mode 1 — 2.34 — Mode 2 — 3.52 — Mode 3 — 4.69 — Mode 4 — 7.03 — Mode 5 — 9.38 — Mode 6 — 14.06 — Mode 7 — 18.75 — Mode 8 — 28.13 — Mode 9 — 37.5 — Mode 10 — 56.25 — Mode 11 — 75 — Mode 12 — 112.5 — Mode 13 — 150 — Mode 14 — 225 — Mode 15 — 300 — — — 400 VIH 1.8 V<= VIOHD <= 2.0 V 0.7 x VIOHD 2.0 V<= VIOHD <= 6 V Input Low Voltage N-Channel Sink Current Limit (2.7 V <= VIOHD <= 6 V, VOL = 0.8V) Total N-Channel Sink Current on P4.0-P4.5 (DC) VIL ISINKL ISINKLT Preliminary Rev. 0.8 mA 31 SiM3U1xx Table 3.18. Port I/O (Continued) Parameter Symbol Conditions Min Typ Max Units ISRCL Mode 0 — 0.88 — mA Mode 1 — 1.17 — Mode 2 — 1.76 — Mode 3 — 2.34 — Mode 4 — 3.52 — Mode 5 — 4.69 — Mode 6 — 7.03 — Mode 7 — 9.38 — Mode 8 — 14.06 — Mode 9 — 18.75 — Mode 10 — 28.13 — Mode 11 — 37.5 — Mode 12 — 56.25 — Mode 13 — 75 — Mode 14 — 112.5 — Mode 15 — 150 — ISRCLT — — 400 mA Pin Capacitance CIO — 30 — pF Weak Pull-Up Current in Low Voltage Mode IPU VIOHD = 1.8 V –6 –3.5 –2 µA VIOHD = 3.6 V –30 –20 –10 µA VIOHD = 2.7 V –15 –10 –5 µA VIOHD = 6 V –30 –20 –10 µA –1 — 1 µA P-Channel Source Current Limit (2.7 V <= VIOHD <= 6 V, VOH = VIOHD - 0.8V) Total P-Channel Source Current on P4.0-P4.5 (DC) Weak Pull-Up Current in High Voltage Mode Input Leakage (Pullups off) 32 IPU ILK Preliminary Rev. 0.8 SiM3U1xx 3.2. Thermal Conditions Table 3.19. Thermal Conditions Parameter Thermal Resistance* Symbol Conditions Min Typ Max Units JA LGA-92 Packages — 35 — °C/W TQFP-80 Packages — 40 — °C/W QFN-64 Packages — 25 — °C/W TQFP-64 Packages — 30 — °C/W QFN-40 Packages — 30 — °C/W *Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad. 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.20 may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3.20. Absolute Maximum Ratings Parameter Symbol Conditions Min Max Units Ambient Temperature Under Bias TBIAS –55 125 °C Storage Temperature TSTG –65 150 °C Voltage on VDD VDD VSS–0.3 4.2 V EXTVREG0 Not Used VSS–0.3 6.0 V EXTVREG0 Used VSS–0.3 3.6 V VIO > 3.3 V VSS–0.3 5.8 V VIO < 3.3 V VSS–0.3 VIO+2.5 V VIO VSS–0.3 4.2 V VIOHD VSS–0.3 6.5 V RESET, VIO > 3.3 V VSS–0.3 5.8 V RESET, VIO < 3.3 V VSS–0.3 VIO+2.5 V Port Bank 0, 1, and 2 I/O VSS–0.3 VIO+0.3 V Port Bank 4 I/O VSSHD–0.3 VIOHD+0.3 V D+ and D–, VIO > 3.3 V VSS–0.3 5.8 V D+ and D–, VIO < 3.3 V VSS–0.3 VIO+2.5 V Voltage on VREGIN Voltage on VBUS Voltage on VIO Voltage on VIOHD Voltage on I/O pins, non Port Bank 3 I/O VREGIN VBUS VIN *Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be connected to the same potential on board. Preliminary Rev. 0.8 33 SiM3U1xx Table 3.20. Absolute Maximum Ratings (Continued) Parameter Voltage on I/O pins, Port Bank 3 I/O Symbol Conditions Min Max Units VIN SiM3U1x7, PB3.0– PB3.7, VIO > 3.3 V VSS–0.3 5.8 V SiM3U1x7, PB3.0– PB3.7, VIO < 3.3 V VSS–0.3 VIO+2.5 V SiM3U1x7, PB3.8 PB3.11 VSS–0.3 Lowest of VIO+2.5, VREGIN+0.3, or 5.8 V SiM3U1x6, PB3.0– PB3.5, VIO > 3.3 V VSS–0.3 5.8 V SiM3U1x6, PB3.0– PB3.5, VIO < 3.3 V VSS–0.3 VIO+2.5 V SiM3U1x6, PB3.6– PB3.9 VSS–0.3 Lowest of VIO+2.5, VREGIN+0.3, or 5.8 V SiM3U1x4, PB3.0– PB3.3 VSS–0.3 Lowest of VIO+2.5, VREGIN+0.3, or 5.8 V Total Current Sunk into Supply Pins ISUPP VDD, VREGIN, VIO, VIOHD — 400 mA Total Current Sourced out of Ground Pins IVSS VSS, VSSHD 400 — mA Current Sourced or Sunk by Any I/O Pin IPIO PB0, PB1, PB2, PB3, and RESET –100 100 mA PB4 –300 300 mA PB0, PB1, PB2, PB3, and RESET –100 100 mA PB4 –300 300 mA IINJ Sum of all I/O and RESET –400 400 mA PD LGA-92 Package — 570 mW TQFP-80 Package — 500 mW QFN-64 Package — 800 mW TQFP-64 Package — 650 mW QFN-40 Package — 650 mW Current Injected on Any I/O Pin Total Injected Current on I/O Pins Power Dissipation at TA = 85 °C IINJ *Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be connected to the same potential on board. 34 Preliminary Rev. 0.8 SiM3U1xx 4. Precision32™ SiM3U1xx System Overview The SiM3U1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 6.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. MHz maximum operating frequency. Branch target cache and prefetch buffers to minimize wait states. 80 Memory: 32–256 kB Flash; in-system programmable, 8–32 kB SRAM (including 4 kB retention SRAM, which preserves state in PM9 mode). Power: Low drop-out (LDO) regulator for CPU core voltage. reset circuit and brownout detectors. 3.3 V output LDO for direct power from 5 V supplies. External transistor regulator. Power Management Unit (PMU). Power-on I/O: Up to 65 total multifunction I/O pins: Up to six programmable high-power capable (5–300 mA, 1.8–5 V). to twelve 5 V tolerant general purpose pins. Two flexible peripheral crossbars for peripheral routing. Up Clock Sources: oscillator with PLL: 23–80 MHz with ± 1.5% accuracy in free-running mode. Internal 48 MHz oscillator with clock recovery supports crystal-less full speed USB operation with ± 0.25% accuracy. Low-power internal oscillator: 20 MHz and 2.5 MHz modes. Low-frequency internal oscillator: 16.4 kHz. External RTC crystal oscillator: 32.768 kHz. External oscillator: Crystal, RC, C, CMOS clock modes. Programmable clock divider allows any oscillator source to be divided by binary factor from 1-128. Internal Data Peripherals: 16-Channel DMA Controller. Hardware AES Encryption. 16/32-bit CRC. 128/192/256-bit Timers/Counters and PWM: 6-channel Enhanced Programmable Counter Array (EPCAn) supporting advanced PWM and capture/compare. 2 x 2-channel Standard Programmable Counter Array (PCAn) supporting PWM and capture/compare. 2 x 32-bit Timers - can be split into 4 x 16-bit Timers, support PWM and capture/compare. Real Time Clock (RTCn). Low Power Timer. Watchdog Timer. Communications Peripherals: External Memory Interface. 2.0-compliant full speed with integrated transceiver, 5 bidirectional endpoints and dedicated 2 kB buffer. 2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard support. 3 x SPIs. 2 x I2C. USB I 2 S (receive and transmit). Analog: 2 x 12-Bit Analog-to-Digital Converters (SARADC). x 10-Bit Digital-to-Analog Converter (IDAC). 16-Channel Capacitance-to-Digital Converter (CAPSENSE). 2 x Low-Current Comparators (CMP). 1 x Current-to-Voltage Converter (IVC) module with two channels. 2 On-Chip Debugging Preliminary Rev. 0.8 35 SiM3U1xx With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the SiM3U1xx devices are truly standalone system-on-a-chip solutions. The Flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings. The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging. Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RESET pins are powered from the IO supply voltage. The SiM3U1xx devices are available in 40-pin or 64pin QFN, 64-pin or 80-pin TQFP, or 92-pin LGA packages. All package options are lead-free and RoHS compliant. See Table 6.1 for ordering information. A block diagram is included in Figure 4.1. Debug / Programming Hardware Analog Core ARM Cortex M3 AHB APB Watchdog Timer (WDTIMER0) Power On Reset / PMU SARADC0 SARADC1 IDAC0 IDAC1 Comparator 0 Comparator 1 Memory Voltage Supply Monitor (VMON0) 32/64/128/256 kB Flash IVC0 Capacitive Sensing 0 4/12/28 kB RAM Power I/O 4 kB retention RAM Low Dropout Regulator (LDO0) USB0 EMIF Voltage Regulator (VREG0) DMA 2 kB Buffer Crossbars External Regulator (EXTVREG0) 16-Channel Controller 5 Bidirectional Endpoints Standard I/O pins Power Management Unit (PMU) Peripheral Crossbar Internal Oscillator 5 V tolerant pins High Drive pins Clocking Digital Real-Time Clock (RTC0OSC) USART0 USART1 UART0 UART1 Low Frequency Oscillator (LFOSC0) SPI0 SPI1 SPI2 Low Power Oscillator (LPOSC0) USB Oscillator (USB0OSC) Clock Control I2C0 I2C1 I2S0 External Oscillator Control (EXTOSC0) EPCA0 PCA0 PCA1 Phase-Locked Loop (PLL0OSC) AES0 Peripheral Clock Control (CLKCTRL) CRC0 Timer 0 Timer 1 Low Power Timer (LPTIMER0) DMA access available for these peripherals Figure 4.1. Precision32™ SiM3U1xx Family Block Diagram 36 Preliminary Rev. 0.8 SiM3U1xx 4.1. Power 4.1.1. LDO and Voltage Regulator (VREG0) The SiM3U1xx devices include two internal regulators: the core LDO Regulator and the Voltage Regulator (VREG0). The LDO Regulator converts a 1.8–3.6 V supply to the core operating voltage of 1.8 V. This LDO consumes little power and provides flexibility in choosing a power supply for the system. The Voltage Regulator regulates from 5.5 to 2.7 V and can serve as an input to the LDO. This allows the device to be powered from USB without any external components other than bypass capacitors. 4.1.2. Voltage Supply Monitor (VMON0) The SiM3U1xx devices include a voltage supply monitor which allows devices to function in known, safe operating condition without the need for external hardware. The supply monitor includes additional circuitry that can monitor the main supply voltage and the VREGIN input voltage divided by 4 (VREGIN / 4). The supply monitor module includes the following features: Main supply “VDD Low” (VDD below the early warning threshold) notification. the device in reset if the main VDD supply drops below the VDD Reset threshold. VREGIN divided by 4 (VREGIN / 4) supply “VREGIN Low” notification. Holds 4.1.3. External Regulator (EXTVREG0) The External Regulator provides all the circuitry needed for a high-power regulator except the power transistor (NPN or PNP) and current sensing resistor (if current limiting is enabled). The External Regulator module has the following features: Interfaces with either an NPN or PNP external transistor that serves as the pass device for the high current regulator. Automatic current limiting. Automatic foldback limiting. Sources up to 1 A for use by external circuitry. Variable output voltage from 1.8–3.6 V in 100 mV steps. 4.1.4. Power Management Unit (PMU) The Power Management Unit on the SiM3U1xx manages the power systems of the device. On power-up, the PMU ensures the core voltages are a proper value before core instruction execution begins. It also recognizes and manages the various wake sources for low-power modes of the device. The PMU module includes the following features: Up to 16 pin wake inputs can wake the device from Power Mode 9. Low Power Timer, RTC0 (alarms and oscillator fail), Comparator 0, and the RESET pin can also serve as wake sources for Power Mode 9. All PM9 wake sources (except for the RESET pin) can also reset the Low Power Timer or RTC0 modules. Disables the level shifters to pins and peripherals to further reduce power usage in PM9. These level shifters must be re-enabed by firmware after exiting PM9. Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM9. The Preliminary Rev. 0.8 37 SiM3U1xx 4.1.5. Device Power Modes The SiM3U1xx devices feature four low power modes in addition to normal operating mode. Several peripherals provide wake up sources for these low power modes, including the Low-Power Timer (LPT0), RTC0 (alarms and oscillator failure notification), Comparator 0, and PMU Pin Wake. All power modes are detailed in Table 4.1. Table 4.1. SiM3U1xx Power Modes Mode Description Mode Entrance Mode Exit Execute code from RAM Jump to code in Flash WFI or WFE instruction NVIC or WIC wakeup Core Normal operating at full speed Code executing from Flash Core Power Mode 1 (PM1) operating at full speed Code executing from RAM Core Power Mode 2 (PM2) halted AHB and APB operate at full speed for peripherals All Power Mode 3 Fast Wake (PM3FW) clocks stopped except LFOSC0 or RTC0OSC AHB and APB set to Low Power Oscillator Core clock set to LFOSC0 or RTC0OSC DMACTRL0 disabled wake mode enabled in PM3CN AHB switched to Low Power Oscillator WFI or WFE instruction Fast NVIC or WIC wakeup DMACTRL0 Power Mode 3 (PM3) All clocks stopped disabled Clocks disabled in PM3CN WFI or WFE instruction NVIC or WIC wakeup SLEEPDEEP Power Mode 9 (PM9) Low power shutdown set in the ARM System Requires a reset defined by Control Register the PMU as a wake up source WFI or WFE instruction In addition, all peripherals can have their clocks disconnected to reduce power consumption whenever a peripheral is not being used using the clock control (CLKCTRL) registers. 38 Preliminary Rev. 0.8 SiM3U1xx 4.1.5.1. Normal Mode Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will vary depending on AHB/APB clock speeds and the settings of CLKCTRL and the peripherals. 4.1.5.2. Power Mode 1 Power Mode 1 occurs when the core executes code from RAM instead of Flash. The power consumption of the device is slightly less than normal mode when in PM1. 4.1.5.3. Power Mode 2 In Power Mode 2, the core halts and the peripherals run at full speed. To place the device in this mode, the clock settings in CLKCTRL should remain the same as Normal or Power Mode 1 and the core should execute a wait-forinterrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM2 must be of a sufficient priority to be recognized by the core. 4.1.5.4. Power Mode 3 Fast Wake Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0OSC. The core and the peripherals are halted in this mode. The following sequence places the device in Power Mode 3 Fast Wake: 1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller (DMACTRL0). 2. Firmware should enable PM3 Fast Wake in the PM3CN register and set the core clock to run off of the LFOSC0 or RTC0OSC to achieve the lowest power. 3. CLKCTRL CONTROL register settings must be modified to set the AHB and APB clocks to the Low Power Oscillator. 4. Firmware should then execute a WFI or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3FW must be of a sufficient priority to be recognized by the core. By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low Power Oscillator, the device can wake up faster than in standard Power Mode 3 at the expense of higher power consumption. 4.1.5.5. Power Mode 3 Power Mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted. The following sequence places the device in Power Mode 3: 1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller (DMACTRL0). 2. Firmware should disable PM3 Fast Wake in the PM3CN register. 3. Firmware should then execute a WFI or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the core. 4.1.5.6. Power Mode 9 In Power Mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are set to a lower power mode. In addition, standard RAM contents are not preserved, though retention RAM contents are still available after exiting the power mode. This mode provides the lowest power consumption for the device, but requires an appropriate reset to exit. The available reset sources to wake from PM9 are controlled by the Power Management Unit (PMU). To enter this mode, firmware must write the SLEEPDEEP bit in the ARM System Control Register. Firmware must then execute a WFI or WFE instruction. The core will remain in PM9 until an enabled reset source occurs. Preliminary Rev. 0.8 39 SiM3U1xx 4.2. I/O 4.2.1. General Features The SiM3U1xx ports have the following features: Push-pull or open-drain output modes and analog or digital modes. Option for high or low output drive strength. Port Match allows the device to recognize a change on a port pin value. Internal pull-up resistors are enabled or disabled on a port-by-port basis. Two external interrupts with up to 16 inputs provide monitoring capability for external signals. Internal Pulse Generator Timer (PB2 only) to generate simple square waves. A subset of pins can also serve as inputs to the Port Mapped Level Shifters available on the High Drive Pins. 4.2.2. High Drive Pins (PB4) The High Drive pins have the following additional features: Programmable safe state: high, low, or high impedance. Programmable drive strength and slew rates. Programmable current limiting. Powered from a separate source (VIOHD, which can be up to 6 V) from the rest of the device. Supports various functions, including GPIO, UART1 pins, EPCA0 pins, or Port Mapped Level Shifting. 4.2.3. 5 V Tolerant Pins (PB3) The 5 V tolerant pins can be connected to external circuitry operating at voltages above the device supply without needing extra components to shift the voltage level. 4.2.4. Crossbars The SiM3U1xx devices have two Crossbars with the following features: Flexible peripheral assignment to port pins. Pins can be individually skipped to move peripherals as needed for design or layout considerations. The Crossbars have a fixed priority for each I/O function and assign these functions to the port pins. When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned, the Crossbars skip that pin when assigning the next selected resource. Additionally, the Crossbars will skip port pins whose associated bits in the PBSKIPEN registers are set. This provides some flexibility when designing a system: pins involved with sensitive analog measurements can be moved away from digital I/O and peripherals can be moved around the chip as needed to ease layout constraints. 40 Preliminary Rev. 0.8 SiM3U1xx 4.3. Clocking The SiM3U1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC0 Oscillator, the Low Frequency Oscillator, the Low Power Oscillator, the divided Low Power Oscillator, the External Oscillator, the PLL0 Oscillator, and the USB0 Oscillator. In addition, a divider for the AHB clock provides flexible clock options for the device. The APB clock services data peripherals and is synchronized with the AHB clock. The APB clock can be equal to the AHB clock (if AHB is less than or equal to 50 MHz) or set to the AHB clock divided by two. Clock Control allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. Most peripherals have clocks off by default after a power-on reset. Clock Control RAM RTC0 Oscillator DMA LFOSC0 AHB clock LPOSC0 Flash EMIF AHB Clock Divider USB Buffer PLL0 Registers External Oscillator PLL0 Oscillator PBCFG and PB0/1/2/3/4 APB Clock Divider APB clock USART0 USART1 USB0 Oscillator UART0 Preliminary Rev. 0.8 41 SiM3U1xx 4.3.1. PLL (PLL0) The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference frequency. The reference frequency for Frequency-Lock and Phase-Lock modes can use one of multiple sources (including the USB0 oscillator or external oscillator) to provide maximum flexibility for different application needs. Because the PLL module generates its own clock, the DCO can be locked to a particular reference frequency and then moved to Free-Running mode to reduce system power and noise. The PLL module includes the following features: Five output ranges with output frequencies ranging from 23 to 80 MHz. Multiple reference frequency inputs. Three output modes: free-running DCO, frequency-locked, and phase-locked. Ability to sense the rising edge or falling edge of the reference source. DCO frequency LSB dithering to provide finer average output frequencies. Spectrum spreading to reduce generated system noise. Low jitter and fast lock times. Ability to suspend all output frequency updates (including dithering and spectrum spreading) using the STALL bit during jitter-sensitive operations. 4.3.2. Low Power Oscillator (LPOSC0) The Low Power Oscillator is the default AHB oscillator on SiM3U1xx devices and enables or disables automatically, as needed. The Low Power Oscillator has the following features: 20 MHz and divided 2.5 MHz frequencies available for the AHB clock. starts and stops as needed. Automatically 4.3.3. Low Frequency Oscillator (LFOSC0) The low frequency oscillator (LFOSC0) provides a low power internal clock source running at approximately 16.4 kHz for the RTC0 timer and other peripherals on the device. No external components are required to use the low frequency oscillator 4.3.4. External Oscillators (EXTOSC0) The EXTOSC0 external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. The external oscillator output may be selected as the AHB clock or used to clock other modules independent of the AHB clock selection. The External Oscillator control has the following features: Support for external crystal, RC, C, or CMOS oscillators. external CMOS frequencies from 10 kHz to 50 MHz and external crystal frequencies from 10 kHz to 30 MHz. Various drive strengths for flexible crystal oscillator support. Internal frequency divide-by-two option available. Support 42 Preliminary Rev. 0.8 SiM3U1xx 4.4. Data Peripherals 4.4.1. 16-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the system, as the device can spend more time in low-power modes. The DMA controller has the following features: Utilizes ARM PrimeCell uDMA architecture. 16 channels. DMA crossbar supports SARADC0, SARADC1, IDAC0, IDAC1, four bidirectional USB0 Endpoints (EP1-4 IN/OUT), I2C0, I2S0, SPI0, SPI1, USART0, USART1, AES0, EPCA0, external pin triggers, and timers. Supports primary, alternate, and scatter-gather data structures to implement various types of transfers. Access allowed to all AHB and APB memory space. Implements 4.4.2. 128/192/256-bit Hardware AES Encryption (AES0) The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This hardware accelerator translates to more core bandwidth available for other functions or a power savings for lowpower applications. The AES module includes the following features: Operates on 4-word (16-byte) blocks. key sizes of 128, 192, and 256 bits for both encryption and decryption. Generates the round key for decryption operations. All cipher operations can be performed without any firmware intervention for a set of 4-word blocks (up to 32 kB). Support for various chained and stream-ciphering configurations with XOR paths on both the input and output. Internal 4-word FIFOs to facilitate DMA operations. Integrated key storage. Hardware acceleration for Cipher-Block Chaining (CBC) and Counter (CTR) algorithms utilizing integrated counterblock generation and previous-block caching. Supports 4.4.3. 16/32-bit CRC (CRC0) The CRC module is designed to provide hardware calculations for Flash memory verification and communications protocols. The CRC module supports four common polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3). The three supported 16-bit polynomials are 0x1021 (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). The CRC module includes the following features: Support for four common polynomials (one 32-bit and three 16-bit options). Byte-level bit reversal for the CRC input. Byte-order reorientation of words for the CRC input. Word or half-word bit reversal of the CRC result. Ability to configure and seed an operation in a single register write. Support for single-cycle parallel (unrolled) CRC computation for 32- or 8-bit blocks. Capability to CRC 32 bits of data per peripheral bus (APB) clock. Support for DMA writes using firmware request mode. Preliminary Rev. 0.8 43 SiM3U1xx 4.5. Counters/Timers and PWM 4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1) The SiM3U1xx devices include two types of PCA module: Enhanced and Standard. The Enhanced Programmable Counter Array (EPCA0) and Standard Programmable Counter Array (PCA0, PCA1) modules are timer/counter systems allowing for complex timing or waveform generation. Multiple modules run from the same main counter, allowing for synchronous output waveforms. The Enhanced PCA module is multi-purpose, but is optimized for motor control applications. The EPCA module includes the following features: Three sets of channel pairs (six channels total) capable of generating complementary waveforms. and edge-aligned waveform generation. Programmable dead times that ensure channel pairs are never both active at the same time. Programmable clock divisor and multiple options for clock source selection. Waveform update scheduling. Option to function while the core is inactive. Multiple synchronization triggers and outputs. Pulse-Width Modulation (PWM) waveform generation. High-speed square wave generation. Input capture mode. DMA capability for both input capture and waveform generation. PWM generation halt input. The Standard PCA module (PCA) includes the following features: Center- Two independent channels. Center- and edge-aligned waveform generation. Programmable clock divisor and multiple options for clock source selection. Pulse-Width Modulation waveform generation. 4.5.2. 32-bit Timer (TIMER0, TIMER1) Each timer module is independent, and includes the following features: Operation as a single 32-bit or two independent 16-bit timers. Clocking options include the APB clock, the APB clock scaled using an 8-bit prescaler, the external oscillator, or falling edges on an external input pin (synchronized to the APB clock). Auto-reload functionality in both 32-bit and 16-bit modes. Up/Down count capability, controlled by an external input pin. Rising and falling edge capture modes. Low or high pulse capture modes. Duty cycle capture mode. Square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle. 32- or 16-bit pulse-width modulation mode. 44 Preliminary Rev. 0.8 SiM3U1xx 4.5.3. Real-Time Clock (RTC0) The RTC0 module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a 32.768 kHz watch crystal. The RTC0 provides three alarm events in addition to a missing clock event, which can also function as interrupt, reset, or wakeup sources on SiM3U1xx devices. The RTC0 module includes internal loading capacitors that are programmable to 16 discrete levels, allowing compatibility with a wide range of crystals. The RTC0 output can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. The module also includes a low power internal low frequency oscillator that reduces low power mode current and is available for other modules to use as a clock source. The RTC module includes the following features: 32-bit timer (supports up to 36 hours) with three separate alarms. for one alarm to automatically reset the RTC timer. Missing clock detector. Can be used with the internal low frequency oscillator (LFOSC0), an external 32.768 kHz crystal (no additional resistors or capacitors necessary), or with an external CMOS clock. Programmable internal loading capacitors support a wide range of external 32.768 kHz crystals. Operates directly from VDD and remains operational even when the device goes into its lowest power down mode. The output can be buffered and routed to an I/O pin to provide an accurate, low frequency clock to other devices while the core is in its lowest power down mode. Option 4.5.4. Low Power Timer (LPTIMER0) The Low Power Timer (LPTIMER0) module runs from the clock selected by the RTC0 module, allowing the LPTIMER0 to operate even if the AHB and APB clocks are disabled. The LPTIMER0 counter can increment using one of two clock sources: the clock selected by the RTC0 module, or rising or falling edges of an external signal. The Low Power Timer includes the following features: Runs on a low-frequency clock (RTC0OSC or LFOSC0 selected in RTC0) or an external source (rising or falling edge). Overflow and threshold-match detection, which can generate an interrupt, reset the timer, or wake some devices from low power modes. Timer reset on threshold-match allows square-wave generation at a variable output frequency. 4.5.5. Watchdog Timer (WDTIMER0) The WDTIMER0 module includes a 16-bit timer, a programmable early warning interrupt, and a programmable reset period. The timer registers are protected from inadvertent access by an independent lock and key interface. The watchdog timer runs from the low frequency oscillator (LFOSC0). The Watchdog Timer has the following features: Programmable timeout interval. Optional interrupt to warn when the Watchdog Timer is nearing the reset trip value. Lock-out feature to prevent any modification until a system reset. Preliminary Rev. 0.8 45 SiM3U1xx 4.6. Communications Peripherals 4.6.1. External Memory Interface (EMIF0) The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD controllers, to appear as part of the system memory map. The EMIF0 module includes the following features: Provides a memory mapped view of multiple external devices. Support for byte, half-word and word accesses regardless of external device data-width. Error indicator for certain invalid transfers. Minimum external timing allows for 3 clocks per write or 4 clocks per read. Output bus can be shared between non-muxed and muxed devices. Available extended address output allows for up to 24-bit address with 8-bit parallel devices. Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals. Support for internally muxed devices with dynamic address shifting. Fully programmable control signal waveforms. 4.6.2. USB0 The USB0 module has complete Full/Low Speed USB function for USB peripheral implementations. The USB Function Controller (USBn) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 2k FIFO block, and dedicated USBn oscillator with clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant. The USB0 module includes the following features: Full and Low Speed functionality. Implements 5 bidirectional endpoints, with 4 of these capable of initiating autonomous DMA transfers. USB 2.0 compliant USB peripheral support (no host capability). Direct module access to 2k bytes of RAM for dedicated FIFO memory. Dedicated USB0 oscillator with clock recovery to meet USB clocking requirements with no external components. Additional clocking options include PLL or external oscillator outputs. 4.6.3. USART (USART0, USART1) The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single device. In addition to these signals, the USART0 module can optionally use a clock (UCLK) or hardware handshaking (RTS and CTS). The USART module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud rate generators. or asynchronous transmissions and receptions. Clock master or slave operation with programmable polarity and edge controls. Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX or RX). Individual enables for generated clocks during start, stop, and idle states. Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation (with separate enables). Transmit and receive hardware flow-control. Independent inversion correction for TX, RX, RTS, and CTS signals. Synchronous 46 Preliminary Rev. 0.8 SiM3U1xx IrDA modulation and demodulation with programmable pulse widths. Smartcard ACK/NACK support. Parity error, frame error, overrun, and underrun detection. Multi-master and half-duplex support. Multiple loop-back modes supported. Multi-processor communications support. 4.6.4. UART (UART0, UART1) The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single device. The UART module provides the following features: Independent transmitter and receiver configurations with separate 16-bit baud-rate generators. transmissions and receptions. Up to 5 Mbaud (TX or RX) or 1 Mbaud Smartcard (TX or RX). Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from 5 to 9 bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the LIN SYNC byte. Automatic parity generation (with enable). Automatic start and stop generation. Transmit and receive hardware flow-control. Independent inversion correction for TX, RX, RTS, and CTS signals. IrDA modulation and demodulation with programmable pulse widths. Smartcard ACK/NACK support. Parity error, frame error, overrun, and underrun detection. Multi-master and half-duplex support. Multiple loop-back modes supported. Asynchronous 4.6.5. SPI (SPI0, SPI1) SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select signal. The SPI module includes the following features: Supports 3- or 4-wire master or slave modes. Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode. Support for all clock phase and slave select (NSS) polarity modes. 16-bit programmable clock rate. Programmable MSB-first or LSB-first shifting. 8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers. Programmable FIFO threshold level to request data service for DMA transfers. Support for multiple masters on the same data lines. 4.6.6. I2C (I2C0, I2C1) The I2C interface is a two-wire, bi-directional serial bus. The two clock and data signals operate in open-drain mode with external pull-ups to support automatic bus arbitration. Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clocklow duration is available to accommodate devices with different speed capabilities on the same bus. Preliminary Rev. 0.8 47 SiM3U1xx The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/ stop control and generation. The I2C module includes the following features: Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. operate down to APB clock divided by 32768 or up to APB clock divided by 8. Support for master, slave, and multi-master modes. Hardware synchronization and arbitration for multi-master mode. Clock low extending (clock stretching) to interface with faster masters. Hardware support for 7-bit slave and general call address recognition. Firmware support for 10-bit slave address decoding. Ability to disable all slave states. Programmable clock high and low period. Programmable data setup/hold times. Spike suppression up to 2 times the APB period. Can 4.6.7. I2S (I2S0) The I2S module receives digital data from an external source over a data line in the standard I2S, left-justified, rightjustified, or time domain multiplexing format, de-serializes the data, and generates requests to transfer the data using the DMA. The module also reads stereo audio samples from the DMA, serializes the data, and sends it out of the chip on a data line in the same standard serial format for digital audio. The I2S receive interface consists of 3 signals: SCK (bit clock), WS (word select or frame sync), and SD (data input). The block’s transmit interface consists of 3 signals: SCK (bit clock), WS (word select or frame sync) and SD (data output). The I2S module includes the following features: Master or slave capability. Flexible 10-bit clock divider with 8-bit fractional clock divider provides support for various common sampling frequencies (16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz) for up to two 32-bit channels. Support for DMA data transfers. Support for various data formats. 48 Preliminary Rev. 0.8 SiM3U1xx 4.7. Analog 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1) The SARADC0 and SARADC1 modules on SiM3U1xx devices are Successive Approximation Register (SAR) Analog to Digital Converters (ADCs). The key features of the SARADC module are: Single-ended 12-bit and 10-bit modes. Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in 10-bit mode. Operation in low power modes at lower conversion speeds. Selectable asynchronous hardware conversion trigger with hardware channel select. Output data window comparator allows automatic range checking. Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts supported. Flexible output data formatting. Sequencer allows up to 8 sources to be automatically scanned using one of four channel characteristic profiles without software intervention. Eight-word conversion data FIFO for DMA operations. Multiple SARADC modules can work together synchronously or by interleaving samples. Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external reference, and support for an external signal ground. 4.7.2. Sample Sync Generator (SSG0) The SSG module includes a phase counter and a pulse generator. The phase counter is a 4-bit free-running counter clocked from the SARADC module clock. Counting-up from zero, the phase counter marks sixteen equallyspaced events for any number of SARADC modules. The ADCs can use this phase counter to start a conversion. The programmable pulse generator creates a 50% duty cycle pulse with a period of 16 phase counter ticks. Up to four programmable outputs available to external devices can be driven by the pulse generator with programmable polarity and a defined output setting when the pulse generator is stopped. The Sample Sync Generator module has the following features: Connects multiple modules together to perform synchronized actions. a clock synchronized to the internal sampling clock used by any number of SARADC modules to pins for use by external devices. Includes a phase counter, pulse generator, and up to four programmable outputs. Outputs 4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) The IDAC takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module includes the following features: 10-bit current DAC with support for four timer, up to seven external I/O, on demand, and SSG0 output update triggers. Ability to update on rising, falling, or both edges for any of the external I/O trigger sources (DACnTx). Supports an output update rate greater than 600 k samples per second. Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA. Four-word FIFO to aid with high-speed waveform generation or DMA interactions. Individual FIFO overrun, underrun, and went-empty interrupt status sources. Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per word, or four 8-bit samples per word. Support for left- and right-justified data. Preliminary Rev. 0.8 49 SiM3U1xx 4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) The Capacitance Sensing module measures capacitance on external pins and converts it to a digital value. The CAPSENSE module has the following features: Multiple start-of-conversion sources (CSnTx). to convert to 12, 13, 14, or 16 bits. Automatic threshold comparison with programmable polarity (“less than or equal” or “greater than”). Four operation modes: single conversion, single scan, continuous single conversion, and continuous scan. Auto-accumulate mode that will take and average multiple samples together from a single start of conversion signal. Single bit retry options available to reduce the effect of noise during a conversion. Supports channel bonding to monitor multiple channels connected together with a single conversion. Scanning option allows the module to convert a single or series of channels and compare against the threshold while the AHB clock is stopped and the core is in a low power mode. Option 4.7.5. Low Current Comparators (CMP0, CMP1) The Comparators take two analog input voltages and output the relationship between these voltages (less than or greater than) as a digital signal. The Low Power Comparator module includes the following features: Multiple sources for the positive and negative poles, including VDD, VREF, and 8 I/O pins. Two outputs are available: a digital synchronous latched output and a digital asynchronous raw output. Programmable hysteresis and response time. Falling or rising edge interrupt options on the comparator output. 4.7.6. Current-to-Voltage Converter (IVC0) The IVC module provides inputs to the SARADCn modules so the input current can be measured. The IVC module has the following features: Two independent channels. Programmable input ranges (1–6 mA full-scale). 50 Preliminary Rev. 0.8 SiM3U1xx 4.8. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. External port pins are forced to a known state. Interrupts and timers are disabled. Clocks to all AHB peripherals other than the USB0 buffers are enabled. Clocks to all APB peripherals other than Watchdog Timer, EMIF0, and DMAXBAR are disabled. All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal oscillator. The Watchdog Timer is enabled with the Low Frequency Oscillator (LFO0) as its clock source. Program execution begins at location 0x00000000. Reset Sources RESET VDD Supply Monitor Missing Clock Detector Watchdog Timer Software Reset system reset Comparator 0 Comparator 1 USB0 RTC0 Alarm PMU / Wakeup Core Reset Preliminary Rev. 0.8 51 SiM3U1xx 4.9. Security The peripherals on the SiM3U1xx devices have a register lock and key mechanism that prevents any undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence must be written in order to the KEY register to modify any of the bits in PERIPHLOCKx. Any subsequent write to KEY will then inhibit any accesses of PERIPHLOCKx until it is unlocked again through KEY. Reading the KEY register indicates the current status of the PERIPHLOCKx lock state. If a peripheral’s registers are locked, all writes will be ignored. The registers can always be read, regardless of the peripheral’s lock state. Peripheral Lock and Key USART0/1, UART0/1 SPI0/1/2 I2C0/1 PERIPHLOCK0 EPCA0, PCA0/1 KEY PERIPHLOCK1 TIMER0/1 USB0 SARADC0/1 4.10. On-Chip Debugging The SiM3U1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for instruction trace. The JTAG interface is supported on SiM3U1x7 and SiM3U1x6 devices, and the ETM interface is supported on SiM3U1x7 devices. The JTAG and ETM interfaces can be optionally enabled to provide more visibility while debugging at the cost of using several Port I/O pins. Additionally, if the core is configured for Serial Wire (SW) mode and not JTAG, then the Serial Wire Viewer (SWV) is available to provide a single pin to send out TPIU messages on SiM3U1x7 and SiM3U1x6 devices. Most peripherals have the option to halt or continue functioning when the core halts in debug mode. 52 Preliminary Rev. 0.8 SiM3U1xx 5. Pin Definitions and Packaging Information 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RESET DD+ VBUS VREGIN VSS VDD VIO PB0.0 PB0.1 PB0.2 PB0.3 PB0.4 PB0.5 PB0.6 PB0.7 PB0.8 PB0.9 PB0.10 PB0.11 5.1. SiM3U1x7 Pin Definitions PB4.5 PB4.4 PB4.3 1 60 PB0.12 2 59 3 58 PB0.13 PB0.14 VSSHD VIOHD PB4.2 PB4.1 4 57 5 56 6 55 7 54 PB4.0 PB3.11 PB3.10 PB3.9 8 53 9 52 PB1.3/TDO/SWV PB1.4/TDI 51 PB1.5/ETM0 10 80-Pin TQFP PB0.15 PB1.0 PB1.1 PB1.2/TRST 17 44 SWDIO/TMS 18 43 PB1.10 19 42 PB3.0 20 41 PB1.11 PB1.12 27 26 25 24 23 22 21 PB2.14 PB2.13 PB2.12 PB2.11 PB2.10 PB2.9 PB2.8 PB2.7 PB2.6 PB2.5 PB2.4 VIO VSS PB2.3 PB2.2 PB2.1 PB2.0 PB1.15 PB1.14 PB1.13 40 SWCLK/TCK 39 45 38 16 37 PB1.9/TRACECLK PB3.4 PB3.3 PB3.2 PB3.1 36 PB1.8/ETM3 46 35 47 15 34 14 33 PB1.7/ETM2 32 48 31 VIO 13 30 PB3.8 PB3.7 PB3.6 PB3.5 29 PB1.6/ETM1 49 28 50 12 11 Figure 5.1. SiM3U1x7-GQ Pinout Preliminary Rev. 0.8 53 A41 A40 A39 PB4.4 A1 D5 PB4.3 A2 B36 B35 B34 B33 B32 B31 B30 B29 B1 PB0.13 A34 PB0.15 A33 PB1.0 A32 PB1.2* A31 PB1.4* A30 PB1.6* A29 VIO A28 PB1.9* A27 SWDIO* A26 PB1.10 D7 A25 PB1.11 D3 PB1.12 B3 PB3.11 PB1.1 B25 B4 PB3.10 PB1.3* B24 B5 PB3.9 A4 A5 A6 92 pin LGA PB1.5* B23 (Top View) A7 PB3.7 PB1.7* B22 B7 PB3.5 PB1.8* B21 B8 PB3.3 A8 A9 VSS SWCLK* B20 VSS PB2.2 PB2.0 A10 B11 B12 B13 B14 B15 B16 B17 A13 A14 A15 A16 PB2.12 PB2.11 PB2.9 B18 A17 A18 A19 A20 A21 A22 A23 A24 PB1.13 D2 B10 PB1.14 D6 PB1.15 A12 PB2.1 PB3.0 B19 PB2.3 A11 PB2.14 PB3.1 PB2.13 B9 VIO PB3.2 A35 B26 PB2.4 PB3.4 PB0.12 VSSHD B6 PB3.6 A36 PB2.5 PB3.8 D8 B28 B2 PB2.6 PB4.0 D4 PB2.7 PB4.1 A37 A3 PB2.8 PB4.2 A38 PB0.14 B27 PB2.10 VIOHD PB0.11 PB0.8 A42 PB0.10 PB0.6 A43 PB0.9 PB0.4 A44 PB0.7 PB0.2 A45 PB0.5 VIO A46 PB0.3 VDD A47 PB0.1 VREGIN A48 PB0.0 D+ D1 VSS D- PB4.5 VBUS RESET SiM3U1xx *Noted pins are listed in the pinout table and 80-pin TQFP package figure with additional names. These alternate functions are also present on the 92-pin LGA package and are identical to those on the 80-pin TQFP package. Figure 5.2. SiM3U1x7-GM Pinout 54 Preliminary Rev. 0.8 SiM3U1xx Port-Mapped Level Shifter 74 A44 VIO Power (I/O) 32 A19 49 A29 73 A43 VREGIN Power (Regulator) 76 A45 VSSHD Ground (High Drive) 4 B2 VIOHD Power (High Drive) 5 A3 RESET Active-low Reset 80 A48 D– USB Data- 79 A47 D+ USB Data+ 78 A46 VBUS USB Bus Sense 77 B35 SWCLK / TCK Serial Wire / JTAG 45 B20 SWDIO / TMS Serial Wire / JTAG 44 A27 PB0.0 Standard I/O 72 B33 XBR0 ADC0.0 PB0.1 Standard I/O 71 B32 XBR0 ADC0.1 CS0.0 PB0.2 Standard I/O 70 A42 XBR0 ADC0.2 CS0.1 PB0.3 Standard I/O 69 B31 XBR0 ADC0.3 CS0.2 PB0.4 Standard I/O 68 A41 XBR0 ADC0.4 CS0.3 PB0.5 Standard I/O 67 B30 XBR0 ADC0.5 CS0.4 PB0.6 Standard I/O 66 A40 XBR0 CS0.5 Preliminary Rev. 0.8 Functions Power (Core) Analog or Additional VDD External Trigger Inputs 33 B15 75 B34 Output Toggle Logic Ground (m = muxed mode) Port Match VSS Pin Numbers LGA-92 Type Pin Numbers TQFP-80 Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 55 SiM3U1xx Port-Mapped Level Shifter PB0.8 Standard I/O 64 A39 XBR0 ADC0.7 CS0.7 IVC0.1 PB0.9 Standard I/O 63 A38 XBR0 ADC0.8 RTC1 PB0.10 Standard I/O 62 A37 XBR0 RTC2 PB0.11 Standard I/O 61 D4 XBR0 ADC0.9 VREFGND PB0.12 Standard I/O 60 A36 XBR0 ADC0.10 VREF PB0.13 Standard I/O 59 A35 XBR0 IDAC0 PB0.14 Standard I/O 58 B27 XBR0 IDAC1 PB0.15 Standard I/O 57 A34 XBR0 XTAL1 PB1.0 Standard I/O 56 A33 XBR0 XTAL2 PB1.1 Standard I/O 55 B25 XBR0 ADC0.11 PB1.2/TRST Standard I/O /JTAG 54 A32 XBR0 PB1.3/TDO/ SWV Standard I/O /JTAG/ Serial Wire Viewer 53 B24 XBR0 ADC0.12 ADC1.12 PB1.4/TDI Standard I/O /JTAG 52 A31 XBR0 ADC0.13 ADC1.13 PB1.5/ETM0 Standard I/O /ETM 51 B23 XBR0 ADC0.14 ADC1.14 PB1.6/ETM1 Standard I/O /ETM 50 A30 XBR0 ADC0.15 ADC1.15 PB1.7/ETM2 Standard I/O /ETM 48 B22 XBR0 ADC1.11 CS0.8 56 Preliminary Rev. 0.8 Functions ADC0.6 CS0.6 IVC0.0 Analog or Additional External Trigger Inputs 65 B29 XBR0 Output Toggle Logic Standard I/O (m = muxed mode) Port Match PB0.7 Pin Numbers LGA-92 Type Pin Numbers TQFP-80 Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) SiM3U1xx Port-Mapped Level Shifter PB1.9/ TRACECLK Standard I/O /ETM 46 A28 XBR0 ADC1.9 PB1.10 Standard I/O 43 A26 XBR0 A23m/ A15 DMA0T1 ADC1.8 PB1.11 Standard I/O 42 A25 XBR0 A22m/ A14 DMA0T0 ADC1.7 PB1.12 Standard I/O 41 D3 XBR0 A21m/ A13 PB1.13 Standard I/O 40 A24 XBR0 A20m/ A12 ADC0T15 WAKE.0 ADC1.5 CS0.10 PB1.14 Standard I/O 39 A23 XBR0 A19m/ A11 ADC1T15 WAKE.1 ADC1.4 CS0.11 PB1.15 Standard I/O 38 A22 XBR0 A18m/ A10 WAKE.2 ADC1.3 CS0.12 PB2.0 Standard I/O 37 B17 XBR1 A17m/ A9 LSI0 Yes INT0.0 INT1.0 WAKE.3 ADC1.2 CS0.13 PB2.1 Standard I/O 36 A21 XBR1 A16m/ A8 LSI1 Yes INT0.1 INT1.1 WAKE.4 ADC1.1 CS0.14 PB2.2 Standard I/O 35 B16 XBR1 AD15m/ A7 LSI2 Yes INT0.2 INT1.2 WAKE.5 ADC1.0 CS0.15 PMU_Asleep PB2.3 Standard I/O 34 A20 XBR1 AD14m/ A6 LSI3 Yes INT0.3 INT1.3 WAKE.6 PB2.4 Standard I/O 31 B14 XBR1 AD13m/ A5 LSI4 Yes INT0.4 INT1.4 WAKE.7 Preliminary Rev. 0.8 Functions ADC1.10 CS0.9 Analog or Additional External Trigger Inputs 47 B21 XBR0 Output Toggle Logic Standard I/O /ETM (m = muxed mode) Port Match PB1.8/ETM3 Pin Numbers LGA-92 Type Pin Numbers TQFP-80 Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) ADC1.6 57 SiM3U1xx Port-Mapped Level Shifter INT0.5 INT1.5 PB2.6 Standard I/O 29 B13 XBR1 AD11m/ A3 Yes INT0.6 INT1.6 PB2.7 Standard I/O 28 A17 XBR1 AD10m/ A2 Yes INT0.7 INT1.7 PB2.8 Standard I/O 27 B12 XBR1 AD9m/ A1 Yes PB2.9 Standard I/O 26 A16 XBR1 AD8m/ A0 Yes PB2.10 Standard I/O 25 B11 XBR1 AD7m/ D7 Yes PB2.11 Standard I/O 24 A15 XBR1 AD6m/ D6 Yes CMP0P.0 CMP1P.0 PB2.12 Standard I/O 23 A14 XBR1 AD5m/ D5 Yes CMP0N.0 CMP1N.0 RTC0OSC_OUT PB2.13 Standard I/O 22 A13 XBR1 AD4m/ D4 Yes CMP0P.1 CMP1P.1 PB2.14 Standard I/O 21 D2 XBR1 AD3m/ D3 Yes CMP0N.1 CMP1N.1 PB3.0 5 V Tolerant I/O 20 A12 XBR1 AD2m/ D2 CMP0P.2 CMP1P.2 PB3.1 5 V Tolerant I/O 19 A11 XBR1 AD1m/ D1 CMP0N.2 CMP1N.2 PB3.2 5 V Tolerant I/O 18 A10 XBR1 AD0m/ D0 DAC0T0 DAC1T0 LPT0T0 CMP0P.3 CMP1P.3 PB3.3 5 V Tolerant I/O 17 WR DAC0T1 DAC1T1 INT0.8 INT1.8 CMP0N.3 CMP1N.3 58 B8 XBR1 Preliminary Rev. 0.8 Functions AD12m / LSI5 Yes A4 Analog or Additional External Trigger Inputs 30 A18 XBR1 Output Toggle Logic Standard I/O (m = muxed mode) Port Match PB2.5 Pin Numbers LGA-92 Type Pin Numbers TQFP-80 Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) SiM3U1xx A9 XBR1 OE INT0.9 INT1.9 WAKE.8 CMP0P.4 CMP1P.4 PB3.5 5 V Tolerant I/O 15 B7 XBR1 ALEm DAC0T2 DAC1T2 INT0.10 INT1.10 WAKE.9 CMP0N.4 CMP1N.4 PB3.6 5 V Tolerant I/O 14 A8 XBR1 CS0 DAC0T3 DAC1T3 INT0.11 INT1.11 WAKE.10 CMP0P.5 CMP1P.5 PB3.7 5 V Tolerant I/O 13 B6 XBR1 BE1 DAC0T4 DAC1T4 LPT0T1 INT0.12 INT1.12 WAKE.11 CMP0N.5 CMP1N.5 PB3.8 5 V Tolerant I/O 12 A7 XBR1 CS1 DAC0T5 DAC1T5 LPT0T2 INT0.13 INT1.13 WAKE.12 CMP0P.6 CMP1P.6 EXREGSP PB3.9 5 V Tolerant I/O 11 B5 XBR1 BE0 DAC0T6 DAC1T6 INT0.14 INT1.14 WAKE.13 CMP0N.6 CMP1N.6 EXREGSN PB3.10 5 V Tolerant I/O 10 B4 XBR1 INT0.15 INT1.15 WAKE.14 CMP0P.7 CMP1P.7 EXREGOUT PB3.11 5 V Tolerant I/O 9 B3 XBR1 WAKE.15 CMP0N.7 CMP1N.7 EXREGBD Preliminary Rev. 0.8 Functions 16 Analog or Additional Port Match 5 V Tolerant I/O External Trigger Inputs Crossbar Capability (see Port Config Section) PB3.4 Output Toggle Logic Pin Numbers LGA-92 Port-Mapped Level Shifter Type (m = muxed mode) Pin Name Pin Numbers TQFP-80 External Memory Interface Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) 59 SiM3U1xx LSO0 PB4.1 High Drive I/O 7 A5 LSO1 PB4.2 High Drive I/O 6 A4 LSO2 PB4.3 High Drive I/O 3 A2 LSO3 PB4.4 High Drive I/O 2 A1 LSO4 PB4.5 High Drive I/O 1 D1 LSO5 Functions A6 Analog or Additional 8 External Trigger Inputs High Drive I/O Output Toggle Logic Port-Mapped Level Shifter PB4.0 (m = muxed mode) Pin Numbers LGA-92 External Memory Interface Type Port Match Pin Name Pin Numbers TQFP-80 Crossbar Capability (see Port Config Section) Table 5.1. Pin Definitions and alternate functions for SiM3U1x7 (Continued) Note: All unnamed pins on the LGA-92 package are no-connect pins. They should be soldered to the PCB for mechanical stability, but have no internal connections to the device. 60 Preliminary Rev. 0.8 SiM3U1xx 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RESET DD+ VBUS VREGIN VSS VDD PB0.0 PB0.1 PB0.2 PB0.3 PB0.4 PB0.5 PB0.6 PB0.7 PB0.8 5.2. SiM3U1x6 Pin Definitions PB4.3 1 48 PB0.9 VSSHD VIOHD 2 47 3 46 PB0.10 PB0.11 PB4.2 PB4.1 PB4.0 4 45 5 44 6 43 PB3.9 PB3.8 7 42 PB3.7 PB3.6 9 8 41 64 Pin TQFP 40 PB0.12 PB0.13 PB0.14/TDO/SWV PB0.15/TDI PB1.0 PB1.1 VIO 16 33 PB1.5 32 PB1.2 PB1.3 SWCLK/TCK PB2.3 PB2.2 PB2.1 PB2.0 PB1.15 PB1.14 PB1.13 VIO VSS PB1.12 PB1.11 PB1.10 PB1.9 PB1.8 PB1.7 PB1.6 31 PB3.0 30 SWDIO/TMS PB1.4 29 34 28 15 27 35 26 PB3.2 PB3.1 25 36 14 24 13 23 37 22 12 21 38 20 11 19 PB3.5 PB3.4 PB3.3 18 39 17 10 Figure 5.3. SiM3U1x6-GQ Pinout Preliminary Rev. 0.8 61 RESET D- D+ VBUS VREGIN VSS VDD PB0.0 PB0.1 PB0.2 PB0.3 PB0.4 PB0.5 PB0.6 PB0.7 PB0.8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SiM3U1xx PB4.3 1 48 PB0.9 VSSHD 2 47 PB0.10 VIOHD 3 46 PB0.11 PB4.2 4 45 PB0.12 PB4.1 5 44 PB0.13 PB4.0 6 43 PB0.14/TDO/SWV PB3.9 7 42 PB0.15/TDI PB3.8 8 64 pin QFN 41 PB1.0 PB3.7 9 (TopView) 40 PB1.1 PB3.6 10 39 VIO PB3.5 11 38 PB1.2 PB3.4 12 37 PB1.3 PB3.3 13 36 SWCLK/TCK PB3.2 14 35 SWDIO/TMS PB3.1 15 34 PB1.4 PB3.0 16 33 PB1.5 24 25 26 27 28 29 30 31 32 VIO VSS PB1.12 PB1.11 PB1.10 PB1.9 PB1.8 PB1.7 PB1.6 21 PB1.15 23 20 PB2.0 PB1.13 19 PB2.1 22 18 PB2.2 PB1.14 17 PB2.3 VSS Figure 5.4. SiM3U1x6-GM Pinout 62 Preliminary Rev. 0.8 SiM3U1xx Port-Mapped Level Shifter Power (Core) 58 VIO Power (I/O) 24 39 VREGIN Power (Regulator) 60 VSSHD Ground (High Drive) 2 VIOHD Power (High Drive) 3 RESET Active-low Reset 64 D- USB Data- 63 D+ USB Data+ 62 VBUS USB Bus Sense 61 SWCLK/TCK Serial Wire / JTAG 36 SWDIO/TMS Serial Wire / JTAG 35 PB0.0 Standard I/O 57 XBR0 ADC0.2 CS0.1 PB0.1 Standard I/O 56 XBR0 ADC0.3 CS0.2 PB0.2 Standard I/O 55 XBR0 ADC0.4 CS0.3 PB0.3 Standard I/O 54 XBR0 ADC0.5 CS0.4 PB0.4 Standard I/O 53 XBR0 ADC0.6 CS0.5 IVC0.0 PB0.5 Standard I/O 52 XBR0 ADC0.7 CS0.6 IVC0.1 Preliminary Rev. 0.8 Functions VDD Analog or Additional 25 59 External Trigger Inputs Ground Output Toggle Logic Port Match VSS (m = muxed mode) Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 63 SiM3U1xx Port-Mapped Level Shifter ADC0.8 CS0.7 RTC1 PB0.7 Standard I/O 50 XBR0 RTC2 PB0.8 Standard I/O 49 XBR0 ADC0.9 VREFGND PB0.9 Standard I/O 48 XBR0 ADC0.10 VREF PB0.10 Standard I/O 47 XBR0 ADC1.6 IDAC0 PB0.11 Standard I/O 46 XBR0 IDAC1 PB0.12 Standard I/O 45 XBR0 XTAL1 PB0.13 Standard I/O 44 XBR0 XTAL2 43 XBR0 ADC0.12 ADC1.12 PB0.14/TDO/ Standard I/O / JTAG SWV / Serial Wire Viewer Functions XBR0 Analog or Additional 51 External Trigger Inputs Standard I/O Output Toggle Logic Port Match PB0.6 (m = muxed mode) Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) PB0.15/TDI Standard I/O / JTAG 42 XBR0 ADC0.13 ADC1.13 PB1.0 Standard I/O 41 XBR0 ADC0.14 ADC1.14 PB1.1 Standard I/O 40 XBR0 ADC0.15 ADC1.15 PB1.2 Standard I/O 38 XBR0 ADC1.11 CS0.8 PB1.3 Standard I/O 37 XBR0 ADC1.10 CS0.9 PB1.4 Standard I/O 34 XBR0 ADC1.8 PB1.5 Standard I/O 33 XBR0 ADC1.7 PB1.6 Standard I/O 32 XBR0 64 Preliminary Rev. 0.8 ADC0T15 WAKE.0 ADC1.5 CS0.10 SiM3U1xx Port-Mapped Level Shifter AD15m/ A7 ADC1T15 WAKE.1 ADC1.4 CS0.11 PB1.8 Standard I/O 30 XBR0 AD14m/ A6 WAKE.2 ADC1.3 CS0.12 PB1.9 Standard I/O 29 XBR0 AD13m/ A5 WAKE.3 ADC1.2 CS0.13 PB1.10 Standard I/O 28 XBR0 AD12m/ A4 DMA0T1 WAKE.4 ADC1.1 CS0.14 PB1.11 Standard I/O 27 XBR0 AD11m/ A3 DMA0T0 WAKE.5 ADC1.0 CS0.15 PMU_Asleep PB1.12 Standard I/O 26 XBR0 AD10m/ A2 WAKE.6 PB1.13 Standard I/O 23 XBR0 AD9m/ A1 PB1.14 Standard I/O 22 XBR0 AD8m/ A0 PB1.15 Standard I/O 21 XBR0 AD7m/ D7 PB2.0 Standard I/O 20 XBR1 AD6m/ D6 LSI0 Yes INT0.0 INT1.0 PB2.1 Standard I/O 19 XBR1 AD5m/ D5 LSI1 Yes INT0.1 INT1.1 PB2.2 Standard I/O 18 XBR1 AD4m/ D4 LSI2 Yes INT0.2 INT1.2 CMP0N.0 CMP1N.0 RTC0OSC_OUT PB2.3 Standard I/O 17 XBR1 AD3m/ D3 LSI3 Yes INT0.3 INT1.3 CMP0P.0 CMP1P.0 PB3.0 5 V Tolerant I/O 16 XBR1 AD2m/ D2 Preliminary Rev. 0.8 Functions XBR0 Analog or Additional 31 External Trigger Inputs Standard I/O Output Toggle Logic Port Match PB1.7 (m = muxed mode) Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) CMP0P.1 CMP1P.1 65 SiM3U1xx 66 Port-Mapped Level Shifter AD1m/ D1 PB3.2 5 V Tolerant I/O 14 XBR1 AD0m/ D0 DAC0T0 DAC1T0 LPT0T0 WAKE.8 CMP0P.2 CMP1P.2 PB3.3 5 V Tolerant I/O 13 XBR1 WR DAC0T1 DAC1T1 INT0.4 INT1.4 WAKE.9 CMP0N.2 CMP1N.2 PB3.4 5 V Tolerant I/O 12 XBR1 OE INT0.5 INT1.5 WAKE.10 CMP0P.3 CMP1P.3 PB3.5 5 V Tolerant I/O 11 XBR1 ALEm DAC0T2 DAC1T2 INT0.6 INT1.6 WAKE.11 CMP0N.3 CMP1N.3 PB3.6 5 V Tolerant I/O 10 XBR1 CS0 DAC0T3 DAC1T3 INT0.7 INT1.7 WAKE.12 CMP0P.4 CMP1P.4 EXREGSP PB3.7 5 V Tolerant I/O 9 XBR1 BE1 DAC0T4 DAC1T4 INT0.8 INT1.8 WAKE.13 CMP0N.4 CMP1N.4 EXREGSN PB3.8 5 V Tolerant I/O 8 XBR1 CS1 DAC0T5 DAC1T5 LPT0T1 INT0.9 INT1.9 WAKE.14 CMP0P.5 CMP1P.5 EXREGOUT Preliminary Rev. 0.8 Functions XBR1 Analog or Additional 15 External Trigger Inputs 5 V Tolerant I/O Output Toggle Logic Port Match PB3.1 (m = muxed mode) Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) External Memory Interface Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) CMP0N.1 CMP1N.1 SiM3U1xx 5 V Tolerant I/O 7 PB4.0 High Drive I/O 6 LSO0 PB4.1 High Drive I/O 5 LSO1 PB4.2 High Drive I/O 4 LSO2 PB4.3 High Drive I/O 1 LSO3 BE0 Preliminary Rev. 0.8 DAC0T6 DAC1T6 LPT0T2 INT0.10 INT1.10 WAKE.15 Functions PB3.9 Analog or Additional Type External Trigger Inputs Pin Name Output Toggle Logic Port-Mapped Level Shifter (m = muxed mode) Port Match XBR1 External Memory Interface Crossbar Capability (see Port Config Section) Pin Numbers Table 5.2. Pin Definitions and alternate functions for SiM3U1x6 (Continued) CMP0N.5 CMP1N.5 EXREGBD 67 SiM3U1xx RESET D- D+ VBUS VREGIN VDD PB0.0 PB0.1 PB0.2 PB0.3 40 39 38 37 36 35 34 33 32 31 5.3. SiM3U1x4 Pin Definitions PB4.3 1 30 PB0.4 VSSHD 2 29 PB0.5 VIOHD 3 28 PB0.6 PB4.2 4 27 PB0.7 PB4.1 5 40 pin QFN 26 PB0.8 PB4.0 6 (Top View) 25 PB0.9 PB3.3 7 24 SWCLK PB3.2 8 23 SWDIO PB3.1 9 22 PB0.10 PB3.0 10 21 PB0.11 13 14 15 16 17 18 19 20 VSS PB1.1 PB1.0 PB0.15 PB0.14 PB0.13 PB0.12 12 PB1.2 VIO 11 PB1.3 VSS Figure 5.5. SiM3U1x4-GM Pinout 68 Preliminary Rev. 0.8 SiM3U1xx VDD Power (Core) 35 VIO Power (I/O) 13 VREGIN Power (Regulator) 36 VSSHD Ground (High Drive) 2 VIOHD Power (High Drive) 3 RESET Active-low Reset 40 D- USB Data– 39 D+ USB Data+ 38 VBUS USB Bus Sense 37 SWCLK Serial Wire 24 SWDIO Serial Wire 23 PB0.0 Standard I/O 34 XBR0 ADC0.8 CS0.7 RTC1 PB0.1 Standard I/O 33 XBR0 RTC2 PB0.2 Standard I/O 32 XBR0 ADC0.9 CS0.0 VREFGND PB0.3 Standard I/O 31 XBR0 ADC0.10 CS0.1 VREF PB0.4 Standard I/O 30 XBR0 ADC1.6 CS0.2 IDAC0 PB0.5 Standard I/O 29 Preliminary Rev. 0.8 Functions 14 Analog or Additional Ground External Trigger Inputs Port Match VSS Output Toggle Logic Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 IDAC1 69 SiM3U1xx 70 XBR0 ADC0.0 CS0.3 XTAL1 PB0.7 Standard I/O 27 XBR0 ADC0.1 CS0.4 XTAL2 PB0.8 Standard I/O 26 XBR0 ADC0.14 ADC1.14 PB0.9 Standard I/O 25 XBR0 ADC0.15 ADC1.15 PB0.10 Standard I/O 22 XBR0 DMA0T1 ADC1.8 PB0.11 Standard I/O 21 XBR0 DMA0T0 ADC1.7 PB0.12 Standard I/O 20 XBR0 ADC0T15 WAKE.0 ADC1.5 CS0.10 PB0.13 Standard I/O 19 XBR0 ADC1T15 WAKE.1 ADC1.4 CS0.11 PB0.14 Standard I/O 18 XBR0 WAKE.2 ADC1.3 CS0.12 PB0.15 Standard I/O 17 XBR0 WAKE.3 ADC1.2 CS0.13 PB1.0 Standard I/O 16 XBR0 WAKE.4 ADC1.1 CS0.14 PB1.1 Standard I/O 15 XBR0 WAKE.5 ADC1.0 CS0.15 PMU_Asleep PB1.2 Standard I/O 12 XBR0 CMP0N.0 CMP1N.0 RTC0OSC_OUT PB1.3 Standard I/O 11 XBR0 CMP0P.0 CMP1P.0 Preliminary Rev. 0.8 Functions 28 Analog or Additional Standard I/O External Trigger Inputs Port Match PB0.6 Output Toggle Logic Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 (Continued) SiM3U1xx XBR1 DAC0T0 DAC1T0 LPT0T0 INT0.0 INT1.0 WAKE.12 CMP0P.1 CMP1P.1 EXREGSP PB3.1 5 V Tolerant I/O 9 XBR1 DAC0T1 DAC1T1 LPT0T1 INT0.1 INT1.1 WAKE.13 CMP0N.1 CMP1N.1 EXREGSN PB3.2 5 V Tolerant I/O 8 XBR1 DAC0T2 DAC1T2 LPT0T2 INT0.2 INT1.3 WAKE.14 CMP0P.2 CMP1P.2 EXREGOUT PB3.3 5 V Tolerant I/O 7 XBR1 DAC0T3 DAC1T3 INT0.3 INT1.3 WAKE.15 CMP0N.2 CMP1N.2 EXREGBD PB4.0 High Drive I/O 6 PB4.1 High Drive I/O 5 PB4.2 High Drive I/O 4 PB4.3 High Drive I/O 1 Preliminary Rev. 0.8 Functions 10 Analog or Additional 5 V Tolerant I/O External Trigger Inputs Port Match PB3.0 Output Toggle Logic Type Pin Numbers Pin Name Crossbar Capability (see Port Config Section) Table 5.3. Pin Definitions and alternate functions for SiM3U1x4 (Continued) 71 SiM3U1xx 6. Ordering Information Si M3 U 1 4 4 – B – GM Temperature Grade and Package Type Revision Pin Count – 4 (40 pin), 6 (64 pin), 7 (80 or 92 pin) Memory Size – 3 (32 kB), 4 (64 kB), 5 (128 kB), 6 (256 kB) Feature Set – varies by family Family – U (USB), C (Core) Core – M3 (Cortex M3) Silicon Labs Figure 6.1. SiM3U1xx Part Numbering All devices in the SiM3U1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 80 MHz. Flash Program Memory: 32-256 kB, in-system programmable. RAM: 8–32 kB SRAM, with 4 kB retention SRAM I/O: Up to 65 multifunction I/O pins, including high-drive and 5 V-tolerant pins. Clock Sources: Internal and external oscillator options. 16-Channel DMA Controller. 128/192/256-bit AES. 16/32-bit CRC. Timers: 2 x 32-bit (4 x 16-bit). Real-Time Clock. Low-Power Timer. PCA: 1 x 6 channels (Enhanced), 2 x 2 channels (Standard). PWM, capture, and clock generation capabilites. ADC: 2 x 12-bit 250 ksps (10-bit 1 Msps) SAR. DAC: 2 x 10-bit IDAC. Temperature Sensor. Internal VREF. 16-channel Capacitive Sensing (CAPSENSE). Comparator: 2 x low current. Current to Voltage Converter (IVC). USB: Full or low-speed, crystalless operation using internal USB oscillator. Buses: 2 x USART, 2 x UART, 3 x SPI, 2 x I2C, 1 x I2S. The inclusion of some features varies across different members of the device family. The differences are detailed in Table 6.1. Serial 72 Preliminary Rev. 0.8 SiM3U1xx External Memory Interface (EMIF) Maximum Number of EMIF Address/Data Pins Digital Port I/Os (Total) Digital Port I/Os with High Drive Capability Number of SARADC0 Channels Number of SARADC1 Channels Number of CAPSENSE0 Channels Number of Comparator 0/1 Inputs (+/-) Number of PMU Pin Wake Sources JTAG Debugging Interface ETM Debugging Interface Serial Wire Debugging Interface Lead-free (RoHS Compliant) Package 32 24 65 6 16 16 16 8/8 16 LGA-92 SiM3U167-B-GQ 256 32 24 65 6 16 16 16 8/8 16 TQFP-80 SiM3U166-B-GM 256 32 16 50 4 13 15 15 6/6 15 QFN-64 SiM3U166-B-GQ 256 32 16 50 4 13 15 15 6/6 15 TQFP-64 SiM3U164-B-GM 256 32 28 4 7 11 12 3/3 10 QFN-40 SiM3U157-B-GM 128 32 24 65 6 16 16 16 8/8 16 LGA-92 SiM3U157-B-GQ 128 32 24 65 6 16 16 16 8/8 16 TQFP-80 SiM3U156-B-GM 128 32 16 50 4 13 15 15 6/6 15 QFN-64 SiM3U156-B-GQ 128 32 16 50 4 13 15 15 6/6 15 TQFP-64 SiM3U154-B-GM 128 32 28 4 7 11 12 3/3 10 QFN-40 SiM3U146-B-GM 64 16 16 50 4 13 15 15 6/6 15 QFN-64 SiM3U146-B-GQ 64 16 16 50 4 13 15 15 6/6 15 TQFP-64 SiM3U144-B-GM 64 16 28 4 7 11 12 3/3 10 QFN-40 SiM3U136-B-GM 32 8 16 50 4 13 15 15 6/6 15 QFN-64 SiM3U136-B-GQ 32 8 16 50 4 13 15 15 6/6 15 TQFP-64 SiM3U134-B-GM 32 8 28 4 7 11 12 3/3 10 QFN-40 Flash Memory (kB) SiM3U167-B-GM 256 Ordering Part Number RAM (kB) Table 6.1. Product Selection Guide Preliminary Rev. 0.8 73 SiM3U1xx 6.1. LGA-92 Package Specifications Figure 6.2. LGA-92 Package Drawing Table 6.2. LGA-92 Package Dimensions Dimension A b c D D1 D2 e E E1 E2 aaa bbb ccc ddd eee Min 0.74 0.25 3.15 — — — — — Nominal 0.84 0.30 3.20 7.00 BSC 6.50 BSC 4.00 BSC 0.50 BSC 7.00 BSC 6.50 BSC 4.00 BSC — — — — — Max 0.94 0.35 3.25 0.10 0.10 0.08 0.10 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 74 Preliminary Rev. 0.8 SiM3U1xx Figure 6.3. LGA-92 Landing Diagram Table 6.3. LGA-92 Landing Diagram Dimensions Dimension Typical Max C1 6.50 — C2 6.50 — e 0.50 — f — 0.35 P1 — 3.20 P2 — 3.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 3. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 4. This land pattern design is based on the IPC-7351 guidelines. Preliminary Rev. 0.8 75 SiM3U1xx 6.1.1. LGA-92 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.1.2. LGA-92 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 4. A 2 x 2 array of 1.25 mm square openings on 1.60 mm pitch should be used for the center ground pad. 6.1.3. LGA-92 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 76 Preliminary Rev. 0.8 SiM3U1xx 6.2. TQFP-80 Package Specifications Figure 6.4. TQFP-80 Package Drawing Table 6.4. TQFP-80 Package Dimensions Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.20 0.27 c 0.09 — 0.20 D 14.00 BSC D1 12.00 BSC e 0.50 BSC E 14.00 BSC E1 12.00 BSC Preliminary Rev. 0.8 77 SiM3U1xx Table 6.4. TQFP-80 Package Dimensions (Continued) Dimension Min Nominal Max L 0.45 0.60 0.75 L1 1.00 Ref 0° 3.5° aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.05 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ADD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 78 Preliminary Rev. 0.8 SiM3U1xx Figure 6.5. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension Min Max C1 13.30 13.40 C2 13.30 13.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Preliminary Rev. 0.8 79 SiM3U1xx 6.2.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.2.2. TQFP-80 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.2.3. TQFP-80 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 80 Preliminary Rev. 0.8 SiM3U1xx 6.3. QFN-64 Package Specifications Figure 6.6. QFN-64 Package Drawing Table 6.6. QFN-64 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 3.95 4.10 e 0.50 BSC E 9.00 BSC 4.25 E2 3.95 4.10 4.25 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.8 81 SiM3U1xx Figure 6.7. QFN-64 Landing Diagram Table 6.7. QFN-64 Landing Diagram Dimensions Dimension mm C1 8.90 C2 8.90 E 0.50 X1 0.30 Y1 0.85 X2 4.25 Y2 4.25 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 82 Preliminary Rev. 0.8 SiM3U1xx 6.3.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.3.2. QFN-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.0 mm square openings on a 1.5 mm pitch should be used for the center ground pad. 6.3.3. QFN-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.8 83 SiM3U1xx 6.4. TQFP-64 Package Specifications Figure 6.8. TQFP-64 Package Drawing Table 6.8. TQFP-64 Package Dimensions 84 Dimension Min Nominal Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 — 0.20 D 12.00 BSC D1 10.00 BSC e 0.50 BSC E 12.00 BSC E1 10.00 BSC L 0.45 0.60 0.75 0° 3.5° 7° Preliminary Rev. 0.8 SiM3U1xx Table 6.8. TQFP-64 Package Dimensions (Continued) Dimension Min Nominal Max aaa — — 0.20 bbb — — 0.20 ccc — — 0.08 ddd — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ACD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.8 85 SiM3U1xx Figure 6.9. TQFP-64 Landing Diagram Table 6.9. TQFP-64 Landing Diagram Dimensions Dimension Min Max C1 11.30 11.40 C2 11.30 11.40 E 0.50 BSC X 0.20 0.30 Y 1.40 1.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. 86 Preliminary Rev. 0.8 SiM3U1xx 6.4.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.4.2. TQFP-64 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 6.4.3. TQFP-64 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.8 87 SiM3U1xx 6.5. QFN-40 Package Specifications Figure 6.10. QFN-40 Package Drawing Table 6.10. QFN-40 Package Dimensions Dimension Min Nominal Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 6.00 BSC 4.35 4.50 e 0.50 BSC E 6.00 BSC 4.65 E2 4.35 4.5 4.65 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 88 Preliminary Rev. 0.8 SiM3U1xx Figure 6.11. QFN-40 Landing Diagram Table 6.11. QFN-40 Landing Diagram Dimensions Dimension mm C1 5.90 C2 5.90 E 0.50 X1 0.30 Y1 0.85 X2 4.65 Y2 4.65 Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Preliminary Rev. 0.8 89 SiM3U1xx 6.5.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 6.5.2. QFN-40 Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.1 mm square openings on a 1.6 mm pitch should be used for the center ground pad. 6.5.3. QFN-40 Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 90 Preliminary Rev. 0.8 SiM3U1xx 7. Revision Specific Behavior This chapter details any known differences from behavior as stated in the device datasheet and reference manual. All known errata for the current silicon revision are rolled into this section at the time of publication. Any errata found after publication of this document will initially be detailed in a separate errata document until this datasheet is revised. 7.1. Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information. Figures 7.1, 7.2, 7.3, and 7.4 show how to find the Lot ID Code on the top side of the device package. In addition, firmware can determine the revision of the device by checking the DEVICEID registers. SiM3U167 BGNZEB 1142 This first character identifies the device revision Figure 7.1. LGA-92 SiM3U1x7 Revision Information SiM3U167 A-GQ 1131BCS701 e3 TW This character identifies the device revision Figure 7.2. TQFP-80 SiM3U1x7 Revision Information Preliminary Rev. 0.8 91 SiM3U1xx SiM3U166 BGNZEB 1142 SiM3U166 BGNZEB 1142 This first character identifies the device revision Figure 7.3. SiM3U1x6 Revision Information SIL M3U164 BGNZ 1142+ This first character identifies the device revision Figure 7.4. SiM3U1x4 Revision Information 7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1) 7.2.1. Problem On Revision A and Revision B devices, if the comparator output is high, the comparator rising and falling edge flags will both be set to 1 upon single-step or exit from debug mode. 7.2.2. Impacts Firmware using the rising and falling edge flags to make decisions may see a false trigger of the comparator if the output of the comparator is high during a debug session. This does not impact the non-debug operation of the device. 7.2.3. Workaround There is not a system-agnostic workaround for this issue. 7.2.4. Resolution This issue exists on Revision A and Revision B devices. It may be corrected in a future device revision. 92 Preliminary Rev. 0.8 SiM3U1xx NOTES: Preliminary Rev. 0.8 93 SiM3U1xx CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Precision32 are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 94 Preliminary Rev. 0.8