Si3459 Octal IEEE 802.3at PoE PSE Controller

Si3459
O C TA L I E E E 8 0 2 . 3 A T P O E PSE C O N T R O L L E R
Features

Octal-Port Power Sourcing
Equipment (PSE) controller
 IEEE 802.3at Type I and II
compliant
 Port priority shutdown control
 Adds enhanced features for
maximum design flexibility:
Per-port
current and voltage
monitoring
PoE+ support with programmable
current limits
Multi-point detection
Programmable power MOSFET
gate drive control
Configurable watchdog timer
enables failsafe operation

Maskable interrupt pin
 Comprehensive fault protection
circuitry includes:
Power
undervoltage lockout
current limit and shortcircuit protection
Thermal overload detection
Output

Pin-programmable AUTO modes
Extended operating temp range:
–40 to +85 °C
 56-pin QFN package
(RoHS-compliant)
 On-chip dc-dc converter enables
single-rail power operation

Ordering Information:
See page 49.
Applications
 IEEE Power Sourcing Equipment  IP Phone Systems
(PSE)
 Smartgrid Switches
 Power over Ethernet Switches
 Ruggedized and Industrial
Switches
Description
The Si3459 is a fully-programmable, eight-port power management
controller for IEEE 802.3 compliant Power Sourcing Equipment (PSE).
Designed for use in PSE endpoint (switches), the Si3459 integrates eight
independent ports, each with IEEE-required powered device (PD)
detection and classification functionality. In addition, the Si3459 features a
fully-programmable architecture that enables powered device (PD)
disconnect using a dc sense algorithm, a robust multipoint detection
algorithm, software-configurable per-port current and voltage monitoring,
and programmable current limits to support the IEEE 802.3at standard.
Intelligent protection circuitry includes input undervoltage detection,
output current limit, and short-circuit protection. The Si3459 operates by
host processor control through a three-wire, I2C-compatible serial
interface. Independent serial data input and output pins enable highvoltage isolation through external isolators. An interrupt pin is used to
alert the host processor of various status and fault conditions. The device
also supports pin-programmable AUTO modes for autonomous operation,
without the need for a host processor. The Si3459 also features an onchip dc-dc converter for creating the digital voltage rail from the PoE
voltage, thus enabling single-rail power operation.
Rev. 1.1 10/15
Copyright © 2015 by Silicon Laboratories
Si3459
Si3459
Functional Block Diagrams
SCL
SDAI
SDAO
MCU
HVIO
SPI
C8051
MCU Core
HV
SIO
SRAM
A1
A2
A3
A4
n
Detect
Drive
Drive
Control
Detection MUX
OTP
n
2
INT
n
RESET
AUTO
VPWR
(+52 V)
Detect Xn (/4)
POR
WDT
50MHz
TIMERS
Measure (x2)
Measure
AMUX
Gate
Drive Xn
n
2
ADC
r
Gate
Drive
PGA
AMUX
10 Bit
500Khz
VDD
VDDA
DC-DC
Controller
Temp
Sensor
Bandgap
AGND
DGND CAP DCEN SWO
VPORTn
(VDRAINn – VPWR)
SHDN
n
SENSEn
GATEn
DRAINn
KSENSx
Rsn
VDD (+3.3V)
0.25 
VDRAINn
(NOTE: Only one port shown)
DC-DC Converter Block Diagram
VPWR
VDDA
3.3V
Regulator 4.3V
CAP
DCEN
ISENSE
SWO
AGND
The case shown has both the DC-DC converter and series regulator enabled.
To enable ONLY the series regulator, tie SWO to VPWR. External components are unnecessary.
2
Rev. 1.1
Si3459
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Octal High-Voltage PSE Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3. VDD Ramp Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4. I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. DC-to-DC Converter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1. Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2. Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8. Recommended Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1. Si3459 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
10. Firmware Revision Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 1.1
3
Si3459
1. Electrical Specifications
Table 1. PSE Port Interface Recommended Operating Conditions1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VPWR Input Supply
Voltage
VPWR
When generating
IEEE-compliant output voltage
44
48
57
V
VPWR UVLO Input
Voltage (to turn on)2
VUVLO_ON
—
32
—
V
VPWR UVLO Input
Voltage (to turn off)2
VUVLO_OFF
—
44
—
V
VDD Supply Voltage
VDD
3.0
3.3
3.6
V
VDD UVLO Voltage2
VDD_UVLO
VDD – AGND
—
2.8
—
V
VRESET
VDD voltage
causing an MCU reset
—
1.8
—
V
Power Supply Voltages
Hardware Reset
Voltage
Notes:
1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
4
Rev. 1.1
Si3459
Table 1. PSE Port Interface Recommended Operating Conditions1 (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
IVPWR
During normal operation
—
2
5
mA
—
18
25
mA
Primary detection voltage
—
–4.0
–2.8
V
Secondary detection voltage
–10
–8.0
—
V
Measured when VPORTn = 0 V
—
3
4.9
mA
Power Supply Currents3
VPWR Supply Current
VDD Supply Current
IDD
Detection Specification
Detection Voltage
when RDET = 25.5k
Detection Current Limit
VPORTn
IDET
Minimum Signature
Resistance @ PD
RDET_MIN
15
—
19
k
Maximum Signature
Resistance @ PD
RDET_MAX
26.5
—
33
k
Shorted Port Threshold
RSHORT
150
—
400

Open Port Threshold
ROPEN
100
—
400
k
Classification Specifications
Classification Voltage
VCLASS
0 mA < ICLASS < 45 mA
–20.5
—
–15.5
V
Classification Current
ICLASS
Measured when VPORTn = 0 V
55
—
95
mA
Class 0
0
—
5
mA
Class 1
8
—
13
mA
Class 2
16
—
21
mA
Class 3
25
—
31
mA
Class 4
35
—
45
mA
Classification Current Region
ICLASS_REGION
Notes:
1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
Rev. 1.1
5
Si3459
Table 1. PSE Port Interface Recommended Operating Conditions1 (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
IPORT = 0 mA
–10
—
—
V
IPORT = 5 mA
—
—
–7
V
Classification Mark Specifications
Mark Voltage
VMARK
Output Voltage Sense
Threshold Voltage
for Power Good Sense
VPGOOD
Measured at VDRAINn to AGND
1
—
3
V
Bias Current of DRAINn Pin
IDRAINn
VDRAINn = 0 V
—
–25
—
µA
RSENSE
1% tolerance
0.2475
0.25
0.2525

VSENSEn–VKSENSEn
1x Power Mode
100
106.25
112.5
mV
VSENSEn–VKSENSEn
2x Power Mode
200
212.5
225
mV
VDC_MIN
VSENSEn – VKSENSEn
1.25
1.875
2.5
mV
ISENSE
VSENSEn – AGND
—
–1
—
µA
GATEn pin active
VGATEn = AGND
1x Power Mode
–60
–40
–20
µA
GATEn pin shut off
VGATEn = AGND + 5 V
—
50
—
mA
IGATEn = –1 µA
10.5
12
13
V
Current Sense
Sense resistor value
Sense Voltage
at Current Limit
DC Disconnect
Sense Voltage
SENSEn Pin Bias
Current
VILIM
MOSFET Gate Drive
Drive Current
from GATEn Pin (Active)
Drive Current
from GATEn Pin (Off)
Voltage Difference Between
any GATEn and AGND Pin
Notes:
1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
6
Rev. 1.1
Si3459
Table 1. PSE Port Interface Recommended Operating Conditions1 (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VPWR
VPWR = 50 V
47.5
—
52.5
V
IPORT = 7.5 mA
5
7.5
10
mA
IPORT = 350 mA
335
350
365
mA
IPORT = 700 mA
670
—
730
mA
VPORTn
Force port voltage
–20
–15
–10
V
IPORTn
Force current through sense
resistor
0.5
2.0
4.0
mA
Measurement Accuracy
Voltage Measurement
Current Measurement
Bad FET Measurement (Port
Voltage at the Beginning of
Detection that Causes a Bad
FET Indication)
I (IPORT)
Notes:
1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These
specifications apply over the recommended operating voltage and temperature ranges of the device unless noted
otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.
2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR
(0x02, 0x03)” .
3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.
Table 2. DC-DC Converter Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Regulator Input Voltage
VCAP
—
3.6
4.3
4.6
V
DC-DC Switcher
Output Current
ILOAD
—
0.1
—
200
mA
Regulator Output Voltage
VDDA
55 mA load
3.0
3.3
3.6
V
Regulator Output Current
IDDA
—
0.1
—
55
mA
Rev. 1.1
7
Si3459
Si3483
Si8605
Power Manager IC
Bus Isolator
VDDA
Regulator
Regulator
Regulator
Si3459
Si3459
Si3459
Octal PSE
Octal PSE
Octal PSE
DC‐DC
BOM
VCAP
 Up to six Si3459s with one DC‐DC
 IVCAP is 200mA (max)
 IVDDA is 55mA (max)
Figure 1. 55 mA and 200 mA Budget Load Components
8
Rev. 1.1
Si3459
Table 3. Digital Pin Recommended Operating Conditions1
Parameter
Symbol
Test Condition
Pins
Min
Typ
Max
Unit
Input low Voltage
VIL
RESET, SCL,
SDAI, A4, A3,
A2, A1
—
—
0.8
V
Input High Voltage
VIH
RESET, SCL,
SDAI, A4, A3,
A2, A1
2.0
—
—
V
RESET, SCL,
SDAI, A3, AIN,
INT, DCEN
—
—
6
µA
SHDN
—
—
10
µA
IIH
Input Leakage
Output Low
Voltage2
VDD = 4.2 V,
Vpin = 4.2 V
IIL
VDD = 4.2 V,
Vpin = 0 V
SHDN
—
85
—
µA
IIL
VDD = 3.3 V,
Vpin = 0 V
RESET, SCL,
SDAI, A4, A3,
A2, A1, INT,
DCEN
—
15
50
µA
VOL
ISDAO = 8 mA,
IINT = 8 mA
IAOUT = 8 mA
—
—
0.6
V
Notes:
1. All specification voltages are referenced with respect to DGND. These specifications apply over the recommended
operating voltage and temperature ranges of the device unless noted otherwise.
2. SDAO and INT are open drain outputs. Tie each pin to VDD with a 1 k resistor for normal operation.
Rev. 1.1
9
Si3459
Table 4. AC Timing Specifications
Parameter
Detection Delay Cycle
Detection Time
Classification Delay
Cycle
Symbol
Test Condition
Min
Typ
Max
Unit
tDET_CYCLE
Time from detect command or
when PD is connected to port to
when detection process is completed.* See Figure 6.
70
—
400
ms
tDETECT
Time required to measure PD
signature resistance.*
See Figure 6.
—
70
—
ms
Time from successful detect in
Semi-AUTO mode to classification complete.*
See Figure 6.
10
—
30
ms
Time from classify command in
manual mode to class complete.*
See Figure 6.
10
—
30
ms
See Figure 6*
10
—
20
ms
tCLASS_CYCLE
Classification Time
tCLASS
Inrush Time
tINRUSH
—
60
—
ms
tCUT
—
60
70
ms
tCMPS
—
360
—
ms
Overload Time Limit
Disconnect Delay
tLIM
1.71 ms times the value of
TLIM12 (TLIM34) field rounded
to nearest integer.
0
—
26
ms
DC Disconnect Minimum
Pulse Width Sensitivity
tDC_SEN
VDRAINn = –48 V,
VSENSEn – AGND > 5 mV
—
—
3
ms
SHDN Pin Assertion
Threshold (Time from
SHDN falling edge to port
turn off)
TSHDN
Shutdown Priority Mode
1
—
50
µs
Timer Duration
*Note: This timing is determined by the MCU, and the clock reference is guaranteed to be 1 ms ±5%.
10
Rev. 1.1
Si3459
Table 5. I2C Bus Timing Specifications1,2,3,4,5,6
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Serial Bus Clock Frequency
fSCL
See Figure 5
0
—
800
kHz
SCL High Time
tSKH
See Figure 5
300
—
—
ns
SCL Low Time
tSKL
See Figure 5
650
—
—
ns
Bus Free Time
tBUF
Between STOP and START conditions. See Figure 5
650
—
—
ns
Start Hold Time
tSTH
Between START and first low
SCL. See Figure 5
300
—
—
ns
Start Setup Time
tSTS
Between SCL high and START
condition. See Figure 5
300
—
—
ns
Stop Setup Time
tSPS
Between SCL high and STOP
condition. See Figure 5
300
—
—
ns
Data Hold Time
tDH
See Figure 57
75
—
—
ns
Data Setup Time
tDS
See Figure 5
100
—
—
ns
tRESET
Reset to start condition
5
—
—
ms
Time from Hardware or Software Reset until Start of I2C
Traffic
Notes:
1. All specification voltages are referenced with respect to AGND and DGND at ground. Currents are defined as positive
flowing into a pin and negative flowing out of a pin.
2. Not production tested (guaranteed by design).
3. All timing references measured at VIL and VIH.
4. SDAI must be low within ½ SCL clock cycle of SDAO going low for the following reasons:
a.) During a read transaction, if the Si3459 is letting SDAO go high and another device is driving SDAO low, this should
be recognized as bus contention, and the Si3459 should release the bus. If SDAO low is not present on SDAI within ½
clock cycle, the Si3459 will not recognize this as bus contention and will not release the bus.
b.) During any I2C transaction, the Si3459 will ACK (SDAO low) when its address is sent. The Si3459 “expects” that
SDAI will follow within ½ of the SCL clock cycle. If SDAI is not low, the Si3459 will release the bus.
5. SCL and SDA rise and fall times depend on bus pullup resistance and bus capacitance.
6. The time from a fault event to the INT pin being driven is software-defined. The Si3459 produces a new measurement
result for the Port voltage or current every 3 msec and every 6 msec for the power supplies and temperature. After
each port is monitored, the port status, port event registers, INT register, and INT pin are updated in sequence. For this
reason, the INT pin can lag the contents of the event registers by approximately 5 ms.
7. 250 ns minimum and 350 ns maximum for the case where the Si3459 is transmitting data.
Rev. 1.1
11
Si3459
0V
V PORTn
_ 4V
_
_ 4V
8V
_ 18V
_
Pgood
VPWR
INT
Figure 2. Semi-Auto Timing for Detect, Classification, and Power-Up Sequence
V LIM
V CUT
V SENSEn
AGND, DGND = 0V
tINRUSH,
tOVLD
INT
Figure 3. Current Limit Timing
VSENSEn
VDCMIN
tDC_DIS
tDC_SEN
INT
Figure 4. DC Disconnect Timing
12
Rev. 1.1
Si3459
tR_SCL
fSCL
tF_SCL
tSKH
tSKL
SCL
tBUF
tSTH
SDAI
SDAO
tDS
D7
D6
tDH
D5
D4
Start Bit
tSPS
D3
D0
Stop Bit
Figure 5.
I2 C
Bus Interface Timing
Rev. 1.1
13
Si3459
Table 6. Thermal Characteristics
Parameter
Symbol
Operating Temperature
TA
Thermal Impedance
JA
Junction Temperature
TJ
Test Condition
4-Layer PCB, no airflow
Min
Typ
Max
Unit
–40
—
85
°C
—
24
—
°C/W
–40
—
125
°C
Table 7. Absolute Maximum Ratings1
Type
Parameter
Rating
Unit
VPWR to AGND2
–0.3 to 70
V
VDD to DGND2
–0.3 to 4.2
V
INT, RESET, A4, A3, A2, A1, SCL, SDAI,
SDAO, SHDN, AUTO
DGND–0.3 to DGND+5.8
V
SENSEn
AGND–0.6 to AGND+0.6
V
GATEn3,4
AGND–0.3 to AGND+12
V
DRAINn
–0.3 to VPWR
V
KSENSA, KSENSB
AGND–0.6 to AGND+0.6
V
ISENSE
VPWR–5 to VPWR
V
–2 to +2
kV
125
°C
Operating temperature range
–40 to +85
°C
Ambient Storage Temperature
–65 to 150
°C
260
°C
Supply Voltages
Voltage on Digital Pins
Voltage on Analog Pins
ESD HBM (Human Body Model5) Tolerance
Maximum Junction Temperature6
Lead Temperature (Soldering, 10 Seconds Maximum)
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Functional operation should be constrained to those
conditions specified in Table 1, “PSE Port Interface Recommended Operating Conditions1,” on page 4 and Table 3,
“Digital Pin Recommended Operating Conditions1,” on page 9.
2. AGND is shorted to DGND inside the package.
3. The GATE pins include an integrated clamp to limit the pins to a minimum of 12 V above AGND, GATE voltages in
excess of AGND+12 V may cause permanent disconnect of the affected port.
4. The Si3459 includes protection circuitry to tolerate up to 80 mA of transient current for a maximum of 5 ms.
5. Charged Device Model (CDM), and Cable Discharge Event (CDE) electrical stress tolerance are typically 500 V and
3 kV.
6. Thermal overload protection shuts down the device when the silicon junction temperature exceeds 165 °C, including a
temperature hysteresis of 20 °C.
14
Rev. 1.1
Si3459
2. Typical Performance Characteristics
This section shows various waveforms that describe typical behaviors and performance of the Si3459. The
waveform in Figure 6 shows the part in semi-auto mode with Rgood and Cgood. The Si3459 uses a multi-point
detection algorithm. Typically, a Cbad of >10 µF causes an Rlow indication. The Detection Signature is calculated
for two measurements at the primary voltage and two measurements at the secondary voltage. For there to be an
Rgood indication, the signature must be Rgood in all steps.
Figure 6. Typical Detect and Classify Sequence (Semi-Auto Mode)
Figure 7 shows the FET gate drive set to 50 µA for FET turn-on. The slew time is about 40 µs with this FET gate
drive and is not strongly load-dependent.
Figure 7. Typical Powerup (220  Load)
Rev. 1.1
15
Si3459
The waveform in Figure 8 shows power down when the load is switched to 100 k.
Figure 8. Typical DC Disconnect and Powerdown Sequence
iPORT (A)
Type 2 mode (850mA)
Type 1 mode (425mA)
iMIN=108mA
vDRAIN (V)
Figure 9. Foldback Current in IEEE 802.3at Type 1 (1X) and Type 2 (2X) Current Limit Modes
16
Rev. 1.1
Si3459
Short C ircuit R esponse
0
5 V/div or 500 m A /d
Iport
V gate
Vport
5 µs/div
5 s/d iv
Figure 10. Short Circuit Response
Rev. 1.1
17
Si3459
3. Functional Description
Integrating a high-performance microcontroller with high-resolution A/D and D/A capabilities, along with eight
independent, high-voltage PSE port interfaces, the Si3459 enables an extremely flexible solution for virtually any
PoE switch application. The Si3459 integrates all PSE controller functions needed for an octal-port PoE design.
The Si3459 includes many additional features that can be individually enabled or disabled by programming the
extended register set appropriately.
Per-port
current / voltage monitoring and measurement
Multipoint detection algorithms
802.3at support
Programmable gate drive for external MOSFETs
Watchdog timer (WDT)
3.1. Octal High-Voltage PSE Port Interfaces
In addition to the IEEE 802.3at detection and classification functionality, the high-voltage port interfaces provide
accurate voltage and current control and measurement for each of the eight output ports. The high-voltage port
interface circuitry is controlled by the internal microcontroller and includes the following features beyond the
802.3at standard's base requirements.
3.1.1. Per-Port Measurement and Monitoring
The measurement function supports the following capabilities, which enable flexible per-port voltage and current
monitoring.
Detection
FET
and classification current measurement with on-chip sense resistors.
current measurement through 0.25  sense resistor with 1 A full-scale.
FET
current scaling is changed dynamically so as to allow sensitive and accurate dc disconnect, even for a 2x current
limit.
Current
VPWR
measurement offset calibration circuitry.
and output voltage measurement.
Each
channel and range is factory-calibrated.
parameters can be read from each port’s corresponding registers (output voltage, and current) and are
sampled approximately every three milliseconds.
Channel
Supply
monitors on VDD and VPWR.
3.1.2. DC Disconnect
DC disconnect may be enabled on any port. If dc disconnect is not enabled when the load is disconnected, the port
will not shut off except in response to other fault conditions.
3.1.3. Programmable MOSFET Gate Drivers
To provide maximum system-level design flexibility and optimal EMI performance when interfacing to external highcurrent MOSFET devices, the Si3459 provides eight independent MOSFET gate drivers with the following
features:
Drive
current is 50 µA nominal.
100 mA pull-down that is automatically activated if a current transient of 25% over the programmed
current limit is sensed.
Current limit circuit that can be programmed to 425 or 850 mA typical.
A
limit is based on voltage sensed across 0.25  sense resistor.
channel and range is internally trimmed to ±5% accuracy.
Linear foldback behaves as shown in Figure 9 on page 16.
Current
Each
18
Rev. 1.1
Si3459
3.2. Operating Modes
The Si3459 normally operates in manual or semi-automatic mode when the AUTO pin is held low. If a valid set
voltage level (described in Table 8) is applied to the AUTO pin, the Si3459 enters into fully autonomous operation,
independent of a host. When setup voltages indicated as “Reserved” are applied to the AUTO pin, the Si3459 does
not enter into fully autonomous mode but remains instead in Shutdown mode. The Si3459 also features dc
disconnect detection algorithms to determine when a PD device is disconnected from any of the eight independent
ports.
The AUTO mode can be set via the AUTO pin or from the host via I2C.
At power-up, the Si3459 reads the voltage on the AUTO pin (which can be set by a resistor divider from VDD to
GND). If a valid setup voltage is applied, the Si3459 enters into AUTO mode (all ports operate fully autonomously).
The AUTO pin voltage level configures the Si3459's behavior through the register default values as summarized in
Table 8 below.
In Host-controlled mode, any port can be configured to AUTO mode through the confp_x register. In this case the
Host should set the proper port configuration.
Table 8. Auto Pin Configurations
Voltage on the AUTO Pin
IEEE
Class
Endpoint
vs.
Midspan
Restart
Detect+Classify
Looping
0
Shutdown
(AUTO pin pulled to GND)
0.22
Reserved
0.44
Reserved
0.66
3
0.88
Reserved
1.10
Reserved
1.32
Reserved
1.54
3
1.76
Reserved
1.98
Reserved
2.20
Reserved
2.42
4
2.64
Reserved
2.86
Reserved
3.08
Reserved
3.30
(AUTO pin pulled to VDD)
4
Register Default Values
confp_x tlimp_x icutp_x
0x00
0x00
0x54
Mid
Auto after
2s
Automatic detect/
class loop
0x7f
0x00
0x54
End
Auto after
2s
Automatic detect/
class loop
0x3f
0x00
0x54
Mid
Auto after
2s
Automatic detect/
class loop
0x7f
0x20
0x54
End
Auto after
2s
Automatic detect/
class loop
0x3f
0x20
0x54
Rev. 1.1
19
Si3459
3.2.1. Additional Operating Modes Notes
By
default the Icut limit is set to 375 mA (icutp_x = 0x54; Class 0 or Class 3 limits) initially for all operating
modes
3.2.1.1. AUTO Mode-Specific Behaviors
The
“hpen” bit will be set automatically, but only if the 2-event classification was successful
If there was a successful 2-event classification, then the Icut limit will be increased to 638 mA (Nominal)
automatically (icutp_x = 0x62)
The intmask register is set to 0xff in all pin configured AUTO modes
3.2.1.2. Manual and Semi-Auto Mode Behaviors
To
enable IEEE Type 2 Class 4 operation only the “pongen” bit need be set (tlimp_x = 0x20)
It is the host role to set the “hpen” bit, but only if the 2-event classification was successful (the “pongpd” bit
is set in the pwrstatp_x register)
It is the host role to set the Icut limit properly
3.2.2. Port ON/OFF Control
The Si3459 offers various options for the Host to control the state of the ports. There is also logic in the part which
controls the port state in response to an event.
3.2.2.1. HOST Controlled Port Turn ON
A port can be turned ON in the following ways:
1. In manual Mode, the port can be unconditionally turned on using the proper pushbutton register (set the
“on_x” bit (Bit 0) in the pb_p_x register).
2. In Semi-Auto mode the port can be also turned on using the proper pushbutton register, but the port will not
turn on until a valid PD signature is detected.
3. In Host controlled Auto mode (the AUTO pin is held low), the port will turn on automatically if detection and
classification is enabled, a valid signature is detected, and the classification is successful. Otherwise the
port can also be turned on using the proper pushbutton register, but in this Mode, the port will not turn on
until a valid PD signature is detected. The following steps detail how a port can be turned on in the IEEE
Std 802.3at-2012 Type 2 high-power manner:
a. Enable detection and classification by setting the “detena_x” bit (Bit 2) “classena_x” bit (Bit 3) in the
confp_x register
b. Set the “hpen_x” bit (Bit 7) and the “pongen_x” bit (Bit 6) in the tlimp_x register to enable the 2-Event
classification on the port, and
c. Set the Icut limit in the icutp_x register according to the available power
4. In the Host independent Auto mode (positive voltage is applied to the AUTO pin), the detection and 2-event
classification is enabled by default, so the port will turn on automatically if a valid signature is detected and
the classification is successful. The current limits are set according to the classification result, so both Type
1 and Type 2 PDs are handled correctly.
3.2.2.2. Autonomous port turn ON
The only occurrence when the port could be turned ON automatically by the Si3459 is when the port is in Auto
Mode and the detection and the classification were successful.
3.2.2.3. HOST controlled port turn OFF
A port can be turned OFF at any time using one of the following methods:
1. By setting the “off_x” bit (Bit 1) in the pb_p_x registers (0x17, 0x27, 0x37, 0x47): The port is shut down, the
event and status registers of the port are set to their default value, and the classification enable and
detection enable bits are also cleared in the corresponding confp_x register (0x14, 0x24, 0x34, 0x44). The
value of the other bits of the confp_x register are retained. The associated measurement data registers are
also cleared.
20
Rev. 1.1
Si3459
2. By setting the “rst_x” bit (Bit 4) in the pb_p_x register: The port is shut down, and all associated events and
configurations are cleared (all port registers are set to their default state)
3.2.2.4. Autonomous Port Turn OFF
In the following cases, a port is (or all ports are) turned OFF automatically by the Si3459:
1. In response to the over-temperature event all ports are turned OFF by using the “offall” bit in the pb_global
register (0x0B). This is equivalent to the situation where the “off_x” of pb_p_x registers (0x17, 0x27, 0x37
and 0x47 for ports 1–4, respectively) were set.
2. In response to a UVLO event (either VDD or VPWR UVLO), all ports are reset by using the “rstall” bit in the
pb_global register (0x0B). This is equivalent to the situation where the “rst_x” of the pb_p_x registers
were set.
3. In response to the SHDN pin assertion the low priority ports are turned OFF by using the “off_x” bit (Bit 1)
of pb_p_x register.
4. In response to an over-current event the port is shut down, i.e.: power is removed from the DRAINn pin,
and the “pe_x” (Penable bit; Bit 0) and the “pg_x” (Pgood bit, Bit 1) for that port is set.
The events are not cleared, and the full port configuration is retained.
3.3. VDD Ramp Time
It is recommended that VDD ramp into the operational range within 1 ms if reset is not held low. Slow ramp times
are acceptable if reset is held low until VDD is in the operational range. For additional detail on VDD and
undervoltage lockout, refer to “4.2.2. Global Event Register and Global Event COR (0x02, 0x03)” .
3.4. I2C Protocol
Controlling the features of the Si3459 is possible by programming a series of registers identified in the Register
Map (see "4. Register Map" on page 25). Registers are accessible through a three-wire, I2C-compatible serial
interface.
3.4.1. Slave Address
The Si3459 slave base address is pin-assigned by logical ORing HW pins {A[4:1]} with value 0x20.
The complete base address is formed as “01[A4][A3][A2][A1]A0b”.
A0 is not a hardware bit. The device acts as two “virtual” quad devices with the address of the first quad being
A0 = 0 and the address of the second quad being A0 = 1 in the I2C protocol (see Figure 11 on page 22).
3.4.1.1. Available I2C Transfer Types
Rev. 1.1
21
Si3459
Register Address
Slave Address
Write Data
tSCLA
0
1
A4
A3
A2
A1 A0* R/W#
START
A7
A6
A5
A4
A3
A2
A1
ACK by IC
Fixed IC
Address
A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
ACK by IC
STOP by Master
Write Sequence
Pin-Defined
Address
*A0=0 for 1st Quad or A0=1 for 2nd Quad.
Setup Register Address
Transfer Data to Setup Address
Register Address
Slave Address
Register Data
Slave Address
tSCLA
0
1
A4
A3
A2
START
A1 A0* R/W#
ACK by IC
Fixed IC
Address
Pin-Defined
Address
A7
tSCLA
A6
A5
A4
A3
A2
A1
A0
0
1
A4
A3
A2
ACK by IC
START
*A0=0 for 1st Quad or A0=1 for 2nd Quad.
A1 A0* R/W#
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
Fixed IC
Address
Not ACK by Master
STOP by Master
Pin-Defined
Address
Read Sequence
Figure 11. I2C Read and Write Sequences
8-Bit Read
All registers can be accessed this way, but it is not recommended for reading registers storing parametric
measurement data (Iport and Vport, registers 0x19–0x1c, 0x29–0x2c, 0x39–0x3c, 0x49–0x4c).
Example Sequence
1. START condition, followed by the target slave's 7-bit address, and a write flag. The sequence is ACKed by
the Si3459.
2. Then an 8-bit Si3459 register address is provided followed by an ACK. These steps set up a pointer
register within the Si3459 that points to the address of an internal register to be read.
3. The transaction continues by sending a repeated START condition, followed by the target slave's 7-bit
address, and a read flag. This sequence is ACKed by the Si3459.
4. Then the 8-bit IC register data is provided by the Si3459 (slave). This occurrence is followed by a master
NACK (Not ACK).
5. Then the master frees the bus by sending a STOP condition.
See Figure 11, “I2C Read and Write Sequences,” on page 22 for more details.
8-Bit Write
All registers can be accessed this way (except the read only registers).
Example Sequence
1. START condition, followed by the Si3459 7-bit address, and a write flag. This is ACKed by the IC.
2. Then an 8-bit IC register address is provided followed by an ACK by the Si3459.
3. The transaction is completed by sending 8-bits of register data. This is ACKed by the Si3459.
4. Then the master frees the bus by sending a STOP condition.
See Figure 11, “I2C Read and Write Sequences,” on page 22 for more details.
16-Bit Read
This is the recommended access mode for reading registers storing parametric measurement data (Iport and
Vport, registers 0x19–0x1c, 0x29–0x2c, 0x39–0x3c, 0x49–0x4c). Only these registers can be accessed this way in
this mode.
22
Rev. 1.1
Si3459
The two byte (16-bit) read follows the same protocol described in the 8-bit read paragraph above, with the extra
byte appended to the data field before the STOP condition. In this case, the Master should ACK the first byte, and
NACK the second byte.
Example: Reading 2 Bytes from Offset 0x19 Gives the Current Measurement of Port 1
1. Start condition, followed by the target slave's 7-bit address, and a write flag. The sequence is ACKed by the
Si3459.
2. Then an 8-bit Si3459 register address is provided followed by an ACK. These steps set up a pointer
register within the Si3459 that points to the address of an internal register to be read.
3. The transaction continues by sending a repeated START condition, followed by the target slave's 7-bit
address, and a read flag. This sequence is ACKed by the Si3459.
4. Then the LSB of PORT1 CURRENT MEASUREMENT (8-bit) data is provided by the Si3459 (slave). This
occurrence is followed by a master ACK.
5. Then the MSB of PORT1 CURRENT MEASUREMENT (8-bit) data is provided by the Si3459 (slave). This
occurrence is followed by a master NACK.
6. Then the master frees the bus by sending a STOP condition.
See Figure 11, “I2C Read and Write Sequences,” on page 22 for more details.
Quick Access to the Interrupt Register
Whenever a STOP is detected by the slave, its internal register address pointer is reset. Therefore, the next I2C
Read transaction will return the contents of the Interrupt register (0x00).
The transaction has to be executed on both quads using the A0 address bit to read the Interrupt register of both
quads.
Transfer Data to Setup Address
Slave Address
0
1
A4
A3
A2
Register Data
A1
START
A0* R/W#
D7
D6
D5
D4
D3
ACK by IC
D2
D1
D0
Not ACK by Master
STOP by Master
*A0=0 for 1st Quad or A0=1 for 2nd Quad.
Fixed IC Address Pin-Defined Address
Figure 12. Quick Access Transaction
3.4.1.2. Global Address
Each device on the bus will respond to the global address (100 0000b) in exactly the same way it would to a read
or write transaction using its specific slave address. The global address is primarily used to configure (write) all
slaves the same after the PSE system is powered up. Global read transactions should be avoided.
3.4.1.3. Alert Response Address (ARA)
The ARA is used by the master as a quick way to determine which slaves are asserting (pulling low) the nINT line.
The ARA address is 000 1100b
Each IC (“slave”) implements the following protocol:
Only
slaves that are asserting the nINT line respond when the master uses the ARA in a read cycle. All
slaves that are not asserting nINT ignore read cycles that use the ARA.
Each slave responding to the ARA transmits a byte consisting of its address in the upper 7 bits, and a 1 in
the least significant bit.
Rev. 1.1
23
Si3459
As
each bit in the byte is transmitted, the slave determines whether to continue transmitting the remainder
of the byte or terminate transmission. The slave terminates when it sees a 0 on SDA at a time when it’s
attempting to send a 1; otherwise it continues transmitting bits until the entire byte has been sent.
If a slave completes transmission of the entire byte without terminating, it releases (stops asserting) the
nINT line. Any slave that terminated transmission continues to assert the nINT line.
The result of this protocol is that the slave with the lowest address will complete the transmission and won’t
respond to subsequent ARA read transactions until its event registers have been cleared. Other slaves, with higher
addresses, terminate but will respond to the next ARA read cycle. Therefore, each time the master performs a read
cycle using the ARA it receives the address of a different slave until all slaves have sent their addresses without
terminating.
3.5. DC-to-DC Converter Description
The Si3459 includes a dc-dc converter for generation of an approximately 4.3 V intermediate power rail, which is
further down-regulated to create the 3.3 V VDD power rail necessary for MCU operation and other support.
The dc-dc converter consists of a buck converter with accompanying external components to step down VPWR to
approximately 4.3 V on the enabled “primary” converter. This voltage, called VCAP, can also be bussed to up to
five adjacent “secondary” controllers. Each controller includes a series regulator for generation of 3.3 V for local
use by that controller and an optional digital bus isolator.
The converter is enabled by asserting (tying low) DCEN. In fact, DCEN should be asserted on the primary and all
secondary controllers.
While the primary controller requires several external components to enable the dc-dc (see " DC-DC Converter
Block Diagram" on page 2), the secondary controllers do not require those external components. On the secondary
controllers, the SWO pin should be direct-tied to VPWR.
If DCEN is left floating the dc-dc converter is disabled, which eliminates excess current draw by the VPWR pin. To
disable the dc-dc converter, the related pins (DCENb, CAP, and SWO) should be left floating.
The ISENSE pin implements a cycle-by-cycle current limit by comparing a sensed voltage to an internal reference.
When the external power FET is conducting, if ISENSE drops more than 200 mV below VPWR, the FET will be
shut off immediately to limit excessive currents. An appropriate external resistor should be selected to set the
desired peak current level (i.e., Ipeak = 200 mV/Rsense). If ISENSE is left floating, an internal pull-up will
effectively disable the current limit feature.
In the event of an extreme overcurrent event (e.g., short-circuit), the dc-dc output voltage, CAP, will drop below its
target level of 3.6 V. If CAP falls below 90% of that level (i.e., 3.24 V) a dc-dc fault will be declared and the dc-dc
and LDO will power down. The dc-dc will then attempt to restart in 4 ms intervals until the overcurrent fault is
removed.
24
Rev. 1.1
Si3459
4. Register Map
4.1. Register Set
Table 9 lists the Si3459 registers. The Si3459 appears to software as two “virtual quads” in that there is a complete, independent set of the below registers
associated with each virtual quad. The A0 I2C address bit distinguishes the two virtual quads. A0 is not a hardware pin; it is reported as either 0 or 1
according to which virtual quad is being addressed via the I2C protocol.
Table 9. Si3459 Registers
Register
Addr1
R/W
Port2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset State
Auto Tied to
DGND
Interrupt
0x00
int
RO
Global
Overtemp
fetbad
uvlo3
uvlo48
p_4_ev
p_3_ev
p_2_ev
p_1_ev
0010 0000
0x01
intmask
R/W
Global
Status
ifault
startfault
dis
class
det
pwrgd
pwrena
1000 0000
Global Event Registers
0x02
evn_global
RO
Global
Overtemp
fetbad
uvlo3
uvlo48
tsd
Reserved
Reserved
Reserved
0010 0000
0x03
evn_global_cor
COR
Global
Overtemp
fetbad
uvlo3
uvlo48
tsd
Reserved
Reserved
Reserved
0010 0000
tsd
Reserved
Auto
0000 0000
Global Status Registers
0x05
Status
RO
Global
slave_addr[4:0]
0x06
Temperature
RO
Global
Die Temperature
0000 0000
0x07
VPWR_LSB
RO
Global
Vmain_LSB
0000 0000
0x08
VPWR_MSB
RO
Global
Vmain_MSB
0000 0000
Notes:
1. Register addresses not listed in the table are reserved and should not be written to.
2. The PORT column indicates which ports are associated with each register. For example, “2” means the register is associated with Port 2 only; “Global” refers to
slave-level status and control registers.
Rev. 1.1
25
Si3459
Table 9. Si3459 Registers (Continued)
Register
Addr1
R/W
Port2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset State
Auto Tied to
DGND
Global Configuration Registers
0x0A
config
R/W
Global
intena
detchg
tsddisa
0x0B
pb_global
WO
Global
intclr
pinclr
lowpri
0x0C
devid_sirev
RO
Global
0x0D
firmware
RO
Global
0x0E
manufid_dever
RO
Global
wddis[3:0]
swrst
Reserved
Reserved
Device_ID
rstall
wdstat
1001 0110
offall
0000 0000
Si_Revision
See “4.2.4.3.
Device ID
and Revision Registers (0x0C,
0x0D, 0x0E)”
firmware_rev
Manufacturer_ID
Device_Version
Port 1 Registers
0x10
evnp_1
RO
1
tLIM_1
tCUT_1
tSTART_1
dis_1
cls_1
det_1
pwrgd_1
pwrena_1
0000 0000
0x11
evnp_1_cor
COR
1
tLIM_1
tCUT_1
tSTART_1
dis_1
cls_1
det_1
pwrgd_1
pwrena_1
0000 0000
0x12
statp_1
RO
1
Reserved
class_1[2:0]
Reserved
0x13
pwrstatp_1
RO
1
Reserved
type2flt_1[2:0]
fetbad_1
pongpd_1
0x14
confp_1
R/W
1
legen_1
midsp_1
disena_1
priority_1
classena_1
detena_1
0x15
tlimp_1
R/W
1
Reserved
hpen_1
pongen_1
Reserved
0x16
icutp_1
R/W
1
Reserved
cutrng_1
0x17
pb_p_1
WO
1
Reserved
Reserved
0x19
ip_1_lsb
RO
1
ip_1_lsb[7:0]
0000 0000
0x1A
ip_1_msb
RO
1
ip_1_msb[7:0]
0000 0000
0x1B
vp_1_lsb
RO
1
vp_1_lsb[7:0]
0000 0000
0x1C
vp_1_msb
RO
1
vp_1_msb[7:0]
0000 0000
0x1D
detresp_1
RO
1
p_1_detres[7:0]
0000 0000
detect_1[2:0]
pg_1
0000 0000
pe_1
opmd_1[1:0]
tLIM_1[3:0]
rst_1
cls_1
det_1
0000 0000
0000 0000
Icut_1[5:0]
Reserved
0000 0000
0101 0100
off_1
on_1
0000 0000
Notes:
1. Register addresses not listed in the table are reserved and should not be written to.
2. The PORT column indicates which ports are associated with each register. For example, “2” means the register is associated with Port 2 only; “Global” refers to
slave-level status and control registers.
26
Rev. 1.1
Si3459
Table 9. Si3459 Registers (Continued)
Register
Addr1
R/W
Port2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset State
Auto Tied to
DGND
Port 2 Registers
0x20
evnp_2
RO
2
tLIM_2
tCUT_2
tSTART_2
dis_2
cls_2
det_2
pwrgd_2
pwrena_2
0000 0000
0x21
evnp_2_cor
COR
2
tLIM_2
tCUT_2
tSTART_2
dis_2
cls_2
det_2
pwrgd_2
pwrena_2
0000 0000
0x22
statp_2
RO
2
Reserved
0x23
pwrstatp_2
RO
2
Reserved
Reserved
Reserved
Reserved
fetbad_2
pongpd_2
0x24
confp_2
R/W
2
legen_2
midsp_2
disena_2
priority_2
classena_2
detena_2
0x25
tlimp_2
R/W
2
Reserved
hpen_2
pongen_2
Reserved
0x26
icutp_2
R/W
2
Reserved
cutrng_2
0x27
pb_p_2
WO
2
Reserved
Reserved
0x29
ip_2_lsb
RO
2
ip_2_lsb[7:0]
0000 0000
0x2A
ip_2_msb
RO
2
ip_2_msb[7:0]
0000 0000
0x2B
vp_2_lsb
RO
2
vp_2_lsb[7:0]
0000 0000
0x2C
vp_2_msb
RO
2
vp_2_msb[7:0]
0000 0000
0x2D
detresp_2
RO
2
p_2_detres[7:0]
0000 0000
class_2[_2:0]
Reserved
detect_2[_2:0]
pg_2
0000 0000
pe_2
opmd_2[1:0]
tLIM_2[3:0]
rst_2
cls_2
det_2
0000 0000
0000 0000
Icut_2[5:0]
Reserved
0000 0000
0101 0100
off_2
on_2
0000 0000
Notes:
1. Register addresses not listed in the table are reserved and should not be written to.
2. The PORT column indicates which ports are associated with each register. For example, “2” means the register is associated with Port 2 only; “Global” refers to
slave-level status and control registers.
Rev. 1.1
27
Si3459
Table 9. Si3459 Registers (Continued)
Register
Addr1
R/W
Port2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset State
Auto Tied to
DGND
Port 3 Registers
0x30
evnp_3
RO
3
tLIM_3
tCUT_3
tSTART_3
dis_3
cls_3
det_3
pwrgd_3
pwrena_3
0000 0000
0x31
evnp_3_cor
COR
3
tLIM_3
tCUT_3
tSTART_3
dis_3
cls_3
det_3
pwrgd_3
pwrena_3
0000 0000
0x32
statp_3
RO
3
Reserved
0x33
pwrstatp_3
RO
3
Reserved
Reserved
Reserved
Reserved
fetbad_3
pongpd_3
0x34
confp_3
R/W
3
legen_3
midsp_3
disena_3
priority_3
classena_3
detena_3
0x35
tlimp_3
R/W
3
Reserved
hpen_3
pongen_3
Reserved
0x36
icutp_3
R/W
3
Reserved
cutrng_3
0x37
pb_p_3
WO
3
Reserved
Reserved
0x39
ip_3_lsb
RO
3
ip_3_lsb[7:0]
0000 0000
0x3A
ip_3_msb
RO
3
ip_3_msb[7:0]
0000 0000
0x3B
vp_3_lsb
RO
3
vp_3_lsb[7:0]
0000 0000
0x3C
vp_3_msb
RO
3
vp_3_msb[7:0]
0000 0000
0x3D
detresp_3
RO
3
p_3_detres[7:0]
0000 0000
class_3[2:0]
Reserved
detect_3[2:0]
pg_3
0000 0000
pe_3
opmd_3[1:0]
tLIM_3[3:0]
rst_3
cls_3
det_3
0000 0000
0000 0000
Icut_3[5:0]
Reserved
0000 0000
0101 0100
off_3
on_3
0000 0000
Notes:
1. Register addresses not listed in the table are reserved and should not be written to.
2. The PORT column indicates which ports are associated with each register. For example, “2” means the register is associated with Port 2 only; “Global” refers to
slave-level status and control registers.
28
Rev. 1.1
Si3459
Table 9. Si3459 Registers (Continued)
Register
Addr1
R/W
Port2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reset State
Auto Tied to
DGND
Port 4 Registers
0x40
evnp_4
RO
4
tLIM_4
tCUT_4
tSTART_4
dis_4
cls_4
det_4
pwrgd_4
pwrena_4
0000 0000
0x41
evnp_4_cor
COR
4
tLIM_4
tCUT_4
tSTART_4
dis_4
cls_4
det_4
pwrgd_4
pwrena_4
0000 0000
0x42
statp_4
RO
4
Reserved
0x43
pwrstatp_4
RO
4
Reserved
Reserved
Reserved
Reserved
fetbad_4
pongpd_4
0x44
confp_4
R/W
4
legen_4
midsp_4
disena_4
priority_4
classena_4
detena_4
0x45
tlimp_4
R/W
4
Reserved
hpen_4
pongen_4
Reserved
0x46
icutp_4
R/W
4
Reserved
cutrng_4
0x47
pb_p_4
WO
4
Reserved
Reserved
0x49
ip_4_lsb
RO
4
ip_4_lsb[7:0]
0000 0000
0x4A
ip_4_msb
RO
4
ip_4_msb[7:0]
0000 0000
0x4B
vp_4_lsb
RO
4
vp_4_lsb[7:0]
0000 0000
0x4C
vp_4_msb
RO
4
vp_4_msb[7:0]
0000 0000
0x4D
detresp_4
RO
4
p_4_detres[7:0]
0000 0000
class_4[2:0]
Reserved
detect_4[2:0]
pg_4
0000 0000
pe_4
opmd_4[1:0]
tLIM_4[3:0]
rst_4
cls_4
det_4
0000 0000
0000 0000
Icut_4[5:0]
Reserved
0000 0000
0101 0100
off_4
on_4
0000 0000
Notes:
1. Register addresses not listed in the table are reserved and should not be written to.
2. The PORT column indicates which ports are associated with each register. For example, “2” means the register is associated with Port 2 only; “Global” refers to
slave-level status and control registers.
Rev. 1.1
29
Si3459
4.2. Detailed Register Descriptions
Note that, in the following Register Definition Descriptions, the term “set” means that a bit is a logical 1 (or high)
value, and the term “clear” means that a bit is a logical 0 (or low) value.
4.2.1. Interrupt Registers
These registers either report (0x00) or mask (0x01) interrupts. The Si3459 monitors all interrupt sources and sets
the appropriate bit(s) in the int register (0x00).
The intmask register (0x01) controls the masking of groups of events, enabling or blocking those events from
affecting the state of the INT pin. The intmask register only affects the INT pin behavior.
4.2.1.1. Interrupt Status Register (Address 0x00)
Read only. When set to logic 1 by various interrupt events, bits in this register report the source of a particular
interrupt. Assuming the corresponding bit in the intmask register is set, when bits in this register are asserted, the
INT pin is asserted (pulled to ground). Each bit of the bottom nibble (the 4 least significant bits) in this register is the
logical OR of all bits in the corresponding port’s event register (evnp_x: 0x10, 0x20, 0x30, 0x40) bits. The upper
nibble (the 4 most significant bits) in this register reflects the status of the upper nibble bits of the evn_global
register (0x02). Clearing bits in the int register requires that the corresponding bits in the evn_global register
(0x02) or all bits in the corresponding port event registers be cleared. Alternatively, all bits in the int register can be
cleared by setting bit 7 in the pb_global register (0x0B) to a logical 1 value. The INT pin can be deasserted by
setting bit 6 in the pb_global register (0x0B) to a logical 1 value. Additional detail is found in the register
description below.
Register
Addr
Name
0x00
Int
Bit
Name
7
overtemp
6
5
4
30
fetbad
uvlo3
uvlo48
R/W
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto tied to
DGND
RO
Global
overtemp
fetbad
uvlo3
uvlo48
p_4_ev p_3_ev p_2_ev p_1_ev
Function
Interrupt status bit for over temperature event.
0:
the “overtemp” bit is not set in the evn_global register.
1:
the “overtemp” bit is set in the evn_global register.
Interrupt status bit for external MOSFET failure event.
0:
the “fetbad” bit is not set in the evn_global register.
1:
the “fetbad” bit is set in the evn_global register.
Interrupt status bit for VDD Over Voltage Lock Out failure event.
0:
the “uvlo3” bit is not set in the evn_global register.
1:
the “uvlo3” bit is set in the evn_global register.
Interrupt status bit for VPWR Over Voltage Lock Out failure event.
0:
the “uvlo48” bit is not set in the evn_global register.
1:
the “uvlo48” bit is set in the evn_global register.
Rev. 1.1
0010 0000
Si3459
Register
Addr
Name
0x00
Int
Bit
Name
3
p_4_ev
2
1
0
p_3_ev
p_2_ev
p_1_ev
R/W
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto tied to
DGND
RO
Global
overtemp
fetbad
uvlo3
uvlo48
p_4_ev p_3_ev p_2_ev p_1_ev
0010 0000
Function
Interrupt status bit for Port 4 events.
0:
Port 4 has no active event.
1:
Port 4 has at least one active event.
Interrupt status bit for Port 3 events.
0:
Port 3 has no active event.
1:
Port 3 has at least one active event.
Interrupt status bit for Port 2 events.
0:
Port 2 has no active event.
1:
Port 2 has at least one active event.
Interrupt status bit for Port 1 events.
0:
Port 1 has no active event.
1:
Port 1 has at least one active event.
Rev. 1.1
31
Si3459
4.2.1.2. Interrupt Mask Register (0x01)
Writing a logic 1 to any bit in the intmask register allows the specified event type to propagate to the INT pin.
Writing a logical 0 to any bit of the intmask register stops the specified event type from propagating to the INT pin.
The INT pin can be de-asserted by setting bit 6 in the pb_global register (0x0B) to a logical 1 value. Additional
details can be found in the register description below.
Register
Addr
Name
0x01
intmask
Bit
Name
7
status
6
5
4
3
2
1
0
32
ifault
R/W
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
class
det
pwrgd
pwrena
Reset State
Auto tied
to DGND
R/W
Global
status
ifault
startfault
dis
class
det
pwrgd
pwrena
1000 0000
Function
Interrupt mask bit for overtemp, FETBAD, UVLO3 and UVLO48 global events.
0:
Disables the overtemp, FETBAD, UVLO3 and UVLO48 events in the evn_global register from
propagating to the INT pin.
1:
Enables the overtemp, FETBAD, UVLO3 and UVLO48 events in the evn_global register to propagate to the INT pin.
Interrupt mask bit for Tcut and Tlim events on all ports.
0:
Disables the Tcut and Tlim events from propagating to the INT pin.
1:
Enables the Tcut and Tlim events to propagate to the INT pin.
startfault Interrupt mask bit for Start Fault event on all ports.
dis
Bit 0
0:
Disables the Start Fault event from propagating to the INT pin.
1:
Enables the Start Fault event to propagate to the INT pin.
Interrupt mask bit for disconnect event on all ports.
0:
Disables the disconnect event from propagating to the INT pin.
1:
Enables the disconnect event to propagate to the INT pin.
Interrupt mask bit for classification completed event on all ports.
0:
Disables the classification completed event from propagating to the INT pin.
1:
Enables the classification completed event to propagate to the INT pin.
Interrupt mask bit for detection completed event on all ports.
0:
Disables the detection completed event from propagating to the INT pin.
1:
Enables the detection completed event to propagate to the INT pin.
Interrupt mask bit for the Power Good event on all ports.
0:
Disables the Power Good event from propagating to the INT pin.
1:
Enables the Power Good event to propagate to the INT pin.
Interrupt mask bit for the Power Enabled event on all ports.
0:
Disables the Power Enabled event from propagating to the INT pin.
1:
Enables the Power Enabled event to propagate to the INT pin.
Rev. 1.1
Si3459
4.2.2. Global Event Register and Global Event COR (0x02, 0x03)
Device-related events can be polled using these registers. The content of register 0x03 is identical to that of 0x02,
however, if 0x03 is read, both registers will clear momentarily. The register bits are set again every few milliseconds
if the fault is still present. Additional details can be found in the register description below.
Register
Addr
R/W
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
0x02 evn_global
Bit
Name
7
Overtemp
Reset State
Auto tied to
DGND
RO
Global overtemp fetbad uvlo3 uvlo48
tsd
Reserved Reserved Reserved
0010 0000
Function
Over temperature event bit.
When the part's die temperature is above the over-temperature threshold (135 °C) the “overtemp” bit is set
until register 0x03 is read. All ports are powered down as described in paragraph 3.2.2.4, point 1, if the shutdown on over-temperature feature is not disabled with the “tsddisa” bit (Bit 5 is zero in the config register).
6
fetbad
0:
The part's die temperature is under the over-temperature threshold (135 °C).
1:
The part's die temperature is above the over-temperature threshold (135 °C).
External MOSFET failure event bit.
When there is a leaky FET on any port then the “fetbad” (bit 6) will be set. It will remain set until specifically
cleared by reading the corresponding COR register (0x03). The leaky FET test is performed at the start of a
detection cycle. Note that the “fetbad_x” bit in the individual port’s powerstatp_x registers are updated at the
beginning of each detection cycle. See the “Bad FET Measurement” parameter in Table 1 for test limits.
5
uvlo3
0:
The detection process found the external MOSFET operating correctly.
1:
The detection process found the external MOSFET is damaged.
VDD Over Voltage Lock Out failure event bit
Indicates a VDD supply fault event. This event bit remain latched until cleared by reading the COR register
(0x03), and only “good” to “bad” transitions are reported.
Notes:
1. Measured values, such as temperature, port voltages, and currents are inaccurate if VDD<2.6 V.
2. Until VDD exceeds 2.8 V, all ports are powered down as described in paragraph 3.2.2.4, point 2.
Writing to the confp_x, tlimp_x, icutp_x and pb_p_x registers is prohibited.
4
uvlo48
0:
VDD > 2.8 V (Typ).
1:
VDD < 2.8 V (Typ).
VPWR Over Voltage Lock Out failure event bit.
Indicates a VPWR supply fault event. This event bit remain latched until cleared by reading the
COR register (0x03), and only “good” to “bad” transitions are reported. This event has hysteresis
between 32 V and 44 V.
Note: Until VPWR exceeds 44V, all ports are powered down as described in paragraph 3.2.2.4, point 2.
Writing to the confp_x, tlimp_x, icutp_x and pb_p_x registers is prohibited.
0:
VPWR > 44 V (TYP).
1:
VPWR < 32 V (TYP) if VPWR is decreasing; VPWR < 44V if VPWR is increasing.
Rev. 1.1
33
Si3459
3
tsd
Thermal shutdown event bit.
Set to a logical 1 value when all powered ports have been shut down due to an over-temperature
condition. This event bit remains latched until cleared by reading the COR register (0x03).
2:0
34
0:
The part’s die temperature is under the over-temperature threshold if the shutdown on over-temperature is enabled; otherwise, it is under the safe-temperature threshold.
1:
All powered ports have been shut down due to the fact that the part’s die temperature is above the
over-temperature or the safe-temperature threshold.
Reserved
Rev. 1.1
Si3459
4.2.3. Global Status Registers
These registers provide status information (I2C address, Die Temperature, VPWR Voltage) valid for the full device.
4.2.3.1. Status (0x05)
This register provides information about global (all four ports) status. Additional details can be found in the register
description below.
Register
Addr
Name
0x05
Status
Bit
Name
7
Reserved
6:2
slave_addr[4:0]
R/W
Port
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto Tied to
DGND
RO
Global Reserved
slave_addr[4:0]
Reserved
auto
0000 0000
Function
I2C slave address.
This field is comprised of the state of the 4 address selection pins A[4:1] concatenated with the
I2C-programmed quad address A0, where bit6 = A4...bit2 = A0. (sampled once after reset).
1
Reserved
0
auto
Initial status of the AUTO pin (sampled once after reset).
4.2.3.2. Temperature (0x06)
This register provides information about the die temperature. The actual temperature can be calculated using the
following equation:
T = –20 + N x 0.652 °C, where N is the binary value contained in this register.
The resulting temperature is in the range of –20 to 146.3 °C
4.2.3.3. VPWR Voltage (0x07, 0x08)
VPWR voltage can be accessed via registers 0x07 and 0x08. The voltage measurement are 16-bit words, divided
into two bytes: the Most Significant Byte (MSB, register 0x08) contains the upper 8 bits; and the Least Significant
Byte (LSB, register 0x07) contains the lower 8 bits. Reading the lower byte latches the upper byte until it is read, to
assure they are both from the same sample; therefore, the lower byte should always be read first. After
concatenating the upper and lower bytes, multiply by 5.835 mV/count to obtain the VPWR voltage.
Rev. 1.1
35
Si3459
4.2.4. Global Configuration Registers
The device related configuration is related to all ports and can be set using these registers.
4.2.4.1. config (0x0A)
Additional details can be found in the register description below.
Register
Addr
Name
0x0A
config
Bit
Name
7
intena
6
5
4:1
detchg
tsddisa
wddis[3:0]
R/W
Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto Tied to
DGND
R/W
Global intena detchg
tsddisa
wddis[3:0]
wdstat
1001 0110
Function
Enable or disable the interrupt pin.
0:
The INT pin is asserted when there is an interrupt event which is not masked by the intmask
register.
1:
The INT pin is not active and remains unasserted (logic level 1).
Detect event reporting control bit
0:
The detection complete event bits , as reported by “det_x” (bit 2) of the evnp_x (0x10, 0x20,
0x30, 0x40) registers, are set every time a detection cycle concludes.
1:
The detection complete event bits are only set if there is a change in the result from the last
detection.
Disable shutdown on over-temperature event
0:
The powered ports will be shut down when the part's die temperature is above the
over-temperature threshold (135 °C).
1:
The powered ports will be shut down when the part's die temperature is above the
safe-temperature threshold (146 °C).
Watchdog timer control
The watchdog timer monitors the SCL pin and is reset by transitions on either edge. If the timer is not
reset for approximately 2.5 seconds, all ports will be powered off, and the WD status bit will be set. The
WD status bit (‘wdstat’; bit 0) can only be cleared by writing a zero to this bit or by a RESET. The Watchdog timer is disabled by writing a 1011b to the WD disable field. The POR reset value of WD disable is
1011b (disabled). The WD timer can be enabled by writing any (non-1011b) value to this field; for example, writing 0000b will enable the WD timer.
0
36
wdstat
Watchdog status bit.
0:
The watchdog timer is either not running (disabled) or has not timed out.
1:
The watchdog timer has timed out.
Rev. 1.1
Si3459
4.2.4.2. Global PushButton Register (0x0B)
This is a write only register.
Additional details can be found in the register description below.
Register
Addr
R/W
Bit
Name
7
intclr
WO
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0 Reset State
pinclr
lowpri
swrst
Reserved
2
Reserved
1
rstall
All bits in the int register will be cleared.
De-assert the INT pin.
Setting Bit 6 to a logical 1 value does not clear any interrupt sources.
Turn off the low priority ports
Turn off any already-powered low priority ports (as identified by the per-port confp_x
register “priority” bits).
Software reset
Resets the address bit A0-selected Quad of the Si3459 completely. All ports and registers are reset to their default state.
The config register is not reset; this register controls shared resources (INT pin, watchdog timer) between the Quads.
The MCU is not reset (setting the ‘swrst’ bit is not equivalent to a HW reset caused by
the RESET/ pin).
Single bit control to reset all ports within the address bit A0-selected Quad.
1:
offall
0000 0000
Clear INT pin
1:
3
Global intclr pinclr lowpri swrst Reserved Reserved rstall offall
Clear interrupt status.
1:
0
Bit 5
Function
1:
4
Bit 6
Auto Tied to
DGND
1:
5
Bit 7
Name
0x0B pb_global
6
Port
The ports are reset to the shutdown state as it is described in section 3.2.2.3, point 2.
Single bit control to turn off all ports within the address bit A0-selected Quad.
1:
The ports are turned off as it is described in section 3.2.2.3, point 1.
4.2.4.3. Device ID and Revision Registers (0x0C, 0x0D, 0x0E)
These Registers are Read only.
Register 0x0C is the device identification and silicon revision register. The “Device_ID” bitfield is 0010b for Si3459
devices. The “Si_Revision” bitfield indicates the silicon revision number and contains 0000b.
Register 0x0D is the firmware revision register. Firmware revision is coded as two bytes with only decimal
characters. As an example: Revision 0.3 would be coded as 0x03. See “6. Ordering Guide” for the current
Firmware Revision number.
Register 0x0E is the Manufacturer ID and Device Version register. The Manufacturer ID for Silicon Labs is 0100b.
The Device Version is 0001b.
Rev. 1.1
37
Si3459
4.2.5. Port-Specific Registers
Per-port events, status information, and configuration settings are grouped together in the register set. Each port
has its own register group with exactly the same content.
4.2.5.1. Event Register (evnp_x; 0x10, 0x20, 0x30, 0x40)
This Register is Read only, and each bit has relevance only when it is set.
If any bit is set in this register, then the corresponding p_x_ev bit in the int register (0x00) is also set.
The INT pin will also be asserted if the corresponding mask bit in the intmask register (0x01) is set. For example,
if the “pwrgd” mask bit in the intmask register is set, then when the “pwrgd_x” bit (Bit 1 of evnp_x) becomes one,
the INT pin will be asserted.
Exception: bit 6 and bit 7 of this register have common mask bit 6 (called “ifault”) in the intmask register (0x01), so
the INT pin will be asserted if the ifault mask bit is set in the intmask register and any of the tcut_x or the tlim_x
bits becomes one.
When a bit in this register is set, it latches, and only clears when the corresponding evnp_x_cor (Clear-on-Read)
register is read at the following addresses: 0x11, 0x21, 0x31, 0x41.
Additional details can be found in the register description below.
Register
Addr
Name
0x10,
0x20,
0x30,
0x40
evnp_x
Bit
Name
7
tLIM_x
R/W
tCUT_x
RO
tSTART_x
dis_x
cls_x
det_x
Bit 2
Bit 1
Bit 0
Reset State
1,
2,
3,
4
tLIM_x
tCUT_x
tSTART_x
dis_x
cls_x
det_x
pwrgd_x
pwrena_x
0000 0000
ILIM fault (alternatively called a current limit timeout, with symbol tLIM) has occurred on the port.
ICUT fault (alternatively called a cutoff current timeout, with symbol tCUT) has occurred on the port.
The port is shut down at the end of the tSTART interval due to an overload, which is in turn indicated
by Pgood not being true at the end of tSTART.
Disconnect event bit
The (already turned ON) port has been disconnected due to missing an MPS (Maintain Power Signature) test.
Classification complete event bit
One Classification cycle for the corresponding port has completed.
Note: In Semi-auto mode, when this bit read as logical one, this indicates that the Class Status bitfield in the Port Status registers (statp_x) are valid.
Detection complete event bit
1:
38
Bit 3
tSTART fault event bit
1:
2
Bit 4
tCUT fault event bit
1:
3
Bit 5
ILIM fault event bit
1:
4
Bit 6
Function
1:
5
Bit 7
Auto Tied to
DGND
1:
6
Port
One Detection cycle for the corresponding port has completed.
Note: In Semi-auto mode, when this bit read as logical one, this indicates that the Detect Status bitfield in the Port Status registers (statp_x) are valid.
Rev. 1.1
Si3459
Register
Addr
Name
0x10,
0x20,
0x30,
0x40
evnp_x
Bit
Name
1
pwrgd_x
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto Tied to
DGND
RO
1,
2,
3,
4
tCUT_x
tLIM_x
tSTART_x
dis_x
cls_x
det_x
pwrgd_x
pwrena_x
0000 0000
Function
Power Good event bit.
1:
0
Port
The port's Power Good status bit (Bit 1 in the powerstatp_x register) has changed.
pwrena_x Power Enabled event bit.
1:
The port's Power Enable status bit (Bit 0 in the powerstatp_x register) has changed.
4.2.5.2. Status Register (statp_x; 0x12, 0x22, 0x32, 0x42)
This Register is Read only.
Detection and classification status are reported in this register. The encoding is listed in Table 9.
The “detect_x[2:0]” bit field shows the detection status and similarly the “class_x[2:0]” bit field shows the
classification status.
Table 10. Classification and Detection Encoding
Code
Class Status
Detection Status
000b
Unknown—POR value and also value after a
port is disconnected.
Unknown—POR value and also value after a
port is disconnected.
001b
Class 1
Short circuit
010b
Class 2
Capacitive1
011b
Class 3
Rlow
100b
Class 4
Rgood
101b
Reserved
Rhigh
110b
Class 0
Open circuit
111b
Over current
PSE to PSE2
Notes:
1. Capacitive status is reported when the load capacitance is bigger than 0.5 µF (Cpd > 0.5 µF).
2. The Si3459 is capable of detecting whether it is cross-connected to another PSE controller of a different type. In this
case, the PSE to PSE Status is reported. Detection of another PSE is based on verifying the voltage level on the output
(DRAINn pin) during the detection cycle.
In Semi-Auto and Auto modes, the classification process is not initiated unless Rgood is reported. In this case, the
classification status can be unknown, or it can be the last classification status after the last Rgood.
Rev. 1.1
39
Si3459
4.2.5.3. Power Status Register (pwrstatp_x; 0x13, 0x23, 0x33, 0x43)
This Register is Read only.
Additional details can be found in the register description below.
Register
Addr
Name
0x13,
0x23,
0x33,
0x43
pwrstatp_x
Bit
Name
7
Reserved
6:4
3
2
1
0
R/W
Port
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 0
Reset State
Auto Tied to
DGND
RO
1,
2,
3,
4
Reserved
type2flt_x[2:0]
fetbad_x
pongpd_x
pg_x
pe_x
0000 0000
Function
type2flt_x[2:0] Detection and classification extended status (see the table below for the encoding).
fetbad_x
pongpd_x
pg_x
pe_x
External MOSFET failure event bit.
0:
The detection process found the external MOSFET operating correctly.
1:
The detection process found the external MOSFET is possibly damaged.
Type 2 classification status.
0:
Either not Type 2 PD, or the 2-event classification was not successful.
1:
2-event classification has occurred.
Power Good status.
0:
The voltage on the DRAINx pin is >2 V of AGND; due to an overload or if the port is turned off
for any reason.
1:
The voltage on the DRAINx pin is within ~2 V of AGND, i.e.: the port voltage is almost equal to
VPWR (within 2 V).
Power Enable status.
0:
The port is turned off for any reason (overload, disconnect, or pushbutton).
1:
The port is powered.
Further details for type2flt_x bitfield encoding are described in Table 11.
Table 11. type2flt_x Bitfield Encoding
Code
40
Bit 1
Det/Cls Status
000
unknown
001
Detect and 2-event classification was successful
010
Invalid detection
011
Classification overcurrent
100
2-event classification current mismatch
Rev. 1.1
Si3459
4.2.5.4. Configuration Register (confp_x; 0x14, 0x24, 0x34, 0x44)
This register controls the Port configuration including its operation mode.
Additional details can be found in the register description below.
Register
Addr
Name
0x14,
0x24,
0x34,
0x44
confp_x
Bit
Name
7
legen_x
6
midsp_x
R/W Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto Tied to
DGND
R/W
1,
2,
3,
4
legen_x
midsp_x
disena_x
priority_x
classena_x
detena_x
opmd_x[1:0]
0000 0000
Function
Legacy PD detection enable
0:
Only IEEE standard 802.3at-compliant PD signatures are recognized during detection
1:
The detection status of a PD with large common-mode capacitance is reported as valid (code 100b in the statp_x register). Note that this behavior does not comply with the IEEE standard while this bit is set because the
IEEE standard specifically declares these legacy PDs to be invalid.
midspan functionality support enable
Controls the lenght of the delay after each detection cycle before initiating the next detection cycle
5
4
disena_x
priority_x
0:
back off delay = ~400ms
1:
back off delay > 2s
DC disconnect enable
0:
no active monitoring for the disconnection of a PD
1:
active monitoring for the disconnection of a PD
Port shutdown priority when the SHDN pin is asserted
If there is a minimum 5 μs low pulse on pin 36 (SHDN), then any port with the priority bit set to 1 (low priority) will be
shut down if it is ON (previously OFF ports are unaffected).
This action is equivalent to a pushbutton power off as it is described in paragraph 3.2.2.3, point 1
A high priority port or a port that is not turned on is unaffected by SHDN. Port turn off is enforced for any port with the
priority bit set to 1 (low priority) as long as SHDN is asserted.
When SHDN is de-asserted, port configuration remains intact; however, detect and classify control bits were cleared
during the SHDN assertion, and thus must be re-enabled.
0:
The port's priority is High
1:
The port's priority is Low
Rev. 1.1
41
Si3459
Register
Addr
Name
0x14,
0x24,
0x34,
0x44
confp_x
Bit
Name
3
classena_x
R/W Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Auto Tied to
DGND
R/W
1,
2,
3,
4
legen_x
midsp_x
disena_x
priority_x
classena_x
detena_x
opmd_x[1:0]
0000 0000
Function
Classification enable
This bit has effect only in the Auto and semi-Auto modes. It enables repeated classification, to be performed on the
port. If the port is turned on, then classification will not be attempted. If this bit is set, the port automatically performs
and repeats the classification cycle following the successful detection cycles. In Auto-mode, the port will turn on after a
successful detection if classification is not enabled.
Each time a classification cycle is completed, the result is indicated in the status register (statp_x; addresses 0x12,
0x22, 0x32, 0x42 for ports 1–4, respectively).
Each classification cycle consists either one or two pulses, depending on the state of the corresponding “pongen_x” bit
(tlimp_x; registers 0x15, 0x25, 0x35 and 0x45 for ports 1–4, respectively) at the time the classification cycle is initiated:
• If pongen=1 the classification cycle consists of one or two pulses in accordance with the IEEE 802.3at requirements
for a Type 2 PSE; the second pulse occurs if the PD presented a class 4 signature during the first pulse.
• If pongen=0 the classification cycle consists of one pulse in accordance with the IEEE 802.3at requirements for a
Type 1 PSE. Note: a Type 1 PSE is equivalent to a PSE built to the original IEEE 802.3af spec.
When a port is in Auto mode the ICUT and ILIM are set automatically after the port successfully powers up. The levels
for ICUT and ILIM depend on the class of the PD as shown in Table 11.
This bit will also be set if the Classification pushbutton bit is set.
2
detena_x
0:
Continuous classification is disabled
1:
Continuous classification is enabled
Detection enable
This bit has effect only in the Auto and semi-Auto modes. It enables repeated detection, to be performed on the port. If
the port is turned on, then detection will not be attempted. If this bit is set, the port automatically performs and repeats
the detection cycle. In Auto-mode, the port will turn on after a successful detection, even if classification is not enabled.
Each time a detection cycle is completed, the result is indicated in the status register (statp_x; addresses 0x12, 0x22,
0x32, 0x42 for ports 1–4, respectively). This bit will also be set if the detection pushbutton bit is set.
1:0
0:
Continuous detection is disabled
1:
Continuous detection is enabled
opmd_x[1:0] Port operation mode configuration
This bitfield sets the operation mode of the port. Any time a port is set to Shutdown or Manual mode, the detect and
classification enable bits in this register are reset. In shutdown mode, the pushbuttons will not result in an action. Putting a port in Shutdown mode clears the port status registers.
42
00:
Shutdown
01:
Manual
10:
Semi-Auto
11:
Auto
Rev. 1.1
Si3459
4.2.5.5. Current Limit Register (tlimp_x; 0x15, 0x25, 0x35, 0x45)
Additional details can be found in the register description below.
Register
Addr
Name
0x15,
0x25,
0x35,
0x45
tlimp_x
Bit
Name
7
Reserved
6
hpen_x
R/W Port
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
Reset State
Auto Tied to
DGND
R/W
1,
2,
3,
4
Reserved
hpen_x
pongen_x Reserved tLIM_x[3:0]
0000 0000
Function
High Power Enable
This bit controls the current limit and foldback setting for the port
5
4
3:0
0:
The ILIM threshold is 425 mA ± 5%.
1:
The ILIM threshold is 850 mA ± 5%.
pongen_x 2-event calssification enable.
0:
The classification cycle consists of one pulse in accordance with the IEEE 802.3at requirements for a
Type 1 PSE.
1:
The classification cycle consists of one or two pulses in accordance with the IEEE 802.3at requirements for a Type 2 PSE; the second pulse occurs if the PD presented a class 4 signature during the
first pulse.
Reserved
tLIM_x[3:0] Current limit time
The Tlim Timer duration is 1.71 ms (typ) times the value of ‘tLIM_x[3:0]’ bitfield, rounded to the nearest msec.
Possible returned values in this register are: 0, 2, 3, 5, 7, 9, 10, 12, 14, 15, 17, 19, 21, 22, 24 26. When this
field is written to 0, the Tlim timer is disabled, and the Tcut timer limits the duration of overloads to 60 ms.
4.2.5.6. Cutoff Current Register (icutp_x; 0x16, 0x26, 0x36, 0x46)
This register controls the cutoff current threshold (ICUT) on the port.
Bit 6 “cutrng_x” controls the cutoff current scaling.
Bits 5:0 (“tcut_x[5:0]”) set the ICUT. The conversion scale is: 37.5 mA/count when cutrng = 0; 18.75 mA/count when
cutrng = 1.
Rev. 1.1
43
Si3459
4.2.5.7. Pushbutton Register (pb_p_x; 0x17, 0x27, 0x37, 0x47)
This Register is Write only.
Additional details can be found in the register description below.
Register
Addr
Name
0x17,
0x27,
0x37,
0x47
pb_p_x
Bit
Name
7
Reserved
6
Reserved
5
Reserved
4
rst_x
R/W
cls_x
WO
det_x
off_x
on_x
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
1,
2,
3,
4
Reserved
Reserved
Reserved
rst_x
cls_x
det_x
off_x
on_x
0000 0000
Resets the port to the shutdown state, and all associated events and configurations are cleared.
Please refer to Step 2 in “3.2.2.3. HOST controlled port turn OFF” for further details
Turn on classification
Provide a single classification cycle in manual mode. If it is used in semi-auto mode, then the
“classena_x” bit of the confp_x register will automatically be set (i.e. this action will turn on
repeated classification for the port).
Turn on detection
Provide a single detection cycle in manual mode. If it is used in semi-auto mode, then the
“detena_x” bit of the confp_x register will automatically be set (i.e. this action will turn on repeated
detection for the port).
Turn off the port
1:
0
Bit 5
Reset the port
1:
1
Bit 6
Function
1:
2
Bit 7
Auto Tied to
DGND
1:
3
Port
Please refer to Step 1 in “3.2.2.3. HOST controlled port turn OFF” for further details
Turn on the port
1:
Please refer to “3.2.2.1. HOST Controlled Port Turn ON” for further details
4.2.6. Port-Specific Parametric Measurements Registers
These registers provide real time port voltage, current and detection resistance measurements.
4.2.6.1. Port Current and Voltage (0x19-0x1C, 0x29-0x2C, 0x39-0x3C, 0x49-0x4C)
Once a channel is powered on, port voltage and port current can be accessed via registers 0x19 through 0x1C
(using port 1 as an example). These registers do not give valid information for a port that is off. Each measurement
of voltage is the average of 16 consecutive 10-bit samples taken at 3 ms intervals. Port current is updated once per
100 ms, and the update is the average of all (up to 400) samples taken in the prior 100 ms interval.
The voltage and current measurements are 16-bit words, divided into two bytes: the Most Significant Byte (MSB)
contains the upper 8 bits; and the Least Significant Byte (LSB) contains the lower 8 bits. Reading the lower byte
latches the upper byte to assure they are both from the same sample; therefore, the lower byte should always be
read first. After concatenating the upper and lower bytes, the following conversion factors are used to derive the
meaning of the readings: for current measurements multiply by 122.07 μA/count; and, for voltage measurements,
multiply by 5.835 mV/count.
44
Rev. 1.1
Si3459
4.2.6.2. Port Detection Resistance (detresp_x; 0x1D, 0x2D, 0x3D, 0x4D)
This register contains an approximate resistance value (in kOhm), measured during the rising voltage period of the
detection cycle.
4.2.6.3. VPWR Voltage (0x07, 0x08)
VPWR voltage can be accessed via registers 0x07 and 0x08. The voltage measurement are 16-bit words, divided
into two bytes: the Most Significant Byte (MSB, register 0x08) contains the upper 8 bits; and the Least Significant
Byte (LSB, register 0x07) contains the lower 8 bits. Reading the lower byte latches the upper byte until it is read, to
assure they are both from the same sample; therefore, the lower byte should always be read first. After
concatenating the upper and lower bytes multiply by 5.835 mV/count to obtain the VPWR voltage.
4.2.6.4. Supply Event and Supply Event CoR (0x0A, 0x0B)
When there is a leaky FET on any port, bit6 will be set. It will remain set until specifically cleared with a CoR. The
leaky FET test is performed at the start of a detection cycle. See the “Bad FET Measurement” parameter in Table 1
for test limits.
The event register, 0x0A, indicates a VDD or VPWR supply fault or over-temperature event. The supply event's bits
are latched until cleared, but only “good” to “bad” transitions are reported.
VDD UVLO: set if VDD goes below 2.8 V (TYP). All ports are powered down when this event occurs.
Note: Measured values, such as temperature, port voltages, and currents, are inaccurate if VDD<2.6 V.
In the event of thermal shutdown, the Overtemp bit is set until CoR occurs. Content of register 0x0B is identical to
that of 0x0A, however, if 0x0B is read, both registers will clear momentarily. The register bits are set again every
few milliseconds if the fault is still present.
Rev. 1.1
45
Si3459
GATE1
43 VDD
44 RESET
45 INT
46 DGND
47 AUTO
48 A1
49 A2
50 A3
51 A4
52 NC
53 SCL
54 SDAI
55 SDAO
56 SHDN
5. Pin Descriptions
1
42
GATE8
SENSE1
2
41
SENSE8
DRAIN1
3
40
DRAIN8
KSENSA
4
39
KSENSD
DRAIN2
5
38
DRAIN7
SENSE2
6
37
SENSE7
GATE2
7
36
GATE7
AGND
DGND
28
NC
26
27
DCEN
ISENSE
25
GATE5
CAP
29
24
14
23
GATE4
NC
SENSE5
SWO
30
22
13
VDDA
SENSE4
20
DRAIN5
21
KSENSC
31
NC
32
12
AGND
11
DRAIN4
19
KSENSB
18
DRAIN6
NC
33
NC
10
17
DRAIN3
VPWR
SENSE6
16
GATE6
34
15
35
9
NC
8
NC
GATE3
SENSE3
Table 12. Pin Descriptions
Pin #
Name
1
7
8
14
29
35
36
42
GATE1
GATE2
GATE3
GATE4
GATE5
GATE6
GATE7
GATE8
2
6
9
13
30
34
37
41
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
SENSE8
46
Type
Description
Analog output
Gate drive outputs to external MOSFETs. Connect the GATEn outputs to the external MOSFET gate node gate. A 50 µA pull-up
source is used to turn on the external MOSFET. When a current
limit is detected, the GATEn voltage is reduced to maintain constant current through the external MOSFET. If the fault timer limit is
reached, GATEn pulls down, shutting off the external MOSFET.
GATEn will clamp to 11.5 V (typical) above AGND. If the port is
unused, leave the GATEn pin disconnected or tie to AGND.
Analog input
Current sense inputs for external MOSFETs. The SENSEn pin
measures current through an external 0.25  resistor tied between
the AGND supply rail and the SENSEn input. If the ICUT limit (the
overcurrent limit) is exceeded, the current limit fault timer is incremented. If the voltage across the sense resistor subsequently triggers (the overcurrent limit), the voltage driven onto the GATEn pin
is modulated to provide constant current through the external
MOSFET. Tie the SENSEn pin to AGND when the port is not used.
To accommodate 802.3at (PoE Plus) classification, both the ICUT
and Ilim values can be scaled.
Rev. 1.1
Si3459
Table 12. Pin Descriptions (Continued)
Pin #
Name
Type
Description
3
5
10
12
31
33
38
40
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
DRAIN8
Analog input with
25 µA pull-up to
VPWR
4
KSENSA
Input
Kelvin points for accurate measurement of voltage across 0.25 
sense resistor for ports 1 and 2.
11
KSENSB
Input
Kelvin points for accurate measurement of voltage across 0.25 
sense resistor for ports 3 and 4.
15
16
18
19
20
23
27
28
52
NC
No Connect
17
VPWR
Analog power
Positive PoE voltage (+44 to +56 V) relative to AGND.
21,
ePAD
AGND
Analog ground
Ground connection for VPWR supply. DGND and AGND are tied
together inside the Si3459 package
MOSFET drain output voltage sense. The Power Good bit is set on
each port when the voltage between DRAINn and AGND drops
below 2 V (typical). DRAINn pins should be left floating if the port is
unused.
No connections or nets allowed. Leave floating.
24
SWO
Output
Gate driver output for the external MOSFET component of the dcdc converter. If using only the local regulator of the part, tie SWO to
VPWR. If not using the dc-dc converter or local regulator, leave this
pin floating.
25
CAP
Input
Input from the dc-dc converter. This elevated voltage can be
bussed to up to five additional Si3459’s, where it will be down-regulated to VDD for local use.
Tie DCEN to DGND to enable the dc-dc converter and local regulaDigital input with
tor. If using only the local regulator of the part, DCEN must also be
25 µA pull-up to VDD tied to DGND. If not using the dc-dc converter or local regulator,
leave this pin floating.
26
DCEN
27
ISENSE
Input
Current sense input for dc-dc converter to detect overcurrent and
short circuit conditions.
32
KSENSC
Input
Kelvin points for accurate measurement of voltage across 0.25 
sense resistor for ports 5 and 6.
Rev. 1.1
47
Si3459
Table 12. Pin Descriptions (Continued)
Pin #
Name
Type
39
KSENSD
Input
Kelvin points for accurate measurement of voltage across 0.25 
sense resistor for ports 7 and 8.
43
VDD
Digital power
3.3 V digital supply (relative to DGND). Bypass VDD with a 0.1 µF
capacitor to DGND as close as possible to the Si3459 power supply pins; tied with VDDA.
44
45
RESET
INT
Description
Active low device reset input. Generally, RESET is used at initial
power up. If RESET is asserted (pulled to DGND), the MCU is disabled, all internal registers of the device are set to their default
Digital input with
(power-up) state, and all output ports are shut off. Valid RESET tim25 µA pull-up to VDD
ing pulses must be >10 µs.
If RESET is not used, RESET should either be tied directly to VDD
or through a 10 k resistor to VDD.
Digital output
(open drain)
Interrupt output. This open drain output pin is asserted low (to
DGND) if a fault condition occurs on any of the four ports. The state
of INT is updated for use by the host controller between valid I2C
commands.
Note: When the chip is in Auto mode, this pin should be left unconnected.
46,
ePAD
DGND
47
AUTO
48
49
50
51
A1
A2
A3
A4
53
SCL
54
SDAI
55
SDAO
56
SHDN
Digital ground
Ground connection for 3.3 V digital supply (VDD). DGND and
AGND are tied together inside the Si3459 package.
Tie to DGND for Manual or Semi-Auto Mode, or leave floating or
Analog input with
tied to VDD for default Auto Mode. This pin can also be resistor
25 µA pull-up to VDD
programmed for other startup configurations.
I2C address input. Used to set the base I2C address for the Si3459
in the following (binary) format: 01[A4][A3][A2][A1]A0. Note that A0
is not a physical pin, but rather the address for a “virtual quad” in
Digital input with
the I2C addressing scheme. The two MSB bits of the address are
25 µA pull-up to VDD set to 01. Address values are latched after the deassertion of
RESETB or when VDD ramps and VPWR exceeds the UVLO
threshold voltage. Each address pin should be floating (internal
pull-up pulls high) or tied to either VDD or DGND.
Digital input
Serial clock input. Should be tied directly to the SCL (clock) connection on the I2C bus.
Digital input with
Serial data input. Tie SDAO and SDAI together if a two-wire version
25 µA pull-up to VDD of the I2C bus is available.
Digital output
(open drain)
Serial data output. This open drain output pin is intended to drive
data isolators directly. Tie SDAO and SDAI together if a 2-wire version of the I2C bus is available.
This signal, when driven low, will initiate a shutdown of low-priority
Digital input with
ports.
25 µA pull-up to VDD
Note: When the chip is in Auto mode, this pin should be left unconnected.
48
Rev. 1.1
Si3459
6. Ordering Guide
Ordering Part
Number*
Product
Revision
Firmware
Revision
Firmware
Revision Notes
Si3459-B02-IM
B
3.9
See "10. Firmware
Revision Release
Notes" on page 55.
Package
56-pin QFN
RoHS-compliant
Temperature
Range (Ambient)
–40 to 85 °C
*Note: Add an “R” to the end of the part number for tape and reel option (e.g., Si3459-B02-IM or Si3459-B02-IMR).
Rev. 1.1
49
Si3459
7. Package Outline
Figure 13 illustrates the package details for the Si3459. Table 13 lists the values for the dimensions shown in the
illustration. The Si3459 is packaged in an industry-standard, RoHS-compliant, 56-pin QFN package. The lead
plating material is matte tin.
Figure 13. Package Drawing
50
Rev. 1.1
Si3459
Table 13. Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
8.00 BSC.
5.55
5.70
e
0.50 BSC.
E
8.00 BSC.
5.85
E2
5.55
5.70
5.85
L
0.30
0.40
0.50
m
0.63
0.68
0.73
n
0.21
0.26
0.31
R
0.26 REF
aaa
—
—
0.15
bbb
—
—
0.15
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
51
Si3459
8. Recommended Land Pattern
Figure 14 illustrates the land pattern details for the Si3459. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 14. Si3459 Recommended Land Pattern
52
Rev. 1.1
Si3459
Table 14. PCB Land Pattern Dimensions
Symbol
mm
C1
7.90
C2
7.90
E
0.50
X1
0.30
Y1
0.85
X2
5.85
Y2
5.85
Notes:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.4 mm square openings on 2.0 mm pitch should be used for the center
ground pad to achieve a target of ~50% solder coverage.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.1
53
Si3459
9. Top Marking
9.1. Si3459 Top Marking (QFN)
9.2. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle = 0.75 mm Diameter
(Bottom-Left-Justified)
Line 1 Mark Format:
Device Part Number
Si3459
Line 2 Mark Format:
Device Rev / Type
B02-IM
Line 3 Mark Format:
YY = Year
WW = Work Week
Year and Work Week of Assembly
Manufacturing Code
TTTTTT = Mfg Code
Line 4 Mark Format:
54
Circle = 1.3 mm Diameter
“e3” Pb-Free Symbol
Country of Origin
TW = Taiwan
Rev. 1.1
Si3459
10. Firmware Revision Release Notes
Initial
release
Register set redefinition
Register definition descriptions updates
Rev. 1.1
55
Si3459
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
 This document revision addresses register set
redefinition and register definition description updates.
Revision 0.2 to Revision 1.0

Updated Table 1 on page 4.
Updated
Sense Voltage at Current Limit specs.

Updated Figure 9 on page 16.
 Updated "3.2. Operating Modes" on page 19 to
clarify AUTO mode operation.
 Added “3.4.1.2. Global Address” and "3.4.1.3. Alert
Response Address (ARA) " on page 23.
Revision 1.0 to Revision 1.1
 Updated Table 1 on page 4 to reduce minimum
voltage on “Voltage Difference Between any GATEn and
AGND Pin” and to increase maximum current on Bad
FET Measurement IPORTn parameters.
 Updated Table 2 on page 7 to expand Regulator
Output Voltage Mix and Max slightly.
 Updated Table 3 on page 9 to increase Input
Leakage IIH Max by 1 μA.
 Updated icutp_x register default values in Table 8 on
page 19.
 Updated the default value (reset state; Auto tied to
DGND) of the icutp_x registers (0x16, 0x26, 0x36,
0x46) to 0101 0100.
56
Rev. 1.1
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