Si8900/1/2 I SOLA TED M ONITORING ADC Features ADC 3 input channels 10-bit resolution 2 µs conversion time Isolated serial I/O port UART I 2 (Si8900) C/SMbus (Si8901) MHz SPI port (Si8902) 2.5 Transient immunity: 45 kV/µs (typ) Temperature range: –40 to +85 °C >60-year life at rated working voltage CSA component notice 5A approval IEC 60950, 61010, 60601 VDE/IEC 60747-5-2 UL1577 recognized Up Ordering Information: See page 25. to 5 kVrms for 1 minute Applications Isolated data acquisition AC mains monitor Solar inverters Isolated temp/humidity sensing Switch mode power systems Telemetry Description The Si8900/1/2 series of isolated monitoring ADCs are useful as linear signal galvanic isolators, level shifters, and/or ground loop eliminators in many applications including power-delivery systems and solar inverters. These devices integrate a 10-bit SAR ADC subsystem, supervisory state machine and isolated UART (Si8900), I2C/SMbus port (Si8901), or SPI Port (Si8902) in a single package. Based on Silicon Labs’ proprietary CMOS isolation technology, ordering options include a choice of 2.5 or 5 kV isolation ratings. All products are safety certified by UL, CSA, and VDE. The Si8900/1/2 devices offer a typical common-mode transient immunity performance of 45 kV/µs for robust performance in noisy and high-voltage environments. Devices in this family are available in 16-pin SOIC wide-body packages. Safety Approval UL 1577 recognized Up to 5 kVrms for 1 minute CSA component notice 5A approval IEC VDE certification conformity IED 60747-5-2 (VDE 0884 Part 2) VDDA VDDB VREF NC AIN0 NC AIN1 AIN2 Si8900 NC Tx NC VDDB GNDA GNDB VDDA VDDB VREF NC AIN0 NC AIN1 AIN2 Si8901 RST SCL SDA NC RSDA VDDB GNDA GNDB VDDA VDDB RST VREF AIN0 Copyright © 2012 by Silicon Laboratories Rx RST NC NC 60950, 61010, 60601 Rev. 1.1 10/12 Pin Assignments SDO Si8902 SCLK SDI AIN1 EN AIN2 VDDB GNDA GNDB Si8900/1/2 Si8900/1/2 2 Rev. 1.1 Si8900/1/2 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2. I2C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Rev. 1.1 3 Si8900/1/2 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Condition Min Typ Max Unit Input Side Supply Voltage VDDA With respect to GND1 2.7 — 3.6 V Input Side Supply Current IDDA VDDA = 3.3 V, Si890x active — 10 13.3 mA VDDA = 3.3 V, Si890x idle — 8.6 11.4 Output Side Supply Voltage VDDB With respect to GND2 2.7 — 5.5 V Output Side Supply Current IDDB VDDB = 3.3 V to 5.5 V, Si890x active — 4.4 5.8 mA VDDB = 3.3 V to 5.5 V, Si890x idle — 3.3 3.9 –40 — +85 Operating Temperature TA °C Table 2. Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit ADC Resolution R 10 bits Integral Nonlinearity INL VREF = 2.4 V — ±0.5 ±1 LSB Differential Nonlinearity DNL VREF = 2.4 V, Guaranteed Monotonic — ±0.5 ±1 LSB Offset Error OFS –2 0 +2 LSB Full Scale Error FSE –2 0 +2 LSB Offset Tempco TOS — 45 — ppm/°C Input Voltage Range VIN 0 VREF V Sampling Capacitance CIN — 5 — pF Input MUX Impedance RMUX — 5 — k Power Supply Rejection PSRR — –70 — dB Reference Voltage VREF 0 — VDDA V VREF Supply Current IVREF — 12 — µA ADC Conversion Time tCONV 4 Default VREF = VDDA 2 Rev. 1.1 µs Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol Test Condition Min Typ Max Unit Reset and Undervoltage Lockout Power-on RESET Voltage Threshold High VRSTH — — 1.8 V Power-on RESET Voltage Threshold Low VRSTL 1.7 — — V VDDA Power-On Reset Ramp Time tRAMP Time from VDDA = 0 V to VDDA > VRST — — 1 ms Power-On Reset Delay Time tPOR tRAMP < 1 ms 0.3 ms Output Side UVLO Threshold UVLO — 2.3 — V H — 100 — mV Logic High Level Input Voltage VIH 0.7 x VDDB — — V Logic Low Level Input Voltage VIL — — 0.6 V Logic Input Current IIN +10 µA Input Capacitance CIN Output side UVLO Hysteresis Digital Inputs VIN = 0 V or VDD –10 — 15 — pF VDDB = 5 V, IOH = –4 mA VDDB–0.4 4.8 — V VDDB = 3.3 V, IOH = –4 mA 3.1 — — V VDDB = 3.3 to 5 V, IOL = 4 mA — 0.2 0.4 V — 85 — 60 — 234 kbps — — 240 kbps — — 2.5 Mbps Digital Outputs Logic High Level Output Voltage VOH Logic Low Level Output Voltage VOL Digital Output Series Impedance ROUT Serial Ports UART Bit Rate SMBus/I2C Bit Rate Slave Address = 1111000x SPI Port Rev. 1.1 5 Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol Test Condition Min Typ Max Unit SPI Port Timing EN Falling Edge to SCLK Rising Edge tSE 80 — — ns Last Clock Edge to /EN Rising tSD 80 — — ns EN Falling to SDO Valid tSEZ — — 160 ns EN Rising to SDO High-Z tSDZ — — 160 ns SCLK High Time tCKH 200 — — ns SCLK Low Time tCKL 200 — — ns SDI Valid to SCLK Sample Edge tSIS 80 — — ns SCLK Sample Edge to SDI Change tSIH 80 — — ns SCLK Shift Edge to SDO Change tSOH — — 160 ns EN tSE tCKL tSD SCLK tCLKH tSIS tSIH SDI tSEZ tSOH tSDZ SDO Figure 1. SPI Port Timing Characteristics 6 Rev. 1.1 Si8900/1/2 Table 3. Thermal Characteristics Parameter Symbol IC Junction-to-Air Thermal Resistance Test Condition WB SOIC-16 NB SOIC-16 Unit 100 105 ºC/W JA Safety-Limiting Current (mA) 500 450 VDD1, VDD2 = 2.70 V 400 370 VDD1, VDD2 = 3.6 V 300 220 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 430 400 VDD1, VDD2 = 2.70 V 360 VDD1, VDD2 = 3.6 V 300 210 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. 1.1 7 Si8900/1/2 Table 4. Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit TSTG –65 — 150 °C TA –40 — 85 °C Input-Side Supply Voltage VDDA –0.5 — 6.0 V Output-Side Supply Voltage VDDB –0.5 — 6.0 V Input/Output Voltage VI –0.5 — VDD +0.5 V Output Current Drive IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation Voltage — — 6500 VRMS Storage Temperature Ambient Temperature under Bias *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8 Rev. 1.1 Si8900/1/2 2. Regulatory Information The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes the certification levels supported. Table 5. Regulatory Information CSA The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si89xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. Rev. 1.1 9 Si8900/1/2 3. Functional Description The Si8900/1/2 (Figure 4) are isolated monitoring ADCs that convert linear input signals into digital format and transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port. Options include a UART with on-chip baud rate generator that operates at 234 kbps max (Si8900), an SMBus/I2C port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902). The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user to select an internal or external voltage reference, set the programmable gain amplifier (PGA), and select the ADC MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or continuously (Burst Mode). For more information, see "CNFG_0 Command Byte" on page 18. VDDA VDDB AIN1 MUX PGA 10‐Bit ADC AIN2 VREF ADC Subsystem VREF Tx Tx Data UART Rx Rx Data AIN0 All Blocks GNDB ISOLATION State Machine/ User Registers RST GNDA Si8900 VDDA VDDB AIN1 MUX PGA 10‐Bit ADC AIN2 VREF SCL All Blocks ADC Subsystem VREF RST SDA SMBus/ I2C Tx Data Rx Data AIN0 GNDB ISOLATION State Machine/ User Registers RSDA GNDA Si8901 VDDA VDDB AIN1 MUX PGA AIN2 VREF 10‐Bit ADC VREF ADC Subsystem RST SCK SDI Tx Data SPI Port Rx Data AIN0 SDO EN All Blocks ISOLATION State Machine/ User Registers GND1 Si8902 Figure 4. Si8900/1/2 Block Diagrams 10 Rev. 1.1 GND2 Si8900/1/2 4. ADC Data Transmission Modes The master can access ADC read-only registers ADC_H and ADC_L using either Demand Mode or Burst Mode. In Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode (MODE = 0), the Si890x performs ADC conversions continuously. Master to Slave Slave to Master Master writes CNFG_0 Command Byte to Si8900 Rx CNFG_0 Command Byte MODE = 1 tCONV CNFG_0 Command ADC_H ADC_L Byte Master reads updated CNFG_0 and ADC Data From Si8900 (Tx output) B) Si8900 Demand Mode ADC Read Master to Slave Slave to Master Master writes Slave Address and CNFG_0 Command Byte to Si8901 SDA Slave Address CNFG_0 Command Byte Slave Address tCONV MODE = 1 CNFG_0 Command ADC_H ADC_L Byte Master reads Slave Address, updated CNFG_0 and ADC Data from Si8901 (SDA pin) C) Si8901 Demand Mode ADC Read Master to Slave Master writes CNFG_0 Command Byte to Si8902 SDI Slave to Master CNFG_0 Command Byte tCONV MODE = 1 The master must wait 8µS (track‐and‐hold time) before reading ADC data packet. CNFG_0 Command Byte ADC_H ADC_L Master reads updated CNFG_0 and ADC Data from Si8902 SDO D) Si8902 Demand Mode ADC Read Figure 5. ADC Demand Mode Operation Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.) Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART. The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC conversion data. The Si8901 (Figure 5B) ADC read transaction is identical to that of the Si8900 with the exception of the added I2C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two times shorter versus the Si8900/01. Rev. 1.1 11 Si8900/1/2 The Burst Mode ADC transactions for the Si8900 (Figure 6A) and Si8901 (Figure 6B) are substantially the same. A Burst Mode ADC read is initiated when the master writes a CNFG_0 (MODE = 0) Command Byte to the Si8900/1, which updates the CNFG_0 register and triggers the ADC continuously. Like the Demand Mode example, the Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must write the I2C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 6C) is similar to that of the Si8900/1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading the first Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay. Master writes CNFG_0 Command Byte to Si8900 Rx CNFG_0 Command Byte 0 MODE = 0 Master to Slave tCONV Slave to Master tCONV tCONV CNFG_0 Command Byte ADC_H Data ADC_H Data ADC_L Data ADC_L Data Master reads updated CNFG_0 Command Byte and ADC data from Si8900 Tx A) Si8900 ADC Burst Mode (MODE = 0) Master writes Slave Address & CNFG_0 Command Byte to Si8901 SDA Slave Addrress Write CNFG_0 Command Byte 0 MODE = 0 tCONV tCONV Master to Slave Slave Address Read Slave to Master CNFG_0 Command Byte ADC_H Data ADC_L Data tCONV ADC_H Data ADC_L Data Master reads Slave Address, updated CNFG_0 and ADC data from Si8901 SDA B) Si8901 ADC Burst Mode (MODE = 0) Master writes CNFG_0 Command Byte to Si8902 SDI Master to Slave Slave to Master CNFG_0 Command Byte MODE = 0 tCONV tCONV CNFG_0 Command Byte ADC_H Data ADC_L Data tCONV ADC_H Data ADC_L Data Master reads updated CNFG_0 and ADC data from Si8902 SDO C) Si8902 ADC Burst Mode (MODE = 0) Figure 6. ADC Burst Mode Operation 12 Rev. 1.1 Si8900/1/2 4.1. UART (Si8900) The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit error rate. For more information, see “AN635: AC Line Monitoring Using the Si890x Family of Isolated ADCs”. There are a total of 10 bits per data read/write: One start bit, eight data bits (LSB first), and one stop bit with data transmitted LSB first as shown in Figure 7. Figure 8A and Figure 8B show master/Si8900 ADC read transactions for Demand Mode and Burst Mode, respectively. MARK SPACE BIT TIMES Start Bit D0 D2 D1 D5 D4 D3 D6 D7 STOP BIT BIT SAMPLING Figure 7. UART Data Byte Master to Slave Slave to Master CNFG_0 Read Data D0 D1 D2 D3 D4 D5 D6 D7 STOP D0 D1 D2 D3 D4 D5 0 P S START D0 D1 D2 D3 D4 D5 D6 D7 STOP D6 D7 D8 D9 MX0 MX1 0 1 P S 0 START D0 D1 D2 D3 D4 D5 D6 D7 STOP 0 P S START D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 MX0 MX1 D0 D1 D2 D3 D4 D5 D6 D7 STOP CNFG_0 Read Data 0 1 P S 0 START D0 D1 D2 D3 D4 D5 D6 D7 P S STOP 1 1 START ‐ VREF MX0 MX1 S Periodic ADC Data MODE = 0 D0 D1 D2 D3 D4 D5 D6 D7 P STOP 1 PGA MX1 MX0 VREF MODE=0 PGA 1 START START ‐ D0 D1 D2 D3 D4 D5 D6 D7 A) Si8900 Demand Mode ADC Read CNFG_0 Write Command Byte S D0 D1 D2 D3 D4 D5 D6 D7 0 S STOP D0 D1 D2 D3 D4 D5 D6 D7 0 1 P S 0 STOP 1 1 P S D6 D7 D8 D9 MX0 MX1 ‐ START START S D0 D1 D2 D3 D4 D5 ADC Data STOP START D0 D1 D2 D3 D4 D5 D6 D7 P VREF MX0 MX1 1 PGA 1 MODE = 1 MX1 MX0 VREF PGA ‐ STOP START S MODE = 1 CNFG_0 Write Command Byte B) Si8900 Burst Mode ADC Read Figure 8. Si8900 ADC Read Operation Rev. 1.1 13 Si8900/1/2 4.2. I2C/SMBus (Si8901) The I2C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I2C/SMBus master controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 9). The master terminates a transmission with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high. The data on SDA must remain stable during the high period of the SCL clock pulse because such changes in either line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is not busy. Acknowledge bits (Figure 10) provide detection of successful data transfers, whereas unsuccessful transfers conclude with a not-acknowledge bit (NACK). Both the master and the Si8901 generate ACK and NACK bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master attempts communication at a later time. Figure 11A shows the I2C Slave Address Byte and CNFG_0 byte for the Si8901. Figure 11B and Figure 11C show master/Si8901 ADC read transactions for Demand Mode and Burst Mode, respectively. P SR S SDA SCL Figure 9. Start and Stop Conditions Not Acknowledge (NACK) S SDA Acknowledge (ACK) SCL 1 2 Figure 10. Acknowledge Cycle 14 Rev. 1.1 9 Si8900/1/2 MODE PGA A P Si8901 CNFG_0 Write Data ACK R/W = 0 ‐ STOP Si8901 Slave Address A 1 1 ACK Write START S s6 s5 s4 s3 s2 s1 s0 MX0 VREF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Slave to Master MX1 Master to Slave A) Si8901 CNFG_0 Write 0 A P D7 D6 D5 D4 D3 D2 D1 D0 ACK D0 D1 D2 D3 D4 A 0 STOP D7 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 D8 D9 A 1 0 MX1 MX0 PGA ‐ Si8901 CNFG_0 Read Data ACK MODE=1 R/W = 1 S 1 1 Read Si8901 Read Slave Address START START S s6 s5 s4 s3 s2 s1 s0 ADC Data D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Si8901 Slave Address = 0xF0 MX1 MX0 VREF Si8901 CNFG_0 Write Data STOP PGA A P ACK ‐ MODE=1 MX0 VREF R/W = 0 Write START Si8901 Write Slave Address A 1 1 ACK S s6 s5 s4 s3 s2 s1 s0 MX1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 B) Si8901 Demand Mode ADC Read Periodic ADC Data 0 A D7 D6 D5 D4 D3 D2 D1 D0 P STOP D0 A D1 D2 D3 D4 A 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 D8 D9 MX1 MX0 A 1 0 ACK Si8901 CNFG_0 Read Data PGA MODE=0 ‐ ACK S 1 1 Read START START Si8901 Read Slave Address R/W = 1 D7 D6 D5 D4 D3 D2 D1 D0 S s6 s5 s4 s3 s2 s1 s0 D7 D6 D5 D4 D3 D2 D1 D0 MX1 MX0 VREF ACK Si8901 CNFG_0 Write Data A P STOP ‐ MODE=0 PGA MX0 VREF R/W = 0 A 1 1 ACK Si8901 Slave Address Write START S s6 s5 s4 s3 s2 s1 s0 MX1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 C) Si8901 Burst Mode ADC Read Figure 11. Si8901 ADC Read Operation MASTER SPI Shift Register 7 6 5 4 3 2 1 0 Si8902 MOSI SDI MISO SDO SPI Shift Register 7 6 5 4 3 2 1 0 /EN Receive Buffer Receive Buffer Baud Rate Generator SCLK SCLK EN or Px.y Figure 12. Master Connection to Si8902 Rev. 1.1 15 Si8900/1/2 4.3. SPI Port (Si8902) EN SCLK SDI SDO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 13. Si8902 Data/Clock Timing The Serial Peripheral Interface (SPI port) is a slave mode, full-duplex, synchronous, 4-wire serial bus that connects to the master as shown in Figure 12. The master's clock and data timing must match the Si8902 timing shown Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on page 6). As shown in Figure 13, an SPI bus transaction begins with the master driving EN low and maintaining this state for the duration of the read transaction(s). The master transmits data from its master-out/slave-in terminal (MOSI) to the Si8902 serial read/write input terminal (SDI). The Si8902 transmits data to the master from its serial data-out terminal (SDO) to the master-in/slave-out terminal (MISO), and data transfer ends when the master returns /EN to the high state. Figure 14A shows the Si8902 CNFG_0 Command Byte format, while Figures 14B and 14C show Si8902 Demand Mode and Burst Mode ADC reads. 16 Rev. 1.1 Si8900/1/2 A) Si8902 CNFG_0 Command Byte PGA ‐ MODE=1 MX0 VREF MX1 1 PGA CNFG_0 Write Command Byte D7 D6 D5 D4 D3 D2 D1 D0 1 ‐ MODE 1 MX0 1 VREF Slave to Master MX1 D7 D6 D5 D4 D3 D2 D1 D0 Master to Slave CNFG_0 Write Command Byte Si8902 CNFG_0 Read Byte D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 MX0 MX1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 ADC Data Si8902 CNFG_0 Read Byte 0 D5 D4 D3 D2 D1 D0 0 1 0 D9 D8 D7 D6 0 MX1 MX0 1 0 D5 D4 D3 D2 D1 D0 ‐ MX1 MX0 D9 D8 D7 D6 1 1 MODE = 0 PGA 8µS Delay D7 D0 D7 D0 D7 D0 D7 D0 D7 D0 MX1 MX0 VREF CNFG_0 Write Command Byte 0 PGA ‐ MODE=0 MX0 VREF MX1 1 1 B) Si8902 ADC Demand Mode Read D7 D6 D5 D4 D3 D2 D1 D0 1 PGA ‐ MODE = 1 VREF 1 MX0 1 MX1 8µS Delay D7 D6 D5 D4 D3 D2 D1 D0 0 Periodic ADC Data C) Si8902 ADC Burst Mode Read Figure 14. Si8902 ADC Read Operation 4.4. Master Controller Firmware The user's master controller must include firmware to manage the Si890x Demand and Burst operating modes and serial port control. In some cases, the master controller may also require a firmware moving average function to reduce noise. For more information on master controller firmware, see “AN637: Si890x Master Controller Recommendations”, available for download at www.silabs.com/isolation. Rev. 1.1 17 Si8900/1/2 5. Si8900/1/2 Configuration Registers CNFG_0 Command Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 1 1 MX1 MX0 VREF — MODE PGA Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Bit Name 7:6 1,1 5:4 MX1, MX0 Function Internal use. These bits are always set to 1. ADC MUX Address. ADC MUX address selection is controlled by MX1, MX0 as follows: 18 3 VREF 2 — 1 MODE 0 PGA MX1 MX0 Selected ADC MUX Channel 1 1 Not Used 1 0 AIN2 0 1 AIN1 0 0 AIN0 ADC Voltage Reference Source VDD is selected as the reference voltage when this bit is set to 1. An externally connected voltage reference generator is selected when this bit is reset to 0. Not used. ADC Read Mode ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled when this bit is 0. For more information on Demand and Burst mode operation, please see "ADC Data Transmission Modes" on page 11. PGA Gain Set PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0. Rev. 1.1 Si8900/1/2 ADC_H Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 1 0 MX1 MX0 D9 D8 D7 D6 Type R R R R R R R R Default — — — — — — — — Bit Name 7:6 1,0 5:4 MX1, MX0 3:0 D9: D6 Function Internal use. These bits are always set to 1,0. ADC MUX Address ADC input MUX address for the converted data in ADC_H, ADC_L. ADC conversion data bits D9:D6 Most significant 4 bits of ADC conversion data. ADC_L Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name 0 D5 D4 D3 D2 D1 D0 0 Type R R R R R R R R Default — — — — — — — — Bit Name 7 0 6:1 D5:D0 Function Internal use. This bit is always set to 0. ADC Conversion Data Bits D5:D0 Least significant 6 bits of ADC conversion data. 0 0 Internal use. This bit is always set to 0. Rev. 1.1 19 Si8900/1/2 6. Applications 6.1. Isolated Outputs The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (i.e., circuits with <30 VAC) by a certain distance (creepage/clearance). If a component straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Tables published in the component standards (UL1577, IEC60747, CSA 5A) are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 606011, etc.) requirements before starting any circuit design that uses galvanic isolation. To enhance the robustness of a design, it is further recommended that the user also include 100 resistors in series with the Si890x inputs and outputs if the system is excessively noisy. The nominal impedance of an isolated Si890x output channel is approximately 50 and is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects are a factor, output pins should be appropriately terminated with controlled-impedance PCB traces. The Si890x supply inputs must be bypassed with a parallel combination of 10 µF and 0.1 µF capacitors at VDDA and VDDB as shown in Figure 15A. The capacitors should be placed as close to the package as possible. The Si890x uses the VDDA supply as its internal ADC voltage reference by default. A precision external reference can be installed as shown in Figure 15A and must be bypassed with a parallel combination of 0.1 µF and 4.7 µF capacitors. (Note that the CNFG_0 VREF bit must be set to 0 when using the external reference.) The Si890x has an on-chip power on reset circuit (POR) that maintains the device in its reset state until VDDA has stabilized. A 2 k pull-up resistor on RST is strongly recommended to reduce the possibility of external noise coupling into the reset input. The Si8901 will also require a 5 k pull-up resistor to VDDA on the RSDA input. 2.7 V to 3.6 V Board Edge 2.5 V to 5.5 V 0.1 µF 0.1 µF Si890x 10 µF VDDA VDDA VDDB 10 µF VREF VREF Si890x VDDA 0.1 µF 4.7 µF 5 K 2 K GNDA RST RSDA Optional External VREF GNDA Si8901 Only GNDA GNDB GNDB 8 mm (min) Board Edge Keep‐out Area (No metal in this area) A GNDB B Figure 15. Si890x Installation Figure 15B shows the required PCB ground configuration, where an 8 mm (min) “keep-out area” is provided to ensure adequate creepage and clearance distances between the two grounds. PCB metal traces cannot be present or cross through the keep-out area on the PCB top, bottom, or internal layer. 20 Rev. 1.1 Si8900/1/2 6.2. Device Reset During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause the Si890x to be released from reset before VDDA reaches the VRST level. Figure 16 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving the external RST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from external noise coupling to the RST input. VDDA VD DA VRSTH VRSTL VDDA(min) Internal RESET tPOR VDDA Monitor Reset Power‐On Reset Figure 16. Si890x Power-on and Monitor Reset Rev. 1.1 21 Si8900/1/2 6.3. Application Example Figure 17 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC line current is measured using differential amplifier U1 connected across shunt resistor R1. Data is transferred to the external controller or processor via the isolated UART. BLACK WHITE Single‐Phase AC Line 1.5 V R2 R3 R4 R1 U1 Low Cost Dual OpAmp R5 R17 R6 C2 R7 R18 R9 TX C3 R10 Si8900 AIN1 R11 R8 AIN0 1.5 V C1 RX R12 D1 R13 C4 U2 3.3 V LDO VDDA C5 R14 VDDB 1.5 V R15 GNDA GNDB Figure 17. AC Line Monitor Application Example 22 Rev. 1.1 External Master Controller Output Side Bias Supply Si8900/1/2 7. Device Pin Assignments VDDA VDDB VDDA VDDB VREF NC VREF NC RST AIN0 NC AIN0 NC NC Rx AIN1 SCL VREF Tx AIN2 SDA AIN0 NC RST NC AIN1 EN VDDB AIN2 VDDB GNDB GNDA GNDB AIN1 Si8900 AIN2 NC RST VDDB RSDA GNDA GNDB GNDA Si8901 VDDA VDDB NC SDO Si8902 SCLK SDI Figure 18. Si8900/1/2 Pinout (16SOW) Table 6. Si8900/1/2 Pin Assignments Pin Si8900 Si8901 Si8902 Pin Pin Pin 1 VDDA 2 VREF Description Input side VDD bias voltage (typically 3.3 V) RST Si8900/1: External voltage reference input. Si8902: Active low reset. NC Si8900: ADC analog input channel 0. Si8901: ADC analog input channel 0. Si8902: No connection 3 AIN0 AIN0 4 AIN1 AIN1 VREF Si8900: ADC analog input channel 1. Si8901: ADC analog input channel 1. Si8902: External VREF in. 5 AIN2 AIN2 AIN0 Si8900: ADC analog input channel 2. Si8901: ADC analog input channel 2. Si8902: ADC analog input channel 0. 6 NC RST AIN1 Si8900: No Connection. Si8901: Active low reset. Si8902: ADC analog input channel 1. 7 RST RSDA AIN2 Si8900: Active low reset. Si8901: RSDA bias resistor (typically 5 k). Si8902: ADC analog input channel 2. 8 GNDA Input side ground 9 GNDB Output side ground 10 VDDB Output side VDD bias voltage (2.7 V to 5.5 V) 11 12 NC Tx SDA EN Si8900/1: No connection. Si8902: SPI Port Enable. SDI Si8900: UART unidirectional transmit output. Si8901: I2C Bidirectional data input/output. Si8902: SPI port Serial data in. Rev. 1.1 23 Si8900/1/2 Table 6. Si8900/1/2 Pin Assignments (Continued) Pin 13 14 24 Si8900 Si8901 Si8902 Pin Pin Pin Rx SCL NC SCLK Si8900: UART unidirectional receive input. Si8901: I2C port unidirectional serial clock input. Si8902: SPI port unidirectional serial clock input. SDO 15 NC 16 VDDB Description Si8900/1: No connection. Si8902: SPI port Serial data out (SDO) No connection Si8900/1/2: Output side VDD bias voltage (2.7 V to 5.5 V). Rev. 1.1 Si8900/1/2 8. Ordering Guide Table 7. Product Ordering Information1,2,3 Part Number (OPN) Serial Port Package Isolation Rating Temp Range Si8900B-A01-GS UART WB SOIC 2.5 kV –40 to +85 °C Si8900D-A01-GS UART WB SOIC 5.0 kV –40 to +85 °C Si8901B-A01-GS I2C/SMBus WB SOIC 2.5 kV –40 to +85 °C Si8901D-A01-GS I2C/SMBus WB SOIC 5.0 kV –40 to +85 °C Si8902B-A01-GS SPI Port WB SOIC 2.5 kV –40 to +85 °C Si8902D-A01-GS SPI Port WB SOIC 5.0 kV –40 to +85 °C Notes: 1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”. 2. All packages are RoHS-compliant. 3. Moisture sensitivity level is MSL3 for wide-body SOIC-16 package with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. Rev. 1.1 25 Si8900/1/2 9. Package Outline: 16-Pin Wide Body SOIC Figure 19 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the dimensions shown in the illustration. Figure 19. 16-Pin Wide Body SOIC 26 Rev. 1.1 Si8900/1/2 Table 8. Package Diagram Dimensions Millimeters Symbol Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 θ 0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. Rev. 1.1 27 Si8900/1/2 10. Land Pattern: 16-Pin Wide-Body SOIC Figure 20 illustrates the recommended land pattern details for the Si8900/1/2 in a 16-pin wide-body SOIC. Table 9 lists the values for the dimensions shown in the illustration. Figure 20. 16-Pin SOIC Land Pattern Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 28 Rev. 1.1 Si8900/1/2 11. Top Marking: 16-Pin Wide Body SOIC 11.1. Si8900/1/2 Top Marking Si890XY YYWWRTTTTT e4 TW 11.2. Top Marking Explanation Line 1 Marking: Line 2 Marking: Line 3 Marking: Si890 = Isolator product series X = Serial Port 0 = UART 1 = I2C 2 = SPI (See Ordering Guide for more information). Y = Insulation rating B = 2.5 kV; D = 5.0 kV Base Part Number Ordering Options YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.7 mm Diameter (Center-Justified) “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan Rev. 1.1 29 Si8900/1/2 DOCUMENT CHANGE LIST Revision 0.5 to Revision 1.0 No changes. Revision 1.0 to Revision 1.1 Removed “pending” throughout. Changed AN638 reference to AN637. Updated "Top Marking: 16-Pin Wide Body SOIC" on page 29. 30 Rev. 1.1 Si8900/1/2 NOTES: Rev. 1.1 31 Smart. Connected. Energy-Friendly Products Quality www.silabs.com/products www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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