Si8610/20/21/22 L O W - P O W E R S I N G LE A N D D U A L -C H A N N E L D I G I TA L I S O L A T O R S Features High-speed operation DC to 150 Mbps No start-up initialization required Wide Operating Supply Voltage 2.5–5.5 V Up to 5000 VRMS isolation 60-year life at rated working voltage High electromagnetic immunity Ultra low power (typical) 5 V Operation 1.6 mA per channel at 1 Mbps 5.5 mA per channel at 100 Mbps 2.5 V Operation 1.5 mA per channel at 1 Mbps 3.5 mA per channel at 100 Mbps Schmitt trigger inputs Selectable fail-safe mode Default high or low output (ordering option) Precise timing (typical) 10 ns propagation delay 1.5 ns pulse width distortion 0.5 ns channel-channel skew 2 ns propagation delay skew 5 ns minimum pulse width Transient Immunity 50 kV/µs AEC-Q100 qualification Wide temperature range –40 to 125 °C RoHS-compliant packages SOIC-16 wide body SOIC-8 narrow body Applications Industrial automation systems Medical electronics Hybrid electric vehicles Isolated switch mode supplies Isolated ADC, DAC Motor control Power inverters Communications systems VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) EN60950-1 (reinforced insulation) Ordering Information: See page 27. Safety Regulatory Approvals UL 1577 recognized Up to 5000 VRMS for 1 minute CSA component notice 5A approval IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. All device versions have Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors. Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of less than 10 ns. Ordering options include a choice of isolation ratings (3.75 and 5 kV) and a selectable fail-safe operating mode to control the default output state during power loss. All products >1 kVRMS are safety certified by UL, CSA, and VDE, and products in wide-body packages support reinforced insulation withstanding up to 5 kVRMS. Rev. 1.3 6/12 Copyright © 2012 by Silicon Laboratories Si8610/20/21/22 Si8610/20/21/22 2 Rev. 1.3 Si8610/20/21/22 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Rev. 1.3 3 Si8610/20/21/22 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature* Symbol Test Condition 150 Mbps, 15 pF, 5 V TA VDD1 VDD2 Supply Voltage Min –40 2.5 2.5 Typ 25 — — Max 125* 5.5 5.5 Unit °C V V *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Electrical Characteristics (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Negative-Going Lockout Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 50 — Input Leakage Current 1 Output Impedance Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 4 Rev. 1.3 Si8610/20/21/22 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit DC Supply Current (All inputs 0 V or at Supply) Si8610Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.6 0.8 1.8 0.8 1.2 1.5 2.9 1.5 Si8620Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.8 1.4 3.3 1.4 1.4 2.2 5.3 2.2 Si8621Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 1.2 2.4 2.4 1.9 1.9 3.8 3.8 Si8622Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 3.3 4.0 4.8 4.2 5.3 6.4 7.7 mA mA mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 0.9 2.0 1.5 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 1.6 3.1 2.4 mA Si8621Bx, Ex VDD1 VDD2 — — 1.9 1.9 2.9 2.9 mA Si8622Bx, Ex VDD1 VDD2 — — 3.4 4.2 5.1 6.2 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.3 5 Si8610/20/21/22 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 1.2 2.0 2.0 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 2.2 3.1 3.3 mA Si8621Bx, Ex VDD1 VDD2 — — 2.2 2.2 3.3 3.3 mA Si8622Bx, Ex VDD1 VDD2 — — 3.7 4.4 5.5 6.7 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 4.8 2.0 6.7 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 8.9 3.1 12.5 mA Si8621Bx, Ex VDD1 VDD2 — — 5.8 5.8 8.1 8.1 mA Si8622Bx, Ex VDD1 VDD2 — — 7.6 8.2 10.6 11.4 mA Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si861x/2x Bx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 13 ns PWD See Figure 1 — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 6 Rev. 1.3 Si8610/20/21/22 Table 2. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr CL = 15 pF See Figure 1 — 2.5 4.0 ns Output Fall Time tf CL = 15 pF See Figure 1 — 2.5 4.0 ns Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V 35 50 — kV/µs — 15 40 µs All Models Startup Time3 tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 1.4 V Typical Input tPLH tPHL 90% 90% 10% 10% 1.4 V Typical Output tr tf Figure 1. Propagation Delay Timing Rev. 1.3 7 Si8610/20/21/22 Table 3. Electrical Characteristics (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Negative-Going Lockout Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 50 — Input Leakage Current Output Impedance1 DC Supply Current (All inputs 0 V or at supply) Si8610Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.6 0.8 1.8 0.8 1.2 1.5 2.9 1.5 Si8620Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.8 1.4 3.3 1.4 1.4 2.2 5.3 2.2 Si8621Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 1.2 2.4 2.4 1.9 1.9 3.8 3.8 Si8622Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 3.3 4.0 4.8 4.2 5.3 6.4 7.7 mA mA mA mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 8 Rev. 1.3 Si8610/20/21/22 Table 3. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 0.9 2.0 1.5 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 1.6 3.1 2.4 mA Si8621Bx, Ex VDD1 VDD2 — — 1.9 1.9 2.9 2.9 mA Si8622Bx, Ex VDD1 VDD2 — — 3.4 4.2 5.1 6.2 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 1.0 2.0 1.8 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 1.9 3.1 2.8 mA Si8621Bx, Ex VDD1 VDD2 — — 2.0 2.0 3.0 3.0 mA Si8622Bx, Ex VDD1 VDD2 — — 3.5 4.3 5.3 6.4 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 — — 1.2 3.4 2.0 5.1 mA Si8620Bx, Ex VDD1 VDD2 — — 2.1 6.3 3.1 8.8 mA Si8621Bx, Ex VDD1 VDD2 — — 4.4 4.4 6.1 6.1 mA Si8622Bx, Ex VDD1 VDD2 — — 5.9 6.6 8.2 9.3 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.3 9 Si8610/20/21/22 Table 3. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si861x/2x Bx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 13 ns PWD See Figure 1 — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns All Models Output Rise Time tr CL = 15 pF See Figure 1 — 2.5 4.0 ns Output Fall Time tf CL = 15 pF See Figure 1 — 2.5 4.0 ns Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V 35 50 — kV/µs — 15 40 µs Start-up Time3 tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 10 Rev. 1.3 Si8610/20/21/22 Table 4. Electrical Characteristics (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Negative-Going Lockout Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V Input Hysteresis VHYS 0.40 0.45 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V Input Leakage Current IL — — ±10 µA Output Impedance1 ZO — 50 — DC Supply Current (All inputs 0 V or at supply) Si8610Bx, Ex VDD1 VDD2 VDD1 VDD2 Si8620Bx, Ex VDD1 VDD2 VDD1 VDD2 Si8621Bx, Ex VDD1 VDD2 VDD1 VDD2 Si8622Bx, Ex VDD1 VDD2 VDD1 VDD2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.6 0.8 1.8 0.8 1.2 1.5 2.9 1.5 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 0.8 1.4 3.3 1.4 1.4 2.2 5.3 2.2 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 1.2 1.2 2.4 2.4 1.9 1.9 3.8 3.8 VI = 0(Bx), 1(Ex) VI = 0(Bx), 1(Ex) VI = 1(Bx), 0(Ex) VI = 1(Bx), 0(Ex) — — — — 2.6 3.3 4.0 4.8 4.2 5.3 6.4 7.7 mA mA mA mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.3 11 Si8610/20/21/22 Table 4. Electrical Characteristics (Continued) (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 Si8620Bx, Ex VDD1 VDD2 Si8621Bx, Ex VDD1 VDD2 Si8622Bx, Ex VDD1 VDD2 — — 1.2 0.9 2.0 1.5 mA — — 2.1 1.6 3.1 2.4 mA — — 1.9 1.9 2.9 2.9 mA — — 3.4 4.2 5.1 6.2 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 Si8620Bx, Ex VDD1 VDD2 Si8621Bx, Ex VDD1 VDD2 Si8622Bx, Ex VDD1 VDD2 — — 1.2 1.0 2.0 1.6 mA — — 2.1 1.7 3.1 2.6 mA — — 2.0 2.0 2.9 2.9 mA — — 3.5 4.2 5.2 6.3 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8610Bx, Ex VDD1 VDD2 Si8620Bx, Ex VDD1 VDD2 Si8621Bx, Ex VDD1 VDD2 Si8622Bx, Ex VDD1 VDD2 — — 1.2 2.7 2.0 4.4 mA — — 2.1 5.1 3.1 7.1 mA — — 3.7 3.7 5.2 5.2 mA — — 5.2 6.0 7.3 8.4 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 12 Rev. 1.3 Si8610/20/21/22 Table 4. Electrical Characteristics (Continued) (VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns Timing Characteristics Si861x/2x Bx, Ex Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 5.0 8.0 14 ns PWD See Figure 1 — 0.2 5.0 ns tPSK(P-P) — 2.0 5.0 ns tPSK — 0.4 2.5 ns All Models Output Rise Time tr CL = 15 pF See Figure 1 — 2.5 4.0 ns Output Fall Time tf CL = 15 pF See Figure 1 — 2.5 4.0 ns Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps Common Mode Transient Immunity CMTI VI = VDD or 0 V 35 50 — kV/µs — 15 40 µs Start-Up Time3 tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.3 13 Si8610/20/21/22 Table 5. Regulatory Information* CSA The Si861x/2x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si861x/2x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si861x/2x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. *Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see "6. Ordering Guide" on page 27. Table 6. Insulation and Safety-Related Specifications Value Parameter Symbol Test Condition WB SOIC-16 NB SOIC-8 Unit Nominal Air Gap (Clearance)1 L(IO1) 8.0 4.9 mm Nominal External Tracking (Creepage)1 L(IO2) 8.0 4.01 mm 0.014 0.011 mm 600 600 VRMS 0.019 0.040 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI ED Erosion Depth Resistance (Input-Output) 2 Capacitance (Input-Output)2 Input Capacitance IEC60112 3 12 RIO CIO CI 10 f = 1 MHz 12 10 2.0 2.0 pF 4.0 4.0 pF Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline: 16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8) are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. 14 Rev. 1.3 Si8610/20/21/22 Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings Specification Test Conditions Parameter Basic Isolation Group NB SOIC-8 WB SOIC-16 I I Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-III I-IV Rated Mains Voltages < 400 VRMS I-II I-III Rated Mains Voltages < 600 VRMS I-II I-III Material Group Installation Classification Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx* Characteristic Symbol Parameter Maximum Working Insulation Voltage Input to Output Test Voltage Transient Overvoltage Test Condition WB SOIC-16 NB SOIC-8 Unit 1200 630 Vpeak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2250 1182 VIOTM t = 60 sec 6000 6000 2 2 >109 >109 VIORM Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS Vpeak *Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 9. IEC Safety Limiting Values1 Max Parameter Symbol Case Temperature TS Safety Input, Output, or Supply Current IS Device Power Dissipation2 PD Test Condition JA = 140 °C/W (NB SOIC-8), 100 °C (WB SOIC-16), VI = 5.5 V, TJ = 150 °C, TA = 25 °C Min Typ WB SOIC-16 NB SOIC-8 Unit — — 150 150 °C — — 220 160 mA — — 150 150 mW Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3. 2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. Rev. 1.3 15 Si8610/20/21/22 Table 10. Thermal Characteristics Parameter Symbol JA IC Junction-to-Air Thermal Resistance Safety-Limiting Values (mA) Test Condition WB SOIC-16 NB SOIC-8 Unit 100 140 ºC/W 500 460 VDD1, VDD2 = 2.5 V 375 360 250 VDD1, VDD2 = 3.3 V 220 VDD1, VDD2 = 5.5 V 125 0 0 50 100 150 Case Temperature (ºC) 200 Safety-Limiting Values (mA) Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 400 320 VDD1, VDD2 = 2.5 V 300 270 200 VDD1, VDD2 = 3.3 V 160 VDD1, VDD2 = 5.5 V 100 0 0 50 100 150 Case Temperature (ºC) 200 Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 16 Rev. 1.3 Si8610/20/21/22 Table 11. Absolute Maximum Ratings1 Parameter Symbol Min Typ Max Unit Storage Temperature2 TSTG –65 — 150 °C Operating Temperature TA –40 — 125 °C Junction Temperature TJ — — 150 °C VDD1, VDD2 –0.5 — 7.0 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation (Input to Output) (1 sec) NB SOIC-8 — — 4500 VRMS Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 — — 6500 VRMS Supply Voltage Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from –40 to 150 °C. Rev. 1.3 17 Si8610/20/21/22 2. Functional Description 2.1. Theory of Operation The operation of an Si861x/2x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si861x/2x channel is shown in Figure 4. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 4. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 5 for more details. Input Signal Modulation Signal Output Signal Figure 5. Modulation Scheme 18 Rev. 1.3 Si8610/20/21/22 2.2. Eye Diagram Figure 6 illustrates an eye-diagram taken on an Si8610. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8610 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited. Figure 6. Eye Diagram Rev. 1.3 19 Si8610/20/21/22 3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO– are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when power supply (VDD) is not present. Table 12. Si86xx Logic Operation VI Input1,2 VDDI State1,3,4 VDDO State1,3,4 VO Output1,2 H P P H L P P L X5 UP P L6 H6 Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. X5 P UP Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs. Comments Normal operation. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V. 4. “Unpowered” state (UP) is defined as VDD = 0 V. 5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 6. See "6. Ordering Guide" on page 27 for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs. 20 Rev. 1.3 Si8610/20/21/22 3.1. Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 3.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. UVLO+ UVLO- VDD1 UVLO+ UVLO- VDD2 INPUT tSTART tSD tSTART tSTART tPHL tPLH OUTPUT Figure 7. Device Behavior during Normal Operation Rev. 1.3 21 Si8610/20/21/22 3.3. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5 on page 14 and Table 6 on page 14 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1. Supply Bypass The Si861x/2x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2. Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3.4. Fail-Safe Operating Mode Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on page 20 and "6. Ordering Guide" on page 27 for more information. 22 Rev. 1.3 Si8610/20/21/22 3.5. Typical Performance Characteristics 30.0 30.0 25.0 25.0 20.0 20.0 15.0 5V 3.3V 10.0 Current (mA) Current (mA) The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 2, 3, and 4 for actual specification limits. 15.0 5V 3.3V 10.0 2.5V 2.5V 5.0 5.0 0.0 0.0 0 10 20 30 40 50 60 70 80 0 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 8. Si8610 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation Figure 11. Si8610 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) 30.0 30.0 25.0 20.0 15.0 Current (mA) Current (mA) 25.0 5V 3.3V 10.0 2.50V 2.5V 20.0 15.0 5V 3.3V 10.0 2.5V 5.0 5.0 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0.0 0 Data Rate (Mbps) 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Figure 9. Si8620 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation Figure 12. Si8620 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) 30.0 30.0 25.0 20.0 15.0 5V 1.2 10.0 3.3V 1.2 2.5V 1.2 Current (mA) Current (mA) 25.0 5.0 20.0 15.0 5V 3.3V 10.0 2.5V 5.0 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0.0 Data Rate (Mbps) 0 Figure 10. Si8621 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Figure 13. Si8622 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Rev. 1.3 23 Si8610/20/21/22 10.0 Delay (ns) 9.0 8.0 7.0 6.0 5.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 Temperature (Degrees C) Figure 14. Propagation Delay vs. Temperature 24 Rev. 1.3 Si8610/20/21/22 4. Pin Descriptions (Wide-Body SOIC) GND2 GND1 NC VDD1 A1 RF XMITR NC NC I s o l a t i o n RF RCVR GND1 NC VDD2 VDD1 B1 A1 RF XMITR NC A2 RF XMITR NC NC NC GND1 GND2 NC I s o l a t i o n RF RCVR RF RCVR GND2 GND1 NC NC VDD2 VDD1 B1 A1 RF XMITR B2 A2 RF RCVR NC NC NC GND1 GND2 NC I s o l a t i o n NC VDD2 VDD1 A1 RF RCVR RF XMITR B2 A2 RF XMITR NC NC NC GND1 I s o l a t i o n VDD2 RF XMITR B1 RF RCVR B2 NC NC GND2 NC Si8621 WB SOIC-16 Type NC B1 GND2 SOIC-16 Pin# SOIC-16 Pin# Si8610 Si862x GND2 GND1 NC RF RCVR NC Si8620 WB SOIC-16 Si8610 WB SOIC-16 Name GND2 GND1 NC Si8622 WB SOIC-16 Description GND1 1 1 Ground Side 1 ground. NC* 2, 5, 6, 8,10, 11, 12, 15 2, 6, 8,10, 11, 15 No Connect VDD1 3 3 Supply A1 4 4 Digital I/O Side 1 digital input or output. A2 NC 5 Digital I/O Side 1 digital input or output. GND1 7 7 Ground Side 1 ground. GND2 9 9 Ground Side 2 ground. B2 NC 12 Digital I/O Side 2 digital input or output. B1 13 13 Digital I/O Side 2 digital input or output. VDD2 14 14 Supply Side 2 power supply. GND2 16 16 Ground Side 2 ground. NC Side 1 power supply. *Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. Rev. 1.3 25 Si8610/20/21/22 5. Pin Descriptions (Narrow-Body SOIC) VDD1 VDD2 RF XMITR A1 VDD1/NC I s o l a t i o n RF RCVR VDD2 GND2/NC A1 RF XMITR B1 A2 RF XMITR GND2 GND1 VDD1 I s o l a t i o n VDD2 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF RCVR GND2 GND1 Si8610 NB SOIC-8 VDD1 I s o l a t i o n VDD2 RF RCVR B1 A1 RF RCVR RF XMITR B2 A2 RF XMITR GND2 GND1 Si8620 NB SOIC-8 VDD1 I s o l a t i o n RF XMITR B1 RF RCVR B2 GND2 GND1 Si8622 NB SOIC-8 Si8621 NB SOIC-8 Name SOIC-8 Pin# Si861x SOIC-8 Pin# Si862x Type Description VDD1/NC* 1,3 1 Supply Side 1 power supply. GND1 4 4 Ground Side 1 ground. A1 2 2 Digital I/O Side 1 digital input or output. A2 NA 3 Digital I/O Side 1 digital input or output. B1 6 7 Digital I/O Side 2 digital input or output. B2 NA 6 Digital I/O Side 2 digital input or output. VDD2 8 8 Supply Side 2 power supply. GND2/NC* 5.7 5 Ground Side 2 ground. *Note: No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. 26 Rev. 1.3 Si8610/20/21/22 6. Ordering Guide Table 13. Ordering Guide for Valid OPNs1,2 Ordering Part Number (OPN) Number of Number of Inputs Inputs VDD1 Side VDD2 Side Max Data Rate (Mbps) Default Isolation Output rating State (kV) Temp (C) Package Si8610BC-B-IS 1 0 150 Mbps Low 3.75 –40 to 125 °C SOIC-8 Si8610EC-B-IS 1 0 150 Mbps High 3.75 –40 to 125 °C SOIC-8 Si8610BD-B-IS 1 0 150 Mbps Low 5.0 –40 to 125 °C WB SOIC-16 Si8610ED-B-IS 1 0 150 Mbps High 5.0 –40 to 125 °C WB SOIC-16 Si8620BC-B-IS 2 0 150 Mbps Low 3.75 –40 to 125 °C SOIC-8 Si8620EC-B-IS 2 0 150 Mbps High 3.75 –40 to 125 °C SOIC-8 Si8620BD-B-IS 2 0 150 Mbps Low 5.0 –40 to 125 °C WB SOIC-16 Si8620ED-B-IS 2 0 150 Mbps High 5.0 –40 to 125 °C WB SOIC-16 Si8621BC-B-IS 1 1 150 Mbps Low 3.75 –40 to 125 °C SOIC-8 Si8621EC-B-IS 1 1 150 Mbps High 3.75 –40 to 125 °C SOIC-8 Si8621BD-B-IS 1 1 150 Mbps Low 5.0 –40 to 125 °C WB SOIC-16 Si8621ED-B-IS 1 1 150 Mbps High 5.0 –40 to 125 °C WB SOIC-16 Si8622BC-B-IS 1 1 150 Mbps Low 3.75 –40 to 125 °C SOIC-8 Si8622EC-B-IS 1 1 150 Mbps High 3.75 –40 to 125 °C SOIC-8 Si8622BD-B-IS 1 1 150 Mbps Low 5.0 –40 to 125 °C WB SOIC-16 Si8622ED-B-IS 1 1 150 Mbps High 5.0 –40 to 125 °C WB SOIC-16 Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages. Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages. 2. All devices >1 kVRMS are AEC-Q100 qualified. Rev. 1.3 27 Si8610/20/21/22 7. Package Outline: 16-Pin Wide Body SOIC Figure 15 illustrates the package details for the Triple-Channel Digital Isolator. Table 14 lists the values for the dimensions shown in the illustration. Figure 15. 16-Pin Wide Body SOIC 28 Rev. 1.3 Si8610/20/21/22 Table 14. Package Diagram Dimensions Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. Rev. 1.3 29 Si8610/20/21/22 8. Land Pattern: 16-Pin Wide-Body SOIC Figure 16 illustrates the recommended land pattern details for the Si861x/2x in a 16-pin wide-body SOIC. Table 15 lists the values for the dimensions shown in the illustration. Figure 16. 16-Pin SOIC Land Pattern Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 30 Rev. 1.3 Si8610/20/21/22 9. Package Outline: 8-Pin Narrow Body SOIC Figure 17 illustrates the package details for the Si86xx. Table 16 lists the values for the dimensions shown in the illustration. Figure 17. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 16. Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Rev. 1.3 31 Si8610/20/21/22 10. Land Pattern: 8-Pin Narrow Body SOIC Figure 18 illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. Table 17 lists the values for the dimensions shown in the illustration. Figure 18. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 17. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 32 Rev. 1.3 Si8610/20/21/22 11. Top Marking: 16-Pin Wide Body SOIC 11.1. 16-Pin Wide Body SOIC Top Marking Si86XYSV YYWWRTTTTT e3 TW 11.2. Top Marking Explanation Line 1 Marking: Base Part Number Ordering Options Line 2 Marking: YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.5 mm Diameter (Center-Justified) “e3” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan Line 3 Marking: Si86 = Isolator product series XY = Channel Configuration X = # of data channels (2, 1) (See Ordering Guide for more Y = # of reverse channels (1, 0) information). S = Speed Grade (max data rate) and operating mode: A = 1 Mbps (default output = low) B = 150 Mbps (default output = low) D = 1 Mbps (default output = high) E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV Rev. 1.3 33 Si8610/20/21/22 12. Top Marking: 8-Pin Narrow Body SOIC 12.1. 8-Pin Narrow Body SOIC Top Marking Si86XYSV YYWWRF e3 AIXX 12.2. Top Marking Explanation Line 1 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Line 2 Marking: YY = Year WW = Workweek Si86 = Isolator product series XY = Channel Configuration X = # of data channels (2, 1) Y = # of reverse channels (1, 0) S = Speed Grade (max data rate) and operating mode: A = 1 Mbps (default output = low) B = 150 Mbps (default output = low) D = 1 Mbps (default output = high) E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. R = Product (OPN) Revision F = Wafer Fab Line 3 Marking: 34 Circle = 1.1 mm Diameter Left-Justified “e3” Pb-Free Symbol. First two characters of the manufacturing code. A = Assembly Site I = Internal Code XX = Serial Lot Number Last four characters of the manufacturing code. Rev. 1.3 Si8610/20/21/22 DOCUMENT CHANGE LIST Revision 1.1 to Revision 1.2 Revision 0.1 to Revision 0.2 Updated Table 12 on page 20. Deleted Added chip graphics on page 1. Moved Tables 1 and 11 to page 17. Updated Table 6, “Insulation and Safety-Related Specifications,” on page 14. Updated Table 8, “IEC 60747-5-2 Insulation Characteristics for Si86xxxx*,” on page 15. Moved Table 12 to page 20. Moved “Typical Performance Characteristics” to page 23. Updated "4. Pin Descriptions (Wide-Body SOIC)" on page 25. Updated "5. Pin Descriptions (Narrow-Body SOIC)" on page 26. Updated "6. Ordering Guide" on page 27. reference to EN. Updated "6. Ordering Guide" on page 27 to include MSL2A. Revision 1.2 to Revision 1.3 Updated Table 11 on page 17. Added junction temperature spec. Updated "3.3.1. Supply Bypass" on page 22. Removed “3.3.2. Pin Connections” on page 22. Updated "6. Ordering Guide" on page 27. Removed Rev A devices. Updated "7. Package Outline: 16-Pin Wide Body SOIC" on page 28. Updated Top Marks. Added revision description. Revision 0.2 to Revision 0.3 Added chip graphics on page 1. Moved Tables 1 and 2 to page 17. Updated Table 6, “Insulation and Safety-Related Specifications,” on page 14. Updated Table 8, “IEC 60747-5-2 Insulation Characteristics for Si86xxxx*,” on page 15. Moved Table 12 to page 20. Moved Table 13 to page 27. Moved “Typical Performance Characteristics” to page 23. Updated "4. Pin Descriptions (Wide-Body SOIC)" on page 25. Updated "5. Pin Descriptions (Narrow-Body SOIC)" on page 26. Updated "6. Ordering Guide" on page 27. Revision 0.3 to Revision 1.0 Updated “Table 3. Electrical Characteristics”. Reordered spec tables to conform to new convention. Removed “pending” throughout document. Revision 1.0 to Revision 1.1 Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 8. Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 11. Rev. 1.3 35 Si8610/20/21/22 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 36 Rev. 1.3