Si53019 A01A

S i 5 3 0 1 9 - A 01A
19-O U TP U T PCI E G EN 3 B UFFER
Features







Nineteen 0.7 V current-mode,
HCSL PCIe Gen 3 outputs
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
9 selectable SMBus addresses
Fixed external feedback path
8 dedicated OE pin
PLL or bypass mode








Spread spectrum tolerable
50 ps output-to-output skew
Fixed 0 ps input to output delay
Low phase jitter (Intel QPI, PCIe
Gen 1/Gen 2/Gen 3/Gen 4
common clock compliant
Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
Package: 72-pin QFN
Ordering Information:
See page 32.
Applications
Copyright © 2016 by Silicon Laboratories
17
18
DIF_12
DIF_12
DIF_13
DIF_13
VDD
OE12
DIF_14
DIF_14
VDD
DIF_16
DIF_16
DIF_15
DIF_15
GND
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
Si53019-A01A
VDD
VDD
GND
OE8
DIF_8
DIF_8
OE7
DIF_7
DIF_7
OE6
DIF_5
DIF_5
OE5
DIF_6
DIF_6
DIF_3
DIF_3
DIF_4
DIF_4
OE11
DIF_11
DIF_11
OE10
DIF_10
DIF_10
OE9
DIF_9
DIF_9
33
34
35
36
FB_OUT
FB_OUT
68
67
66
65
64
63
62
61
60
59
58
57
56
55
72 DIF_18
71 DIF_18
70 DIF_17
69 DIF_17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
The Si53019-A01A is a 19-output, current mode HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1900Z specification. The device is optimized for distributing reference
clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/
Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel
SMI) applications. The VCO of the device is optimized to support
100 MHz and 133 MHz operation. Each differential output can be enabled
through I2C for maximum flexibility and power savings. Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at www.silabs.com/pcie-learningcenter.
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
VDDR
CLK_IN
CLK_IN
SA_0
SDA
SCL
SA_1
FB_IN
FB_IN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDA
GNDA
IREF
Description
Rev. 1.4 2/16
Pin Assignments
Data Center
 Network Security

DIF_0
DIF_0
VDD
DIF_1
DIF_1
DIF_2
DIF_2
Server
 Storage

Patents pending
Si53019-A01A
Si53019-A01A
Functional Block Diagram
OE(5_12)
8
FB_OUT
FB_IN
FB_IN
SSC Compatible
PLL
CLK_IN
DIF_[18:0]
CLK_IN
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
Control
Logic
IREF
2
Rev. 1.4
Si53019-A01A
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Pin Descriptions: 72-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9.1. 10x10 mm 72-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.4
3
Si53019-A01A
1. Electrical Specifications
Table 1. DC Operating Characteristics1
VDD_A = 3.3 V±5%, VDD = 3.3 V±5%
Parameter
Symbol
Test Condition
Min
Max
Unit
VDD/VDD_A
3.3 V ±5%
3.135
3.465
V
3.3 V Input High Voltage
VIH
VDD
2.0
VDD+0.3
V
3.3 V Input Low Voltage
VIL
VSS–0.3
0.8
V
2
IIL
0 < VIN < VDD
–5
+5
µA
3.3 V Input High Voltage3
VIH_FS
VDD
0.7
VDD+0.3
V
3
VIL_FS
VSS–0.3
0.35
V
3.3 V Input Low Voltage
VIL_Tri
0
0.9
V
3.3 V Input Med Voltage
VIM_Tri
1.3
1.8
V
VIH_Tri
2.4
VDD
V
3.3 V Core Supply Voltage
Input Leakage Current
3.3 V Input Low Voltage
3.3 V Input High Voltage
4
VOH
IOH = –1 mA
2.4
—
V
Voltage4
VOL
IOL = 1 mA
—
0.4
V
5
CIN
2.5
4.5
pF
Output Capacitance5
COUT
2.5
4.5
pF
Pin Inductance
LPIN
—
7
nH
–40
85
°C
3.3 V Output High Voltage
3.3 V Output Low
Input Capacitance
Ambient Temperature
TA
No Airflow
Notes:
1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS thresholds levels over full operating range.
4. Signal edge is required to be monotonic when transitioning through this region.
5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.4
Si53019-A01A
Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1
Parameter
Symbol
Clock Stabilization Time2
Long Term Accuracy3,4,5
CLK 100 MHz, 133 MHz
Unit
Min
Typ
Max
TSTAB
—
1.5
1.8
ms
LACC
—
—
100
ppm
3,4,6
TABS
9.94900
—
10.05100
ns
Absolute Host CLK Period (133 MHz)3,4,6
TABS
7.44925
7.55075
ns
Slew Rate3,4,7
Edge_rate
1.0
3.0
4.0
V/ns
Slew Rate Matching3,8,10,11
TRISE_MAT/
TFALL_MAT
—
7
20
%
Rise Time Variation3,8,9
∆ Trise
—
—
125
ps
Fall Time Variation3,8,9
∆ Tfall
—
—
125
ps
Voltage High (typ 0.7 V)3,8,12
VHIGH
660
750
850
mV
Voltage Low (typ 0.7 V)3,8,13
VLOW
–150
15
150
mV
Absolute Host CLK Period (100 MHz)
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100  transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85 
transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV
to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of
the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic
through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
Rev. 1.4
5
Si53019-A01A
Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued)
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Min
Typ
Max
Maximum Voltage8
VMAX
—
850
1150
mV
Minimum Voltage3,8,14,15,16
VMIN
–300
—
—
mV
Absolute Crossing Point Voltages
VoxABS
250
450
550
mV
Total Variation of Vcross Over All
Edges3,8,18
Total ∆ Vox
—
14
140
mV
Vswing
300
—
—
mV
DC
45
—
55
%
Vovs
—
—
VHigh + 0.3
V
Vuds
—
—
VLow – 0.3
V
Vrb
0.2
—
N/A
V
Vswing4
Duty Cycle3,4
Maximum Voltage (Overshoot)3,8,19
Maximum Voltage
(Undershoot)3,8,20
Ringback Voltage3,8
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100  transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85 
transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV
to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of
the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic
through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
6
Rev. 1.4
Si53019-A01A
Table 3. SMBus Characteristics
Parameter
Symbol
Min
Max
Unit
VILSMB
—
0.8
V
SMBus Input High Voltage1
VIHSMB
2.1
VDDSMB
V
SMBus Output Low Voltage1
VOLSMB
@ IPULLUP
—
0.4
V
Nominal Bus Voltage1
VDDSMB
@ VOL
2.7
5.5
V
IPULLUP
3 V to 5 V +/–10%
4
—
mA
SCLK/SDAT Rise Time1
tRSMB
(Max VIL – 0.15) to (Min VIH + 0.15)
—
1000
ns
SCLK/SDAT Fall Time1
tFSMB
(Min VIH + 0.15) to (Max VIL – 0.15)
—
300
ns
fMINSMB
Minimum Operating Frequency
—
100
kHz
Min
Typ
Max
Unit
100 MHz, CL = Full Load, Rs=33 
—
310
350
mA
All differential pairs tri-stated
—
6
15
mA
SMBus Input Low Voltage
SMBus sink
1
Current1
SMBus Operating Frequency1,2
Test Condition
Notes:
1. Guaranteed by design and characterization.
2. The differential input clock must be running for the SMBus to be active.
Table 4. Current Consumption
TA = -40–85 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Operating Current
Symbol
IDDVDD
Power Down Current IDDVDDPD
Test Condition
Rev. 1.4
7
Si53019-A01A
Table 5. Clock Input Parameters
TA = -40–85 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input High Voltage
VIHDIF
Differential Inputs
(singled-ended measurement)
600
800
1150
mV
Input Low Voltage
VIHDIF
Differential Inputs
(singled-ended measurement)
Vss-300
0
300
mV
Input Common Mode
Voltage
Vcom
Common mode input voltage
300
—
1000
mV
Input Amplitude
Vswing
Peak to Peak Value
300
—
1450
mV
Input Slew Rate
dv/dt
Measured differentially
0.4
—
8
V/ns
Measurement from differential wave
form
45
50
55
%
Input Duty Cycle
Input Jitter—Cycle to
Cycle
JDFin
Differential measurement
—
—
125
ps
Input Frequency
Fibyp
VDD = 3.3 V, bypass mode
33
—
150
MHz
FiPLL
VDD = 3.3 V, 100 MHz PLL Mode
90
100
110
MHz
FiPLL
VDD = 3.3 V, 133.33 MHz PLL Mode
120
133.33
147
MHz
fMODIN
Triangle Wave modulation
30
31.5
33
kHz
Input SS Modulation
Rate
8
Rev. 1.4
Si53019-A01A
Table 6. Output Skew, PLL Bandwidth and Peaking
TA = -40–85 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Test Condition
Min
TYP
Max
Unit
–100
20
100
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value1,2,3,4
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
Nominal Value2,4,5
2.5
3.4
4.5
ns
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL Mode
Over voltage and temperature2,4,5
–50
0
50
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in Bypass Mode
Over voltage and temperature2,4,5
–250
—
250
ps
CLK_IN, DIF[x:0]
Random differential spread spectrum tracking
error between 2 DB1900Z devices in Hi BW Mode
—
15
75
ps
CLK_IN, DIF[x:0]
Random differential tracking error between 2
DB1900Z devices in Hi BW Mode
—
3
5
ps
(rms)
DIF[18:0]
Output-to-Output Skew across all Outputs
(Common to Bypass and PLL Mode)1,2,3,4,5
0
20
50
ps
PLL Jitter Peaking
(HBW_BYPASS_LBW = 0)6
—
0.4
2.0
dB
PLL Jitter Peaking
(HBW_BYPASS_LBW = 1)6
—
0.1
2.5
dB
PLL Bandwidth
(HBW_BYPASS_LBW = 0)
7
—
0.7
1.4
MHz
PLL Bandwidth
(HBW_BYPASS_LBW = 1)7
—
2
4
MHz
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge
created by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called
PLL jitter peaking.
7. Measured at 3 db down or half power point.
Rev. 1.4
9
Si53019-A01A
Table 7. Phase Jitter
Parameter
Phase Jitter
PLL Mode
Test Condition
Min
Typ
Max
Unit
—
30
86
ps
PCIe Gen 2 Low Band, Common Clock
F < 1.5 MHz1,3,4,5
—
1.0
3.0
ps
(RMS)
PCIe Gen2 High Band, Common Clock
1.5 MHz < F < Nyquist1,3,4,5
—
2.6
3.1
ps
(RMS)
PCIe Gen 3, Common Clock
(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5
—
0.6
1.0
ps
(RMS)
PCIe Gen 3 Separate Reference No Spread, SRNS
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,3,4,5
—
0.42
0.71
ps
(RMS)
PCIe Gen 4, Common Clock
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8
—
0.6
1.0
ps
(RMS)
Intel® QPI & Intel SMI
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7
—
0.25
0.5
ps
(RMS)
Intel QPI & Intel SMI
(8 Gb/s, 100 MHz, 12 UI)1,6
—
0.17
0.3
ps
(RMS)
Intel QPI & Intel SMI
(9.6 Gb/s, 100 MHz, 12 UI)1,6
—
0.15
0.2
ps
(RMS)
1,2,3
PCIe Gen 1, Common Clock
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
10
Rev. 1.4
Si53019-A01A
Table 7. Phase Jitter (Continued)
Additive Phase Jitter
Bypass Mode
PCIe Gen 11,2,3
—
4
—
ps
PCIe Gen 2 Low Band
F < 1.5 MHz1,3,4,5
—
0.08
—
ps
(RMS)
PCIe Gen 2 High Band
1.5 MHz < F < Nyquist1,3,4,5
—
1
—
ps
(RMS)
PCIe Gen 3
(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5
—
0.27
—
ps
(RMS)
PCIe Gen 4, Common Clock
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8
—
0.27
—
ps
(RMS)
Intel QPI & Intel® SMI
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7
—
0.25
—
ps
(RMS)
Intel QPI & Intel® SMI
(8 Gb/s, 100 MHz, 12 UI)1,6
—
0.08
—
ps
(RMS)
Intel QPI & Intel® SMI
(9.6 Gb/s, 100 MHz, 12 UI)1,6
—
0.07
—
ps
(RMS)
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.4
11
Si53019-A01A
Table 8. Clock Periods Differential Clock Outputs with SSC Disabled
SSC OFF
Center
Freq, MHz
Measurement Window
1 Clock
1 µs
0.1 s
-ppm
-C-C Jitter
-SSC
Long
AbsPer
Short
Min
Term AVG Term AVG
Min
Min
0.1 s
Unit
0.1 s
1 µs
0 ppm
Period
Nominal
+SSC
+ppm
Short
Long
Term AVG Term AVG
Max
Max
1 Clock
+C-C
Jitter
AbsPer
Max
100.00
9.94900
9.99900
10.00000
10.00100
10.05100
ns
133.33
7.44925
7.49925
7.50000
7.50075
7.55075
ns
Table 9. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Center
Freq, MHz
Measurement Window
1 Clock
1 µs
0.1 s
-ppm
-SSC
Long
Short
Term AVG Term AVG
Min
Min
-C-C
Jitter
AbsPer
Min
0.1 s
0.1 s
Unit
1 µs
0 ppm
Period
Nominal
+SSC
+ppm
Short
Long
Term AVG Term AVG
Max
Max
1 Clock
+C-C
Jitter
AbsPer
Max
99.75
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
ns
133.00
7.44930
7.49930
7.51805
7.51880
7.51955
7.53830
7.58830
ns
Table 10. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
3.3 V Core Supply Voltage1
VDD/VDD_A
—
4.6
V
3.3 V Input High Voltage1,2
VIH
—
VDD+0.5 V
V
VIL
–0.5
—
V
Storage Temperature1
ts
–65
150
°C
Input ESD protection3
ESD
2000
—
V
3.3 V Input Low Voltage
1
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum VIH is not to exceed maximum VDD.
3. Human body model.
12
Rev. 1.4
Si53019-A01A
2. Functional Description
OE(5_12)
8
FB_OUT
FB_IN
FB_IN
SSC Compatible
PLL
CLK_IN
DIF_[18:0]
CLK_IN
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
Control
Logic
IREF
Figure 1. Si53019-A01A Functional Block Diagram
Table 11. Functionality at Power Up (PLL Mode)
100M_133M
CLK_IN
(MHz)
Conditions
1
100
CLK_IN
0
133.33
CLK_IN
Table 12. PLL Operating Mode Readback Table
HBW_BYPASS_LBW
Byte 0, Bit 7
Byte 0, Bit 6
Mode
Low
0
0
PLL Low BW
Mid (Bypass)
0
1
Bypass
High
1
1
PLL High BW
Rev. 1.4
13
Si53019-A01A
Table 13. Tri-Level Input Thresholds
Parameter
Voltage
Low
<0.8 V
Mid
1.2<Vin<1.8 V
High
Vin>2.2 V
Table 14. Power Connections
Description
Pin Number
VDD
GND
1
2
Analog PLL
8
7
Analog Input
21,31,45,58,68
26,44,63
DIF Outputs
Note: TA = -40–85 °C; supply voltage VDD = 3.3 V ±5%
Table 15. SMBus Addressing
Pin
14
SMBus Address
SMB_A1
SMB_A0
0
0
D8
0
M
DA
0
1
DE
M
0
C2
M
M
C4
M
1
C6
1
0
CA
1
M
CC
1
1
CE
Rev. 1.4
Si53019-A01A
2.1. CLK_IN, CLK_IN
The differential input clock is expected to be sourced from a clock synthesizer or PCH.
2.2. 100M_133M—Frequency Selection
The Si53019-A01A is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.
100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.
Note that the CLK_IN frequency must be equal to the CLK_OUT frequency, meaning Si53019-A01A is operated in
1:1 mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pulldown resistor is attached to this pin to select the input/output frequency. The functionality is summarized in
Table 16.
Table 16. Frequency Program Table
100M_133M
Optimized Frequency (DIF_IN = DIF_x)
0
133.33 MHz
1
100.00 MHz
Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.
2.3. SA_0, SA_1—Address Selection
SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53019-A01A. The two
tri-level input pins can configure the device to nine different addresses.
Table 17. SMBus Address Table
SA_1
SA_0
SMBus Address
L
L
D8
L
M
DA
L
H
DE
M
L
C2
M
M
C4
M
H
C6
H
L
CA
H
M
CC
H
H
CE
Rev. 1.4
15
Si53019-A01A
2.4. CKPWRGD/PWRDN
CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to
indicating a power-down condition. CKPWRGD (assertion) is used by the Si53019-A01A to sample initial
configurations, such as frequency select condition and SA selections. After CKPWRGD has been asserted high for
the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and
instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When
entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to
ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior
to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal
behavior and will meet all AC and DC parameters.
Note: The assertion and deassertion of PWRDN is absolutely asynchronous.
Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.
Operation in this mode may result in glitches, excessive frequency shifting, etc.
Table 18. CKPWRGD/PWRDN Functionality
CKPWRGD/
PWRDN
DIF_IN/
DINF_IN#
SMBus
EN bit
OE# Pin
DIF(5:12)
DIF(5:12)#
Other DIF/
DIF#
FBOUT_NC/
FBOUT_NC#
PLL State
0
X
X
X
Hi-Z*
Hi-Z*
Hi-Z*
OFF
1
Running
0
X
Hi-Z*
Hi-Z*
Running
ON
1
0
Running
Running
Running
ON
1
1
Hi-Z*
Running
Running
ON
*Note: Due to external pull down resistors, Hi-Z results in Low/Low on the True/Complement outputs.
16
Rev. 1.4
Si53019-A01A
2.4.1. PWRDN Assertion
When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held Tristate/Tri-state on the next DIF high-to-low transition. The device will put all outputs in high impedance mode, and
all outputs will be pulled low by the external terminating resistors.
PWRDWN
DIF
DIF
Figure 2. PWRDN Assertion
2.4.2. CKPWRGD Assertion
The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion
of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs
stopped in a Tri-state/Tri-state condition resulting from power down must be driven high in less than 300 µs of
PWRDN deassertion to a voltage greater than 200 mV.
Tstable
<1.8 ms
PWRGD
DIF
DIF
Tdrive_Pwrdn#
<300 µs; > 200 mV
Figure 3. PWRDG Assertion (Pwrdown—Deassertion)
Rev. 1.4
17
Si53019-A01A
2.5. HBW_BYPASS_LBW
The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri
signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In
PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In the case of PLL mode, the input clock is
passed through a PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be
selected by asserting the HBW_BYPASS_LBW input pin to the appropriate level described in Table 19.
Table 19. PLL Bandwidth and Readback Table
HBW_BYPASS_LBW Pin
Mode
Byte 0, Bit 7
Byte 0, Bit 6
L
LBW
0
0
M
BYPASS
0
1
H
HBW
1
1
The Si53019-A01A has the ability to override the latch value of the PLL operating mode from hardware strap Pin 5
via the use of Byte 0 and Bits 2 and 1. Byte 0 Bit 3 must be set to 1 to allow the user to change Bits 2 and 1,
affecting the PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will
have to be accomplished if the user changes these bits.
2.6. Miscellaneous Requirements
Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)
functionality is optional.
Logic Levels: SMBus logic levels are based on a percentage of VDD for the controller and other devices on the
bus. Assume all devices are based on a 3.3 V supply.
Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock
stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than
this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all
data transfers can be completed as specified without the use of clock/data stretching.
General Call: It is assumed that the clock buffer will not have to respond to the “general call.”
Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in
Section 3 of the SMBus 2.0 specification.
Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual
data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board
designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range.
Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock
driver plus one/two more SMBus devices on the platform for capacitive loading purposes.
Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock
buffer is specified as a standard mode device and is not required to support this feature. However, it is considered
a good design practice to include the filters.
PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the
device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and
in the data sheet.
18
Rev. 1.4
Si53019-A01A
3. Test and Measurement Setup
3.1. Input Edge
Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53019A01A is guaranteed to meet all performance specifications.
Table 20. Input Edge Rate
Frequency
Min
Max
Unit
100 MHz
0.35
N/A
V/ns
133 MHz
0.35
N/A
V/ns
3.1.1. Measurement Points for Differential
Slew_fall
Slew_rise
+150 mV
+150 mV
0.0 V
V_swing
0.0 V
-150 mV
-150 mV
Diff
Figure 4. Measurement Points for Rise Time and Fall Time
Vovs
VHigh
Vrb
Vrb
VLow
Vuds
Figure 5. Single-ended Measurement Points for Vovs, Vuds, Vrb
Rev. 1.4
19
Si53019-A01A
TPeriod
Low Duty Cycle %
High Duty Cycle %
Skew measurement
point
0.000 V
Figure 6. Differential (CLOCK–CLOCK) Measurement Points (Tperiod, Duty Cycle, Jitter)
3.2. Termination of Differential Outputs
All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source
terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be
supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC
clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond
200 MHz, trace lengths must be restricted to avoid signal integrity problems.
Table 21. Differential Output Termination
Clock
IREF ( )
Board Trace Impedance
Rs
Rp
Unit
DIFF Clocks—50  configuration
475
100
33+5%
50

DIFF Clocks—43  configuration
412
85
27+5%
42.2 or 43.2

3.2.1. Termination of Differential Current Mode HCSL Outputs
10 inches
RS
Differential Zo
2pF
RP
RP
RS
Figure 7. 0.7 V Configuration Test Load Board Termination
20
Rev. 1.4
2pF
Si53019-A01A
4. Control Registers
4.1. Byte Read/Write
Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register
number.
4.1.1. Byte Read
The standard byte read is as shown in Figure 8. It is an extension of the byte write. The write start condition is
repeated; then the slave device starts sending data, and the master acknowledges it until the last byte is sent. The
master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the
command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte
must be the byte transfer count.
1
7
T Slave
1 1
8
Wr A Command
Command
starT
Condition
1 1
7
A r Slave
Register # to
read
2 x 7 bit = 1
1 1
8
1 1
Rd A Data Byte 0 N P
repeat starT
Acknowledge
Master to
Byte Read Protocol
Not ack
stoP
Condition
Slave to
Figure 8. Byte Read Protocol
4.1.2. Byte Write
Figure 9 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.
For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count.
The count can be between 1 and 32. It is not allowed to be zero or to exceed 32.
1
7
T Slave
Command
starT Condition
1 1
8
Wr A Command
Register # to
write
2 x 7 bit = 1
1
8
1 1
A Data Byte 0 A P
Acknowledge
Byte Write Protocol
stoP Condition
Master to
Slave to
Figure 9. Byte Write Protocol
Rev. 1.4
21
Si53019-A01A
4.2. Block Read/Write
4.2.1. Block Read
After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The
slave acknowledges the register index in the command byte. The master sends a repeat start function. After the
slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master
acknowledges each byte except the last and sends a stop function.
1
7
T Slave
1 1
8
1 1
7
Wr A Command Code A r Slave
Command
starT
Condition
8
1
Data Byte A
1 1
Rd A
Register # to
repeat starT
read
Acknowledge
2 x 7 bit = 1
8
1
8
1 1
Data Byte 0 A Data Byte 1 N P
Master to
Slave to
Not acknowledge
stoP Condition
Block Read Protocol
Figure 10. Block Read Protocol
4.2.2. Block Write
After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The
lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will
be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the
master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this
byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte
received. The transfer is terminated after the slave sends the ACK and the master sends a stop function.
1
7
1 1
T Slave Address Wr A
Command bit
starT
Condition
8
Command
Register # to
write
2 x 7 bit = 0
1
A
Master to
Slave to
Acknowledge
1
8
1
8
1 1
8
Byte Count = 2 A Data Byte 0 A Data Byte 1 A P
stoP Condition
Block Write Protocol
Figure 11. Block Write Protocol
22
Rev. 1.4
Si53019-A01A
4.3. Control Registers
Table 22. Byte 0: PLL Mode and Frequency Select Register
Bit
Pin #
Name
Control Function
0
1
Type
Default
0
4
100M_133M#
Frequency Select
Readback
133 MHz
100 MHz
R
Latch
1
reserved
0
2
reserved
0
3
67/66 Output Enable DIF 16
Output control,
overrides OE# pin
1
4
70/69 Output Enable DIF 17
Output control,
overrides OE# pin
1
5
72/71 Output Enable DIF 18
Output control,
overrides OE# pin
1
6
5
PLL Mode 0
PLL operating mode
readback 0
7
5
PLL Mode1
PLL operating mode
readback 1
See PLL operating
mode readback table
R
Latch
R
Latch
Table 23. Byte 1: Output Enable Control Register
Bit
Pin #
Description
If Bit = 0
If Bit = 1
Type
Default
0
19/20
Output Enable DIF 0
Output control,
overrides OE# pin
Hi-Z
Enabled
RW
1
1
22/23
Output Enable DIF 1
Output control,
overrides OE# pin
RW
1
2
24/25
Output Enable DIF 2
Output control,
overrides OE# pin
RW
1
3
27/28
Output Enable DIF 3
Output control,
overrides OE# pin
RW
1
4
29/30
Output Enable DIF 4
Output control,
overrides OE# pin
RW
1
5
32/33
Output Enable DIF 5
Output control,
overrides OE# pin
RW
1
6
35/36
Output Enable DIF 6
Output control,
overrides OE# pin
RW
1
7
39/38
Output Enable DIF 7
Output control,
overrides OE# pin
RW
1
Rev. 1.4
23
Si53019-A01A
Table 24. Byte 2: Output Enable Control Register
Bit
Pin #
Description
Control Function
If Bit = 0
If Bit = 1
Type
Default
0
42/41
Output Enable DIF 8
Output control,
overrides OE# pin
Hi-Z
Enabled
RW
1
1
47/46
Output Enable DIF 9
Output control,
overrides OE# pin
RW
1
2
50/49
Output Enable DIF 10
Output control,
overrides OE# pin
RW
1
3
53/52
Output Enable DIF 11
Output control,
overrides OE# pin
RW
1
4
56/55
Output Enable DIF 12
Output control,
overrides OE# pin
RW
1
5
60/59
Output Enable DIF 13
Output control,
overrides OE# pin
RW
1
6
62/61
Output Enable DIF 14
Output control,
overrides OE# pin
RW
1
7
65/64
Output Enable DIF 15
Output control,
overrides OE# pin
RW
1
If Bit = 1
Type
Default
OE# pin
High
R
Real
Time
Table 25. Byte 3: Output Enable Pin Status Readback Register
Bit
Pin #
Description
0
34
OE_RB5
Real time readback OE# pin Low
of OE5
1
37
OE_RB6
Real time readback
of OE6
R
Real
Time
2
40
OE_RB7
Real time readback
of OE7
R
Real
Time
3
43
OE_RB8
Real time readback
of OE8
R
Real
Time
4
48
OE_RB9
Real time readback
of OE9
R
Real
Time
5
51
OE_RB10
Real time readback
of OE10
R
Real
Time
6
54
OE_RB11
Real time readback
of OE11
R
Real
Time
7
57
OE_RB12
Real time readback
of OE12
R
Real
Time
24
Control Function
Rev. 1.4
If Bit = 0
Si53019-A01A
Table 26. Byte 4: Reserved Control Register
Bit
Pin #
Description
Control Function
If Bit = 0
If Bit = 1
Type
Default
0
Reserved
0
1
Reserved
0
2
Reserved
0
3
Reserved
0
4
Reserved
0
5
Reserved
0
6
Reserved
0
7
Reserved
0
Table 27. Byte 5: Vendor/Revision Identification Control Register
Bit
Pin #
Description
Control Function
0
—
Vendor ID Bit 0
Vendor ID
1
—
2
Type
Default
R
1
Vendor ID Bit 1
R
0
—
Vendor ID Bit 2
R
0
3
—
Vendor ID Bit 3
R
0
4
—
Revision Code Bit 0
R
X
5
—
Revision Code Bit 1
R
X
6
—
Revision Code Bit 2
R
X
7
—
Revision Code Bit 3
R
X
Type
Default
Revision ID
If Bit = 0
If Bit = 1
–A01A = 0001
–A02A = 0010
Table 28. Byte 6: Device ID Control Register
Bit
Pin #
Description
Control Function
0
—
Device ID 0
R
1
1
—
Device ID 1
R
1
2
—
Device ID 2
R
0
3
—
Device ID 3
R
1
4
—
Device ID 4
R
1
5
—
Device ID 5
R
0
6
—
Device ID 6
R
1
7
—
Device ID 7 (MSB)
R
1
Rev. 1.4
If Bit = 0
If Bit = 1
25
Si53019-A01A
Table 29. Byte 7: Byte Count Register
Bit
Pin #
Description
0
—
BC0
1
—
BC1
2
—
3
4
26
Control Functions
If Bit = 0
If Bit = 1
Type
Default
RW
0
RW
0
BC2
RW
0
—
BC3
RW
1
—
BC4
RW
0
Writing to this register
Default value is 8 hex,
configures how many
so 9 bytes (0 to 8) will
bytes will be read back. be read back by default.
5
Reserved
0
6
Reserved
0
7
Reserved
0
Rev. 1.4
Si53019-A01A
DIF_12
DIF_12
DIF_14
DIF_14
VDD
DIF_16
DIF_16
DIF_15
DIF_15
GND
DIF_13
DIF_13
VDD
OE12
48
47
46
45
44
43
42
41
40
39
38
37
Rev. 1.4
VDD
DIF_11
DIF_11
OE10
DIF_10
DIF_10
OE9
DIF_9
DIF_9
VDD
GND
OE8
DIF_8
DIF_8
OE7
DIF_7
DIF_7
OE6
DIF_5
DIF_5
OE5
DIF_6
DIF_6
DIF_4
DIF_4
DIF_3
DIF_3
OE11
33
34
35
36
Si53019-A01A
GND
FB_OUT
FB_OUT
17
18
54
53
52
51
50
49
19
20
21
22
23
24
25
26
27
28
29
30
31
32
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
VDDR
CLK_IN
CLK_IN
SA_0
SDA
SCL
SA_1
FB_IN
FB_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIF_0
DIF_0
VDD
DIF_1
DIF_1
DIF_2
DIF_2
VDDA
GNDA
IREF
68
67
66
65
64
63
62
61
60
59
58
57
56
55
72 DIF_18
71 DIF_18
70 DIF_17
69 DIF_17
5. Pin Descriptions: 72-Pin QFN
27
Si53019-A01A
Table 30. Si53019-A01A 72-Pin QFN Descriptions
Pin #
Name
Type
1
VDDA
3.3 V 3.3 V power supply for PLL.
2
GNDA
GND
Ground for PLL.
3
IREF
OUT
This pin establishes the reference for the differential current mode output
pairs. It requires a fixed precision resistor to ground. 475  is the
standard value for 100  differential impedance. Other impedances
require different values.
4
100M_133M
I,SE
3.3 V tolerant inputs for input/output frequency selection. An external pullup or pull-down resistor is attached to this pin to select the input/output
frequency.
High = 100 MHz output
Low = 133 MHz output
5
HBW_BYPASS_LBW
I, SE
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
Med = Bypass mode
Low = Low BW mode
6
PWRGD/PWRDN
I
7
GND
GND
Ground for outputs.
8
VDDR
VDD
3.3 V power supply for differential input receiver. This VDDR should be
treated as an analog power rail and filtered appropriately.
9
CLK_IN
I, DIF 0.7 V Differential TRUE input.
10
CLK_IN
I, DIF 0.7 V Differential input.
11
SA_0
I,PU
12
SDA
I/O
Open collector SMBus data.
13
SCL
I/O
SMBus slave clock input.
14
SA_1
I,PU
15
FB_IN
I/O
True differential feedback input. Provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
16
FB_IN
I/O
Complementary differential feedback input. Provides feedback signal to
the PLL for synchronization with the input clock to eliminate phase error.
17
FB_OUT
I/O
Complementary differential feedback output, provides feedback signal to
the PLL for synchronization with input clock to eliminate phase error.
18
FB_OUT
I/O
True differential feedback output, provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
19
DIF_0
O, DIF 0.7 V Differential TRUE clock output.
20
DIF_0
O, DIF 0.7 V Differential Complimentary clock output.
21
VDD
22
DIF_1
28
VDD
Description
3.3 V LVTTL input to power up or power down the device.
3.3 V LVTTL input selecting the address. Tri-level input.
3.3 V LVTTL input selecting the address. Tri-level input.
Power supply for differential outputs.
O, DIF 0.7 V Differential TRUE clock output.
Rev. 1.4
Si53019-A01A
Table 30. Si53019-A01A 72-Pin QFN Descriptions
Pin #
Name
Type
23
DIF_1
O, DIF 0.7 V Differential Complimentary clock output.
24
DIF_2
O, DIF 0.7 V Differential TRUE clock output.
25
DIF_2
O, DIF 0.7 V Differential Complimentary clock output.
26
GND
27
DIF_3
O, DIF 0.7 V Differential TRUE clock output.
28
DIF_3
O, DIF 0.7 V Differential Complimentary clock output.
29
DIF_4
O, DIF 0.7 V Differential TRUE clock output.
30
DIF_4
O, DIF 0.7 V Differential Complimentary clock output.
31
VDD
32
DIF_5
O, DIF 0.7 V Differential TRUE clock output.
33
DIF_5
O, DIF 0.7 V Differential Complimentary clock output.
34
OE5
35
DIF_6
O, DIF 0.7 V Differential TRUE clock output.
36
DIF_6
O, DIF 0.7 V Differential Complimentary clock output.
37
OE6
38
DIF_7
O, DIF 0.7 V Differential TRUE clock output.
39
DIF_7
O, DIF 0.7 V Differential Complimentary clock output.
40
OE7
41
DIF_8
O, DIF 0.7 V Differential TRUE clock output.
42
DIF_8
O, DIF 0.7 V Differential Complimentary clock output.
43
OE8
IN
44
GND
GND
45
VDD
3.3 V 3.3 V power supply
46
DIF_9
O, DIF 0.7 V Differential TRUE clock output.
47
DIF_9
O, DIF 0.7 V Differential Complimentary clock output.
48
OE9
49
DIF_10
GND
Description
Ground for outputs.
3.3 V 3.3 V power supply
IN
IN
IN
IN
Active low input for enabling DIF pair 5
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 6
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 8
1 = disable outputs, 0 = enable outputs
Ground for outputs.
Active low input for enabling DIF pair 9
1 = disable outputs, 0 = enable outputs
O, DIF 0.7 V Differential TRUE clock output.
Rev. 1.4
29
Si53019-A01A
Table 30. Si53019-A01A 72-Pin QFN Descriptions
Pin #
Name
50
DIF_10
51
OE10
52
DIF_11
O, DIF 0.7 V Differential TRUE clock output.
53
DIF_11
O, DIF 0.7 V Differential Complimentary clock output.
54
OE11
55
DIF_12
O, DIF 0.7 V Differential TRUE clock output.
56
DIF_12
O, DIF 0.7 V Differential Complimentary clock output.
57
OE12
58
VDD
59
DIF_13
O, DIF 0.7 V Differential TRUE clock output.
60
DIF_13
O, DIF 0.7 V Differential Complimentary clock output.
61
DIF_14
O, DIF 0.7 V Differential TRUE clock output.
62
DIF_14
O, DIF 0.7 V Differential Complimentary clock output.
63
GND
64
DIF_15
O, DIF 0.7 V Differential TRUE clock output.
65
DIF_15
O, DIF 0.7 V Differential Complimentary clock output.
66
DIF_16
O, DIF 0.7 V Differential TRUE clock output.
67
DIF_16
O, DIF 0.7 V Differential Complimentary clock output.
68
VDD
69
DIF_17
O, DIF 0.7 V Differential TRUE clock output.
70
DIF_17
O, DIF 0.7 V Differential Complimentary clock output.
71
DIF_18
O, DIF 0.7 V Differential TRUE clock output.
72
DIF_18
O, DIF 0.7 V Differential Complimentary clock output.
73
GND
30
Type
Description
O, DIF 0.7 V Differential Complimentary clock output.
IN
IN
IN
Active low input for enabling DIF pair 10
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 11
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 12
1 = disable outputs, 0 = enable outputs
3.3 V 3.3 V power supply
GND
Ground for outputs.
3.3 V 3.3 V power supply
GND
Ground for outputs.
Rev. 1.4
Si53019-A01A
6. Power Filtering Example
6.1. Ferrite Bead Power Filtering
Recommended ferrite bead filtering equivalent to the following:
Figure 12. Schematic Example of the Si53019-A01A Power Filtering
Rev. 1.4
31
Si53019-A01A
7. Ordering Guide
Part Number
Package Type
Temperature
Si53019-A01AGM
72-pin QFN
Extended, –40 to 85 C
Si53019-A01AGMR
72-pin QFN—Tape and Reel
Extended, –40 to 85 C
Lead-free
32
Rev. 1.4
Si53019-A01A
8. Package Outline
Figure 13 illustrates the package details for the Si53019-A01A. Table 31 lists the values for the dimensions shown
in the illustration.
Figure 13. 72-Pin Quad Flat No Lead (QFN) Package
Table 31. Package Diagram Dimensions1,2,3,4
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
E2
5.90
6.00
6.10
A1
0.00
0.02
0.05
L
0.30
0.40
0.50
b
0.18
0.25
0.30
aaa
0.10
bbb
0.10
ccc
0.08
D
D2
10.00 BSC.
5.90
6.00
6.10
e
0.50 BSC.
ddd
0.10
E
10.00 BSC.
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.4
33
Si53019-A01A
9. PCB Land Pattern
9.1. 10x10 mm 72-QFN Package Land Pattern
34
Rev. 1.4
Si53019-A01A
Table 32. PCB Land Pattern
Dimension
mm
C1
9.90
C2
9.90
E
0.50
X1
0.30
Y1
0.85
X2
6.10
Y2
6.10
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
8. A 3x3 array of 1.45 mm square openings on 2.00 mm pitch should be used for the center
ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.4
35
Si53019-A01A
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
 Updated descriptions for pin15, pin16, pin17, and
pin18 in Table 30.
Revision 1.1 to Revision 1.2
Updated Features on page 1.
Updated Description on page 1.
 Updated specs in Table 7, “Phase Jitter,” on
page 10.
 Updated the package drawing and table.


Revision 1.2 to Revision 1.3
January 20, 2016
Updated the package drawing and table.
Updated the land pattern drawing and table.
 Correct specs in Table 1 on page 4.


Revision 1.3 to Revision 1.4
February 22, 2016
 Updated operating characteristics in Table 4,
Table 5, Table 6, and Table 14.
36
Rev. 1.4
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