S i 5 3 115 15-O UTPUT PCI E G EN 3 BUFFER / Z ERO D ELAY B UFFER Features Low phase jitter (Intel® QPI, PCIe Gen 1/Gen 2/Gen 3 compliant) 100 ps input-to-output delay Extended Temperature: –40 to 85 °C 64-pin QFN Description The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Rev. 1.0 11/14 Copyright © 2014 by Silicon Laboratories GND VDD_IO DIF_10 DIF_10 Data center Enterprise switches and routers DIF_12 DIF_12 DIF_11 DIF_11 Server Storage VDD GND Pin Assignments Applications Ordering Information: See page 29. DIF_13 DIF_13 Separate VDDIO for outputs PLL or bypass mode Spread spectrum tolerable 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) GND VDD_IO DIF_14 DIF_14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Fifteen 0.7 V low-power, pushpull HCSL PCIe Gen3 outputs 100 MHz /133 MHz PLL operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch value from HW pin 9 selectable SMBUS addresses SMBus address configurable to allow multiple buffers in a single control network 3.3 V supply voltage operation VDDA GNDA 100M_133M HBW_BYPASS_LBW PWRGD / PWRDN GND VDDR CLK_IN CLK_IN SA_0 SDA SCL SA_1 FBOUT_NC FBOUT_NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Si53115 VDD_IO GND DIF_9 DIF_9 DIF_8 DIF_8 GND VDD DIF_7 DIF_7 DIF_6 DIF_6 VDD_IO GND DIF_5 DIF_5 DIF_0 17 DIF_0 18 VDD_IO 19 GND 20 DIF_1 21 DIF_1 22 DIF_2 23 DIF_2 24 GND 25 VDD 26 DIF_3 27 DIF_3 28 DIF_4 29 DIF_4 30 VDD_IO 31 GND 32 Patents pending Si53115 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). S i 5 3 11 5 Functional Block Diagram FB_OUT SSC Compatible PLL CLK_IN CLK_IN 100M_133 HBW_BYPASS_LBW SA_0 SA_1 PWRGD / PWRDN SDA SCL 2 Control Logic Rev. 1.0 DIF_[14:0] Si53115 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Pin Descriptions: 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Rev. 1.0 3 S i 5 3 11 5 1. Electrical Specifications Table 1. DC Operating Characteristics VDD_A = 3.3 V±5%, VDD = 3.3 V±5% Parameter Symbol Test Condition Min Max Unit VDD/VDD_A 3.3 V ±5% 3.135 3.465 V VDD_IO 1.05 V to 3.3 V ±5% 0.9975 3.465 V 3.3 V Input High Voltage VIH VDD 2.0 VDD+0.3 V 3.3 V Input Low Voltage VIL VSS–0.3 0.8 V 3.3 V Core Supply Voltage 3.3 V I/O Supply Input Leakage Voltage1 Current2 IIL 0 < VIN < VDD –5 +5 µA 3 3.3 V Input High Voltage VIH_FS VDD 0.7 VDD+0.3 V 3 3.3 V Input Low Voltage VIL_FS VSS–0.3 0.35 V 3.3 V Input Low Voltage VIL_Tri 0 0.8 V 3.3 V Input Med Voltage VIM_Tri 1.2 1.8 V 3.3 V Input High Voltage VIH_Tri 2.2 VDD V Voltage4 VOH IOH = –1 mA 2.4 — V 3.3 V Output Low Voltage4 VOL IOL = 1 mA — 0.4 V CIN 2.5 4.5 pF COUT 2.5 4.5 pF LPIN — 7 nH 0 70 °C 3.3 V Output High Input Capacitance Output 5 Capacitance5 Pin Inductance Ambient Temperature TA No Airflow Notes: 1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs. 2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state current requirements. 3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS thresholds levels over full operating range. 4. Signal edge is required to be monotonic when transitioning through this region. 5. Ccomp capacitance based on pad metalization and silicon device capacitance. Not including pin capacitance. 4 Rev. 1.0 Si53115 Table 2. SMBus Characteristics Parameter Symbol Test Condition Min Max Unit 0.8 V VDDSMB V 0.4 V 5.5 V 1 SMBus Input Low Voltage VILSMB SMBus Input High Voltage1 VIHSMB SMBus Output Low Voltage1 VOLSMB @ IPULLUP Nominal Bus Voltage1 VDDSMB @ VOL 2.7 Current1 IPULLUP 3 V to 5 V +/-10% 4 SCLK/SDAT Rise Time1 tRSMB (Max VIL – 0.15) to (Min VIH + 0.15) 1000 ns SCLK/SDAT Fall Time1 tFSMB (Min VIH + 0.15) to (Max VIL – 0.15) 300 ns fMINSMB Minimum Operating Frequency SMBus Sink SMBus Operating Frequency1, 2 2.1 mA 100 kHz Notes: 1. Guaranteed by design and characterization. 2. The differential input clock must be running for the SMBus to be active. Table 3. Current Consumption TA = 0–70 °C; supply voltage VDD = 3.3 V ±5% Parameter Operating Current Power Down Current Symbol Test Condition Min Typ Max Unit IDDVDD 133 MHz, VDD Rail — 25 30 mA IDDVDDA 133 MHz, VDDA + VDDR, PLL Mode — 20 25 mA IDDVDDIO 133 MHz, CL = Full Load, VDD IO Rail — 100 110 mA IDDVDDPD Power Down, VDD Rail — 0.5 1 mA IDDVDDAPD Power Down, VDDA Rail — 4 7 mA IDDVDDIOPD Power Down, VDD_IO Rail — 0.4 0.7 mA Rev. 1.0 5 S i 5 3 11 5 Table 4. Clock Input Parameters TA = 0–70 °C; supply voltage VDD = 3.3 V ±5% Parameter Symbol Test Condition Min Typ Max Unit Input High Voltage VIHDIF Differential Inputs (singled-ended measurement) 600 700 1150 mV Input Low Voltage VIHDIF Differential Inputs (singled-ended measurement) Vss300 0 300 mV Input Common Mode Voltage Vcom Common mode input voltage 300 1000 mV Input Amplitude—CLK_IN Vswing Peak to Peak Value 300 1450 mV Input Slew Rate—CLK_IN dv/dt Measured differentially 0.4 8 V/ns Measurement from differential wave form 45 55 % 125 ps 150 MHz Input Duty Cycle 50 Input Jitter—Cycle to Cycle JDFin Differential measurement Input Frequency Fibyp VDD = 3.3 V, bypass mode 33 FiPLL VDD = 3.3 V, 100 MHz PLL Mode 90 100 110 MHz FiPLL VDD = 3.3 V, 133.33 MHz PLL Mode 120 133.33 147 MHz fMODIN Triangle Wave modulation 30 31.5 33 kHz Input SS Modulation Rate 6 Rev. 1.0 Si53115 Table 5. Output Skew, PLL Bandwidth and Peaking TA = 0–70 °C; supply voltage VDD = 3.3 V ±5% Parameter Test Condition Min Typ Max Unit CLK_IN, DIF[x:0] Input-to-Output Delay in PLL Mode Nominal Value1,2,3,4 –100 18 100 ps CLK_IN, DIF[x:0] Input-to-Output Delay in Bypass Mode Nominal Value2,4,5 2.5 3.6 4.5 ns CLK_IN, DIF[x:0] Input-to-Output Delay Variation in PLL mode Over voltage and temperature2,4,5 –50 20 50 ps CLK_IN, DIF[x:0] Input-to-Output Delay Variation in Bypass Mode Over voltage and temperature2,4,5 –250 — 250 ps Output-to-Output Skew across all 15 Outputs (Common to Bypass and PLL Mode)1,2,3,4,5 0 20 50 ps PLL Jitter Peaking (HBW_BYPASS_LBW = 0)6 — 0.4 2.0 dB PLL Jitter Peaking (HBW_BYPASS_LBW = 1)6 — 0.1 2.5 dB PLL Bandwidth (HBW_BYPASS_LBW = 0) 7 — 0.7 1.4 MHz PLL Bandwidth (HBW_BYPASS_LBW = 1)7 — 2 4 MHz DIF[11:0] Notes: 1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point. 3. This parameter is deterministic for a given device. 4. Measured with scope averaging on to find mean value. 5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 7. Measured at 3 db down or half power point. Rev. 1.0 7 S i 5 3 11 5 Table 6. Phase Jitter Parameter Phase Jitter PLL Mode Additive Phase Jitter Bypass Mode Test Condition Min Typ Max Units — 29 86 ps PCIe Gen2 Low Band F < 1.5 MHz1,3,4,5 — 1.0 3.0 ps (RMS) PCIe Gen2 High Band 1.5 MHz < F < Nyquist1,3,4,5 — 1.7 3.1 ps (RMS) PCIe Gen3 (PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 — 0.45 1.0 ps (RMS) Intel® QPI & Intel SMI (4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 — 0.21 0.5 ps (RMS) Intel QPI & Intel SMI (8 Gb/s, 100 MHz, 12 UI)1,6 — 0.13 0.3 ps (RMS) Intel QPI & Intel SMI (9.6 Gb/s, 100 MHz, 12 UI)1,6 — 0.11 0.2 ps (RMS) PCIe Gen 11,2,3 — 10 — ps PCIe Gen2 Low Band F < 1.5 MHz1,3,4,5 — 1.0 — ps (RMS) PCIe Gen2 High Band 1.5 MHz < F < Nyquist1,3,4,5 — 1.0 — ps (RMS) PCIe Gen3 (PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 — 0.3 — ps (RMS) Intel QPI & Intel® SMI (4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 — 0.12 — ps (RMS) Intel QPI & Intel® SMI (8 Gb/s, 100 MHz, 12 UI)1,6 — 0.1 — ps (RMS) Intel QPI & Intel® SMI (9.6 Gb/s, 100 MHz, 12 UI)1,6 — 0.1 — ps (RMS) PCIe Gen 1 1,2,3 Notes: 1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a smaller sample size have to be extrapolated to this BER target. 2. ζ = 0.54 implies a jitter peaking of 3 dB. 3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest specification. 4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target. 8 Rev. 1.0 Si53115 Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 Parameter Symbol Clock Stabilization Time2 Long Term Accuracy3,4,5 CLK 100 MHz, 133 MHz Unit Min Typ Max TSTAB — 1.5 1.8 ms LACC — — 100 ppm 3,4,6 TABS 9.94900 — 10.05100 ns Absolute Host CLK Period (133 MHz)3,4,6 TABS 7.44925 — 7.55075 ns Edge_rate 1.0 3.0 4.0 V/ns ∆ Trise — — 125 ps ∆ Tfall — — 125 ps TRISE_MAT/TFALL_MAT — 7 20 % Voltage High (typ 0.7 V)3,8,12 VHIGH 660 750 850 mV Voltage Low (typ 0.7 V)3,8,13 VLOW –150 15 150 mV Maximum Voltage VMAX — 850 1150 mV Minimum Voltage VMIN –300 — — mV VoxABS 300 450 550 mV Total ∆ Vox — 14 140 mV DC 45 — 55 % Vovs — — VHigh + 0.3 V Absolute Host CLK Period (100 MHz) Slew Rate 3,4,7 Rise Time Variation3,8,9 Fall Time Variation 3,8,9 Rise/Fall Matching3,8,10,11 Absolute Crossing Point Voltages3,8,14,15,16 Total Variation of Vcross Over All Edges 3,8,18 Duty Cycle 3,5 Maximum Voltage (Overshoot) 3,8,19 Rev. 1.0 9 S i 5 3 11 5 Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued) Parameter Symbol CLK 100 MHz, 133 MHz Min Typ Max Unit Maximum Voltage (Undershoot) 3,8,20 Vuds — — VLow – 0.3 V Ringback Voltage Vrb 0.2 — N/A V Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the time that stable clocks are output from the buffer chip (PLL locked). 3. Test configuration is Rs = 33.2 , 2 pF for 100 transmission line; Rs = 27 , 2 pF for 85 transmission line. 4. Measurement taken from differential waveform. 5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz. 6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum specified period. 7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be monotonic through the Vol to Voh region for Trise and Tfall. 8. Measurement taken from single-ended waveform. 9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max. 10. Measured with oscilloscope, and averaging on. The difference between the rising edge rate (average) of clock verses the falling edge rate (average) of CLOCK. 11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall). 12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function. 13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function. 14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK. 15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 16. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel) Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 3–4 for further clarification). 18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the maximum allowed variance in Vcross for any particular system. 19. Overshoot is defined as the absolute value of the maximum voltage. 20. Undershoot is defined as the absolute value of the minimum voltage. 10 Rev. 1.0 Si53115 Table 8. Clock Periods Differential Clock Outputs with SSC Disabled SSC OFF Center Freq, MHz Measurement Window 1 Clock –C-C Jitter AbsPer Min 1 µs 0.1 s –ppm –SSC Long Short Term AVG Term AVG Min Min 0.1 s Unit 0.1 s 1 µs 0 ppm Period Nominal +SSC +ppm Short Long Term AVG Term AVG Max Max 1 Clock +C-C Jitter AbsPer Max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns Table 9. Clock Periods Differential Clock Outputs with SSC Enabled SSC ON Center Freq, MHz Measurement Window 1 Clock –C-C Jitter AbsPer Min 1 µs 0.1 s –ppm –SSC Long Short Term AVG Term AVG Min Min 0.1 s 0.1 s Unit 1 µs 0 ppm Period Nominal +SSC +ppm Short Long Term AVG Term AVG Max Max 1 Clock +C-C Jitter AbsPer Max 99.75 9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126 ns 133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845 ns Table 10. Absolute Maximum Ratings Parameter Symbol Min Max Unit VDD/VDD_A — 4.6 V VDD_IO — 4.6 V VIH — 4.6 V VIL −0.5 — V Storage Temperature1 ts –65 150 °C Input ESD protection3 ESD 2000 — V 3.3 V Core Supply Voltage1 3.3 V I/O Supply Voltage1 3.3 V Input High Voltage1,2 3.3 V Input Low Voltage1 Notes: 1. Consult manufacturer regarding extended operation in excess of normal DC operating parameters. 2. Maximum VIH is not to exceed maximum VDD. 3. Human body model. Rev. 1.0 11 S i 5 3 11 5 2. Functional Description 2.1. CLK_IN, CLK_IN The differential input clock is expected to be sourced from a clock synthesizer or PCH. 2.2. 100M_133M—Frequency Selection The Si53115 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz. 100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs. Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53115 is operated in 1:1 mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 11. Table 11. Frequency Program Table 100M_133M Optimized Frequency (DIF_IN = DIF_x) 0 133.33 MHz 1 100.00 MHz Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner. 2.3. SA_0, SA_1—Address Selection SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53115. These are the two tri-level input pins that can configure the device to nine different addresses. Table 12. SMBUS Address Table 12 SA_1 SA_0 SMBUS Address L L D8 L M DA L H DE M L C2 M M C4 M H C6 H L CA H M CC H H CE Rev. 1.0 Si53115 2.4. CKPWRGD/PWRDN CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to indicating a power down condition. CKPWRGD (assertion) is used by the Si53115 to sample initial configurations, such as frequency select conditions and SA selections. After CKPWRGD has been asserted high for the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering powersaving mode, PWRDN should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all AC and DC parameters. Note: The assertion and deassertion of PWRDN is absolutely asynchronous. Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended. Operation in this mode may result in glitches, excessive frequency shifting, etc. Table 13. CKPWRGD/PWRDN Functionality CKPWRGD/ PWRDN DIF_IN/ DINF_IN# SMBus EN bit DIF-x/ DIF_x# FBOUT_NC/ FBOUT_NC# PLL State 0 X X Low/Low Low/Low OFF 1 Running 0 Low/Low Running ON 1 Running Running ON Rev. 1.0 13 S i 5 3 11 5 2.4.1. PWRDN Assertion When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/ LOW on the next DIF high-to-low transition. PWRDWN DIF DIF Figure 1. PWRDN Assertion 2.4.2. CKPWRGD Assertion The power up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN deassertion to a voltage greater than 200 mV. Tstable <1.8 ms DIF DIF Tdrive_Pwrdn# <300 µs; > 200 mV Figure 2. PWRDG Assertion (Pwrdown—Deassertion) 14 Rev. 1.0 Si53115 2.5. HBW_BYPASS_LBW The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In the PLL mode, the input clock is passed through a PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be selected by asserting the HBW_BYPASS_LBW input pin to the appropriate level described in Table 14. Table 14. PLL Bandwidth and Readback Table HBW_BYPASS_LBW Pin Mode Byte 0, Bit 7 Byte 0, Bit 6 L LBW 0 0 M BYPASS 0 1 H HBW 1 1 The Si53115 has the ability to override the latch value of the PLL operating mode from hardware strap Pin 5 via the use of Byte 0 and Bits 2 and 1. Byte 0 Bit 3 must be set to 1 to allow the user to change Bits 2 and 1, affecting the PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will have to be accomplished if the user changes these bits. 2.6. Miscellaneous Requirements Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps) functionality is optional. Logic Levels: SMBus logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are based on a 3.3 V supply. Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of clock/data stretching. General Call: It is assumed that the clock buffer will not have to respond to the “general call.” Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in Section 3 of the SMBus 2.0 specification. Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range. Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock driver plus one/two more SMBus devices on the platform for capacitive loading purposes. Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock buffer is specified as a standard mode device and is not required to support this feature. However, it is considered a good design practice to include the filters. PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and in the data sheet. Rev. 1.0 15 S i 5 3 11 5 3. Test and Measurement Setup 3.1. Input Edge Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53115 is guaranteed to meet all performance specifications. Table 15. Input Edge Rate Frequency Min Max Unit 100 MHz 0.35 N/A V/ns 133 MHz 0.35 N/A V/ns 3.1.1. Measurement Points for Differential Slew_fall Slew_rise +150 mV +150 mV 0.0 V V_swing 0.0 V -150 mV -150 mV Diff Figure 3. Measurement Points for Rise Time and Fall Time Vovs VHigh Vrb Vrb VLow Vuds Figure 4. Single-ended Measurement Points for Vovs, Vuds, Vrb 16 Rev. 1.0 Si53115 TPeriod Low Duty Cycle % High Duty Cycle % Skew measurement point 0.000 V Figure 5. Differential (CLOCK–CLOCK) Measurement Points (Tperiod, Duty Cycle, Jitter) 3.2. Termination of Differential Outputs All differential outputs are to be tested into a 100 or 85 differential impedance transmission line. Source terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond 200 MHz, trace lengths must be restricted to avoid signal integrity problems. Table 16. Differential Output Termination Clock Board Trace Impedance Rs Rp Unit DIFF Clocks—50 configuration 100 33+5% N/A DIFF Clocks—43 configuration 85 27+5% N/A 3.2.1. Termination of Differential NMOS Push-Pull Type Outputs Si53115 Clock Rs T-Line 10" Typical Receiver 2 pF Source Terminated 2 pF Clock # Rs T-Line 10" Typical Figure 6. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull Rev. 1.0 17 S i 5 3 11 5 4. Control Registers 4.1. Byte Read/Write Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register number. 4.1.1. Byte Read The standard byte read is as shown in Figure 7. It is an extension of the byte write. The write start condition is repeated; then, the slave device starts sending data, and the master acknowledges it until the last byte is sent. The master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count. 1 7 T Slave 1 1 8 Wr A Command Command starT Condition 1 1 7 A r Slave Register # to read 2 x 7 bit = 1 1 1 8 1 1 Rd A Data Byte 0 N P repeat starT Acknowledge Master to Byte Read Protocol Not ack stoP Condition Slave to Figure 7. Byte Read Protocol 4.1.2. Byte Write Figure 8 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count. The count can be between 1 and 32. It is not allowed to be zero or to exceed 32. 1 7 T Slave Command starT Condition 1 1 8 Wr A Command Register # to write 2 x 7 bit = 1 1 8 1 1 A Data Byte 0 A P Acknowledge Byte Write Protocol Master to Slave to Figure 8. Byte Write Protocol 18 stoP Condition Rev. 1.0 Si53115 4.2. Block Read/Write 4.2.1. Block Read After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The slave acknowledges the register index in the command byte. The master sends a repeat start function. After the slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master acknowledges each byte except the last and sends a stop function. 1 7 T Slave 1 1 8 1 1 7 Wr A Command Code A r Slave Command starT Condition 8 1 Data Byte A 1 1 Rd A Register # to repeat starT read Acknowledge 2 x 7 bit = 1 8 1 8 1 1 Data Byte 0 A Data Byte 1 N P Master to Slave to Not acknowledge stoP Condition Block Read Protocol Figure 9. Block Read Protocol 4.2.2. Block Write After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte received. The transfer is terminated after the slave sends the ACK and the master sends a stop function. 1 7 1 1 T Slave Address Wr A Command bit starT Condition 8 Command Register # to write 2 x 7 bit = 0 1 A Master to Slave to Acknowledge 1 8 1 8 1 1 8 Byte Count = 2 A Data Byte 0 A Data Byte 1 A P stoP Condition Block Write Protocol Figure 10. Block Write Protocol Rev. 1.0 19 S i 5 3 11 5 4.3. Control Registers Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 100M_133M# Frequency Select 133 MHz 100 MHz R Latched at power up DIF[11:0] 1 Reserved 0 2 Reserved 0 3 Output Enable DIF 13 Low/Low Enable RW 1 DIF_13 4 Output Enable DIF 14 Low/Low Enable RW 1 DIF_14 5 Reserved 0 6 PLL Mode 0 See PLL Operating Mode Readback Table R Latched at power up 7 PLL Mode 1 See PLL Operating Mode Readback Table R Latched at power up Table 18. Byte 1: Output Enable Control Register Bit Description 0 If Bit = 1 Type Reserved Default Output(s) Affected 0 1 Output Enable DIF 0 Low/Low Enabled RW 1 DIF[0] 2 Output Enable DIF 1 Low/Low Enabled RW 1 DIF[1] 3 Output Enable DIF 2 Low/Low Enabled RW 1 DIF[2] 4 Output Enable DIF 3 Low/Low Enabled RW 1 DIF[3] 5 Output Enable DIF 4 Low/Low Enabled RW 1 DIF[4] 6 7 20 If Bit = 0 Reserved Output Enable DIF 5 Low/Low 0 Enabled Rev. 1.0 RW 1 DIF[5] Si53115 Table 19. Byte 2: Output Enable Control Register Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 Output Enable DIF 6 Low/Low Enabled RW 1 DIF[6] 1 Output Enable DIF 7 Low/Low Enabled RW 1 DIF[7] 2 Output Enable DIF 8 Low/Low Enabled RW 1 DIF[8] 3 Output Enable DIF 9 Low/Low Enabled RW 1 DIF[9] 4 Reserved 0 5 Output Enable DIF 10 Low/Low Enabled RW 1 DIF[10] 6 Output Enable DIF 11 Low/Low Enabled RW 1 DIF[11] 7 Output Enable DIF 12 Low/Low Enabled RW 1 DIF[12] Default Output(s) Affected Table 20. Byte 3: Reserved Control Register Bit Description If Bit = 0 0 Reserved 0 1 Reserved 0 2 Reserved 0 3 Reserved 0 4 Reserved 0 5 Reserved 0 6 Reserved 0 7 Reserved 0 Rev. 1.0 If Bit = 1 Type 21 S i 5 3 11 5 Table 21. Byte 4: Reserved Control Register Bit Description If Bit = 0 If Bit = 1 Type Default 0 Reserved 0 1 Reserved 0 2 Reserved 0 3 Reserved 0 4 Reserved 0 5 Reserved 0 6 Reserved 0 7 Reserved 0 Output(s) Affected Table 22. Byte 5: Vendor/Revision Identification Control Register Bit Description 0 If Bit = 0 If Bit = 1 Type Default Output(s) Affected Vendor ID Bit 0 R Vendor Specific 0 1 Vendor ID Bit 1 R Vendor Specific 0 2 Vendor ID Bit 2 R Vendor Specific 0 3 Vendor ID Bit 3 R Vendor Specific 1 4 Revision Code Bit 0 R Vendor Specific 0 5 Revision Code Bit 1 R Vendor Specific 0 6 Revision Code Bit 2 R Vendor Specific 0 7 Revision Code Bit 3 R Vendor Specific 0 Table 23. Byte 6: Device ID Control Register 22 Bit Description 0 If Bit = 0 If Bit = 1 Type Default Device ID 0 R 0 1 Device ID 1 R 1 2 Device ID 2 R 1 3 Device ID 3 R 1 4 Device ID 4 R 0 5 Device ID 5 R 1 6 Device ID 6 R 1 7 Device ID 7 (MSB) R 1 Rev. 1.0 Output(s) Affected Si53115 Table 24. Byte 7: Byte Count Register Bit Description 0 If Bit = 0 If Bit = 1 Type Default BC0: Writing to this register configures how many bytes will be read back RW 0 1 BC1: Writing to this register configures how many bytes will be read back RW 0 2 BC2: Writing to this register configures how many bytes will be read back RW 0 3 BC3: Writing to this register configures how many bytes will be read back RW 1 4 BC4: Writing to this register configures how many bytes will be read back RW 0 5 Reserved 0 6 Reserved 0 7 Reserved 0 Rev. 1.0 Output(s) Affected 23 S i 5 3 11 5 GND VDD_IO DIF_10 DIF_10 DIF_12 DIF_12 DIF_11 DIF_11 VDD GND DIF_13 DIF_13 GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IO DIF_14 DIF_14 5. Pin Descriptions: 64-Pin QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND 16 Si53115 DIF_0 17 DIF_0 18 VDD_IO 19 GND 20 DIF_1 21 DIF_1 22 DIF_2 23 DIF_2 24 GND 25 VDD 26 DIF_3 27 DIF_3 28 DIF_4 29 DIF_4 30 VDD_IO 31 GND 32 VDDA GNDA 100M_133M HBW_BYPASS_LBW PWRGD / PWRDN GND VDDR CLK_IN CLK_IN SA_0 SDA SCL SA_1 FBOUT_NC FBOUT_NC 24 Rev. 1.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD_IO GND DIF_9 DIF_9 DIF_8 DIF_8 GND VDD DIF_7 DIF_7 DIF_6 DIF_6 VDD_IO GND DIF_5 DIF_5 Si53115 Table 25. Si53115 64-Pin QFN Descriptions Pin # Name Type Description 1 VDDA 3.3 V 3.3 V power supply for PLL. 2 GNDA GND Ground for PLL. 3 100M_133M I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pullup or pull-down resistor is attached to this pin to select the input/output frequency. High = 100 MHz output Low = 133 MHz output 4 HBW_BYPASS_LBW I, SE Tri-Level input for selecting the PLL bandwidth or bypass mode. High = High BW mode Med = Bypass mode Low = Low BW mode 5 PWRGD/PWRDN I 6 GND GND Ground for outputs. 7 VDDR VDD 3.3 V power supply for differential input receiver. This VDDR should be treated as an analog power rail and filtered appropriately. 8 CLK_IN I, DIF 0.7 V Differential input. 9 CLK_IN I, DIF 0.7 V Differential input. 10 SA_0 I,PU 11 SDA I/O Open collector SMBus data. 12 SCL I/O SMBus slave clock input. 13 SA_1 I,PU 14 FBOUT_NC I/O Complementary differential feedback output. There are active signals on Pins 15 and 16, do not connect anything to this pin. 15 FBOUT_NC I/O True differential feedback output. There are active signals on Pins 15 and 16; do not connect anything to Pin 15. 16 GND GND 17 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 18 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 19 VDDIO 20 GND 21 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 22 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 23 DIF_2 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 24 DIF_2 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 3.3 V LVTTL input to power up or power down the device. 3.3 V LVTTL input selecting the address. Tri-level input. 3.3 V LVTTL input selecting the address. Tri-level input. Ground for outputs. 3.3 V 3.3 V power supply for differential outputs. GND Ground for outputs. Rev. 1.0 25 S i 5 3 11 5 Table 25. Si53115 64-Pin QFN Descriptions (Continued) Pin # Name Type 25 GND GND 26 VDD 3.3 V 3.3 V power supply. 27 DIF_3 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 28 DIF_3 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 29 DIF_4 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 30 DIF_4 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 31 VDD_IO VDD Power supply for differential outputs. 32 GND GND Ground for outputs. 33 DIF_5 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 34 DIF_5 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 35 GND GND Ground for outputs. 36 VDD_IO VDD Power supply for differential outputs. 37 DIF_6 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 38 DIF_6 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 39 DIF_7 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 40 DIF_7 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 41 VDD 3.3 V 3.3 V power supply. 42 GND GND 43 DIF_8 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 44 DIF_8 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 45 DIF_9 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 46 DIF_9 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 47 GND GND Ground for outputs. 48 VDD_IO VDD Power supply for differential outputs. 49 DIF_10 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 50 DIF_10 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 51 VDD_IO VDD Power supply for differential outputs. 52 GND GND Ground for outputs. 53 DIF_11 26 Description Ground for outputs. Ground for outputs. O, DIF 0.7 V Differential clock outputs. Default is 1:1. Rev. 1.0 Si53115 Table 25. Si53115 64-Pin QFN Descriptions (Continued) Pin # Name Type Description 54 DIF_11 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 55 DIF_12 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 56 DIF_12 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 57 GND GND 58 VDD 3.3 V 3.3 V power supply for outputs. 59 DIF_13 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 60 DIF_13 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 61 DIF_14 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 62 DIF_14 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 63 VDD_IO VDD Power supply for differential outputs. 64 GND GND Ground for outputs. Ground for outputs. Rev. 1.0 27 S i 5 3 11 5 6. Power Filtering Example 6.1. Ferrite Bead Power Filtering Silicon Labs recommends using a ferrite bead with characteristics matching Murata BLM15EG221SN1. Figure 11. Recommended Si53115 Power Filtering 28 Rev. 1.0 Si53115 7. Ordering Guide Part Number Package Type Temperature Si53115-A01AGM 64-pin QFN Extended, –40 to 85 C Si53115-A01AGMR 64-pin QFN—Tape and Reel Extended, –40 to 85 C Lead-free Rev. 1.0 29 S i 5 3 11 5 8. Package Outline Figure 12 illustrates the package details for the Si53115. Table 26 lists the values for the dimensions shown in the illustration. Figure 12. 64-Pin Quad Flat No Lead (QFN) Package Table 26. Package Dimensions1,2,3,4 Dimension Min Nom Max Dimension Min Nom Max A 0.80 0.85 0.90 E2 6.00 6.10 6.2 A1 0.00 0.02 0.05 L 0.30 0.40 0.5 b 0.18 0.25 0.30 aaa 0.10 bbb 0.10 ccc 0.08 D D2 9.00 BSC. 6.00 6.10 6.20 e 0.50 BSC. ddd 0.10 E 9.00 BSC. eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 30 Rev. 1.0 Si53115 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. 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