Si53365

Si53365
1:8 L O W J I T T E R CMOS C LOCK B U FF E R (<200 MH Z )
Features

8 LVCMOS outputs

Low additive jitter: 125 fs rms typ

 Wide frequency range: 1 to 200 MHz

 Asynchronous output enable
 Low output-output skew: <100 ps
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Footprint-compatible with
CDCLVC1108
 1.8, 2.5, or 3.3 V operation
 16-TSSOP

Applications




High-speed clock distribution
Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
Storage
Telecom
 Industrial
 Servers
 Backplane clock distribution
Ordering Information:
See page 9.
Pin Assignments
Description
The Si53365 is an ultra low jitter eight output LVCMOS buffer. The Si53365
utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc
to 200 MHz with guaranteed low additive jitter, low skew, and low propagation
delay variability. The Si53365 supports operation over the industrial temperature
range and can be operated from a 1.8 V, 2.5 V, or 3.3 V supply.
Functional Block Diagram
VDD
Power
Supply
Filtering
Q0
Q1
CLK
1
16 Q1
OE
2
15 Q3
Q0
3
14
GND
4
13 Q2
VDD
5
12 GND
Q4
6
11 Q5
GND
7
10 VDD
Q6
8
9
VDD
Q7
Q2
Q3
Patents pending
CLK
Q4
Q5
Q6
Q7
GND
Rev. 1.0 4/15
OE
Copyright © 2015 by Silicon Laboratories
Si53365
Si53365
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.4. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Description: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1. 16-TSSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1. 16-TSSOP Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1. Si53365 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2
Rev. 1.0
Si53365
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
Parameter
Ambient Operating
Temperature
Test Condition
TA
Supply Voltage Range
VDD
LVCMOS
Min
Typ
Max
Unit
–40
—
85
°C
1.71
1.8
1.89
V
2.38
2.5
2.63
V
2.97
3.3
3.63
V
Table 2. Input Clock Specifications
(VDD=1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, TA=–40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LVCMOS Input High Voltage
VIH
VDD = 2.5 V± 5%, 1.8 V± 5%,
3.3 V± 10%
VDD x 0.7
—
—
V
LVCMOS Input Low Voltage
VIL
VDD = 2.5 V± 5%, 1.8 V± 5%,
3.3 V± 10%
—
—
VDD x 0.3
V
Input Capacitance
CIN
CLK pins with respect to GND
—
5
—
pF
Table 3. DC Common Characteristics
(VDD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
—
150
Max
Unit
Supply Current
IDD
Input High Voltage
VIH
OE
0.8 x VDD
—
—
V
Input Low Voltage
VIL
OE
—
—
0.2 x VDD
V
Internal Pull-up
Resistor
RUP
OE
—
25
—
kΩ
mA
Table 4. Output Characteristics—LVCMOS
(VDD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Voltage High
VOH
IOH = –12 mA
0.8x VDD
—
—
V
Output Voltage Low
VOL
IOL = 12 mA
—
—
0.2 x VDD
V
Rev. 1.0
3
Si53365
Table 5. AC Characteristics
(VDD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency
F
LVCMOS
dc
—
200
MHz
Duty Cycle
DC
200 MHz, 50 Ω to VDD/2, 20/80%
TR/TF<10% of period
40
50
60
%
Minimum Input Clock
Slew Rate
SR
Required to meet prop delay and
additive jitter specifications
(20–80%)
0.75
—
—
V/ns
Output Rise/Fall Time
TR/TF
200 MHz, 50 Ω, 20/80%,
2 pF load, 12 mA drive strength
—
—
850
ps
Minimum Input Pulse
Width
TW
2
—
—
ns
3.3 V, 200 MHz,
Vin = 1.7 VPP @ 1 V/ns
—
130
180
fs-rms
3.3 V, 156.25 MHz,
Vin = 2.18 VPP @ 1 V/ns
—
125
220
fs-rms
2.5 V, 200 MHz,
Vin = 1.7 VPP @ 1 V/ns
—
115
250
fs-rms
2.5 V, 156.25 MHz,
Vin = 2.18 VPP @ 1 V/ns
—
125
240
fs-rms
TPLH,
TPHL
Low-to-high, high-to-low
Single-ended, CL = 2 pF
1.5
3.0
4.5
ns
TEN
F = 1 MHz
—
10
—
ns
F = 100 MHz
—
10
—
ns
F = 1 MHz
—
20
—
ns
F = 100 MHz
—
20
—
ns
Parameter
Note: 50% input duty
cycle.
Additive Jitter
(12 kHz – 20 MHz)
Propagation Delay
Output Enable Time
Output Disable Time
J
TDIS
Part to Part Skew
TSKPP
CL = 2 pF
0
—
300
ps
Output to Output
Skew
TSK
CL = 2 pF
—
40
125
ps
4
Rev. 1.0
Si53365
Table 6. Thermal Conditions
Parameter
Symbol
Test Condition
Value
Unit
θJA
Still air
124.4
°C/W
Thermal Resistance,
Junction to Ambient
Table 7. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Unit
TS
–55
—
150
°C
Supply Voltage
VDD
–0.5
—
3.8
V
Input Voltage
VIN
–0.5
—
VDD+
0.3
V
Output Voltage
VOUT
—
—
VDD+
0.3
V
ESD Sensitivity
HBM
2000
—
—
V
ESD Sensitivity
CDM
500
—
—
V
Peak Soldering Reflow
Temperature
TPEAK
—
—
260
°C
—
—
125
°C
Storage Temperature
Maximum Junction
Temperature
Symbol
Test Condition
HBM, 100 pF, 1.5 kΩ
Pb-Free; Solder reflow profile
per JEDEC J-STD-020
TJ
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Rev. 1.0
5
Si53365
2. Functional Description
The Si53365 is a low jitter, low skew 1:8 CMOS buffer with asynchronous output enable. The Si53365 is ideal for
low jitter LVCMOS clock distribution.
2.1. Input Termination
Figure 1 shows the recommended input clock termination.
VDDO = 3.3V, 2.5V, 1.8V
VDD
Si533xx
CMOS
Driver
Rs
CLK
50
Note: VDDO and VDD must be at the same voltage level.
Figure 1. LVCMOS DC-Coupled Input Termination
2.2. Output Enable Logic
The table below summarizes the input and output clock state based on the output enable pin setting.
Table 8. Output Logic
INPUTS
OUTPUTS
CLK
OE
Qn
X
L
L
L
H
L
H
H
H
2.3. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused output clocks should be left floating.
CMOS
Receivers
Si533xx
CMOS Driver
Zout
Rs
Zo
50
CL = 15 pF
Figure 2. LVCMOS Output Termination
6
Rev. 1.0
Si53365
2.4. AC Timing Waveforms
TPHL
TSK
CLK
QN
VPP/2
Q
VPP/2
QM
VPP/2
VPP/2
TPLH
TSK
Propagation Delay
Output-Output Skew
TF
Q
80% VPP
20% VPP
80% VPP
Q
20% VPP
TR
Rise/Fall Time
Figure 3. AC Waveforms
Rev. 1.0
7
Si53365
3. Pin Description: 16-Pin TSSOP
CLK
1
16 Q1
OE
2
15 Q3
Q0
3
14
GND
4
13 Q2
VDD
5
12 GND
Q4
6
11 Q5
GND
7
10 VDD
Q6
8
9
VDD
Q7
Table 9. Si53365 Pin Description
Pin #
Name
1
CLK
Input clock.
2
OE
Output enable.
When OE=high, the clock outputs are enabled.
When OE=low, the clock outputs are low.
OE contains an internal pull-up resistor.
3
Q0
Output clock 0.
4
GND
Ground.
5
VDD
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible.
6
Q4
Output clock 4.
7
GND
8
Q6
Output clock 6.
9
Q7
Output clock 7.
10
VDD
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible.
11
Q5
Output clock 5.
12
GND
13
Q2
Output clock 2.
14
VDD
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible.
15
Q3
Output clock 3.
16
Q1
Output clock 1.
8
Description
Ground.
Ground.
Rev. 1.0
Si53365
4. Ordering Guide
Part Number
Package
PB-Free, ROHS-6
Temperature
Si53365-B-GT
16-TSSOP
Yes
–40 to 85 °C
Rev. 1.0
9
Si53365
5. Package Outline
5.1. 16-TSSOP Package Diagram
Figure 4. Si53365 16-TSSOP Package Diagram
Table 10. Package Dimensions
Dimension
Min
Nom
Max
Dimension
A
—
—
1.20
e
A1
0.05
—
0.15
L
A2
0.80
1.00
1.05
L2
b
0.19
—
0.30
θ
c
0.09
—
0.20
aaa
0.10
D
4.90
5.00
5.10
bbb
0.10
ccc
0.20
6.40 BSC
E
E1
4.30
4.40
Min
Nom
Max
0.65 BSC
0.45
0.60
0.75
0.25 BSC
0°
—
8°
4.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10
Rev. 1.0
Si53365
6. PCB Land Pattern
6.1. 16-TSSOP Package Land Pattern
Figure 5. Si53365 16-TSSOP Package Land Pattern
Table 11. PCB Land Pattern
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.80
E
Pad Row Pitch
0.65
X1
Pad Width
0.45
Y1
Pad Length
1.40
Notes:
1. This Land Pattern Design is based on the IPC-7351
guidelines.
2. All feature sizes shown are at Maximum Material
Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
Rev. 1.0
11
Si53365
7. Top Marking
7.1. Si53365 Top Marking
7.2. Top Marking Explanation
12
Mark Method:
Laser
Font Size:
2.0 Point (0.71 mm)
Right-Justified
Line 1 Marking: Customer Part Number
Si53365
Line 2 Marking: TTTTTT = Mfg Code
Manufacturing Code from the
Assembly Purchase Order form.
Line 3 Marking: YY = Year
WW = Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
Rev. 1.0
Si53365
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0







Updated Table 2, “Input Clock Specifications,” on
page 3.
Updated Table 3, “DC Common Characteristics,” on
page 3.
Added Table 4, “Output Characteristics—LVCMOS,”
on page 3.
Updated Table 10, “Package Dimensions,” on
page 10 to include improved data for additive jitter
specifications.
Updated output voltage specifications
Improved performance specifications with more
detail.
Added pin type description to the pin descriptions
table.
Rev. 1.0
13
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