Si53323 1:4 L O W - J I T T E R LV PECL C L O C K B U F F E R WI TH 2 : 1 I N P U T M UX Features 4 LVPECL outputs Ultra-low additive jitter: 55 fs rms Wide frequency range: dc to 1250 MHz 2:1 input mux Universal input stage accepts differential or LVCMOS clock VDD: 2.5 / 3.3 V Small size: 16-QFN (3 mm x 3 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C Applications 4 Q2 Q2 8 CLK1 NC 3 7 CLK1 12 EXPOSED GND PAD CLK0 2 13 1 14 The Si53323 features minimal cross-talk and excellent supply noise rejection, simplifying low-jitter clock distribution in noisy environments. GND CLK_SEL 15 The Si53323 is an ultra-low-jitter four-output LVPECL buffer. The Si53323 features a 2:1 input mux, making it ideal for redundant clocking applications. Utilizing Silicon Laboratories’ advanced fan-out clock technology, the Si53323 guarantees low additive jitter, low skew, and low propagation delay variability from dc to 1250 MHz. 16 Description Q3 Pin Assignments Q3 6 Ordering Information: See page 18. 5 Storage Telecom Industrial Servers Backplane clock distribution VDD High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 CLK0 Functional Block Diagram Q1 11 Q1 10 Q0 9 Q0 Patents pending VDD Power Supply Filtering Q0 Q0 CLK0 Q1 CLK0 Q1 Q2 CLK1 Q2 CLK1 Q3 CLK_SEL Rev. 1.0 7/15 Switching Logic Q3 Copyright © 2015 by Silicon Laboratories Si53323 Si53323 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3. Input Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.4. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.5. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.7. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.8. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1. Si53323 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Rev. 1.0 2 Si53323 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Operating Temperature Test Condition TA Supply Voltage Range VDD LVPECL Min Typ Max Unit –40 — 85 °C 2.38 2.5 2.63 V 2.97 3.3 3.63 V Table 2. Input Clock Specifications (2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V 5%, 3.3 V 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V 5%, 3.3 V 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V 5%, 3.3 V 10% — — VDD x 0.3 V Input Capacitance CIN CLK0 and CLK1 pins with respect to GND — 5 — pF Table 3. DC Common Characteristics (2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Symbol Test Condition Min Typ Max Unit Supply Current IDD Measured using accoupled termination shown in Figure 6 — 210 — mA Input High Voltage VIH CLK_SEL 0.8 x VDD — — V Input Low Voltage VIL CLK_SEL — — 0.2 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL — 25 — k Parameter Rev. 1.0 3 Si53323 Table 4. Output Characteristics (LVPECL) (VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDD – 1.595 — VDD – 1.245 V VSE 0.40 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. AC Characteristics (VDD = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit dc — 1250 MHz Frequency F Duty Cycle DC 20/80% TR/TF<10% of period (Differential input clock) 47 50 53 % DC 20/80% TR/TF<10% of period (Single-Ended input clock) 45 50 55 % Minimum Input Clock Slew Rate SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF 20–80% — — 350 ps Minimum Input Pulse Width TW 360 — — ps TPLH, TPHL 600 800 1000 ps Output to Output Skew1 TSK — 20 50 ps Part to Part Skew2 TPS Differential — — 150 ps PSRR 10 kHz sinusoidal noise — –70 — dBc 100 kHz sinusoidal noise — –65 — dBc 500 kHz sinusoidal noise — –60 — dBc 1 MHz sinusoidal noise — –57.5 — dBc Note: 50% input duty cycle. Duty Cycle Note: 50% input duty cycle. Propagation Delay Power Supply Noise Rejection3 Notes: 1. Output-to-output skew specified for outputs with identical configuration. 2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 4 Rev. 1.0 Si53323 Table 6. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Differential Clock Format 20%-80% Slew Rate (V/ns) (Single-Ended, Peak-to-Peak) Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 55 95 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 2.5 725 Differential 0.15 0.637 LVPECL 55 95 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Table 7. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. PSPL 5310A CLK SYNTH SMA103A 50 Si533xx DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm /CLKx 50 Balun Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 5 Si53323 Table 8. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient JA Still air 57.6 °C/W Thermal Resistance, Junction to Case JC Still air 41.5 °C/W Table 9. Absolute Maximum Ratings Parameter Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM — — 2000 V ESD Sensitivity CDM — — 500 V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Storage Temperature Maximum Junction Temperature Symbol Test Condition HBM, 100 pF, 1.5 kΩ Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 6 Rev. 1.0 Si53323 2. Functional Description The Si53323 is a low-jitter, low-skew 1:4 LVPECL buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. 2.1. Universal, Any-Format Input The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, lowpower LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 10 and 11 summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Table 10. LVPECL, LVCMOS, and LVDS Input Clock Options LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 11. HCSL and CML Input Clock Options HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si533xx CLKx 100 /CLKx 0.1 µF Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination VDD 1 k VDD = 3.3 V or 2.5 V VDD Si533xx CMOS Driver CLKx 50 /CLKx Rs VTERM = VDD/2 1 k VREF Figure 3. LVCMOS DC-Coupled Input Termination Rev. 1.0 7 Si53323 VDD DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDD = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 VTERM = VDD – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDD = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDD – 2V DC Coupled LVDS Termination VDD VDD = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Source Termination Scheme VDD = 3.3V 33 Si533xx 50 Standard HCSL Driver VDD CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 4. Differential DC-Coupled Input Terminations 8 Rev. 1.0 Si53323 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to VDD. The inverting input is biased with a 75 k pull-up to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 k RPD = 18.75 k Figure 5. Input Bias Resistors 2.3. Input Mux The Si53323 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 12. Input Mux Logic CLK_SEL CLK0 CLK1 Q1 Q L L X L H L H X H L H X L L H H X H H L Notes: 1. On the next negative transition of CLK0 or CLK1. Rev. 1.0 9 Si53323 2.4. Output Clock Termination Options The recommended output clock termination options are shown below. Unused outputs should be left unconnected. VDD DC Coupled LVPECL Termination Scheme 1 R1 R1 VDD = 3.3V or 2.5V Si533xx VDD 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDD – 2 V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD = 3.3 V or 2.5 V Si533xx VDD 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDD – 2V VDD AC Coupled LVPECL Termination Scheme 1 R1 VDD = 3.3 V or 2.5 V Si533xx R1 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3 V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5 V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 VDD = 3.3V or 2.5V Si533xx 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb Rb 50 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 6. LVPECL Output Termination 10 Rev. 1.0 Si53323 2.5. AC Timing Waveforms TPHL TSK CLK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 7. AC Waveforms Rev. 1.0 11 Si53323 2.6. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 5. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 8. Source Jitter (156.25 MHz) 12 Rev. 1.0 Si53323 Figure 9. Single-Ended Total Jitter (312.5 MHz) Rev. 1.0 13 Si53323 Figure 10. Differential Total Jitter (625 MHz) 14 Rev. 1.0 Si53323 2.7. Input Mux Noise Isolation The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. Figure 11 below is a measurement of the input mux’s noise isolation. LVPECL [email protected]; Selected clk is active Unselected clk is static Mux Isolation = 61dB LVPECL [email protected]; Selected clk is static Unselected clk is active Figure 11. Input Mux Noise Isolation 2.8. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks”. Rev. 1.0 15 Si53323 Q3 Q2 Q2 6 7 8 CLK0 NC 4 CLK0 CLK1 5 3 EXPOSED GND PAD VDD CLK1 13 2 14 CLK_SEL 15 1 16 GND Q3 3. Pin Description: 16-Pin QFN 12 Q1 11 Q1 10 Q0 9 Q0 Figure 12. 16-QFN Pin Diagram (Top View) Table 13. Pin Descriptions 16 Pin Name Type* Description 1 GND GND 2 CLK_SEL I Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. 3 CLK1 I Input Clock 1 4 CLK1 I Input clock 1 (complement) When CLK1 is driven by a single-ended input, connect CLK1 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). 5 VDD P Core Voltage Supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible. 6 CLK0 I Input Clock 0 7 CLK0 I Input Clock 0 (Complement) When CLK0 is driven by a single-ended input, connect CLK0 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). 8 NC — Ground No connect. Do not connect this pin. Rev. 1.0 Si53323 Table 13. Pin Descriptions (Continued) Pin Name Type* Description 9 Q0 O Output Clock 0 10 Q0 O Output Clock 0 (complement) 11 Q1 O Output Clock 1 12 Q1 O Output Clock 1 (complement) 13 Q2 O Output Clock 2 14 Q2 O Output Clock 2 (complement) 15 Q3 O Output Clock 3 16 Q3 O Output Clock 3 (complement) GND Pad GND GND Ground Rev. 1.0 17 Si53323 4. Ordering Guide 18 Part Number Package Pb-Free, ROHS-6 Temperature Si53323-B-GM 16-QFN Yes –40 to 85 C Si53301/4-EVB NA Yes –40 to 85 C Rev. 1.0 Si53323 5. Package Outline Figure 13 shows the package dimensions for the 3x3 mm 16-pin QFN package. Table 14 lists the values for the dimensions shown in the illustration. Figure 13. Si53323 3x3 mm 16-QFN Package Diagram Table 14. Package Diagram Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 3.00 BSC. 1.65 1.70 e 0.50 BSC. E 3.00 BSC. 1.75 E2 1.65 1.70 1.75 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 eee — — 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev. 1.0 19 Si53323 6. PCB Land Pattern Figure 14 shows the PCB land pattern dimensions for the 3x3 mm 16-pin QFN package. Table 15 lists the values for the dimensions shown in the illustration. Figure 14. Si53323 3x3 mm 16-QFN Package Land Pattern Table 15. PCB Land Pattern Dimensions Dimension mm C1 3.00 C2 3.00 E 0.50 X1 0.30 Y1 0.80 X2 1.75 Y2 1.75 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 20 Rev. 1.0 Si53323 7. Top Marking 7.1. Si53323 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 0.635 mm (25 mils) Right-Justified Line 1 Marking: Product ID 3323 Line 2 Marking: TTTT = Mfg Code Manufacturing Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified) Pin 1 Identifier YWW = Date Code Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date. Rev. 1.0 21 Si53323 DOCUMENT CHANGE LIST Revision 0.9 to 1.0 Update operating conditions, including LVCMOS and HCSL voltage support. Removed voltage reference feature. Updated Table 2, “Input Clock Specifications,” on page 3. Updated Table 3, “DC Common Characteristics,” on page 3. Updated Table 4, “Output Characteristics (LVPECL),” on page 4. Updated Table 10, “LVPECL, LVCMOS, and LVDS Input Clock Options,” on page 7. Updated output voltage specifications. Improved data for additive jitter specifications. Improved typical phase noise plots. Updated input/output termination recommendations. Improved performance specifications with more detail. Added pin type description to the pin descriptions table. Updated ESD specifications. Rev. 1.0 22 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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