Si5344H-42H Data Sheet Errata for Product Revision D This document contains information on the errata of product revision D of Si5344H/42H. ERRATA DEFINITIONS The device data sheet explains how to identify chip revision, either from package marking or electronically. Impact Definition: Each erratum is marked with an impact, as defined below: • Minor—Workaround(s) exists. Errata effective date: 25 April 2016. Applies to the Si5344H/42H Data Sheet revision 0.98. Note: This document applies to Ordering Part Numbers (OPNs) which refer to product revision D (silicon revision B1). For example: Si5342H-D-GM or Si5342H-Dxxxxx-GM, where xxxxx is the custom OPN ID, and D refers to the product revision. • Major—Errata that does not conform to the data sheet or standard. • Information—The device behavior is not ideal but acceptable. Typically, the data sheet and/or ClockBuilder Pro may be changed to match or address the device behavior. Table .1. Errata Status Summary Erratum Title/Problem Impact Workarounds Resolution 1 Impedance in LVCMOS high-Z mode is too low Information Yes Si5344H/42H Data Sheet and CBPro have been updated. Will also be fixed in the next silicon revision. 2 Output-to-output clock skew beMajor tween clocks generated from different MultiSynth dividers is not consistent at high junction temperatures No Will be fixed in the next silicon revision. 3 Input-to-output clock delay variation is not consistent at high junction temperatures Minor No Will be fixed in the next silicon revision. 4 INTRb pin activity while RSTb held low Information Yes Will be fixed in the next silicon revision. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 Data Sheet Errata for Product Revision D LVCMOS High-Impedance Mode is Too Low 1. LVCMOS High-Impedance Mode is Too Low Description LVCMOS high-impedance is too low. Impact without Workarounds LVCMOS and differential output formats are user-configurable to disable in a low logic state, a high logic state, or in stop mid (highimpedance or Hi-Z) state. In LVCMOS Hi-Z mode, there is 570 Ω impedance between CKOUT and CKOUTB. The LVCMOS high-impedance mode should not be used. Workaround Select the disable state as stop-high or stop-low. Resolution This erratum will be fixed in the next silicon revision. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 1 Data Sheet Errata for Product Revision D Output-to-Output Clock Skew 2. Output-to-Output Clock Skew Description Output-to-output clock skew between clocks generated from different MultiSynth dividers is not consistent at high junction temperatures. Impact If the chip is powered-up, or a hard or soft reset is performed when the junction temperature exceeds 110 °C, the output-to-output skew may exceed the data sheet specification (for all outputs connected to different MultiSynth fractional dividers). Consult the data sheet addendum generated from ClockBuilder Pro to determine which output clocks in your plan are connected to one of the various MultiSynth dividers. CBPro also includes a junction temperature estimator and measurement utility to help keep you informed about your configuration’s power consumption. Note: When clock outputs are connected to the same MultiSynth fractional divider, data sheet specifications have been added for output-to-output skew. In this case, the output-to-output skew specifications are 20 ps (typical) and 50 ps (max). Workaround None. Resolution This erratum will be fixed in the next revision. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 2 Data Sheet Errata for Product Revision D Input-to-Output Clock Delay Variation 3. Input-to-Output Clock Delay Variation Description The input-to-output clock delay variation performance is not consistent when operating the chip at high junction temperatures. Impact If the chip is powered-up, or a hard or soft reset is performed when the junction temperature exceeds 100 °C, the input-to-output clock delay variation may exceed the data sheet specification of 2 ns (typical). Note: The input-to-output delay variation specification (previously and erroneously referred to as input-to-output delay in data sheet revisions up to v0.95) is 2 ns (typical). Workaround None. Resolution This erratum will be fixed in the next silicon revision. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 3 Data Sheet Errata for Product Revision D INTRb Pin Activity while RSTb Held Low 4. INTRb Pin Activity while RSTb Held Low Description The INTRb pin voltage varies at approximately 5 MHz while the RSTb reset input pin is held low (active). Impact Activity on the INTRb pin while RSTb is held low may appear as an interrupt to the system. Note: The INTRb pin is driven low (active) when exiting the reset state. Workaround The INTRb signal can be ignored or masked by the system until RSTb is released or driven high. Resolution This erratum will be fixed in the next silicon revision. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 4 Data Sheet Errata for Product Revision D Revision History 5. Revision History 5.1 Revision 1.0 v1.0: April 2016 • Initial revision of this document for Si5344H/42H errata. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 5 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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