ETC SI5318

Si5318
SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C
Features
Jitter generation as low as
0.7 psRMS (typ), compliant with
GR-253-CORE OC-48
specifications
„ No external components
(other than a resistor and
standard bypassing)
„ Input clock ranges at 19, 39, 78,
and 155 MHz
„
„
„
„
„
„
„
Output clock ranges at 19 or
155 MHz
Digital hold for loss of input clock
Selectable loop bandwidth
Loss-of-signal alarm output
Low power
Small size (9x9 mm)
Si5318
Si5318
Ordering Information:
Applications
SONET/SDH line/port cards
„ Optical modules
Core switches
„ Digital cross connects
„ Terabit routers
„
„
See page 26.
Description
The Si5318 is a precision clock multiplier designed to exceed the requirements of
high-speed communication systems, including OC-48. The device phase locks to
an input clock in the 19, 39, 78, or 155 MHz frequency range and generates a low
jitter output clock in the 19 or 155 MHz range. Silicon Laboratories’ DSPLL®
technology delivers all PLL functionality with unparalleled performance while
eliminating external loop filter components, providing programmable loop
parameters, and simplifying design. The Si5318 establishes a new standard in
performance and integration for ultra-low-jitter clock generation. It operates from a
single 3.3 V supply.
Functional Block Diagram
REXT
VDD
GND
Biasing & Supply Regulation
FXDDELAY
CLKIN+
CLKIN–
VALTIME
LOS
CAL_ACTV
2
÷
÷
Signal
Detect
3
INFRQSEL[2:0]
Rev. 1.0 4/05
DSPLL
DH_ACTV
®
2
Calibration
BWSEL[1:0]
2
CLKOUT+
CLKOUT–
FRQSEL[1:0]
RSTN/CAL
DBLBW
Copyright © 2005 by Silicon Laboratories
Si5318
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5318
NOTES:
2
Rev. 1.0
Si5318
TA B L E O F C O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Pin Descriptions: Si5318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.0
3
Si5318
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5318 Supply Voltage3
Symbol
Test Condition
Min1
Typ
Max1
Unit
TA
–202
25
85
°C
VDD33
3.135
3.3
3.465
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5318 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient
temperature of –20 to 85° C.
3. The Si5318 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 13.
4
Rev. 1.0
Si5318
CLKIN+
CLKIN–
VIS
A. Operation with Single-Ended Clock Input
Note: When using single-ended clock sources, the unused clock
input on the Si5318 must be ac-coupled to ground.
CLKIN+
0.5 VID
CLKIN–
(CLKIN+) – (CLKIN–)
VID
B. Operation with Differential Clock Input
Note: Transmission line termination, when required, must be provided
externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
tF
tR
Figure 2. Rise/Fall Time Measurement
(C L K IN + ) – (C L K IN – )
0 V
tLOS
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 1.0
5
Si5318
Table 2. DC Characteristics, VDD = 3.3 V
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Supply Current
Power Dissipation Using 3.3 V Supply
Common Mode Input Voltage
(CLKIN)
1,2,3
Symbol
Test Condition
Min
Typ
Max
Unit
IDD
Clock in = 19.44 MHz
Clock out = 155.52 MHz
—
135
145
mA
PD
Clock in = 19.44 MHz
Clock out = 155.52 MHz
—
445
479
mW
1.0
1.5
2.0
V
VICM
Single-Ended Input Voltage2,3,4
(CLKIN)
VIS
See Figure 1A
200
—
5004
mVPP
Differential Input Voltage Swing2,3,4
(CLKIN)
VID
See Figure 1B
200
—
5004
mVPP
Input Impedance
(CLKIN+, CLKIN–)
RIN
—
80
—
kΩ
Differential Output Voltage Swing
(CLKOUT)
VOD
100 Ω Load
Line-to-Line
720
938
1155
mVPP
Output Common Mode Voltage
(CLKOUT)
VOCM
100 Ω Load
Line-to-Line
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
ISC(–)
–60
—
—
mA
Output Short to VDD25 (CLKOUT)
ISC(+)
—
15
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
—
—
50
µA
Input High Current (LVTTL Inputs)
IIH
—
—
50
µA
Internal Pulldowns (All LVTTL Inputs)
Ipd
—
—
50
µA
Input Impedance (LVTTL Inputs)
RIN
50
—
—
kΩ
Output Voltage Low (LVTTL Outputs)
VOL
IO = .5 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO = .5 mA
2.0
—
—
V
Notes:
1. The Si5318 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5318 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mVPP for optimal performance.
6
Rev. 1.0
Si5318
Table 3. AC Characteristics
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
19.436
38.872
77.744
155.48
—
—
—
—
21.685
43.369
86.738
173.48
MHz
Input Clock Frequency (CLKIN)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
fCLKIN
Input Clock Rise Time (CLKIN)
tR
Figure 2
—
—
11
ns
Input Clock Fall Time (CLKIN)
tF
Figure 2
—
—
11
ns
CDUTY_IN
40
50
60
%
fO_19
fO_155
—
19.436
155.48
—
—
—
—
21.685
173.48
MHz
Input Clock Duty Cycle
CLKOUT Frequency Range*
FRQSEL[1:0] = 00 (no output)
FRQSEL[1:0] = 01
FRQSEL[1:0] = 10
CLKOUT Rise Time
tR
Figure 2; single-ended; after
3 cm of 50 Ω FR4 stripline
—
213
260
ps
CLKOUT Fall Time
tF
Figure 2; single-ended; after
3 cm of 50 Ω FR4 stripline
—
191
260
ps
CDUTY_O
Differential:
(CLKOUT+) – (CLKOUT–)
48
—
52
%
20
—
—
ns
6/
fo_155
8/
fo_155
s
/fo_155
3
/fo_155
5/
2 x fo_155
9
/4 x fo_155
9
/4 x fo_155
—
—
—
—
—
—
0.09
12.0
—
—
0.22
14.1
s
CLKOUT Duty Cycle
UT
RSTN/CAL Pulse Width
tRSTN
Transitionless Period Required on
CLKIN for Detecting a LOS
Condition.
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
tLOS
Recovery Time for Clearing an
LOS Condition
VALTIME = 0
VALTIME = 1
tVAL
Figure 3
4
Measured from when a valid
reference clock is applied
until the LOS flag clears
8
/fo_155
8
/fo_155
8/
fo_155
8
/fo_155
8
/fo_155
*Note: The Si5318 provides a 1/8, 1/4, 1/2, 1, 2, 4 or 8x clock frequency multiplication function.
Rev. 1.0
7
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 8 Hz
1000
—
—
ns
f = 80 Hz
100
—
—
ns
f = 800 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.87
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.3
10.0
ps
FBW
BW = 800 Hz
—
800
—
Hz
JP
< 800 Hz
—
0.0
0.05
dB
f = 16 Hz
500
—
—
ns
f = 160 Hz
50
—
—
ns
f = 1600 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.78
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.0
9.0
ps
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.00
0.05
dB
JTOL(PP)
f = 16 Hz
1000
—
—
ns
f = 160 Hz
100
—
—
ns
f = 1600 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.82
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.3
10.0
ps
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.0
0.1
dB
Wander/Jitter at 800 Hz Bandwidth
(BWSEL[1:0] = 10 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 10 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 10)
Wander/Jitter Transfer Peaking
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
8
Rev. 1.0
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
f = 32 Hz
500
—
—
ns
f = 320 Hz
50
—
—
ns
f = 3200 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.72
0.9
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.8
10.0
ps
FBW
BW = 3200 Hz
—
3200
—
Hz
JP
< 3200 Hz
—
0.05
0.1
dB
JTOL(PP)
f = 32 Hz
1000
—
—
ns
f = 320 Hz
100
—
—
ns
f = 3200 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.86
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.7
10.0
ps
FBW
BW = 3200 Hz
—
3200
—
Hz
JP
< 3200 Hz
—
0.05
0.1
dB
f = 64 Hz
500
—
—
ns
f = 640 Hz
50
—
—
ns
f = 6400 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.7
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.6
9.0
ps
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
Rev. 1.0
9
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 64 Hz
1000
—
—
ns
f = 640 Hz
100
—
—
ns
f = 6400 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
1.0
1.4
ps
JGEN(PP)
12 kHz to 20 MHz
—
9.4
12.0
ps
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
f = 128 Hz
500
—
—
ns
f = 1280 Hz
50
—
—
ns
f = 12800 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.74
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.9
9.0
ps
FBW
BW = 12800 Hz
—
12800
—
Hz
JP
< 12800 Hz
—
0.05
0.1
dB
TAQ
RSTN/CAL high to
CAL_ACTV low, with valid
clock input and
VALTIME = 0
—
300
350
ms
CCO_TG
Stable Input Clock;
Temperature
Gradient <10 °C/min;
800 Hz Loop BW
—
—
50
ps/
°C/
min
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 11 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 12800 Hz Bandwidth
(BWSEL[1:0] = 11 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Acquisition Time
Clock Output Wander with
Temperature Gradient 1,2
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
10
Rev. 1.0
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Initial Frequency Accuracy in Digital Hold
Mode (first 100 ms with supply voltage and
temperature held constant)
CDH_FA
Stable Input Clock
Selected until entering
Digital Hold
—
—
10
ppm
Clock Output Frequency Accuracy Over
Temperature in Digital Hold Mode
CDH_T
Constant Supply Voltage
—
16.7
30
ppm
/°C
Clock Output Frequency Accuracy Over
Supply Voltage in Digital Hold Mode
CDH_V33
Constant Temperature
—
—
250
ppm
/V
Clock Output Phase Step3 (See Figure 8)
tPT_MTIE
0
200
ps
—
—
—
—
10
5
2.5
1.25
ps/
µs
Clock Output Phase Step Slope3 (See
Figure 8)
BWSEL[1:0] = 11, DBLBW = 0
BWSEL[1:0] = 00, DBLBW = 0
BWSEL[1:0] = 01, DBLBW = 0
BWSEL[1:0] = 10, DBLBW = 0
mPT
When hitlessly recovering –200
from Digital Hold mode
When hitlessly recovering
from Digital Hold mode
6400 Hz
3200 Hz
1600 Hz
800 Hz
—
—
—
—
Max Unit
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
Rev. 1.0
11
Si5318
Table 5. Absolute Maximum Ratings
Parameter
3.3 V DC Supply Voltage
LVTTL Input Voltage
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pf, 1.5 kΩ)
Symbol
VDD33
VDIG
TJCT
TSTG
Value
–0.5 to 3.6
–0.3 to (VDD33 + 0.3)
±50
–55 to 150
–55 to 150
1.0
Unit
V
V
mA
°C
°C
kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
Test Condition
Value
Unit
θJA
Still Air
20
°C/W
0.00
-20.00
Phase Noise (dBc/Hz)
-40.00
-60.00
-80.00
-100.00
-120.00
-140.00
-160.00
-180.00
10 1
10 2
10 3
10 4
10 5
10 6
10 7
10 8
Offset Frequency
Figure 4. Typical Si5318 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 155.52 MHz, and
Loop BW = 800 Hz)
12
Rev. 1.0
Si5318
3.3 V Supply
Ferrite Bead
0.1 µF
2200 pF
22 pF
10 kΩ 1%
GND
VDD25
VDD33
REXT
33 µF
0.1 µF
0.1 µF
CLKIN+
CLKOUT+
100 Ω
Input Clock Source
0.1 µF
Input Clock Frequency Select
(19, 38, 77, or 155 MHz)
PLL Bandwidth Select
Bandwidth Doubling
Fixed Delay Mode Control
LOS Validation Time
Reset/Calibration Control
Clock Output
(19 or 155 MHz)
CLKOUT–
CLKIN-
0.1 µF
INFRQSEL[2:0]
BWSEL[1:0]
Si5318
DBLBW
FRQSEL[1:0]
LOS
FXDDELAY
Clock Output
Frequency Select
Loss of Signal (LOS)
DH_ACTV
Digital Hold Active
CAL_ACTV
Calibration Active
Status Output
VALTIME
RSTN/CAL
Figure 5. Si5318 Typical Application Circuit (3.3 V Supply)
Rev. 1.0
13
Si5318
2. Functional Description
The Si5318 is a high-performance precision clock
multiplication and clock generation device. This device
accepts a clock input in the 19, 39, 78, or 155 MHz
range, attenuates significant amounts of jitter, and
generates a clock output in the 19 or 155 MHz range.
The Si5318 employs Silicon Laboratories DSPLL®
technology to provide excellent jitter performance while
minimizing the external component count and
maximizing flexibility and ease-of-use. The Si5318
DSPLL phase locks to the input clock signal, attenuates
jitter, and multiplies the clock frequency to generate the
device SONET/SDH-compliant clock output. The
DSPLL loop bandwidth is user-selectable, allowing the
Si5318 jitter performance to be optimized for different
applications. The Si5318 can produce a clock output
with jitter generation as low as 1.0 psRMS (see Table 4),
making the device an ideal solution for clock
multiplication in SONET/SDH systems.
This digital technology also allows for highly stable and
consistent operation over all process, temperature, and
voltage variations.
2.1.1. Selectable Loop Filter Bandwidth
The digital nature of the DSPLL loop filter allows control
of the loop filter parameters without the need to change
external components. The Si5318 provides the user
with up to eight user-selectable loop bandwidth settings
for different system requirements. The base loop
bandwidth is selected using the BWSEL [1:0] and
DBLBW = 0 pins. When DBLBW is driven high, the
bandwidth selected on the BWSEL[1:0] pins is doubled.
(See Table 7.)
When DBLBW is asserted, the Si5318 shows improved
jitter generation performance. DBLBW function is
defined only when hitless recovery from digital hold is
disabled. Therefore, when DBLBW is high, the user
must also drive FXDDELAY high for proper operation.
2.2. Clock Input and Output Rate Selection
The Si5318 monitors the clock input signal for loss-ofsignal, and provides a loss-of-signal (LOS) alarm when
missing pulses are detected. The Si5318 provides a
digital hold capability to continue generation of a stable
output clock when the input reference is lost.
The Si5318 provides a 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, or 8x
clock frequency multiplication function. Output rates
vary in accordance with the input clock rate. The
multiplication factor is configured by selecting the input
and output clock frequency ranges for the device.
2.1. DSPLL®
The Si5318 accepts an input clock in the 19, 39, 78, or
155 MHz frequency range. The input frequency range is
selected using the INFRQSEL[2:0] pins. The
INFRQSEL[2:0] settings and associated output clock
rates are given in Table 8.
The Si5318 phase-locked loop (PLL) uses Silicon
Laboratories' DSPLL technology to eliminate jitter,
noise, and the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltagecontrolled oscillator (VCO). The technology produces a
low phase noise clock with less jitter than is generated
using traditional methods. See Figure 4 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated, making the DSPLL less
susceptible to board-level noise sources.
14
The Si5318 DSPLL phase locks to the clock input signal
to generate an internal VCO frequency that is a multiple
of the input clock frequency. The internal VCO
frequency is divided down to produce a clock output in
the 19 or 155 MHz frequency range. The clock output
range is selected using the Frequency Select
(FRQSEL[1:0]) pins. The FRQSEL[1:0] settings and
associated output clock rates are given in Table 9.
The Si5318 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates scale accordingly. When a 19.44 MHz input clock
is used, the clock output frequency is 19.44 or
155.52 MHz.
Rev. 1.0
Si5318
2.3. PLL Performance
Table 7. Loop Bandwidth Settings
Loop
Bandwidth
BWSEL1
BWSEL0
DBLBW*
12800 Hz
1
1
1
6400 Hz
1
1
0
6400 Hz
0
0
1
3200 Hz
0
0
0
3200 Hz
0
1
1
1600 Hz
0
1
0
1600 Hz
1
0
1
800 Hz
1
0
0
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
also a function of the PLL bandwidth setting. Higher
loop bandwidth settings may result in lower jitter
generation, but may also result in less attenuation of
jitter on the input clock signal.
2.3.2. Jitter Transfer
*Note: When DBLBW = 1, FXDDELAY must be asserted.
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
Reserved
Reserved
Reserved
155 MHz
78 MHz
39 MHz
19 MHz
Reserved
INFRQSEL2 INFRQSEL1 INFRQSEL0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Table 9. Nominal Clock Output Frequencies
Output Clock Frequency
Range
Reserved
155 MHz
19 MHz
Driver Powerdown
The Si5318 PLL is designed to provide extremely low
jitter generation, high jitter tolerance, and a wellcontrolled jitter transfer function with low peaking and a
high degree of jitter attenuation.
FRQSEL1
FRQSEL0
1
1
0
0
1
0
1
0
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5318 provides tightlycontrolled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board, providing more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. (See Table 7.) Lower bandwidth
selection settings result in more jitter attenuation of the
incoming clock but may result in higher jitter generation.
Table 4 on page 8 gives the 3 dB bandwidth and
peaking values for specified BWSEL settings. Figure 6
shows the jitter transfer curve mask.
Jitter
Transfer
Jitter Out
(s)
Jitter In
0 dB
Peaking
–20 dB/dec.
F BW
f Jitter
Figure 6. PLL Jitter Transfer Mask/Template
Rev. 1.0
15
Si5318
2.3.3. Jitter Tolerance
Clock Output Phase
Jitter tolerance for the Si5318 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency, because tolerance
improves for lower input jitter frequency. See Figure 7.
Input
Jitter
Am plitude
–20 dB/dec.
mPT
t PT_MTIE
Excessive Input Jitter Range
t
10 ns
Recovery from
Digital Hold
Figure 8. Recovery from Digital Hold
F BW
f Jitter In
Figure 7. Jitter Tolerance Mask/Template
2.4. Digital Hold of the PLL
When no valid input clock is available, the Si5318
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is again valid. This clock maintains very
stable operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 8.
2.5. Hitless Recovery from Digital Hold
When the Si5318 device is locked to a valid input clock,
a loss of the input clock causes the device to
automatically switch to digital hold mode. When the
input clock signal returns, the device performs a
“hitless” transition from digital hold mode back to the
selected input clock. That is, the device performs
“phase build-out” to absorb the phase difference
between the internal VCO clock operating in digital hold
mode and the new/returned input clock. The maximum
phase step size seen at the clock output during this
transition and the maximum slope for this phase step
are given in Table 4 on page 8.
This feature can be disabled by asserting the
FXDDELAY pin. When the FXDDELAY pin is high, the
output clock is phase and frequency locked with a
known phase relationship to the input clock.
Consequently, any abrupt phase change on the input
clock propagates through the device, and the output
slews at the selected loop bandwidth until the original
phase relationship is restored.
Note: When the DBLBW is asserted, hitless recovery must
also be disabled by driving FXDDELAY high for proper
operation.
16
2.6. Loss-of-Signal Alarm
The Si5318 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this
divided-down input clock to search for extended periods
of time without input clock transitions. If the LOS
circuitry detects four consecutive samples of the
divided-down input clock that are the same state (i.e.,
1111 or 0000), a LOS condition is declared, the Si5318
goes into digital hold mode, and the LOS output alarm
signal is set high. The LOS sampling circuitry runs at a
frequency of fO_155/2, where fO_155 is the output clock
frequency when the FRQSEL[1:0] pins are set to 10.
Table 3 on page 7 lists the minimum and maximum
transitionless time periods required for declaring a LOS
on the input clock (tLOS).
Once the LOS alarm is asserted, it is held high until the
input clock is validated over a time period designated by
the VALTIME pin. When VALTIME is low, the validation
time period is about 100 ms. When VALTIME is high,
the validation time period is about 13 s. If another LOS
condition is detected on the input clock during the
validation time (i.e., if another set of 1111 or 0000
samples are detected), the LOS alarm remains
asserted, and the validation time starts over. When the
LOS alarm is finally released, the Si5318 exits digital
hold mode and locks to the input clock. The LOS alarm
is automatically set high at power-on and at every lowto-high transition of the RSTN/CAL pin. In these cases,
the Si5318 undergoes a self-calibration before releasing
the LOS alarm and locking to the input clock.
Rev. 1.0
Si5318
The Si5318 also provides an output indicating the digital
hold status of the device, DH_ACTV. The Si5318 only
enters the digital hold mode upon the loss of the input
clock. When this occurs, the LOS alarm will also be
active. Therefore, applications that require monitoring of
the status of the Si5318 need only monitor the
CAL_ACTV and either the LOS or DH_ACTV outputs to
know the state of the device.
2.7. Reset
The Si5318 provides a Reset/Calibration pin, RSTN/
CAL, which resets the device and disables the outputs.
When the RSTN/CAL pin is driven low, the internal
circuitry enters into the reset mode, and all LVTTL
outputs are forced into a high-impedance state. Also,
the CLKOUT+ and CLKOUT– pins are forced to a
nominal CML logic LOW and HIGH respectively (See
Figure 9). This feature is useful in in-circuit test
applications. A low-to-high transition on RSTN/CAL
initializes all digital logic to a known condition and
initiates self-calibration of the DSPLL. Upon completion
of self-calibration, the DSPLL begins to lock to the clock
input signal.
VDD 2.5 V
100 Ω
If the self-calibration is initiated without a valid clock
present, the device waits for a valid clock before
completing the self-calibration. The Si5318 clock output
is set to the lower end of the operating frequency range
while the device is waiting for a valid clock. After the
clock input is validated, the calibration process runs to
completion; the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require recalibration. If the clock input is lost following selfcalibration, the device enters digital hold mode. When
the input clock returns, the device re-locks to the input
clock without performing a self-calibration. During the
calibration process, the output clock frequency is
indeterminate and may jump as high as 5% above the
final locked value.
2.9. Bias Generation Circuitry
The Si5318 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 kΩ
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
100 Ω
CLKOUT–
CLKOUT+
The Si5318 provides a differential input for the clock
input, CLKIN. This input is internally biased to a voltage
of VICM (see Table 2 on page 6) and may be driven by a
differential or single-ended driver circuit. For differential
transmission lines, the termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
15 mA
The Si5318 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
Figure 9. CLKOUT± Equivalent Circuit, RSTN/
CAL asserted LOW
For single-ended output operation, simply connect to
either CLKOUT+ or CLKOUT–, and leave the unused
signal unconnected.
2.12. Power Supply Connections
2.8. PLL Self-Calibration
The Si5318 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss of power condition. Selfcalibration can also be manually initiated by a low-tohigh transition on the RSTN/CAL input.
Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires the
presence of a valid input clock.
The Si5318 incorporates an on-chip voltage regulator.
The
voltage
regulator
requires
an
external
compensation circuit of one resistor and one capacitor
to ensure stability over all operating conditions.
Internally, the Si5318 VDD33 pins are connected to the
on-chip voltage regulator input, and the VDD33 pins also
supply power to the device’s LVTTL I/O circuitry. The
VDD25 pins supply power to the core DSPLL circuitry
and are also used for connection of the external
compensation circuit.
Rev. 1.0
17
Si5318
The regulator’s compensation circuit is in reality a
resistor and a capacitor in series between the VDD25
node and ground. (See Figure 5 on page 13.) Typically,
the resistor is incorporated into the capacitor’s
equivalent series resistance (ESR). The target RC time
constant for this combination is 15 to 50 µs. The
capacitor used in the Si5318 evaluation board is a
33 µF tantalum capacitor with an ESR of 0.8 Ω. This
gives an RC time constant of 26.4 µs. The Venkel part
number, TA6R3TCR336KBR, is an example of a
capacitor that meets these specs.
To get optimal performance from the Si5318 device, the
power supply noise spectrum must comply with the plot
in Figure 10. This plot shows the power supply noise
tolerance mask for the Si5318. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
Vn (µ V/√ Hz)
2100
42
f
10 kHz
100 MHz
500 kHz
Figure 10. Power Supply Noise Tolerance Mask
18
Rev. 1.0
Si5318
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5318, consider the following:
„
Power the device from 3.3 V since the internal
regulator provides at least 40 dB of isolation to the
VDD25 pins (which power the PLL circuitry).
„
Use an isolated local plane to connect the VDD25
pins. Avoid running signal traces over or below this
plane without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mVPP to
500 mVPP differential range.
„
„
„
Excessive high-frequency harmonics of the input
clock should be minimized. The use of filters on the
input clock signal can be used to remove highfrequency harmonics.
Rev. 1.0
19
Si5318
3. Pin Descriptions: Si5318
8
7
6
5
4
3
2
1
RSVD_NC
RSVD_NC
RSVD_NC
RSVD_NC
RSVD_NC
RSVD_GND
RSVD_GND
RSVD_NC
RSVD_GND
RSVD_GND
RSVD_NC
FXDDELAY
RSVD_GND
RSVD_GND
BWSEL[0]
B
RSVD_GND
GND
GND
GND
GND
GND
VDD33
BWSEL[1]
C
DH_ACTV
VDD25
VDD25
VDD33
VDD33
VDD33
DBLBW
CLKIN+
D
CAL_ACTV
VDD25
VDD25
VDD33
VDD33
VDD33
GND
LOS
VDD25
VDD25
VDD25
VDD25
VDD25
GND
INFRQSEL[0]
F
GND
GND
GND
GND
GND
GND
GND
INFRQSEL[1]
G
FRQSEL[1]
CLKOUT–
CLKOUT+
FRQSEL[0]
VALTIME
RSTN/CAL
REXT
INFRQSEL[2]
H
A
CLKIN–
Bottom View
Figure 11. Si5318 Pin Configuration (Bottom View)
20
Rev. 1.0
E
Si5318
1
A
2
3
4
5
6
7
8
RSVD_GND
RSVD_GND
RSVD_NC
RSVD_NC
RSVD_NC
RSVD_NC
RSVD_NC
B
BWSEL[0]
RSVD_GND
RSVD_GND
FXDDELAY
RSVD_NC
RSVD_GND
RSVD_GND
RSVD_NC
C
BWSEL[1]
VDD33
GND
GND
GND
GND
GND
RSVD_GND
D
CLKIN+
DBLBW
VDD33
VDD33
VDD33
VDD25
VDD25
DH_ACTV
E
CLKIN–
GND
VDD33
VDD33
VDD33
VDD25
VDD25
CAL_ACTV
F
INFRQSEL[0]
GND
VDD25
VDD25
VDD25
VDD25
VDD25
LOS
G
INFRQSEL[1]
GND
GND
GND
GND
GND
GND
GND
H
INFRQSEL[2]
REXT
RSTN/CAL
VALTIME
FRQSEL[0]
CLKOUT+
CLKOUT–
FRQSEL[1]
Top View
Figure 12. Si5318 Pin Configuration (Transparent Top View)
Rev. 1.0
21
Si5318
Table 10. Si5318 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
B4
FXDDELAY
I*
LVTTL
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications that
require a known, or constant, input-to-output phase
relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from digital
hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
"phase build out" to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized. In
this case, the input-to-output phase relationship following the transition out of digital hold mode is determined by the phase relationship at the time that
switching occurs.
Note: FXDDELAY should remain at a static high or static
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin is
low. FXDDELAY must be set high when DBLBW is
set high.
D1
E1
CLKIN+
CLKIN–
I
AC Coupled
System Clock Input.
200–500 mVPPD Clock input to the DSPLL circuitry. The frequency of
(See Table 2) the CLKIN signal is multiplied by the DSPLL to generate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The frequency of the CLKIN clock input can be in the 19, 39,
78, or 155 MHz range (nominally 19.44, 38.88,
77.76, or 155.52 MHz) as indicated in Table 3 on
page 7. The clock input frequency is selected using
the INFRQSEL[2:0] pins. The clock output frequency
is selected using the FRQSEL[1:0] pins.
*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
22
Rev. 1.0
Si5318
Table 10. Si5318 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
F1
G1
H1
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
I*
LVTTL
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 39 MHz range.
011 = 78 MHz range.
100 = 155 MHz range.
101 = Reserved.
110 = Reserved.
111 = Reserved.
F8
LOS
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5318 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or
13 seconds of a valid CLKIN clock input, depending
on the setting of the VALTIME input.
D8
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the current
state of the DSPLL and forces the DSPLL to continue
generation of the output clock with no additional
phase or frequency information from the input clock.
H3
RSTN/CAL
I*
LVTTL
Reset/Calibrate.
When low, the internal circuitry enters the reset mode
and all LVTTL outputs are forced into a high-impedance state. Also, the CLKOUT+ and CLKOUT– pins
are forced to a nominal CML logic LOW and HIGH
respectively. This feature is useful for in-circuit test
applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
Upon completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
Rev. 1.0
23
Si5318
Table 10. Si5318 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
H6
H7
CLKOUT+
CLKOUT–
O
CML
Differential Clock Output.
High frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multiplication factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19 or 155 MHz
range as indicated in Table 3 on page 7. The clock
output frequency is selected using the FRQSEL[1:0]
pins. The clock input frequency is selected using the
INFRQSEL[2:0] pins.
H5
H8
FRQSEL[0]
FRQSEL[1]
I*
LVTTL
Clock Output Frequency Range Select
Select frequency range of the clock output, CLKOUT.
(See Table 3 on page 7.)
00 = Clock Driver Powerdown.
01 = 19 MHz Frequency Range.
10 = 155 MHz Frequency Range.
11 = Reserved.
B1
C1
BWSEL[0]
BWSEL[1]
I*
LVTTL
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note: The loop filter bandwidth will be twice the value
indicated when DBLBW is set high.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-calibration and the subsequent initial lock acquisition
period.
H4
VALTIME
I*
LVTTL
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately
13 seconds. When VALTIME is low, the validation
time is approximately 100 ms.
A2, A3, B2,
B3, B6, B7,
C8
RSVD_GND
—
LVTTL
Reserved—GND.
This pin must be tied to GND for normal operation.
*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
24
Rev. 1.0
Si5318
Table 10. Si5318 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
A4–8, B5, B8
RSVD_NC
—
LVTTL
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
C2, D3–D5,
E3–E5
VDD33
VDD
Supply
3.3 V Supply.
3.3 V power is applied to the VDD33 pins. Typical
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
D6, D7, E6,
E7, F3–F7
VDD25
VDD
Supply
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
C3–C7, E2,
F2, G2–G8
GND
GND
Supply
Ground.
Must be connected to system ground. Minimize the
ground path impedance for optimal performance of
the device.
H2
REXT
I
Analog
External Biasing Resistor.
Used by on-chip circuitry to establish bias currents
within the device. This pin must be connected to
GND through a 10 kΩ (1%) resistor.
D2
DBLBW
I*
LVTTL
Double Bandwidth
Active high input to boost the selected bandwidth 2x.
When this pin is high, the loop filter bandwidth
selected on BWSEL[1:0] is doubled. When this pin is
high, FXDDELAY must also be high.
*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
Rev. 1.0
25
Si5318
4. Ordering Guide
Part Number
Package
Temperature
Si5318-X-BC
63-Ball CBGA
–20 to 85 °C
Note: “X” denotes product revision.
26
Rev. 1.0
Si5318
5. Package Outline
Figure 13 illustrates the package details for the Si5318. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 13. 63-Ball Ceramic Ball Grid Array (CBGA)
Table 11. Package Drawing Dimensions
Dimension
Description
Minimum
Nominal
Maximum
A
Total Package Height
2.13
2.28
2.43
A1
Standoff
0.60
0.70
0.80
A2
Ceramic Thickness
0.88
0.98
1.08
A3
Mold Cap Thickness
0.55
0.60
0.65
b
Solder Ball Diameter
0.65
0.70
0.75
D
Ceramic Body Size
8.85
9.00
9.15
D1
Mold Cap Size
8.55
8.75
8.95
e
Solder Ball Pitch
1.00 BSC
S
Pitch to Centerline
0.50 BSC
Rev. 1.0
27
Si5318
6. 9x9 mm CBGA Card Layout
Placement Courtyard
Table 12. Recommended Land Pattern Dimensions
Symbol
Parameter
Dimension
Notes
Min
Nom
Max
C
Column Width
—
7.00 REF
—
D
Row Height
—
7.00 REF
—
E
Pad Pitch
—
1.00 BSC
—
F
Placement Courtyard
10.00
—
—
1
X
Pad Diameter
0.64
0.68
0.72
2, 3
Notes:
1. The Placement Courtyard is the minimum keep-out area required to assure assembly clearances.
2. Pad Diameter is Copper Defined (Non-Solder Mask Defined/NSMD).
3. OSP Surface Finish Recommended.
4. Controlling dimension is millimeters.
5. Land Pad Dimensions comply with IPC-SM-782 guidelines.
6. Target solder paste volume per pad is 0.065 mm3 ± 0.010 mm3 (4000 mils3 ± 600 mils3).
Recommended stencil aperture dimensions to achieve target solder paste volume are 0.191 mm
thick x 0.68±0.01 mm diameter, with a 0.025 mm taper.
7. Recommended stencil type is chemically etched stainless steel with circularly tapered apertures.
28
Rev. 1.0
Si5318
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
„
Updated θJA in Table 6, “Thermal Characteristics,” on page 12.
Rev. 1.0
29
Si5318
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
30
Rev. 1.0