Si5326-VTSS-EVB Si5326 S YNC - E V ITESSE T IMING M O D U L E U SER ' S G UIDE 1. Introduction The Si5326-VTSS-EVB is a platform for evaluating Silicon Laboratories' Si5326 Any-Frequency Precision Clock. The Si5326 Any-Frequency Precision Clock is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. The device has excellent phase noise and jitter performance. The Si5326 jitter attenuating clock multiplier supports jitter generation of 0.3 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz– 80 MHz jitter filter bandwidths. The DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. This device is ideal for providing clock multiplication/clock division, jitter attenuation, and clock distribution in mid-range and high-performance timing applications. The Si5326-VTSS-EVB is designed as an add-on to a Vitesse Ethernet switch reference board. The compatible reference boards are listed below, along with each board's Vitesse devices and other features. For more information on any of these boards, visit www.vitesse.com. VSCxxxxEV—VSC7407 28-port 1GbE L2 Switch + VSC8664 Synchronous Ethernet PHYs 24-port 1GbE RJ45 + 4-port 10GbE L2/L3 Carrier Ethernet Switch + VSC8664 Synchronous Ethernet PHYs VSC5607EV—VSC7460 24-port 1GbE SFP + 4-port 10GbE L2/L3 Carrier Ethernet Switch VSC5608EV—VSC7460 48-port 1GbE RJ45 L2/L3 Carrier Ethernet Switch + VSC8512 PHYs VSC5611EV—VSC7429 26-port 1GbE L2 Carrier Ethernet Switch + VSC8512 Synchronous Ethernet PHY VSC7428EV—VSC7428 8-port 1GbE + 2-port 2.5GbE L2/L3 Carrier Ethernet Switch with fully integrated 1GbE PHYs Sophisticated management of the Si5326-VTSS-EVB is fully-integrated into the switch management software, which is run by the ARM9™ CPU embedded in the switch engine. The Vitesse VSCxxxxEV Ethernet switch reference board and the Si5326-VTSS-EVB provide a low-cost, no-risk, sophisticated Sync-E-capable Gigabit Ethernet switch solution. The Si5326-VTSS-EVB is compliant with the Vitesse specification, RDR-0017-01-03SyncE_addon_board. VSC5606EV—VSC7640 Rev. 0.2 12/11 Copyright © 2011 by Silicon Laboratories Si5326-VTSS-EVB Si5326-VTSS-EVB Figure 1. Si5326-VTSS-EVB Top Figure 2. Si5326-VTSS-EVB Bottom 2 Rev. 0.2 Si5326-VTSS-EVB 2. Applications The Si5326 Any-Frequency Precision Clock has a comprehensive feature set, including any-frequency synthesis, two clock inputs, two clock outputs, alarm and status outputs, hitless switching between input clocks, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), output phase adjustment between output clocks, and output phase adjustment between all output clocks and the selected reference input clock (phase increment/decrement). The Si5326 is controlled by a microprocessor or MCU (microcontroller unit) via an I2C or SPI interface and is a jitter-attenuating clock multiplier with a loop bandwidth ranging from 60 Hz to 8.4 kHz. For more details, consult the Silicon Laboratories timing products website at www.silabs.com/timing. The evaluation board (EVB) has a Silicon Labs MCU (C8051F340) that supports USB communications with a PC host. The device is controlled and monitored through the serial port (either SPI or I2C). The serial port can connect to either the MCU or to the Vitesse Ethernet switch reference board. A CPLD that performs arbitration between the slaves and hosts sits between the MCU, the switch reference board, and the Any-Frequency Precision Clock device. The EVB is configured for CMOS clock inputs and outputs. Clock IO going to/from the Vitesse Ethernet switch reference board can be monitored using separate SMA connectors. The EVB can also be run stand-alone using either a separate power supply connector or directly from USB power. LEDs are provided for convenient monitoring of key status signals. 3. Features The Si5326-VTSS-EVB includes the following: CD with documentation and EVB software including the DSPLLsim configuration software utility circuit board including an Si5326 User's Guide (this document) EVB Rev. 0.2 3 Si5326-VTSS-EVB 4. Si5326-VTSS-EVB Configuration and Management Quick Start The Si5326-VTSS-EVB can be configured, controlled, and monitored with the Vitesse VSCxxxxEV evaluation board or by a host PC's USB port. The USB port should be used when it is necessary to customize the Si5326's configuration. For more information, see "7.Installing Software for the Direct Control of the Si5326-VTSS-EVB" on page 10. 4.1. Managing the Vitesse VSCxxxxEV Ethernet Switch Reference Board and an Attached Si5326-VTSS-EVB through a Web GUI Before you can log in to this, you must know the IP address of the VSCxxxxEV board. First, connect any of the VSCxxxxEV Ethernet ports to your computer network, which should provide access to a DHCP server. Power up the VSCxxxxEV board and wait a few minutes. Now, the VSCxxxxEV board has received an IP address from the DHCP server. Next, connect your PC to the VSCxxxxEV board using a serial cable (DB9 connector) and a terminal program, such as Windows' Hyperterm (115200 baud, 8 data bits, 1 stop bit, no parity) for getting access to the VSCxxxxEV command line interface. The CLI command "ip conf" will return the IP address of the VSCxxxxEV. Then you can log in to the VSCxxxxEV management web GUI using a web browser and the IP address from above (type "http://xx.xx.xx.xx" in your browser's address line, with xx.xx.xx.xx being the IP address of the VSCxxxxEV). A password request will appearl; user name is "admin", and password is blank/empty. Select the SyncE bullet in the configuration menu, and you are presented with the Si5326-VTSS-EVB management GUI shown in Figure 3. Figure 3. Si5326-VTSS-EVB Management GUI The GUI help pages provide information on the fields available in the management interface and are accessed through the question mark button at the top right. If you need to update the VSCxxxxEV firmware, refer to Vitesse application note “AN0123: Reference System Software Update", which is available as part of the "VSC7407 Software, Tools, and Application Notes" collateral package at www.vitesse.com. 4 Rev. 0.2 Si5326-VTSS-EVB 5. Functional Description The Si5326-VTSS-EVB and its software allow for a complete and simple evaluation of the functions, features, and performance of the Si5326 Any-Frequency Precision Clock. 5.1. Block Diagram Refer to the block diagram of the evaluation board shown in Figure 4. The VSCxxxxEV communicates to the Si5326 through the CPLD. The MCU also communicates to the host PC over a USB connection, also through the CPLD. Si530 Serial Number 114.285 MHz CPLD MCU SPI Si5326 Si5326 SPI USB MCU LOL Reset Switch Late Reset EEPROM SyncE SPI SMA ClkIn CKOUT ClkOut CKIN SyncE QTE Connector Figure 4. Si5326-VTSS-EVB Block Diagram 5.2. Si5326 Input and Output Clocks The Si5326 has two clock inputs coming from the VSCxxxxEV that are dc-coupled and can be monitored at two SMA output connectors. These SMA connectors can optionally be configured to be clock inputs instead of being clock monitoring outputs. A 114.285 MHz differential PECL Si530 oscillator provides the reference supply to the Si5326. There are optional provisions for using a lower-cost third overtone crystal instead of the Si530 oscillator. The clock outputs go to both the VSCxxxxEV and two SMA connectors. All clock input and output is configured for dc-coupled LVCMOS operating at 3.3 V. The CPLD arbitrates between the two possible SPI bus masters: the MCU and the VSCxxxxEV. The arbitration logic is very simple: the MCU has priority over the VSCxxxxEV and will override it at any time. The CPLD also generates the Late Reset signal that goes to the VSCxxxxEV. Late Reset holds the VSCxxxxEV in a reset condition until the clock output of the Si5326 has been initialized and its output clock is stable. The CPLD also buffers the alarm output of the Si5326 and sends it to the VSCxxxxEV interrupt. Rev. 0.2 5 Si5326-VTSS-EVB 120 ms 230 ms rst_26_n late_reset_n LOL CKOUT0 > 20 ms Figure 5. Late Reset Timing The MCU connects to a host PC's USB port. It also loads the Si5326 with a power-up frequency plan immediately after a reset condition goes away. The power-up frequency plan is contained in the EEPROM, and the EVB has an MCU-readable serial number device so that the EVB can be uniquely identified. 6 Rev. 0.2 Si5326-VTSS-EVB 6. Connectors and LEDs 6.1. LEDs The board contains eight LEDs that provide a quick and convenient means of determining board status. Table 1. LED Status and Description LED Color Label Description D1 yellow MCU Normally ON; flashes for MCU errors D2 yellow M_M MCU Master; ON when the MCU is the SPI bus master D3 green CA OFF when CKIN1 is selected, ON for CKIN2 or Free Run D4 red C2B ON when CKIN2 is bad or not present D5 red C1B ON when CKIN1 is bad or not present D6 red LOL ON when there is a loss of lock (LOL) D7 green V_M ON when VSCxxxxEV is the SPI bus master D8 Green 3.3V ON when 3.3 V is present 6.2. User Jumpers and Headers See Figure 6 to locate the jumpers and connectors described below. J8 MCU J4 on bottom of board Si5326 J14 CPLD J15 J17 J6 J16 reset Figure 6. Connectors and Jumper Header Locations J14 and J15 are the SMA output connectors for monitoring CKIN0 and CKIN2, respectively. By adding and removing components (see schematic), these connectors can be configured as 3.3 V LVCMOS clock inputs. J16 and J17 are the SMA clock output monitor connectors for CKOUT0 and CKOUT1, respectively. They are dccoupled 3.3 V LVCMOS outputs that include series termination. Rev. 0.2 7 Si5326-VTSS-EVB J4 is the connector that goes to the VSCxxxxEV motherboard. It supplies the power, clock inputs/outputs, SPI bus signal, and other control and monitoring signals. The pinout for J4 is a subset of that described in Vitesse specification RDR-0017-01-03-SyncE_addon_board. Table 2. Pin Names 8 Pin Name Pin Name 1 FastLink_N_0 2 — 3 ClkIn0 4 — 5 FastLink_N_1 6 — 7 ClkIn1 8 — 9 — 10 — 11 Gnd 12 — 13 — 14 Gnd 15 — 16 — 17 — 18 — 19 — 20 — 21 — 22 — 23 — 24 — 25 — 26 — 27 — 28 — 29 Gnd 30 Gnd 31 — 32 — 33 — 34 — 35 — 36 — 37 — 38 — 39 Gnd 40 Gnd 41 FreeClkIn 42 — 43 ClkOut0 44 — 45 — 46 — 47 ClkOut1 48 — 49 Gnd 50 — 51 ClkOut2 52 — 53 Gnd 54 — 55 — 56 — 57 Gnd 58 Gnd 59 SPI_EN_n 60 SPI_MOSI 61 SPI_CLK 62 SPI_MISO 63 Gnd 64 Gnd 65 I2C_SDA 66 LATE_RESET_n Rev. 0.2 Si5326-VTSS-EVB Table 2. Pin Names (Continued) Pin Name Pin Name 67 I2C_SCL 68 INT_n 69 VCC_3V3 70 PRESENT_n 71 VCC_3V3 72 Gnd 73 RST_N (Spare0) 74 TCK (Spare4) 75 C2CK (Spare1) 76 TDI (Spare5) 79 C2D (Spare2) 78 TDO (Spare6) 79 VCCAUX (Spare3) 80 TMS, Spare7) 6.2.1. Stand Alone Power The EVB can optionally be powered from the USB connector for stand-alone operation. J6 is normally jumpered from pin1 to pin 2 so that power comes from the VSCxxxxEV. To power the Si5326-VTSS-EVB from the USB port, jumper J6 pin 2 to J6 pin 3. 6.2.2. USB Connection J8 is the USB connector that goes to the PC host. The Si5326-VTSS-EVB is normally powered from the VSCxxxxEV, not the USB port. Rev. 0.2 9 Si5326-VTSS-EVB 7. Installing Software for the Direct Control of the Si5326-VTSS-EVB Some applications may call for the input and/or output frequency of the Si5326-VTSS-EVB to be custom-tailored. It may also be necessary to change or monitor internal Si5326 registers. To accomplish this, the Precision Clock EVB Software should be installed. The following sections describe how to install the EVB software. The procedure for installing the Precision Clock EVB Software, DSPLLsim, is included on the release CD for the Si5326-VTSS-EVB. DSPLLsim and its release notes can also be downloaded from the Silabs web site: www.silabs.com/timing. Follow the links for 1-PLL Jitter Attenuators and look under the Tools tab. Note: These programs can control any of the Any-Frequency Precision Clock devices including the Si5316, Si532x, and Si536x devices. This software can be installed once per PC and used for all available Precision Clock EVBs. 10 Rev. 0.2 0 ohm SDO SCLK RST_26_N SDI SS_N CLK_IN_1 CLK_IN_0 0 ohm C28 100N V3P3 R27 R22 A NC U14 37.4 R3 0 ohm R20 NOPOP C31 100N 1 4 J15 Clk+ Clk- Vdd 1 C34 10NF C19 10NF Si530_PECL Gnd OE NC1 U13 R62 49.9 NOPOP 3 2 1 J14 SMA_VERT 1 CKIN0 CKIN1 SMA_VERT R59 49.9 NOPOP 37.4 R53 0 ohm R25 NOPOP 1 4 NOPOP 49.9 R60 R12 Y NC7SV34 U1 NC Y A 0 ohm V3P3 2 2 5 Vcc Gnd 3 5 Vcc Gnd 3 2 3 4 5 NC7SV34 4 5 6 2 1 R63 118 4 4 0 ohm 37.4 C5 10NF R64 118 100N R10 R11 3 C6 10NF C30 100N C29 1 36 2 27 26 25 24 23 22 14 9 20 19 12 13 16 17 6 7 R4 U3 RST CMODE FRQTBL SDI_FRQSEL3 A2_SS_FRQSEL2 A1_FRQSEL1 A0_FRQSEL0 INT_C1B C2B SFOUT0 SFOUT1 CKOUT2+ CKOUT2- CKOUT1+ CKOUT1- LOL CKSEL/CK_ACTV Si532x SDA_SDO_BWSEL1 SCL_SCLK_BWSEL0 DBL2_BY AUTOSEL INC DEC CKIN_2+ CKIN_2- CKIN1+ CKIN1- XA XB NOPOP 0 ohm 1 4 R9 R8 1 4 37.4 R7 C32 100N V3P3 37.4 R6 10 1 J17 CKOUT1 SMA_VERT 1 J16 CKOUT0 SMA_VERT 18 21 3 4 33 30 LOL CS_CA 18 19 9 Si5326 CLK_OUT_1 37.4 U15 Y NC7SV34 NC A 37.4 2 Locate very close to Si5326 U2 NC Y NC7SV34 CLK_OUT_0 C1B C2B A 35 34 C4 100N C2 1UF 2 C27 100N 28 29 C3 100N C1 100N L1 Ferrite Figure 7. Si5326 Schematic V3P3 114.285 MHz 2 GND NOPOP X1 1 3 dual footprint: either the Xtal or two resistors R2 0 ohm 15 Rate1 C26 100N 11 Rate0 2 3 4 5 2 1 5 10 32 VDD1 VDD2 VDD3 GND1 GND2 GND5 Rev. 0.2 8 31 37 5 Vcc Gnd 3 5 Vcc Gnd 3 2 3 4 5 2 3 4 5 V3P3 27 1 28 36 Si5326-VTSS-EVB 8. Si5326-VTTS-EVB Schematics 11 Rev. 0.2 C15 100N + 2 L2 1 MCU debug RST_N C2CK C2D 4 3 2 1 gnd1 R56 R10x4 5 6 7 8 gnd1 NOPOP 0 ohm R52 I2C_SDA I2C_SCL 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 85 83 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J4 gnd1 C16 C17 220UF 1UF Ferrite V_SPI_SS_N V_SPI_CLK U4C XC2C64 TO_MAX811_N FB4_11 FB4_13 FB4_14 FB4_15 FB4_7 FB4_1 FB4_2 FB2_12 FB2_13 FB2_5 FB2_6 FB2_1 FB2_2 gnd1 NOPOP 0 ohm R55 CLK_OUT_1 FREE_CLK_IN CLK_OUT_0 FASTLINK_N_1 CLK_IN_1 12 13 14 16 8 5 6 2 3 41 42 39 40 Bank 1 FB2_7_GCK0 FB2_8_GCK1 FB2_10_GCK2 gnd1 1UF C14 V3P3 USB_PWR 1 2 3 0 ohm FASTLINK_N_0 CLK_IN_0 R18 NOPOP R54 43 44 1 gnd2 J6 R17 to SDO 37.4 NOPOP 0 ohm flop_not gnd4 Power Source Selection FASTLINK_N_1 V_SPI_SS_N V_SPI_CLK V_SPI_MOSI V_SPI_MISO FASTLINK_N_0 MCU_MASTER INT_N RST_26_N CS_CA C1B NOPOP R13 0 ohm 81 82 12 gnd3 87 88 FREE_CLK_IN Bank 2 FB1_13_GSR 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 86 84 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 QTE-040 FB3_10 FB3_11 FB3_12 FB3_14 FB3_15 FB3_6 FB3_1 FB3_2 FB3_3 FB1_3 FB1_2 FB1_1 FB1_12_GTS2 FB1_11_GTS3 FB1_10_GTS0 FB1_9_GTS1 30 4 3 2 1 22 21 20 19 18 23 29 28 27 36 37 38 31 32 33 34 R57 5 6 7 8 RST Vcc C33 100N 2 4 INT_N 35 24 10 11 9 VCCAUX TDO TMS TCK TDI R14 JTAG U4B LATE_RESET_N C7 100N XC2C64 V_SPI_MOSI V_SPI_MISO R61 0 ohm MAX811 Gnd MR U5 37.4 REG_ADR1 MCU_MISO MCU_SCLK C8 1UF V3P3 2 3 1 Out FB Vreg R24 0 ohm 37.4 R23 66.5 4 5 37.4 37.4 TPS76201 Gnd EN In U6 R50 10k V3P3 PRESENT_N +3.3V V_MASTER LATE_RESET_N Figure 8. Si5326 CPLD R10x4 R58 10k V3P3 1 3 V3P3 RST_FROM_MAX811_N REG_ADR2 REG_ADR0 MCU_MOSI MCU_SS_N CPLD_RST_N R19 V1P8 R21 113 C12 1UF R16 R15 + C9 33UF C13 100N C10 1UF 1.8V 23 11 100N C11 22 12 26 7 15 U4A 34 44 GND2 GND1 33 1 VCCIO2 GND3 XC2C64 VCCIO1 VCC XC2C64 to/from Si5326 CPLD power SCLK SDO SDI LOL SS_N 25 17 4 Si5326-VTSS-EVB CS MCU_LED MCU_MASTER CS_CA C2B C1B LOL V_MASTER C25 100N MCU_SS_N MCU_MOSI MCU_MISO MCU_SCLK 7 3 1 1 19 2 3 4 5 6 7 8 9 37.4 R37 10k OE1 OE2 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 O0 O1 O2 Q3 O4 O5 O6 O7 V3P3 18 17 16 15 14 13 12 11 Buffer R36 37.4 74LCX541 U12 V3P3 R42 R41 R40 37.4 37.4 R35 37.4 M95040 HOLD EEPROM W Q 8 Vcc Vss 4 2 1 1 1 1 1 1 1 1 D1 Grn Grn D6 D8 D7 Red Red D5 Red D4 D3 Yel Grn D2 Yel 3.3V 2 V_M 2 LOL 2 C1B 2 C2B 2 2 CA 2 M_M MCU 2 R32 37.4 1 2 3 4 4 3 2 1 V3P3 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 C23 100N U10 Si8051F340 46 45 44 43 42 41 40 39 6 5 4 3 2 1 48 47 R150x4 R48 8 7 6 5 R47 R150x4 5 6 7 8 C22 1UF C2CK C2D C8051F340 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 24 13 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 R39 27.4 36 1 37 48 Ser No. I/O NO 3 4 5 C24 100N SW1 4 3 CPLD_RST_N ground pins NC1 NC2 NC3 U11 reset 1 2 V3P3 R31 R29 DS2411 2 R43 1K C21 100N 10 10 serial number EVB_SER_NUM MCU_LED R44 C8051-F340 25 12 37.4 R38 R28 1K 27.4 C20 1UF 1K REG_ADR2 REG_ADR1 REG_ADR0 R33 Figure 9. Si5326-MCU GND 7 RST_N 10 11 Vdd REGIN 1 1 1 1 1 + J13 J12 J11 J10 J9 C35 33UF VBUS + 2 3 2 1 USB Clamp VIN VOUT NC1 U16 FAN1540B C36 33UF U8 SN65220 1 NC1 A 6 5 6 13 14 RST/C2CK C2D 3 NC2 B 4 D Clk 12 8 9 VBUS D+ D- P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 38 37 36 35 34 33 32 31 6 Vcc GND 1 #4 D+ D- J8 H1 NC2 NC3 GND 3 2 U9 USB Clamp Gnd V USB USB #4 H2 #4 H3 USB_PWR #4 H4 3.3V regulator 4 1 SN65220 mounting holes 4 5 6 6 5 Gnd1 5 PAD 7 1 NC1 A 6 S2 1 Gnd2 1 2 Gnd1 Gnd2 3 NC2 B 4 S1 5 MCU debug 1 V3P3 1 U7 20 Vcc GND R26 10k A A C18 100N C C A A C C A A A 10 C A Rev. 0.2 C C C V3P3 Si5326-VTSS-EVB 13 Si5326-VTSS-EVB 9. Bill of Materials Table 3. Bill of Materials Item Qty Reference Part Mfgr Mfr Part Num 1 20 C1,C3,C4,C7,C11, C13,C15,C18,C21, C23,C24,C25,C26, C27,C28,C29,C30, C31,C32,C33 100 nF Venkel C0603X7R160-104KNE 2 8 C2,C8,C10,C12,C14, C17,C20,C22 1 µF Venkel C0603X7R6R3-105KNE 3 4 C5,C6,C19,C34 10 nF Venkel C0603X7R160-103KNE 4 3 C9,C35,C36 33 µF Venkel TA006TCM336MBR 5 1 C16 220 µF Kemet T494B227M004AT 399-4631-1-ND 6 2 D1,D2 Yel Lumex SML-LXT0805YW-TR 67-1554-1-ND 7 3 D3,D7,D8 Grn Lumex SML-LXT0805GW-TR 67-1553-1-ND 8 3 D4,D5,D6 Red Lumex SML-LXT0805SRW-TR 67-1555-1-ND 10 1 J4 QTE-040 Samtec QTE-040-01-L-D-A SAM8132-ND 11 1 J6 Jmpr_3pin 12 1 J8 USB FCI 61729-0010BLF 609-1039-ND 13 5 J9,J10,J11,J12,J13 Jmpr_1pin 14 4 J14,J15,J16,J17 SMA_VERT Johnson 142-0701-211 J494-ND 15 2 L1,L2 Ferrite Venkel FBC1206-471H 16 7 R2,R10,R12, R22,R24,R27,R61 0 Venkel CR0603-16W-000T 17 19 R3,R6,R7,R8,R9,R11, R14,R15,R16,R17, R19,R32,R35,R36, R40,R41,R42,R44, R53,R54,R55 37.4 Venkel CR0603-16W-37R4FT 19 1 R21 113 Venkel CR0603-16W-1130FT 20 1 R23 66.5 Venkel CR0603-16W-66R5FT 21 4 R26,R37, R50,R58 10 k Venkel CR603-16W-1002FT 22 3 R28,R33,R43 1 k Venkel CR0603-16W-1001FT 23 2 R29,R31 10 Venkel CR0603-16W-10R0FT 24 2 R38,R39 27.4 Venkel CR0603-16W-27R4FT 25 2 R47,R48 R150x4 Panasonic EXB-38V151JV Y9151CT-ND 26 2 R56,R57 R10x4 Panasonic EXB-38V100JV Y9100CT-ND 28 1 SW1 NO Mountain Switch 101-0161-EV 101-0161(Mouser) 14 Rev. 0.2 Digi-Key Si5326-VTSS-EVB Table 3. Bill of Materials Item Qty Reference Part Mfgr Mfr Part Num Digi-Key 29 4 U1,U2,U14,U15 NC7SV34 Fairchild NC7SV34P5X NC7SV34P5X-ND 30 1 U3 Si5326C-C-GM Silicon Labs 5326C-C-GM 32 1 U4 XC2C64 Xilinx XC2C64A-7VQG44C 122-1410-ND 33 1 U5 MAX811 Maxim MAX811TEUS MAX811TEUS-ND 34 1 U6 TPS76201 TI TPS76201DBVT 296-11013-1-ND 35 1 U7 M95040 ST Micro M95040-WMN6P 36 2 U8,U9 SN65220 TI SN65220DBVT 37 1 U10 Si8051F340 Silicon Labs C8051F340-GQ 38 1 U11 DS2411 Maxim/Dallas DS2411P 39 1 U12 74LCX541 Fairchild 74LCX541MTC_NL 40 1 U13 Si530_PECL Silabs 530AC114M285DG 40 1 U13 alternate* Si530_CML Silabs 530HB121M109DG 41 1 U16 FAN1540B Fairchild FAN1540B 296-9694-1-ND TC74LCX541FTFCTND FAN1540MPXCT-ND *Note: The alternate Si530 cannot be used without changing the EVB configuration. Contact Silicon Labs for details. Rev. 0.2 15 Si5326-VTSS-EVB Figure 10. Top Layer 10. Si5326-VTSS-EVB Layout 16 Rev. 0.2 Figure 11. Ground Layer Si5326-VTSS-EVB Rev. 0.2 17 Figure 12. Signal Layer (1 of 2) Si5326-VTSS-EVB 18 Rev. 0.2 Figure 13. Signal Layer (2 of 2) Si5326-VTSS-EVB Rev. 0.2 19 Figure 14. Power Layer Si5326-VTSS-EVB 20 Rev. 0.2 Figure 15. Bottom Layer Si5326-VTSS-EVB Rev. 0.2 21 Si5326-VTSS-EVB APPENDIX A—POWERUP AND F A C T O R Y D E F AULT S E T T I N G S The Si5326-VTSS-EVB power-up frequency plan is as follows: Si5326 Frequency Plan CKIN Frequencies (MHz) CKIN1: 125.000000 CKIN2: 114.281820 Input Clock Multiplcation Ratios CKIN2 to CKIN1: 5714091/6250000 fosc: 5.000000 GHz Output Clock Multiplication Ratios CKOUT1 to CKIN1: 1/1 CKOUT Frequencies (MHz) CKOUT1: 125.000000 PLL Divider Settings (Note: These are not binary register values.) N1_HS: 10 NC1_LS: 4 N2_HS: 11 N2_LS: 3520 N31: 968 N32: 885 f3: 0.129132 MHz Free Run Mode Enabled (FREE_RUN_EN = 1) XA-XB Frequency: 114.285000 MHz Available Loop Bandwidths using BWSEL (kHz) 0.06 (BWSEL_REG = 7) 0.12 (BWSEL_REG = 6) 0.24 (BWSEL_REG = 5) 0.49 (BWSEL_REG = 4) 0.98 (BWSEL_REG = 3) 22 Rev. 0.2 Si5326-VTSS-EVB 2.02 (BWSEL_REG = 2) 4.28 (BWSEL_REG = 1) Input Frequency Operating Range (MHz) CKIN1 Min: 121.250000 Max: 141.750000 CKIN2 Min: 110.853564 Max: 129.595816 Output Frequency Operating Range (MHz) CKOUT1 Min: 121.250000 Max: 141.750000 Phase Offset Resolution for Independent Skew: 2.0000 ns Free Run Mode Details: Actual CKOUT1: 125.003254 MHz Error between Actual and Desired CKOUT1: 26.032000 ppm Actual CKOUT1/XA-XB Frequency Ratio: 1.093785 Si5326-VTSS-EVB Power Up Register Setup Description: <?xml version="1.0" encoding="us-ascii" standalone="yes" ?> - <!-- Note: Do not edit the first line or type above it. --> - <!-- Created on: Thursday, March 27, 2008 2:59 PM --> - <settings version="2" chipType="Si5326"> - <!-- pin-based controls --> <entry name="RSTb" data="1" /> <entry name="CMODE" data="1" /> <entry name="RATE" data="MM" /> - <!-- register-based controls --> <entry name="FREE_RUN_EN" data="1" /> <entry name="CKOUT_ALWAYS_ON" data="0" /> <entry name="BYPASS_REG" data="0" /> <entry name="FXDLY" data="0" /> <entry name="CK_PRIOR2" data="1" /> <entry name="CK_PRIOR1" data="0" /> <entry name="CKSEL_REG" data="0" /> <entry name="DHOLD" data="0" /> <entry name="SQ_ICAL" data="0" /> <entry name="BWSEL_REG" data="7" /> <entry name="AUTOSEL_REG" data="2" /> <entry name="HIST_DEL" data="12" /> <entry name="ICMOS" data="3" /> <entry name="SLEEP" data="0" /> <entry name="SFOUT2_REG" data="0" /> Rev. 0.2 23 Si5326-VTSS-EVB <entry name="SFOUT1_REG" data="2" /> <entry name="FOSREFSEL" data="2" /> <entry name="HLOG_2" data="0" /> <entry name="HLOG_1" data="0" /> <entry name="HIST_AVG" data="18" /> <entry name="DSBL2_REG" data="1" /> <entry name="DSBL1_REG" data="0" /> <entry name="PD_CK2" data="0" /> <entry name="PD_CK1" data="0" /> <entry name="CLAT" data="0" /> <entry name="FLAT" data="0" /> <entry name="FLAT_VALID" data="1" /> <entry name="FOS_EN" data="0" /> <entry name="FOS_THR" data="1" /> <entry name="VALTIME" data="1" /> <entry name="LOCKT" data="4" /> <entry name="CK2_BAD_PIN" data="1" /> <entry name="CK1_BAD_PIN" data="1" /> <entry name="LOL_PIN" data="1" /> <entry name="INT_PIN" data="0" /> <entry name="INCDEC_PIN" data="1" /> <entry name="CK1_ACTV_PIN" data="1" /> <entry name="CKSEL_PIN" data="1" /> <entry name="CK_ACTV_POL" data="1" /> <entry name="CK_BAD_POL" data="1" /> <entry name="LOL_POL" data="1" /> <entry name="INT_POL" data="1" /> <entry name="LOS2_MSK" data="1" /> <entry name="LOS1_MSK" data="1" /> <entry name="LOSX_MSK" data="1" /> <entry name="FOS2_MSK" data="1" /> <entry name="FOS1_MSK" data="1" /> <entry name="LOL_MSK" data="1" /> <entry name="NC1_HS" data="6" /> <entry name="NC1_LS" data="3" /> <entry name="NC2_LS" data="1" /> <entry name="N2_LS" data="DBF" /> <entry name="N2_HS" data="7" /> <entry name="N31" data="3C7" /> <entry name="N32" data="374" /> <entry name="CLKIN2RATE" data="0" /> <entry name="CLKIN1RATE" data="0" /> <entry name="LOS1_EN" data="3" /> 24 Rev. 0.2 Si5326-VTSS-EVB <entry name="LOS2_EN" data="3" /> <entry name="FOS1_EN" data="1" /> <entry name="FOS2_EN" data="1" /> <entry name="INDEPENDENTSKEW1" data="0" /> <entry name="INDEPENDENTSKEW2" data="0" /> - <!-- Run the ICAL to start the internal self-calibration after the new settings are loaded. --> <entry name="ICAL" data="1" /> </settings> Rev. 0.2 25 Si5326-VTSS-EVB A PPENDIX B— A PPLICATION B OARD D ESIGN E XAMPLE The purpose of this appendix is to provide guidance to users attempting to use the Si5326-VTSS-EVB as an example for designing an application board with a Vitesse VSCxxxxEV and an Si5326. One issue that needs to be considered is startup and initialization. The Si5326-VTSS-EVB supplies the clock to the VSCxxxxEV board, and the VSCxxxxEV can then be used to program the Si5326-VTSS-EVB for different options and frequency plans. As shown in Figure 4, “Si5326-VTSS-EVB Block Diagram,” on page 5, the Si5326-VTSSEVB has an MCU that loads the Si5326 at power up so that the Si5326 can provide a clock to the VSCxxxxEV device. If the MCU were to be removed, there would be a problem because the Si5326 cannot generate a clock until it has been programmed, and the VSCxxxxEV cannot load the Si5326 until it gets a clock. This means that all designs must load the Si5324 from some other source, such as an MCU or FPGA. Once the Si5326 has been initialized, the VSCxxxxEV can be used to change the Si5326's programming. The other source that loads the Si5326 can be an MCU, a CPLD, or some other similar device. Though the Si5326VTSS-EVB uses SPI as its serial port, I2C can also be used, and the same concepts would apply. For further information on how a small and inexpensive MCU can be dedicated to this task, see “AN428: Jump-Start: InSystem, Flash-Based Programming for Silicon Labs’ Timing Products”. The Si5326-VTSS-EVB uses an Si530 as its XAXB reference source because drift during holdover may be an issue in some applications. Crystals with a total drift of 20 ppm or less are available, which may be acceptable in some applications. For a list of qualified crystals, see “AN591: Crystal Selection for the Si5315, Si5317, and other Si53xx Any-Frequency Jitter Attenuating Clocks”, which can be downloaded from www.silabs.com. Most applications will have no need to implement a USB interface. In these cases, the serial number device is not needed. The EEPROM contents contain the power-up Si5326 register map. However, most applications will choose to put this information into the flash of the EEPROM. Care must be taken so that the VSCxxxxEV is held in reset until after the output of the Si5326 is available and stable. This manual provides a description of one way that this can be implemented with a CPLD. To assist, the CPLD source code files are provided below. 26 Rev. 0.2 Si5326-VTSS-EVB `timescale 1ns / 100ps ///////////////////////////////////////////////////////////////// ///////////////// // Create Date: 16 May 08 // Design Name: // Module Name: CPLD for the Vitesse SyncE Add On Board // Description: Mar 08 initial release // Revision: Rev 1 // Revision 26 Mar 08 - initial release // 16 May 08 - added force so that subsequent LOL's do not issue reset // - added IRQ; a simple open drain buffer // Additional Comments: ///////////////////////////////////////////////////////////////// ///////////////// module MCU_CPLD ( // inputs from the MCU: mcu_mosi, Addr, mcu_ss_n, mcu_sclk, cpld_rst_n, // inputs from DUT: lol, dut_sdo, irq_in, // inputs from SyncE: v_spi_en_n, v_spi_clk, v_spi_mosi, // misc inputs: rst_from_max811_n, // outputs to MCU: mcu_miso, // outputs to DUT: dut_sdi, dut_sclk, dut_ss_n, dut_rst_n, // outputs to SyncE: late_reset_n, v_spi_miso, v_irq_out_n, // misc outputs: v_master, mcu_master, to_max811_n, flop_not ); input mcu_mosi, mcu_ss_n, mcu_sclk, cpld_rst_n, lol, dut_sdo, v_spi_en_n, irq_in, v_spi_clk, v_spi_mosi, rst_from_max811_n; input [2:0] Addr; output mcu_miso, dut_sdi, dut_sclk, dut_ss_n, dut_rst_n, late_reset_n, v_spi_miso, v_irq_out_n, v_master, mcu_master, to_max811_n, flop_not; // internal stuff: wire mcu_ss; // positive true version of mcu_ss_n assign mcu_ss = ~mcu_ss_n; wire v_spi_en; // positive true version of v_spi_en_n assign v_spi_en = ~v_spi_en_n; wire flop; LOL from the wire flop_not; // create an RS flip flop that gates away // reset logic after the power up sequenc Rev. 0.2 27 Si5326-VTSS-EVB has completed. wire cpld_rst; // create a positive true version of cpld_rst_n assign cpld_rst = ~cpld_rst_n; assign flop = ~(cpld_rst | flop_not); assign flop_not = ~(rst_from_max811_n | flop); // first do the interrupt request from the DUT to the main board: // invert the signal and make it open drain assign v_irq_out_n = (irq_in) ? 0'b0 : 1'bz; // do the reset and delayed reset functions: // pass thru the reset from the DUT. assign dut_rst_n = cpld_rst_n; // OR LOL with cpld_rst whenever cpld_rst is active // after cpld_rst is negated, gate away LOL so it can cause a reset to the MAX811 assign to_max811_n = ~(cpld_rst | (lol & flop_not)); assign late_reset_n = (rst_from_max811_n) ? 1'bz : 1'b0; open collector // mux the two SPI busses to the DUT: assign dut_ss_n = (Addr == 0) v_spi_en_n; assign dut_sdi = ((Addr == 0) && mcu_ss) v_spi_mosi; assign dut_sclk = ((Addr == 0) && mcu_ss) v_spi_clk; assign v_spi_miso = (~mcu_ss && v_spi_en) assign mcu_miso = ((Addr == 0) && mcu_ss) assign mcu_master = mcu_ss; assign v_master = v_spi_en; endmodule 28 ? mcu_ss_n : ? mcu_mosi : ? mcu_sclk : ? dut_sdo : 1'bz; ? dut_sdo : 1'bz; // to an LED // to an LED Rev. 0.2 // Si5326-VTSS-EVB #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "Addr<0>" LOC = "P36" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "Addr<1>" LOC = "P37" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "Addr<2>" LOC = "P38" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "cpld_rst_n" LOC = "P30" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "dut_rst_n" LOC = "P3" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "dut_sclk" LOC = "P19" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "dut_sdi" LOC = "P21" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "dut_sdo" LOC = "P20" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "dut_ss_n" LOC = "P23" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "flop_not" LOC = "P39" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "irq_in" LOC = "P44" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "late_reset_n" LOC = "P29" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "lol" LOC = "P22" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "mcu_master" LOC = "P6" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "mcu_miso" LOC = "P34" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "mcu_mosi" LOC = "P33" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "mcu_sclk" LOC = "P32" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "mcu_ss_n" LOC = "P31" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "rst_from_max811_n" LOC = "P28" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "to_max811_n" LOC = "P8" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_irq_out_n" LOC = "P2" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_master" LOC = "P27" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_spi_clk" LOC = "P13" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_spi_en_n" LOC = "P12" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_spi_miso" LOC = "P16" | IOSTANDARD = LVCMOS33 | KEEPER ; NET "v_spi_mosi" LOC = "P14" | IOSTANDARD = LVCMOS33 | KEEPER ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE Rev. 0.2 29 Si5326-VTSS-EVB DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Added new Vitesse EVBs. Added "Appendix B—Application Board Design Example" on page 26. Simplified "7.Installing Software for the Direct Control of the Si5326-VTSS-EVB" on page 10. Changed “any-rate” to “any-frequency” throughout. 30 Rev. 0.2 Si5326-VTSS-EVB NOTES: Rev. 0.2 31 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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