Si5340D Datasheet Addendum Device Configuration Summary for Si5340D-B-GM Page 1 of 4 4-Output Low Jitter Any-Frequency Clock Generator Overview ======== Part: Design ID: Created By: Timestamp: Si5340 5340BP2 ClockBuilder Pro v1.7 [2015-03-26] 2015-03-26 09:25:10 GMT-05:00 Device Grade ============ Device Grade --------Si5340A Si5340B Si5340C Si5340D* Output Clock Frequency Range ----------------100 Hz to 712.5 MHz 100 Hz to 350 MHz 100 Hz to 712.5 MHz 100 Hz to 350 MHz Supported Frequency Synthesis Modes (Typical Jitter) ------------------------------------------Integer (<100 fs) and fractional (< 150 fs) " Integer only (< 100 fs) " * Device Grade Design ====== Host Interface: I/O Power Supply: VDD (Core) SPI Mode: 4-Wire I2C Address Range: 116d to 119d / 0x74 to 0x77 (selected via A0/A1 pins) Inputs: XAXB: IN0: IN1: IN2: Unused Unused Unused Unused Outputs: OUT0: OUT1: OUT2: OUT3: Unused Unused Unused Unused Frequency Plan ============== No plan Settings ======== Location -----------0x000B[0:6] 0x0017[0] 0x0017[1] 0x0017[2] 0x0017[3] 0x0017[5] 0x0018[0:3] 0x0021[0] 0x0021[1:2] 0x0022[1] 0x002B[3] 0x002B[5] Setting Name ------------------I2C_ADDR SYSINCAL_INTR_MSK LOSXAXB_INTR_MSK LOSREF_INTR_MSK LOL_INTR_MSK SMB_TMOUT_INTR_MSK LOSIN_INTR_MSK IN_SEL_REGCTRL IN_SEL OE SPI_3WIRE AUTO_NDIV_UPDATE Decimal Value ------------116 0 0 0 0 0 15 0 0 0 0 0 Hex Value -------------0x74 0x0 0x0 0x0 0x0 0x0 0xF 0x0 0x0 0x0 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5340D Datasheet Addendum Device Configuration Summary for Si5340D-B-GM Page 2 of 4 0x002C[0:3] 0x002C[4] 0x002D[0:1] 0x002D[2:3] 0x002D[4:5] 0x002D[6:7] 0x002E[0:15] 0x0030[0:15] 0x0032[0:15] 0x0034[0:15] 0x0036[0:15] 0x0038[0:15] 0x003A[0:15] 0x003C[0:15] 0x0041[0:4] 0x0042[0:4] 0x0043[0:4] 0x0044[0:4] 0x009E[4:7] 0x0102[0] 0x0112[0] 0x0112[1] 0x0112[2] 0x0113[0:2] 0x0113[3] 0x0113[4:5] 0x0113[6:7] 0x0114[0:3] 0x0114[4:6] 0x0115[0:2] 0x0115[6:7] 0x0117[0] 0x0117[1] 0x0117[2] 0x0118[0:2] 0x0118[3] 0x0118[4:5] 0x0118[6:7] 0x0119[0:3] 0x0119[4:6] 0x011A[0:2] 0x011A[6:7] 0x0126[0] 0x0126[1] 0x0126[2] 0x0127[0:2] 0x0127[3] 0x0127[4:5] 0x0127[6:7] 0x0128[0:3] 0x0128[4:6] 0x0129[0:2] 0x0129[6:7] 0x012B[0] 0x012B[1] 0x012B[2] 0x012C[0:2] 0x012C[3] 0x012C[4:5] 0x012C[6:7] 0x012D[0:3] 0x012D[4:6] 0x012E[0:2] 0x012E[6:7] LOS_EN LOSXAXB_DIS LOS0_VAL_TIME LOS1_VAL_TIME LOS2_VAL_TIME LOS3_VAL_TIME LOS0_TRG_THR LOS1_TRG_THR LOS2_TRG_THR LOS3_TRG_THR LOS0_CLR_THR LOS1_CLR_THR LOS2_CLR_THR LOS3_CLR_THR LOS0_DIV_SEL LOS1_DIV_SEL LOS2_DIV_SEL LOS3_DIV_SEL LOL_SET_THR OUTALL_DISABLE_LOW OUT0_PDN OUT0_OE OUT0_RDIV_FORCE2 OUT0_FORMAT OUT0_SYNC_EN OUT0_DIS_STATE OUT0_CMOS_DRV OUT0_CM OUT0_AMPL OUT0_MUX_SEL OUT0_INV OUT1_PDN OUT1_OE OUT1_RDIV_FORCE2 OUT1_FORMAT OUT1_SYNC_EN OUT1_DIS_STATE OUT1_CMOS_DRV OUT1_CM OUT1_AMPL OUT1_MUX_SEL OUT1_INV OUT2_PDN OUT2_OE OUT2_RDIV_FORCE2 OUT2_FORMAT OUT2_SYNC_EN OUT2_DIS_STATE OUT2_CMOS_DRV OUT2_CM OUT2_AMPL OUT2_MUX_SEL OUT2_INV OUT3_PDN OUT3_OE OUT3_RDIV_FORCE2 OUT3_FORMAT OUT3_SYNC_EN OUT3_DIS_STATE OUT3_CMOS_DRV OUT3_CM OUT3_AMPL OUT3_MUX_SEL OUT3_INV 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 0x0 0x1 0x0 0x0 0x0 0x0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x00 0x00 0x00 0x0 0x1 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5340D Datasheet Addendum Device Configuration Summary for Si5340D-B-GM Page 3 of 4 0x013F[0:11] 0x0141[5] 0x0141[7] 0x0202[0:31] 0x0206[0:1] 0x0208[0:47] 0x020E[0:31] 0x0212[0:47] 0x0218[0:31] 0x021C[0:47] 0x0222[0:31] 0x0226[0:47] 0x022C[0:31] 0x0235[0:43] 0x023B[0:31] 0x0250[0:23] 0x0253[0:23] 0x025C[0:23] 0x025F[0:23] 0x026B[0:7] 0x026C[0:7] 0x026D[0:7] 0x026E[0:7] 0x026F[0:7] 0x0270[0:7] 0x0271[0:7] 0x0272[0:7] 0x0302[0:43] 0x0308[0:31] 0x030D[0:43] 0x0313[0:31] 0x0318[0:43] 0x031E[0:31] 0x0323[0:43] 0x0329[0:31] 0x0339[0:4] 0x033B[0:43] 0x0341[0:43] 0x0347[0:43] 0x034D[0:43] 0x0359[0:15] 0x035B[0:15] 0x035D[0:15] 0x035F[0:15] 0x090E[0] 0x090E[1] 0x091C[0:2] 0x0943[0] 0x0949[0:3] 0x0949[4:7] 0x0A02[0:4] 0x0A03[0:4] 0x0A04[0:4] 0x0A05[0:4] 0x0B44[0:3] 0x0B4A[0:4] OUTX_ALWAYS_ON OUT_DIS_LOL_MSK OUT_DIS_MSK_LOS_PFD XAXB_FREQ_OFFSET PXAXB P0 P0_SET P1 P1_SET P2 P2_SET P3 P3_SET M_NUM M_DEN R0_REG R1_REG R2_REG R3_REG DESIGN_ID0 DESIGN_ID1 DESIGN_ID2 DESIGN_ID3 DESIGN_ID4 DESIGN_ID5 DESIGN_ID6 DESIGN_ID7 N0_NUM N0_DEN N1_NUM N1_DEN N2_NUM N2_DEN N3_NUM N3_DEN N_FSTEP_MSK N0_FSTEPW N1_FSTEPW N2_FSTEPW N3_FSTEPW N0_DELAY N1_DELAY N2_DELAY N3_DELAY XAXB_EXTCLK_EN XAXB_PDNB ZDM_EN IO_VDD_SEL IN_EN IN_PULSED_CMOS_EN N_ADD_0P5 N_CLK_TO_OUTX_EN N_PIBYP N_PDNB PDIV_ENB N_CLK_DIS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53 51 52 48 66 80 50 0 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 4 0 8 0 0 15 0 15 0 0 0x000 0x0 0x0 0x00000000 0x0 0x000000000000 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x00000000000 0x00000000 0x000000 0x000000 0x000000 0x000000 0x35 0x33 0x34 0x30 0x42 0x50 0x32 0x00 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x1F 0x00000000000 0x00000000000 0x00000000000 0x00000000000 0x0000 0x0000 0x0000 0x0000 0x0 0x0 0x4 0x0 0x8 0x0 0x00 0x0F 0x00 0x0F 0x0 0x00 This datasheet addendum is provided as supplemental information to the Si5340D datasheet, located at www.silabs.com/timing. You can search for and download any datasheet addendum for Si534x/8x part numbers. Go to http://www.silabs.com/custom-timing for more information. Silicon Laboratories Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5340D Datasheet Addendum Device Configuration Summary for Si5340D-B-GM Page 4 of 4 400 West Cesar Chavez Austin, TX 78701 Phone (512) 416-8500 www.silabs.com Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.