A NY - F REQUENCY, A NY - O UTPUT J I T T E R - A TTENUATORS / C LOCK M ULTIPLIERS Si5345, Si5344, Si5342 F AMILY R EFERENCE M ANUAL Rev. 1.0 8/15 Copyright © 2015 by Silicon Laboratories Si5345-44-42-RM Si5345-44-42-RM TABLE O F C ONTENTS 1. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.1. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1. Work Flow Expectations with ClockBuilder Pro™ and the Register Map . . . . . . . . . . . . .9 2.2. Family Product Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3. Available Software Tools and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3. DSPLL and MultiSynth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1. Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2.1. Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.1. Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2. Dynamic PLL Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3. NVM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.4. Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.5. Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.6. Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.7. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5. Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1.1. Manual Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.2. Automatic Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. Types of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.2.1. Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2. Hitless Input Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3. Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4. Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 23 5.3. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.3.1. Input Loss of Signal (LOS) Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.2. Out of Frequency (OOF) Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.3. Loss of Lock Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 6. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.1. Output Crosspoint Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.2. Performance Guidelines for Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 6.3. Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.3.1. Differential Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2. Differential Output Swing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3. Programmable Common Mode Voltage for Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5. LVCMOS Output Impedance and Drive Strength Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.6. LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7. LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.8. Output Driver Settings for LVPECL, LVDS, HCSL, and CML . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 35 36 36 37 38 39 6.4. Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.4.1. Output Driver State When Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2 Rev. 1.0 Si5345-44-42-RM 6.4.2. Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5. Output Skew Control (t0–t4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 8. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8.1. DCO with Frequency Increment/Decrement Pins/Bits . . . . . . . . . . . . . . . . . . . . . . . . . .46 8.2. DCO with Direct Register Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 9.2. SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 10. Field Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 11. XAXB External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 11.1. Performance of External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 11.2. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 11.3. Recommended Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 11.4. Register Settings to Control External XTAL Reference . . . . . . . . . . . . . . . . . . . . . . . .64 11.4.1. XAXB_FREQ_OFFSET Frequency Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.4.2. XAXB_EXTCLK_EN Reference Clock Selection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.4.3. PXAXB Pre-scale Divide Ratio for Reference Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 65 12. Crystal and Device Circuit Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.1. 64-Pin QFN Si5345 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.1.1. Si5345 Applications without a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.2. Si5345 Crystal Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1.3. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.2. 44-Pin QFN Si5344/42 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . .71 12.2.1. Si5342/44 Applications without a Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.2.2. Si5342/44 Crystal Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 13.1. Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 13.2. Power Supply Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 13.3. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 13.4. Grounding Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 14. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 14.1. Base vs. Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 14.1.1. “Base” Devices (a.k.a. “Blank” Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.1.2. “Factory Preprogrammed” (Custom OPN) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.2. Register Map Overview and Default Settings Values . . . . . . . . . . . . . . . . . . . . . . . . . .78 14.3. Si5345 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 14.3.1. Page 0 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.3.2. Page 1 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.3.3. Page 2 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3.4. Page 3 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.3.5. Page 4 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.3.6. Page 5 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14.3.7. Page 9 Registers Si5345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.3.8. Page A Registers Si5345. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.3.9. Page B Registers Si5345. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.4. Si5344 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 14.4.1. Page 0 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.4.2. Page 1 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.4.3. Page 2 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Rev. 1.0 3 Si5345-44-42-RM 14.4.4. Page 3 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.5. Page 4 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.6. Page 5 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.7. Page 9 Registers Si5344 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.8. Page A Registers Si5344. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.9. Page B Registers Si5344. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 139 140 145 146 147 14.5. Si5342 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 14.5.1. Page 0 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2. Page 1 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3. Page 2 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4. Page 3 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5. Page 4 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.6. Page 5 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.7. Page 9 Registers Si5342 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.8. Page A Registers Si5342. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.9. Page B Registers Si5342. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 162 165 168 171 172 177 178 179 Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 4 Rev. 1.0 Si5345-44-42-RM L I S T OF F IGURES Figure 1. Block Diagram Si5345/44/42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Si5345/44/42 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Initialization from Hard Reset and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Programmable Holdover Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Input Termination for Standard and Pulsed CMOS Inputs. . . . . . . . . . . . . . . . . . . . Figure 8. Generating an Averaged Non Gapped Output Frequency from a Gapped Input. . . Figure 9. Si5342/44/45 Fault Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10. LOS Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11. OOF Status Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. Example of Precise OOF Monitor Assertion and De-assertion Triggers . . . . . . . . Figure 13. LOL Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14. LOL Set and Clear Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15. Interrupt Pin Status Flag Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16. MultiSynth to Output Driver Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17. Supported Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18. Vpp_se and Vpp_diff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20. Example of Independently-Configurable Path Delays . . . . . . . . . . . . . . . . . . . . . . Figure 21. Si5345 Zero Delay Mode Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22. DCO with FINC/FDEC Pins or Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23. I2C/SPI Device Connectivity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24. I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25. 7-bit I2C Slave Address Bit-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26. I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27. I2C Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28. SPI Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29. Example Writing Three Data Bytes Using the Write Commands . . . . . . . . . . . . . . Figure 30. Example of Reading Three Data Bytes Using the Read Commands. . . . . . . . . . . Figure 31. SPI “Set Address” Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 32. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing . . . . . . Figure 33. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing . . . . . Figure 34. SPI “Burst Data Write” Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 35. Crystal Resonator and External Reference Clock Connection Options . . . . . . . . . Figure 36. Clipped Sine Wave TCXO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37. CMOS TCXO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38. Maximum ESR vs. C0 for 25 MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 39. Maximum ESR vs. C0 for 48–54 MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1) . . . . . . . . . Figure 41. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) . . . . . . . . . . . . . Figure 42. Crystal Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43. Power Plane (Layer 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.0 10 11 14 14 15 17 21 23 23 24 25 26 27 27 29 30 34 34 36 42 44 47 49 51 51 52 52 53 54 55 55 56 57 57 59 60 60 63 63 67 67 68 68 5 Si5345-44-42-RM Figure 44. Layer 5 Power Routing on Power Plane (Layer 5). . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 45. Ground Plane (Layer 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 46. Output Clock Layer (Layer 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 47. Bottom Layer Ground Flooded (Layer 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 48. Device Layer (Layer 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 49. Crystal Shield Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 50. Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 51. Power Plane and Clock Output Power Supply Traces (Layer 4) . . . . . . . . . . . . . . 73 Figure 52. Clock Input Traces (Layer 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 53. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) . . . . . . . . . 74 Figure 54. FINC, FDEC Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 55. Logic Diagram of the FINC/FDEC Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 56. Logic Diagram of the FINC/FDEC Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 57. FINC, FDEC Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6 Rev. 1.0 Si5345-44-42-RM L I S T OF TABLES Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. PLL_BW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Fastlock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Reset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. NVM Programming Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Holdover Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Input Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8. Manual Input Selection using IN_SEL[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Registers for Automatic Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Register 0x0949 Clock Input Control and Configuration . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Hitless Switching Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12. Loss of Signal Status Monitoring and Control Registers . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Out-of-Frequency Status Monitoring and Control Registers . . . . . . . . . . . . . . . . . . 26 Table 14. Loss of Lock Status Monitor and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 15. Output Driver Crosspoint Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 16. Example of Output Clock Frequency Sequencing Choice . . . . . . . . . . . . . . . . . . . 32 Table 17. Output Signal Format Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 18. Differential Output Voltage Swing Control Registers. . . . . . . . . . . . . . . . . . . . . . . . 35 Table 19. Differential Output Common Mode Voltage Control Registers . . . . . . . . . . . . . . . . 35 Table 20. Output Impedance and Drive Strength Selections . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21. LVCMOS Drive Strength Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 22. LVCMOS Output Polarity Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 23. Output Polarity of OUTx and OUTx Pins in LVCMOS Mode. . . . . . . . . . . . . . . . . . 38 Table 24. Settings for LVDS, LVPECL, and HCSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 25. Output Enable/Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 26. Output Driver State Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 27. Synchronous Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 28. Output Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 29. Zero Delay Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 30. Frequency Increment/Decrement Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 31. I2C/SPI Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. SMBus Timeout Error Bit Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 33. SPI Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 34. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 35. Recommended Oscillator Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 36. XAXB Frequency Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 37. XAXB External Clock Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 38. Pre-Scale Divide Ratio Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 39. Pre-Scale Divide Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 40. Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 41. Register Map Paging Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 42. Registers that Follow the Same Definitions Above . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 43. Registers that Follow the P0_NUM and P0_DEN Above . . . . . . . . . . . . . . . . . . . . 98 Rev. 1.0 7 Si5345-44-42-RM Table 44. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 45. Registers that Follow the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 102 Table 46. Registers that Follow the N0_FSTEPW Definitions . . . . . . . . . . . . . . . . . . . . . . . 103 Table 47. Registers that Follow the Same Definitions Above . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 48. Registers that Follow the P0_NUM and P0_DEN . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 49. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 50. Registers that Follow the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 136 Table 51. Registers that Follow the N0_FSTEPW Definition . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 52. Registers that Follow the Same Definition as Above . . . . . . . . . . . . . . . . . . . . . . 164 Table 53. Registers that Follow the P0_NUM and P0_DEN Definitions . . . . . . . . . . . . . . . . 166 Table 54. Registers that Follow the R0_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 55. Register that Follows the N0_NUM and N0_DEN Definitions . . . . . . . . . . . . . . . . 168 Table 56. Registers that Follow the N0_FSTEPW Definition . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 57. Registers that Follow the N0_DELAY Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 58. Output Differential Common Mode Voltage Settings. . . . . . . . . . . . . . . . . . . . . . . 180 Table 59. Typical Differential Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8 Rev. 1.0 Si5345-44-42-RM 1. Scope This Family Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the Si5345/44/42 devices in end applications. The official device specifications can be found in the Si5345/44/42 data sheets. 1.1. Related Documents Si5345/44/42 Data Sheet Si5345/44/42 Device Errata Si5345/44/42-EVB User Guide 2. Overview The Si5345/44/42 jitter attenuating clock multipliers combine 4th generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation for applications that require the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) ensuring power up with a known frequency configuration. Free-run, synchronous, and holdover modes of operation are supported offering both automatic and manual input clock switching. The loop filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable providing jitter performance optimization at the application level. These devices are capable of generating any combination of output frequency from any input frequency within the specified input and output range. 2.1. Work Flow Expectations with ClockBuilder Pro™ and the Register Map This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes. The primary purpose of the software is that it saves having to understand all the complexities of the device. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document. 2.2. Family Product Comparison Table 1 lists a comparison of the different family members. Table 1. Product Selection Guide Part Number Number of Inputs Number of MultiSynths Number of Outputs Si5342 4 2 2 44-QFN Si5344 4 4 4 44-QFN Si5345 4 5 10 64-QFN Rev. 1.0 Package Type 9 Si5345-44-42-RM 48-54MHz XTAL or REFCLK VDDA VDD Si5345/44/42 3 XA XB OSC IN_SEL[1:0] ÷ PXAXB IN0 IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷ P0n P0d ÷ P1n P1d DSPLL ÷ P2n P2d PD ÷ P3n P3d LPF ÷ Optional External Feedback Multi N ÷ 1n Synth N1d t1 Multi N ÷ 2n Synth N2d t2 Multi N ÷ 3n Synth N3d t3 Multi N ÷ 4n Synth N4d t4 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C NVM A0/CS OE FINC RST LOL Status Monitors FDEC INTR Si5345 ÷R0 Si5344 t0 Si5342 Multi N ÷ 0n Synth N0d Mn Md Figure 1. Block Diagram Si5345/44/42 2.3. Available Software Tools and Support ClockBuilder Pro is a software tool that is used for the Si5345/44/42 family and other product families, capable of configuring the timing chip in an intuitive, easy-to-use, step-by-step process. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to a device or written to the EVB and a custom part number can be created. This is all done with one software tool. ClockBuilder Pro integrates all the data sheets, application notes and information that might be helpful in one environment. It is intended that customers will use the software tool for the proper configuration of the device. Register map descriptions given in the document should not be the only source of information for programming the device. The complexity of the algorithms is embedded in the software tool. 10 Rev. 1.0 Si5345-44-42-RM 3. DSPLL and MultiSynth The DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth generated frequencies to any of the outputs. A single MultiSynth output can connect to two or more output drivers. Additional integer division (R) determines the final output frequency as shown in Figure 2. 48-54MHz XTAL or REFCLK XA XB OSC IN_SEL[1:0] ÷PXAXB IN0 IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN P ÷ 0n P0d ÷ P1n P1d DSPLL ÷ P2n P2d PD ÷ P3n P3d LPF ÷ Optional External Feedback Multi N ÷ 0n Synth N0d t0 Multi N ÷ 1n Synth N1d t1 Mn Md ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-volatile memory or RAM. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software. Rev. 1.0 11 Si5345-44-42-RM 3.1. Dividers There are five divider classes within the Si5345/4/2. See Figure 1 for a block diagram that shows all of these dividers. Wide range input dividers P3, P2, P1, P0 MultiSynth divider bit numerator, 32 bit denominator Min value is 1 Practical range limited by phase detector and VCO range Each divider has an update bit that must be written to cause a newly written divider value to take effect. 48 Narrow Only range input divider Pxaxb divides by 1, 2, 4, 8 Feedback M divider MultiSynth divider or fractional divide values 56 bit numerator, 32-bit denominator Practical range limited by phase detector and VCO range Each divider has an update bit that must be written to cause a newly written divider value to take effect. Integer Output N divider MultiSynth divider or fractional divide values 44 bit numerator, 32 bit denominator Each divider has an update bit that must be written to cause a newly written divider value to take effect. Integer Output R divider Only Min even integer divide values value is 2 Maximum value is 225 – 2 3.2. DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. The DSPLL loop bandwidth is set in registers 0x0508-0x050D and are determined using ClockBuilder Pro. Table 2. PLL_BW Registers Register Name BW_PLL 12 Hex Address [Bit Field] Function Si5345 Si5344 Si5342 0x0508[7:0]0x050D[7:0] 0x0508[7:0]0x050D[7:0] 0x0508[7:0]0x050D[7:0] Rev. 1.0 Determines the loop BW for the DSPLL. Si5345-44-42-RM 3.2.1. Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLL to lock faster. Fastlock Loop Bandwidth settings in the range from 100 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once lock acquisition has completed. Table 3. Fastlock Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 FASTLOCK_AUTO_EN 0x052B[0] 0x052B[0] 0x052B[0] Auto Fastlock Enable/ Disable FASTLOCK_MAN 0x052B[1] 0x052B[1] 0x052B[1] 0 for normal operation, 1 to force fast lock FAST_BW_PLL 0x050E[7:0]0x0513[7:0] 0x050E[7:0]0x0513[7:0] 0x050E[7:0]0x0513[7:0] Fastlock BW selection. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in "5.3.3. Loss of Lock Fault Monitoring" on page 27. Rev. 1.0 13 Si5345-44-42-RM 4. Modes of Operation After initialization the DSPLL will operate in one of the following modes: Free-run, lock-acquisition, locked, or holdover. Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected An input is qualified and available for selection Lock Acquisition (Fast Lock) Phase lock on selected input clock is achieved Holdover Mode No s Ye Is holdover history valid? Selected input clock fails Locked Mode Figure 3. Modes of Operation 4.1. Reset and Initialization Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the SPI or I2C serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available: hard reset and soft reset. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. Table 4 lists the reset and control registers. NVM 2x OTP RAM Figure 4. Si5345/44/42 Memory Configuration 14 Rev. 1.0 Si5345-44-42-RM Table 4. Reset Registers Register Name Hex Address [Bit Field] Si5345 Si5344 Function Si5342 HARD_RST 0x001E[1] 0x001E[1] 0x001E[1] Performs the same function as power cycling the device. All registers will be restored to their default values. SOFT_RST 0x001C[0] 0x001C[0] 0x001C[0] Performs a soft reset. Initiates register configuration changes. Power-Up Hard Reset bit asserted RST pin asserted NVM download Soft Reset bit asserted Initialization Serial interface ready Figure 5. Initialization from Hard Reset and Soft Reset The Si5345/44/42 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8V) and VDDA (3.3 V) pins. Rev. 1.0 15 Si5345-44-42-RM 4.2. Dynamic PLL Changes It is possible for a PLL to become unresponsive (i.e., lose lock indefinitely) when it is dynamically reprogrammed or changed via the serial port. Reprogramming/changing the N divider does not affect the PLL. Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following special sequence of writes. Changes to the following registers can cause the VCO frequency change by more than 250 ppm. XAXB_FREQ_OFFSET PXAXB MXAXB_NUM MXAXB_DEN 1. |First, the preamble Write 0x0B24 = 0xD8 Write 0x0B25 = 0x00 2. Wait 300 ms. 3. Then perform the desired register modifications 4. Write SOFT_RST - x001C[0] = 1 5. Write the post-amble Write 0x0B24 = 0xDB Write 0x0B25 = 0x02 4.3. NVM Programming The NVM is two time writable. Because it can only be written two times, it is important to configure the registers correctly before beginning the NVM programming process. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Note: In-circuit programming is only supported over a temperature range of 0° to 80°C. The procedure for writing registers into NVM is as follows: 1. Write all registers as needed. 2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the content of NVM bank. 3. Write 0xC7 to NVM_WRITE register. 4. Wait until DEVICE_READY = 0x0F 5. Set NVM_READ_BANK 0x00E4[0] = “1”. 6. Wait until DEVICE_READY = 0x0F. 7. Steps 5 and 6 can be replaced by simply powering down and then powering up the device. Table 5. NVM Programming Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 ACTIVE_NVM_BANK 0x00E3[7:0] 0x00E3[7:0] 0x00E3[7:0] Indicates number of user bank writes carried out so far.A NVM_WRITE 0x00E3[7:0] 0x00E3[7:0] 0x00E3[7:0] Initiates an NVM write when written with 0xC7 NVM_READ_BANK 0x00E4[0] 0x00E4[0] 0x00E4[0] DEVICE_READY 0x00FE[7:0] 0x00FE[7:0] 0x00FE[7:0] 16 Rev. 1.0 Download register values with content stored in NVM Indicates that the device serial interface is ready to accept commands. Si5345-44-42-RM 4.4. Free Run Mode The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a low-jitter XAXB source will be needed for low-jitter clock outputs. 4.5. Acquisition Mode The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 4.6. Locked Mode Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point any XTAL frequency drift will typically not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved. See “5.3.3. Loss of Lock Fault Monitoring” for more details on the operation of the loss of lock circuit. 4.7. Holdover Mode The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in Figure 6. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120s Programmable historical data window used to determine the final holdover value Programmable delay 30ms, 60ms, 1s,10s, 30s, 60s 0s 1s,10s, 30s, 60s Figure 6. Programmable Holdover Window When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled by the DSPLL bandwidth, the Fastlock bandwidth, or an artificial linear ramp rate selectable from 0.75 ppm/s up to 40 ppm/s. These options are register programmable. Rev. 1.0 17 Si5345-44-42-RM Table 6. Holdover Mode Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 HOLD 0x000E[5] 0x000E[5] 0x000E[5] Holdover status indicator. Indicates when the DSPLL is in holdover or free-run mode and not synchronized to an input clock on IN3, IN2, IN1, or IN0. The DSPLL is in holdover state only when the historical frequency data is valid; otherwise, the DSPLL should be considered to be in free-run mode. HOLD_FLG 0x0013[5] 0x0013[5] 0x0013[5] Holdover status monitor sticky bit. Sticky bits will remain asserted when an holdover event occurs until cleared. Writing a zero to a sticky bit will clear it. HOLD_HIST_VALID 0x053F[1] 0x053F[1] 0x053F[1] Holdover historical frequency data valid. Indicates if there is enough historical frequency data collected for valid holdover. Holdover Status Holdover Control and Settings HOLD_HIST_LEN HOLD_HIST_DELAY 0x052E[4:0] 0x052E[4:0] 0x052E[4:0] Holdover historical average window. Selectable as 1 s, 10 s, 30 s, 60 s. Register values determined using ClockBuilder Pro 0x052F[4:0] 0x052F[4:0] 0x052F[4:0] Holdover average delay window. Selectable as 30 ms, 60 ms, 1 s, 30 s, 60 s. Register values determined using ClockBuilder Pro FORCE_HOLD 0x0535[0] 0x0535[0] 0x0535[0] These bits allow forcing the DSPLL into holdover HOLD_EXIT_BW_SEL 0x052C[4] 0x052C[4] 0x052C[4] Selects the exit from holdover bandwidth. Options are: 0- exit out of holdover using the fastlock bandwidth 1- exit out of holdover using the DSPLL loop bandwidth HOLD_RAMP_BYP 0x052C[3] 0x052C[3] 0x052C[3] Must be set to 1 for normal operation. 18 Rev. 1.0 Si5345-44-42-RM 5. Clock Inputs The Si5342/44/45 support 4 inputs that can be used to synchronize to the internal DSPLL. 5.1. Inputs (IN0, IN1, IN2, IN3) The inputs accept both standard format inputs and low-duty-cycle pulsed CMOS clocks. Input selection from CLK_SWITCH_MODE can be manual (pin or register controlled) or automatic with user definable priorities. Register 0x052A is used to select pin or register control, and to configure the input as shown below in Table 7. Table 7. Input Selection Configuration Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 CLK_SWITCH_MODE 0x0536[1:0] 0x0536[1:0] 0x0536[1:0] Selects manual or automatic switching modes. Automatic mode can be revertive or non-revertive. Selections are the following: 00 Manual,01 Automatic non-revertive 02 Automatic revertive, 03 Reserved IN_SEL_REGCTRL 0x052A [0] 0x052A [0] 0x052A [0] 0 for pin controlled clock selection 1 for register controlled clock selection IN_SEL 0x052A [2:1] 0x052A [2:1] 0x052A [2:1] 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) 5.1.1. Manual Input Switching In manual mode, CLK_SWITCH_MODE=0x00. Input switching can be done manually using the IN_SEL[1:0] device pins from the package or through register 0x052A IN_SEL[2:1]. Bit 0 of register 0x052A determines if the input selection is pin selectable or register selectable. The default is pin selectable. The following table describes the input selection on the pins. Note that when Zero Delay Mode is enabled, the FB_IN pins will become the feedback input and IN3 therefore is not available as a clock input. Also, in Zero Delay Mode, ZDM_EN must be set and register based input clock selection must be done with ZDM_IN_SEL. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. Table 8. Manual Input Selection using IN_SEL[1:0] Pins IN_SEL[1:0] DEVICE PINS Zero Delay Mode Disabled Zero Delay Mode Enabled 00 IN0 IN0 01 IN1 IN1 10 IN2 IN2 11 IN3 Reserved Rev. 1.0 19 Si5345-44-42-RM 5.1.2. Automatic Input Selection In automatic mode CLK_SWITCH_MODE = 0x01 (non-revertive) or 0x02 (revertive) An automatic input selection is available in addition to the above mentioned manual switching option described in “5.1.1. Manual Input Switching”. In automatic mode, the selection criteria is based on input clock qualification, input priority and the revertive option. The IN_SEL[1:0] pins or IN_SEL[2:1] register bits are not used in automatic input selection. Also, only input clocks that are valid (i.e., with no active alarms) can be selected by the automatic clock selection. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated. Note that automatic input selection is not available when in zero delay mode. Table 9. Registers for Automatic Input Selection Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 CLK_SWITCH_MODE 0x0536[1:0] 0x0536[1:0] 0x0536[1:0] ZDM_EN 0x0487[0] 0x0487[0] 0x0487[0] ZDM_IN_SEL 0x0487[2:1] 0x0487[2:1] 0x0487[2:1] IN0_PRIORITY 0x0538[2:0] 0x0538[2:0] 0x0538[2:0] IN1_PRIORITY 0x0538[6:4] 0x0538[6:4] IN2_PRIORITY 0x0539[2:0] 0x0539[2:0] IN0, IN1, IN2, IN3 priority select for the auto0x0538[6:4] matic selection state machine. Priority selections are 1,2,3,4, or zero for never selected. 0x0539[2:0] IN3_PRIORITY 0x0539[6:4] 0x0539[6:4] 0x0539[6:4] IN_LOS_MSK 0x0537[3:0] 0x0537[3:0] 0x0537[3:0] Determines the LOS status for IN3,2,1,0 and is used in determining a valid clock for automatic input selection 0 to use LOS in clock selection logic, 1 to mask LOS from the clock selection logic IN_OOF_MSK 0x0537[7:4] 0x0537[7:4] 0x0537[7:4] Determines the OOF status for IN3,2,1,0 and is used in determining a valid clock for the automatic input selection 0 to use OOF in the clock selection logic, 1 to mask the OOF from the clock selection logic Selects manual or automatic switching modes. Automatic mode can be revertive or non-revertive. Selections are the following: 00 Manual,01 Automatic non-revertive 02 Automatic revertive, 03 Reserved 0 disable zero delay mode 1 enable zero delay mode Selects the input when in manual register controlled mode when zero delay mode is enabled. Selections are IN0,IN1,IN2. A register value of 3 is not allowed. When in zero delay mode (ZDM_EN (0x0487[0]) the phase difference between the output, which is connected to the selected input, will be nulled to zero. When in zero delay mode, the DSPLL cannot have either hitless or automatic switching. Pin controlled clock selection is available in ZD mode (register 0x052A). 20 Rev. 1.0 Si5345-44-42-RM Note that when ZDM_EN (0x0487[0]) and IN_SEL_REGCTRL (0x052A[0]) are both high, IN_SEL (0x052A[2:1]) does not do anything and the clock selection is register controlled. When IN_SEL_REGCTRL is low, IN_SEL register does not do anything and the clock selection is pin controlled. 5.2. Types of Inputs Each of the four different inputs IN0-IN3 can be configured as standard LVDS, LVPECL, HCL, CML, and singleended LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be AC-coupled and use the “Standard” Input Buffer selection as these pins are internally dcbiased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals, having a duty cycle much less than 50%. These pulsed CMOS signals are DCcoupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown in Figure 7. The resistor divider values given below will work with up to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance. Standard AC Coupled Differential LVDS 50 100 Si5347/46 Standard INx 50 3.3V, 2.5V LVDS or CML INx Pulsed CMOS Standard AC Coupled Differential LVPECL 50 INx Si5347/46 Standard 100 INx 50 3.3V, 2.5V LVPECL Pulsed CMOS Standard AC Coupled Single Ended 50 INx 3.3V, 2.5V, 1.8V LVCMOS Si5347/46 Standard INx Pulsed CMOS Pulsed CMOS DC Coupled Single Ended R1 Si5347/46 50 INx 3.3V, 2.5V, 1.8V LVCMOS VDD 1.8V 2.5V 3.3V R2 R1 () 549 680 750 R2 () 442 324 243 Standard INx Pulsed CMOS Figure 7. Input Termination for Standard and Pulsed CMOS Inputs Rev. 1.0 21 Si5345-44-42-RM Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as shown in Figure 6 above, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to connect the inverting INx input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0. Table 10. Register 0x0949 Clock Input Control and Configuration Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 IN_EN 0x0949[3:0] 0x0949[3:0] 0x0949[3:0] Enables for the four inputs clocks, IN0 through IN3. 1 to enable. IN_PULSED_CMOS_EN 0x0949[7:4] 0x0949[7:4] 0x0949[7:4] Selects CMOS or differential receiver for IN3, IN2, IN1, IN0. Defaults to differential input. Differential=0, CMOS=1 5.2.1. Unused Inputs Unused inputs can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the unused input bits will disable them. 5.2.2. Hitless Input Switching Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, which means that they have to be exactly the same frequency. When hitless switching is enabled (register 0x0536 bit 2 = 1), the DSPLL absorbs the phase difference between the current input clock and the new input clock. When disabled (register 0x0536 bit 2 = 0), the phase difference between the two inputs will propagate to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz. Note that hitless switching is not available in zero delay mode. Table 11. Hitless Switching Enable Bit Register Name HSW_EN Hex Address [Bit Field] Si5345 Si5344 0x0536[2] 0x0536[2] Function Si5342 0x0536[2] Hitless switching is enabled = 1, or disabled = 0. For the Si5345/44/42 to meet the hitless switching specification, there are restrictions on the clock input frequencies and the use of fractional P input dividers. When an input P divider is fractional, the associated input frequency must be 300 MHz or higher to meet the hitless switching specifications. 5.2.3. Glitchless Input Switching The DSPLL has the ability to switch between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency at a rate determined by the DSPLL loop bandwidth. The DSPLL loop bandwidth is set using registers 0x0508–0x050D. Note that if “Fastlock” is enabled then the DSPLL will pull-in to the new frequency using the Fastlock Loop Bandwidth. Depending on the LOL configuration settings, the loss of lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency. There will never be output runt pulses generated at the output during the transition. 22 Rev. 1.0 Si5345-44-42-RM 5.2.4. Synchronizing to Gapped Input Clocks The DSPLL supports locking to an input clock that has missing clock periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, truly periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8. When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification of up to 1.5 ns for a maximum phase transient, when the switch occurs during a gap in either input clocks. Figure 8 shows a 100 MHz clock with one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 2 3 4 5 6 7 8 9 1 10 Period Removed 10 ns 2 3 4 5 6 7 8 9 11.11111... ns Figure 8. Generating an Averaged Non Gapped Output Frequency from a Gapped Input 5.3. Fault Monitoring The four clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF). Note that the reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss of Lock (LOL) indicator asserted when the DSPLL loses synchronization within the feedback loop. Figure 9 shows the fault monitors for each input path going into the DSPLL, which includes the crystal input as well as IN0-3. XA XB Si5345/44/42 OSC IN0 IN0 IN1 IN1 IN2 IN2 IN3/FB_IN IN3/FB_IN ÷P0 LOS OOF Precision Fast ÷P1 LOS OOF Precision Fast ÷P2 LOS OOF Precision Fast ÷P3 LOS OOF Precision Fast LOS DSPLL LOL PD LPF ÷M Figure 9. Si5342/44/45 Fault Monitors Rev. 1.0 23 Si5345-44-42-RM 5.3.1. Input Loss of Signal (LOS) Fault Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register when set, always stays asserted until cleared. Monitor Sticky LOS LOS LOS en Live Figure 10. LOS Status Indicators A LOS monitor is also available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when LOSXAXB is detected. This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. Table 12 lists the loss of signal status indicators and fault monitoring control registers. Table 12. Loss of Signal Status Monitoring and Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 LOS 0x000D[3:0] 0x000D[3:0] SYSINCAL 0x000C[0] 0x000C[0] 0x000C[0] Asserted when in calibration LOSXAXB 0x000C[1] 0x000C[1] 0x000C[1] LOS status monitor for the STAL or REFCLK at the XA/XB pins LOS_FLG 0x0012[3:0] 0x0012[3:0] SYSINCAL_FLG 0x0011[0] 0x0011[0] 0x0011[0] SYSINCAL sticky bit. Sticky bits will remain asserted until written with a zero to clear. LOSXAXB_FLG 0x0011[1] 0x0011[1] 0x0011[1] LOS status monitor sticky bits for XAXB. Sticky bits will remain asserted when a LOS event occurs until cleared. Writing zero to the bit will clear it. LOS_EN 0x002C[3:0] 0x002C[3:0] 24 Si5342 0x000D[3:0] LOS status monitor for IN3 (bit3), IN2 (bit2), IN1(bit1), IN0 (bit0) indicates if a valid clock is detected. A set bit indicates the input is LOS. 0x0012[3:0] LOS status monitor sticky bits for IN3, IN2, IN1, IN0. Sticky bits will remain asserted when a LOS event occurs until manually cleared. Writing zero to the bit will clear it. 0x002C[3:0] LOS monitor enable for IN3, IN2, IN1, IN0. Allows disabling the monitor if unused. Rev. 1.0 Si5345-44-42-RM Table 12. Loss of Signal Status Monitoring and Control Registers (Continued) Register Name Hex Address [Bit Field] Si5345 LOS_TRIG_THR LOS_CLR_THR Si5344 Function Si5342 0x002E[7:0]- 0x002E[7:0]- 0x002E[7:0]- Sets the LOS trigger threshold and clear sensitiv0x0035[7:0] 0x0035[7:0] 0x0035[7:0] ity for IN3, IN2, IN1, IN0. These 16- bit values are determined by ClockBuilder Pro 0x0036[7:0]- 0x0036[7:0]- 0x0036[7:0]0x003D[7:0] 0x003D[7:0] 0x003D[7:0] LOS_VAL_TIME 0x002D[7:0] 0x002D[7:0] 0x002D[7:0] LOS clear validation time for IN3, IN2, IN1, IN0. This sets the time that an input must have a valid clock before the LOS condition is cleared. Settings of 2ms, 100ms, 200ms, and 1 s are available. LOS_INTR_MSK 0x0018[3:0] 0x0018[3:0] 0x0018[3:0] This is the LOS interrupt mask, which can be cleared to trigger an interrupt on the INTR pin if an LOS occurs for IN0-3. 5.3.2. Out of Frequency (OOF) Fault Detection Each input clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its 0 ppm reference. This OOF reference can be selected as either: XA/XB pins Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in Figure 9. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared. Monitor Sticky en Precision LOS OOF OOF Fast Live en Figure 11. OOF Status Indicator The precision OOF monitor circuit measures the frequency of all input clocks to within up to ±2 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency range of from ±2 ppm to ±500 ppm in steps of 2 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in Figure 12. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register configurable. Rev. 1.0 25 Si5345-44-42-RM OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) 0 ppm OOF Reference +4 ppm (Clear) +6 ppm (Set) Figure 12. Example of Precise OOF Monitor Assertion and De-assertion Triggers Table 13 lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. Table 13. Out-of-Frequency Status Monitoring and Control Registers Register Name 26 Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OOF 0x000D[7:4] 0x000D[7:4] 0x000D[7:4] OOF status monitor for IN3, IN2, IN1, IN0. Indicates if a valid clock is detected or if a OOF condition is detected. OOF_FLG 0x0012[7:4] 0x0012[7:4] 0x0012[7:4] OOF status monitor sticky bits for IN3, IN2, IN1, IN0. Stick bits will remain asserted when an OOF event occurs until cleared. Writing zero to the bit will clear it. OOF_REF_SEL 0x0040[2:0] 0x0040[2:0] 0x0040[2:0] This selects the clock that the OOF monitors use as the 0 ppm reference. Selections are XA/XB, IN0, IN1, IN2, IN3. Default is XAXB. OOF_EN 0x003F[3:0] 0x003F[3:0] 0x003F[3:0] This allows to enable/disable the precision OOF monitor for IN3, IN2, IN1, IN0 FAST_OOF_EN 0x003F[7:4] 0x003F[7:4] 0x003F[7:4] This allows to enable/disable the fast OOF monitor for IN3, IN2, IN1, IN0 OOF_SET_THR 0x0046[7:0]0x0049[7:0] 0x0046[7:0]0x0049[7:0] 0x0046[7:0]0x0049[7:0] Determines the OOF alarm set threshold for IN3, IN2, IN1, IN0. Range is from ±2 ppm to ±500 ppm in steps of 2 ppm OOF_CLR_THR 0x004A[7:0]0x004D[7:0] 0x004A[7:0]0x004D[7:0] 0x004A[7:0]0x004D[7:0] Determines the OOF alarm clear threshold for Inx. Range is from ±2 ppm to ±500 ppm in steps of 2 ppm Rev. 1.0 Si5345-44-42-RM Table 13. Out-of-Frequency Status Monitoring and Control Registers (Continued) FAST_OOF_SET_THR 0x0051[7:0]0x0054[7:0] 0x0051[7:0]0x0054[7:0] 0x0051[7:0]0x0054[7:0] Determines the fast OOF alarm set threshold for IN3, IN2, IN1, IN0. FAST_OOF_CLR_THR 0x0055[7:0]0x0058[7:0] 0x0055[7:0]0x0058[7:0] 0x0055[7:0]0x0058[7:0] Determines the fast OOF alarm clear threshold for IN3, IN2, IN1, IN0. 5.3.3. Loss of Lock Fault Monitoring The Loss of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. A block diagram of the LOL monitor is shown in Figure 13. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor. LOL Monitor Sticky LOL Clear Timer LOS LOL LOL Set Live LOL DSPLL fIN PD LPF Feedback Clock ÷M Si5345/44/42 Figure 13. LOL Status Indicators The LOL frequency monitors has an adjustable sensitivity which is register configurable from 0.2 ppm to 20000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there's more than 2 ppm frequency difference is shown in Figure 14. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.2 2 20,000 Phase Detector Frequency Difference (ppm) Figure 14. LOL Set and Clear Thresholds Rev. 1.0 27 Si5345-44-42-RM Table 14. Loss of Lock Status Monitor and Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 LOL 0x000E[1] 0x000E[1] 0x000E[1] Status bit that indicates if the DSPLL is locked to an input clock LOL_FLG 0x0013[1] 0x0013[1] 0x0013[1] Sticky bits for LOL register. Writing 0 to a sticky bit will clear it. LOL_SET_THR 0x009E[7:4] 0x009E[7:4] 0x009E[7:4] Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,20000. Values are in ppm. Default is 0.2ppm. LOL_CLR_THR 0x00A0[7:4] 0x00A0[7:4] 0x00A0[7:4] Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,20000. Values are in ppm. Default is 2 ppm. LOL_CLR_DELAY 0x00A8[7:0]0x00AB[7:0] 0x00A8[7:0]0x00AB[7:0] 0x00A8[7:0]- This is a 35-bit register that configures the 0x00AB[7:0] delay value for LOL Clear delay. Selectable from 0 ns to over 500 seconds. LOL_TIMER_EN 0x00A2[1] 0x00A2[1] 0x00A2[1] Allows bypassing the LOL clear timer. 0-bypassed, 1-enabled. The settings in Table 14 are handled by ClockBuilder Pro. Manual settings should be avoided. 28 Rev. 1.0 Si5345-44-42-RM 5.4. Interrupt Configuration There is an interrupt pin available on the device which is used to indicate a change in state of one or several of the status indicators. Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status register that caused the interrupt. If an interrupt occurs the various status registers from the unmasked flags must be checked and then cleared. Register Bit Locations mask 0x0012[0] IN0_LOS_FLG 0x0012[4] IN0_OOF_FLG mask IN0 mask 0x0012[1] IN1_LOS_FLG 0x0012[5] IN1_OOF_FLG 0x0012[2] IN2_LOS_FLG 0x0012[6] IN2_OOF_FLG mask IN1 mask mask IN2 INTR mask 0x0012[3] IN3_LOS_FLG 0x0012[7] IN3_OOF_FLG 0x0013[1] LOL_FLG 0x0013[5] HOLD_FLG 0x0011[1] XAXB_LOS_FLG mask IN3 mask mask mask Figure 15. Interrupt Pin Status Flag Options The _FLG bits are “sticky” versions of the alarm bits and will stay high until cleared. An _FLG bit can be cleared by writing a zero to the _FLG bit. When an _FLG bit is high and its corresponding alarm bit is low, the _FLG bit can be cleared. During run time, the source of an interrupt can be determined by reading the _FLG register values and logically ANDing them with the corresponding _MSK register bits (after inverting the _MSK bit values). If the result is a logic one, then the _FLG bit will cause an interrupt. For example, if LOS_FLG[0] is high and LOS_INTR_MSK[0] is low, then the INTR pin will be active (low) and cause an interrupt. If LOS[0] is zero and LOS_MSK[0] is one, writing a zero to LOS_MSK[0] will clear the interrupt (assuming that there are no other interrupt sources). If LOS[0] is high, then LOS_FLG[0] and the interrupt cannot be cleared. Rev. 1.0 29 Si5345-44-42-RM 6. Output Clocks Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3, 2.5, or 1.8 V) providing up to 20 single-ended outputs or any combination of differential and single-ended outputs. 6.1. Output Crosspoint Switch A crosspoint switch allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 16. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up. Any MultiSynth output can connect to multiple output drivers. Multi N ÷ 0n Synth N0d t0 Multi N ÷ 1n Synth N1d t1 Multi N ÷ 2n Synth N2d t2 Multi N ÷ 3n Synth N3d t3 Multi N ÷ 4n Synth N4d t4 ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 Figure 16. MultiSynth to Output Driver Crosspoint 30 Rev. 1.0 Si5345-44-42-RM Table 15 is used to set up the routing from the MultiSynth frequency selection to the output. Table 15. Output Driver Crosspoint Configuration Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_MUX_SEL 0x010B[2:0] 0x0115[2:0] 0x0115[2:0] OUT1_MUX_SEL 0x0110[2:0] 0x011A[2:0] 0x011A[2:0] OUT2_MUX_SEL 0x0115[2:0] 0x0129[2:0] — OUT3_MUX_SEL 0x011A[2:0] 0x012E[2:0] — OUT4_MUX_SEL 0x011F[2:0] — — OUT5_MUX_SEL 0x0124[2:0] — — OUT6_MUX_SEL 0x0129[2:0] — — OUT7_MUX_SEL 0x012E[2:0] — — OUT8_MUX_SEL 0x0133[2:0] — — OUT9_MUX_SEL 0x0138[2:0] — — Rev. 1.0 Connects the output drivers to one of the N dividers. Selections are N0, N1, N2, N3, N4 for each output divider. 31 Si5345-44-42-RM 6.2. Performance Guidelines for Outputs Whenever a number of high frequency, fast rise time, large amplitude signals are all close to one another, the laws of physics dictate that there will be some amount of crosstalk. The jitter of the Si5342/44/45 is so low that crosstalk can become a significant portion of the final measured output jitter. Some of the source of the crosstalk will be the Si5342/44/45 and some will be introduced by the PCB. It is difficult (and possibly irrelevant) to allocate the jitter portions between these two sources because the jitter can only be measured when a Si5342/44/45 is mounted on a PCB. For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying the arrangements of different output clocks. For example, consider the following lineup of output clocks in Table 16. Table 16. Example of Output Clock Frequency Sequencing Choice Output Not Recommended (Frequency MHz) Recommended (Frequency MHz) 0 155.52 155.52 1 156.25 155.52 2 155.52 622.08 3 156.25 Not used 4 200 156.25 5 100 156.25 6 622.08 625 7 625 Not used 8 Not used 200 9 Not used 100 Using this example, a few guidelines are illustrated: 1. Avoid adjacent frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock. If the jitter integration bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart. 2. Adjacent frequency values that are integer multiples of one another are okay and these outputs should be grouped accordingly. Noting that because 155.52 x 4 = 622.08 and 156.25 x 4 = 625, it is okay to place these frequency values close to one another. 3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. In this case, see OUT3 and OUT7. If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible to crosstalk. These guidelines typically only need to be followed by those applications that wish to achieve the highest possible levels of jitter performance. Because CMOS outputs have large pk-pk swings, are single ended, and do not present a balanced load to the VDDO supplies, CMOS outputs generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided whenever possible. When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines. For more information on these issues, see AN862 “Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.” 32 Rev. 1.0 Si5345-44-42-RM 6.3. Output Signal Format The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS, LVPECL, HCSL. For CML applications, see “ Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes”. The differential formats can be either normal or low power. Low power format uses less power for the same amplitude but has the drawback of slower rise/fall times. The source impedance in low power format is much higher than 100 ohms. See Appendix A for register settings to implement variable amplitude differential outputs. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins. See “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for additional information. Table 17. Output Signal Format Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_FORMAT 0x0109[2:0] 0x0113[2:0] 0x0113[2:0] OUT1_ FORMAT 0x010E[2:0] 0x0118[2:0] 0x0118[2:0] OUT2_ FORMAT 0x0113[2:0] 0x0127[2:0] — OUT3_ FORMAT 0x0118[2:0] 0x012C[2:0] — OUT4_ FORMAT 0x011D[2:0] — — OUT5_ FORMAT 0x0122[2:0] — — OUT6_ FORMAT 0x0127[2:0] — — OUT7_ FORMAT 0x012C[2:0] — — OUT8_ FORMAT 0x0131[2:0] — — OUT9_ FORMAT 0x0136[2:0] — — Rev. 1.0 Selects the output signal format as differential or LVCMOS mode. 33 Si5345-44-42-RM 6.3.1. Differential Output Terminations The differential output drivers support both ac and dc-coupled terminations as shown in Figure 17. AC Coupled LVDS/LVPECL DC Coupled LVDS VDDO = 3.3 V, 2.5 V, 1.8 V VDDO = 3.3 V, 2.5 V 50 OUTx 50 OUTx 100 OUTx 100 OUTx 50 50 Internally self-biased Si5345/44/42 Si5345/44/42 AC Coupled HCSL AC Coupled LVPECL/CML VDDRX VDDO = 3.3 V, 2.5 V, 1.8 V VDD – 1.3 V R1 R1 VDDO = 3.3 V, 2.5 V 50 50 OUTx Standard HCSL Receiver OUTx 50 Si5345/44/42 R2 OUTx VDDRX 3.3 V 2.5 V 1.8 V 50 OUTx For VCM = 0.37V R2 50 50 R1 R2 442 56.2 332 59 243 63.4 Si5345/44/42 Figure 17. Supported Differential Output Terminations 6.3.2. Differential Output Swing Modes There are two selectable differential output swing modes: Normal and High. Each output can support a unique mode. Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific reason to do otherwise. When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. Table 18 lists the registers that control the output voltage swing. The output impedance in the Normal Swing Mode is 100 differential. Any of the terminations shown in Figure 17 are supported in this mode. Differential High Swing Mode—When an output driver is configured in high swing mode, its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 PCB traces. Any of the terminations shown in Figure 17 are supported. The use of High Swing mode will result in larger pk-pk output swings that draw less power. The trade off will be slower rise and fall times. Vpp_diff is 2 x Vpp_se as shown in Figure 18. OUTx Vcm Vpp_se Vcm Vpp_se Vcm OUTx Figure 18. Vpp_se and Vpp_diff 34 Rev. 1.0 Vpp_diff = 2*Vpp_se Si5345-44-42-RM Table 18. Differential Output Voltage Swing Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_AMPL 0x010A[6:4] 0x0114[6:4] 0x0114[6:4] OUT1_ AMPL 0x010F[6:4] 0x0119[6:4] 0x0119[6:4] OUT2_ AMPL 0x0114[6:4] 0x0128[6:4] — OUT3_ AMPL 0x0119[6:4] 0x012D[6:4] — OUT4_ AMPL 0x011E[6:4] — — OUT5_ AMPL 0x0123[6:4] — — OUT6_ AMPL 0x0128[6:4] — — OUT7_ AMPL 0x012D[6:4] — — OUT8_ AMPL 0x0132[6:4] — — OUT9_ AMPL 0x0137[6:4] — — Sets the voltage swing for the differential output drivers for both normal and high swing modes. 6.3.3. Programmable Common Mode Voltage for Differential Outputs The common mode voltage (VCM) for the differential Normal and High Swing modes is programmable in 100 mV increments from 0.7 to 2.3 V depending on the voltage available at the output's VDDO pin. Setting the common mode voltage is useful when dc coupling the output drivers. High swing mode may also cause an increase in the rise/fall time. Table 19. Differential Output Common Mode Voltage Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_CM 0x010A[3:0] 0x0114[3:0] 0x0114[3:0] OUT1_ CM 0x010F[3:0] 0x0119[3:0] 0x0119[3:0] OUT2_ CM 0x0114[3:0] 0x0128[3:0] — OUT3_ CM 0x0119[3:0] 0x012D[3:0] — OUT4_ CM 0x011E[3:0] — — OUT5_ CM 0x0123[3:0] — — OUT6_ CM 0x0128[3:0] — — OUT7_ CM 0x012D[3:0] — — OUT8_ CM 0x0132[3:0] — — OUT9_ CM 0x0137[3:0] — — Rev. 1.0 Sets the common mode voltage for the differential output driver. 35 Si5345-44-42-RM 6.3.4. LVCMOS Output Terminations LVCMOS outputs are dc-coupled as shown in Figure 19. DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V 50 OUTx Rs OUTx 50 Rs Figure 19. LVCMOS Output Terminations 6.3.5. LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO option as shown in Table 20. The value for the OUTx_CMOS_DRIVE bits are given. Table 20. Output Impedance and Drive Strength Selections VDDO OUTx_CMOS_DRV Source Impedance (Rs) Drive Strength (Iol/Ioh) 3.3 V 0x01 38 10 mA 0x02 30 12 mA 0x03* 22 17 mA 0x01 43 6 mA 0x02 35 8 mA 0x03* 24 11 mA 0x03* 31 5 mA 2.5 V 1.8 V *Note: Use of the lowest impedance setting is recommended for all supply voltages. 36 Rev. 1.0 Si5345-44-42-RM Table 21. LVCMOS Drive Strength Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_CMOS_DRV 0x0109[7:6] 0x0113[7:6] 0x0113[7:6] OUT1_ CMOS_DRV 0x010E[7:6] 0x0118[7:6] 0x0118[7:6] OUT2_ CMOS_DRV 0x0113[7:6] 0x0127[7:6] — OUT3_ CMOS_DRV 0x0118[7:6] 0x012C[7:6] — OUT4_ CMOS_DRV 0x011D[7:6] — — OUT5_ CMOS_DRV 0x0122[7:6] — — OUT6_ CMOS_DRV 0x0127[7:6] — — OUT7_ CMOS_DRV 0x012C[7:6] — — OUT8_ CMOS_DRV 0x0131[7:6] — — OUT9_ CMOS_DRV 0x0136[7:6] — — LVCMOS output impedance. 6.3.6. LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage. Rev. 1.0 37 Si5345-44-42-RM 6.3.7. LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers. Table 22. LVCMOS Output Polarity Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_INV 0x010B[7:6] 0x0115[7:6] 0x0115 [7:6] OUT1_ INV 0x0110[7:6] 0x011A[7:6] 0x011A [7:6] OUT2_ INV 0x0115[7:6] 0x0129[7:6] — OUT3_ INV 0x011A[7:6] 0x012E[7:6] — OUT4_ INV 0x011F[7:6] — — OUT5_ INV 0x0124[7:6] — — OUT6_ INV 0x0129[7:6] — — OUT7_ INV 0x012E[7:6] — — OUT8_ INV 0x0133[7:6] — — OUT9_ INV 0x0138[7:6] — — Controls the output polarity of the OUTx and OUTx pins when in LVCMOS mode. Selections are below in Table 23. Table 23. Output Polarity of OUTx and OUTx Pins in LVCMOS Mode 38 OUTx_INV Register Settings OUTx OUTx Comment 0x00 CLK CLK Non-inverted 0x01 CLK CLK Both in phase (default) 0x02 CLK CLK Inverted 0x03 CLK CLK Both out of phase Rev. 1.0 Si5345-44-42-RM 6.3.8. Output Driver Settings for LVPECL, LVDS, HCSL, and CML Each differential output has four settings for control 1. Normal or Low Power Format 2. Amplitude (sometimes called Swing) 3. Common Mode Voltage 4. Stop High or Stop Low The normal Format setting has a 100 ohm internal resistor between the plus and minus output pins. The Low Power Format setting removes this 100 ohm internal resistor and then the differential output resistance will be > 500 . However as long as the termination impedance matches the differential impedance of the pcb traces the signal integrity across the termination impedance will be good. For the same output amplitude the Low Power Format will use less power than the Normal Format. The Low Power Format also has a lower rise/fall time than the Normal Format. See the Si5345/44/42 data sheet for the rise/fall time specifications. For LVPECL and LVDS standards, ClockBuilder Pro does not support the Low Power Differential Format. Stop High means that when the output driver is disabled the plus output will be high and the minus output will be low. Stop Low means that when the output driver is disabled the plus output will be low and the minus output will be high. The Format, Amplitude and Common Mode settings for the various supported standards are shown in Table 24. Table 24. Settings for LVDS, LVPECL, and HCSL OUTx_FORMAT Standard VDDO Volts OUTx_CM (Decimal) OUTx_AMPL (Decimal) 001 = Normal Differential LVPECL 3.3 11 6 001 = Normal Differential LVPECL 2.5 11 6 002 = Low Power Differential LVPECL 3.3 11 3 002 = Low Power Differential LVPECL 2.5 11 3 001 = Normal Differential LVDS 3.3 3 3 001 = Normal Differential LVDS 2.5 11 3 001 = Normal Differential Sub-LVDS1 1.8 13 3 002 = Low Power Differential LVDS 3.3 3 1 002 = Low Power Differential LVDS 2.5 11 1 002 = Low Power Differential Sub-LVDS1 1.8 13 1 002 = Low Power Differential 2 HCSL 3.3 11 3 002 = Low Power Differential HCSL2 2.5 11 3 002 = Low Power Differential HCSL2 1.8 13 3 Notes: 1. The common mode voltage produced is not compliant with LVDS standards, therefore AC coupling the driver to an LVDS receiver is highly recommended. 2. Creates HCSL compatible signal. See Figure 9. 3. The low-power format will cause the rise/fall time to increase by approximately a factor of two. See the Si5345/44/42 data sheet for more information. The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes. See Appendix A for additional information. Rev. 1.0 39 Si5345-44-42-RM 6.4. Output Enable/Disable The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high all outputs will be disabled. When the pin is not driven, the device defaults to all outputs on. Outputs in the enabled state can be individually disabled through register control. If the pin is high register control is disabled and all outputs will be disabled. Table 25. Output Enable/Disable Control Registers Register Name 40 Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUTALL_ DISABLE_LOW 0x0102[0] 0x0102[0] 0x0102[0] Disables all output drivers: 0 - all outputs disabled, 1 – all outputs enabled. This bit essentially has the same function as the OE pin if the OE pin is held low. If the OE pin is held high, then all outputs will be disabled regardless of the state of this register bit. OUT0_OE 0x0108[1] 0x0112[1] 0x0112[1] OUT1_ OE 0x010D[1] 0x0117[1] 0x0117[1] OUT2_ OE 0x0112[1] 0x0126[1] — Allows enabling/disabling individual output drivers. Note that the OE pin must be held low in order to enable an output. OUT3_ OE 0x0117[1] 0x012B[1] — OUT4_ OE 0x011C[1] — — OUT5_ OE 0x0121[1] — — OUT6_ OE 0x0126[1] — — OUT7_ OE 0x012B[1] — — OUT8_ OE 0x0130[1] — — OUT9_ OE 0x0135[1] — — Rev. 1.0 Si5345-44-42-RM 6.4.1. Output Driver State When Disabled The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance. Table 26. Output Driver State Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_DIS_STATE 0x0109[5:4] 0x0113[5:4] 0x0113[5:4] OUT1_ DIS_STATE 0x010E[5:4] 0x0118[5:4] 0x0118[5:4] OUT2_ DIS_STATE 0x0113[5:4] 0x0127[5:4] — OUT3_ DIS_STATE 0x0118[5:4] 0x012C[5:4] — OUT4_ DIS_STATE 0x011D[5:4] — — OUT5_ DIS_STATE 0x0122[5:4] — — OUT6_ DIS_STATE 0x0127[5:4] — — OUT7_ DIS_STATE 0x012C[5:4] — — OUT8_ DIS_STATE 0x0131[5:4] — — OUT9_ DIS_STATE 0x0136[5:4] — — Determines the state of an output driver when disabled. Selectable as: Disable logic low Disable logic high Disable high-impedance Note that in high-impedance mode the differential driver will output the common mode voltage and no signal. The default disabled state is high-impedance. 6.4.2. Synchronous Output Disable Feature The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete. The default state is for the synchronous output to be disabled. Table 27. Synchronous Disable Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 OUT0_SYNC_EN 0x0109[3] 0x0113[3] 0x0113[3] OUT1_ SYNC_EN 0x010E[3] 0x0118[3] 0x0118[3] OUT2_ SYNC_EN 0x0113[3] 0x0127[3] — OUT3_ SYNC_EN 0x0118[3] 0x012C[3] — OUT4_ SYNC_EN 0x011D[3] — — OUT5_ SYNC_EN 0x0122[3] — — OUT6_ SYNC_EN 0x0127[3] — — OUT7_ SYNC_EN 0x012C[3] — — OUT8_ SYNC_EN 0x0131[3] — — OUT9_ SYNC_EN 0x0136[3] — — Rev. 1.0 Synchronous output disable. When this feature is enabled, the output clock will always finish a complete period before disabling. When this feature is disabled, the output clock will disable immediately without waiting for the period to complete. This feature is disabled by default. 41 Si5345-44-42-RM 6.5. Output Skew Control (t0–t4) The Si5345 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t0–t4) associated with each of these dividers is available for applications that need a specific output skew configuration. This is useful for PCB trace length mismatch compensation or for applications that require quadrature clock generation. The resolution of the phase adjustment is approximately 1 ps per step definable in a range of ±8.32 ns. Phase adjustments are register configurable. An example of generating two frequencies with unique configurable path delays is shown in Figure 20. ÷N0 t0 ÷R0 VDDO0 OUT0 OUT0 VDDO1 OUT1 OUT1 ÷N1 t1 ÷R1 ÷N2 t2 ÷R2 VDDO2 OUT2 OUT2 ÷N3 t3 ÷R3 VDDO3 OUT3 OUT3 ÷N4 t4 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 Figure 20. Example of Independently-Configurable Path Delays 42 Rev. 1.0 Si5345-44-42-RM All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RST pin. Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or after power-on reset, or after a hardware reset using the RST pin. Table 28. Output Delay Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 N0_DELAY 0x0359[7:0]0x035A[7:0] 0x0359[7:0]0x035A[7:0] 0x0359[7:0]0x035A[7:0] N1_DELAY 0x035B [7:0]0x035C[7:0] 0x035B [7:0]0x035C[7:0] 0x035B [7:0]0x035C[7:0] N2_DELAY 0x035D[7:0]0x035E[7:0] 0x035D[7:0]0x035E[7:0] — N3_DELAY 0x035F[7:0]0x0360[7:0] 0x035F[7:0]0x0360[7:0] — N4_DELAY 0x0361[7:0]0x0362[7:0] — — Rev. 1.0 Configures path delay values for each N divider. Each 16 bit number is 2s complement. The output delay is Nx_DELAY/(256 x Fvco) where Fvco is the frequency of the VCO in Hz and the delay is in seconds. Register values determined using ClockBuilder Pro. 43 Si5345-44-42-RM 7. Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in Figure 21. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection in the Si5345. OUT3 and FB_IN pins are recommended for the external feedback in the Si5344. OUT1 or OUT2 are recommended with FB_IN in the Si5342. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. IN0 Si5345/44/42 ÷P0 IN0 IN1 DSPLL ÷P1 IN1 IN2 PD ÷P2 IN2 15GHz LPF ÷M IN3/FB_IN 100 ÷P3 ÷R0 VDDO0 OUT0 OUT0 IN3/FB_IN ÷N0 t0 ÷R1 VDDO1 OUT1 OUT1 ÷N1 t1 ÷R2 VDDO2 OUT2 OUT2 ÷N2 t2 ÷N3 t3 ÷R7 VDDO7 OUT7 OUT7 ÷N4 t4 ÷R8 VDDO8 OUT8 OUT8 ÷R9 VDDO9 OUT9 OUT9 External Feedback Path Figure 21. Si5345 Zero Delay Mode Set-up 44 Rev. 1.0 Si5345-44-42-RM Table 29 lists the registers used for the Zero Delay mode. Table 29. Zero Delay Mode Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 ZDM_EN 0x0487[0] 0x0487[0] 0x0487[0] ZDM_IN_SEL 0x0487[2:1] 0x0487[2:1] 0x0487[2:1] Rev. 1.0 0: Disable zero delay mode. 1: Enable zero delay mode. Selects (normal feedback IN0-IN3) by creating an external feedback through FB_IN (zero delay mode). 45 Si5345-44-42-RM 8. Digitally-Controlled Oscillator (DCO) Mode An output that is controlled as a DCO is useful for simple tasks, such as frequency margining, CPU speed control, or just changing the output frequency. The output can also be used for more sophisticated tasks, such as FIFO management, by adjusting the frequency of the read or write clock to the FIFO or using the output as a variable Local Oscillator in a radio application. The N dividers can be digitally controlled so that all outputs connected to the N divider change frequency in real time without any transition glitches. There are two ways to control the N divider to accomplish this task: Use the Frequency Increment/Decrement Pins or register bits. Write directly to the numerator or denominator of the N divider. The output N divider can be changed from its minimum value to its maximum value in very small fractional increments or in a single large increment. Each N divider has a value of Nx_NUM/Nx_DEN. Nx_NUM is a 44-bit word, and Nx_DEN is a 32-bit word. Clockbuilder Pro left-shifts these values as far as possible before writing them to the actual Nx_NUM and Nx_DEN registers. For example, an integer Nx divider of 30/1, when left shifted, becomes Nx_NUM=6442509440 (decimal) and Nx_DEN=2147483648 (decimal). By adjusting the size of the Nx_NUM and Nx_DEN but keeping the ratio the same, the resolution of the LSbit of numerator or denominator can be controlled. When changing the N divider(s) to fractional values, the setting name, N_PIBYP[4:0], must be a 0 for the N divider that is being changed. This applies when using FINC/FDEC or when directly writing to the N divider. 8.1. DCO with Frequency Increment/Decrement Pins/Bits The FSTEPW (Frequency STEP Word) is a 44-bit word that is used to change the value of the Nx_NUM word. Whenever an FINC or FDEC is asserted, the FSTEPW will automatically add or subtract from the Nx_NUM word so that the output frequency will, respectively, increment (FINC) or decrement (FDEC). Each of the N dividers can be independently stepped up or down in numerical, predefined steps with a maximum resolution that varies from ~ 0.05 ppb to a ~0.004 ppb depending upon the frequency plan. One or more N dividers can be controlled by FINC/FDEC at the same time by use of the N_FSTEP_MSK bits. Any N divider that is masked by its corresponding bit in the N_FSTEP_MSK field will not change when FINC or FDEC is asserted. The magnitude of the frequency change caused by FINC or FDEC is determined by the value of the FSTEPW word and the magnitude of the word in Nx_NUM. For a specific frequency step size, it may be necessary to adjust the Nx_NUM value while keeping the ratio of Nx_NUM/Nx_DEN the same. When the FINC or FDEC pin or register bit is asserted, the selected N dividers will have their numerator changed by the addition or subtraction of the Nx_FSTEPW so that an FINC will increase the output frequency, and an FDEC will decrease the output frequency. A FINC or FDEC can be followed by another FINC or FDEC in 1 µs minimum. Because the output frequency = FVCO*Nx_DEN/(Rx*Nx_NUM), subsequent changes to Nx_NUM by the FSTEPW will not produce exactly the same output frequency change. The amount of error in the frequency step is extremely small and, in a vast number of applications, will not cause a problem. When consecutive frequency steps must be exactly the same, it is possible to set FINC and FDEC to change the Nx_DEN instead of Nx_NUM, and then, consecutive FINCs or FDECs will be exactly the same frequency change. However, there are some special setups that are necessary to achieve this. For more information, contact Silicon Labs at https://www.silabs.com/ support/pages/contacttechnicalsupport.aspx. 46 Rev. 1.0 Si5345-44-42-RM Si5345 N0_FSTEP_MASK 0x0339 Multi N ÷ n0 Synth Nd0 t0 + Frequency - Step Word 0x033B – 0x0340 N1_FSTEP_MASK 0x0339 Multi N ÷ n1 Synth Nd1 t1 + Frequency - Step Word 0x0341 – 0x0346 N2_FSTEP_MASK 0x0339 FINC FDEC Multi N ÷ n2 Synth Nd2 t2 + Frequency - Step Word 0x001D 0x0347 – 0x034C N3_FSTEP_MASK 0x0339 Multi N ÷ n3 Synth Nd3 t3 + Frequency - Step Word 0x034D – 0x0352 N4_FSTEP_MASK 0x0339 I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C Multi N ÷ n4 Synth Nd4 t4 + Frequency - Step Word 0x0353 – 0x0358 FINC FDEC A0/CS Figure 22. DCO with FINC/FDEC Pins or Bits Rev. 1.0 47 Si5345-44-42-RM Table 30. Frequency Increment/Decrement Control Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 FINC 0x001D[0] 0x001D[0] 0x001D[0] Asserting this bit will increase the DSPLL output frequency by the frequency step word. FDEC 0x001D[1] 0x001D[1] 0x001D[1] Asserting this bit will decrease the DSPLL output frequency by the frequency step word. N0_FSTEPW 0x033B[7:0]0x0340[7:0] 0x033B[7:0]0x0340[7:0] 0x033B[7:0]0x0340[7:0] N1_FSTEPW 0x0341[7:0]0x0346[7:0] 0x0341[7:0]0x0346[7:0] 0x0341[7:0]0x0346[7:0] N2_FSTEPW 0x0347[7:0]0x034C[7:0] 0x0347[7:0]0x034C[7:0] — N3_FSTEPW 0x034D[7:0]0x0352[7:0] 0x034D[7:0]0x0352[7:0] — N4_FSTEPW 0x0353[7:0]0x0358[7:0] — — N_FSTEP_MSK 0x0339[4:0] 0x0339[3:0] 0x0339[1:0] This is a 44-bit frequency step word for each of the MultiSynths. The FSTEPW will be added or subtracted to the output frequency during assertion of the FINC/FDEC bits or pins. The FSTEPW is calculated based on the frequency configuration and is easily determined using the ClockBuilder Pro This mask bit determines if a FINC or FDEC affects N0, N1, N2, N3, N4. 0 = FINC/FDEC will Increment/decrement the FSTEPW to the selected MultiSynth(s), 1 = Ignores FINC/FDEC. 8.2. DCO with Direct Register Writes When an N divider numerator (Nx_NUM) and its corresponding update bit (Nx_UPDATE) are written, the new numerator value will take effect, and the output frequency will change without any glitches. The N divider numerator and denominator terms (Nx_NUM and Nx_DEN) can be left- and right-shifted so that the least significant bit of the numerator word represents the exact step resolution that is needed for your application. Each N divider has an update bit (Nx_UPDATE) that must be written to cause the written values to take effect. All N dividers can be updated at the same time by writing the N_UPDATE_ALL bit. Writing this bit will NOT cause any output glitching on an N divider that did not have its numerator or denominator changed. When changing the N divider denominator (Nx_DEN), it is remotely possible that a small phase hit of ~550 fs may occur at the exact time of the frequency change. However, with the proper setup, it is possible to change Nx_DEN and never have a phase hit. If your application requires changing an N divider denominator, contact Silicon Labs at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx for support. 48 Rev. 1.0 Si5345-44-42-RM 9. Serial interface Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I2C or SPI interface. Both of these serial interfaces are based on 8-bit addressing, which means that the page byte must be written every time you need to access a different page in the register map. See the PAGE byte at register 0x0001 for more information. The I2C_SEL pin selects I2C or SPI operation. The Si5345/44/42 supports communication with a 3.3 or 1.8 V host by setting the IO_VDD_SEL (0x0943[0]) configuration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. I2C SPI 4-Wire SPI 3-Wire I2C_SEL pin = High I2C_SEL pin = Low SPI_3WIRE = 0 I2C_SEL pin = Low SPI_3WIRE = 1 IO_VDD_SEL = 0 (Default) IO_VDD_SEL = 0 (Default) 1.8V Host = 1.8V 1.8V 1.8V I2C SDA HOST SCLK 3.3V 1.8V VDDA VDD SDA CS SPI HOST SDO SDI SCLK Si5345/44/42 SCLK IO_VDD_SEL = 1 3.3V I2C SDA HOST SCLK 3.3V 3.3V 1.8V VDDA VDD 1.8V CS SPI HOST SDI SDO CS SDIO SCLK 3.3V 1.8V VDDA VDD SDA SCLK CS SPI HOST SDO 1.8V VDDA VDD CS SDIO SCLK Si5345/44/42 IO_VDD_SEL = 1 3.3V 1.8V VDDA VDD 3.3V CS SPI HOST SDI SDI SDO SCLK SCLK Si5345/44/42 3.3V SCLK Si5345/44/42 IO_VDD_SEL = 1 3.3V Host = 3.3V IO_VDD_SEL = 0 (Default) CS SDIO SCLK Si5345/44/42 3.3V 1.8V VDDA VDD CS SDIO SCLK Si5345/44/42 Figure 23. I2C/SPI Device Connectivity Configurations Rev. 1.0 49 Si5345-44-42-RM Table 31 lists register settings of interest for the I2C/SPI. Table 31. I2C/SPI Register Settings Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 IO_VDD_SEL 0x0943[0] 0x0943[0] 0x0943[0] The IO_VDD_SEL bit determines whether the VDD or VDDA supply voltage is used for the serial port, control pins, and status pins voltage references. See the register map description of this bit for additional details. SPI_3WIRE 0x002B[3] 0x002B[3] 0x002B[3] The SPI_3WIRE configuration bit selects the option of 4-wire or 3-wire SPI communication. By default, the SPI_3WIRE configuration bit is set to the 4-wire option. In this mode, the Si5345/44/42 will accept write commands from a 4-wire or 3- wire SPI host allowing configuration of device registers. For full bidirectional communication in 3-wire mode, the host must write the SPI_3WIRE configuration bit to “1”. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected, and tie SDA/SDIO and SCLK low. 50 Rev. 1.0 Si5345-44-42-RM 9.1. I2C Interface When in I2C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in StandardMode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 26. Both the SDA and SCL pins must be connected to a supply via an external pull-up (4.7 k) as recommended by the I2C specification as shown in Figure 24. Two address select bits (A0, A1) are provided allowing up to four Si5345/44/42 devices to communicate on the same bus. This also allows four choices in the I2C address for systems that may have other overlapping addresses for other I2C devices. I2C VDD VDDI2C I2C_SEL SDA To I2C Bus or Host SCLK A0 LSBs of I2C Address A1 Si5345/44/42 Figure 24. I2C Configuration The 7-bit slave device address of the Si5345/44/42 consists of a 5-bit fixed address plus 2 pins which are selectable for the last two bits, as shown in Figure 25. Slave Address 6 5 4 3 2 1 1 0 1 0 1 0 A1 A0 Figure 25. 7-bit I2C Slave Address Bit-Configuration Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 28. A write burst operation is also shown where subsequent data words are written using to an auto-incremented address. Rev. 1.0 51 Si5345-44-42-RM Write Operation – Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P A Data [7:0] Write Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P Reg Addr +1 Host Si5345/44/42 Host Si5345/44/42 1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition Figure 26. I2C Write Operation A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in Figure 27. Read Operation – Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A S Slv Addr [6:0] 1 A Data [7:0] P N P Read Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] S Slv Addr [6:0] 1 A Data [7:0] A A P Data [7:0] N P Reg Addr +1 Host Si5345/44/42 Host Si5345/44/42 1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition Figure 27. I2C Read Operation The I2C bus supports SDA timeout for compatibility with the SMBus interfaces. The error flags are found in the registers listed in Table 32. 52 Rev. 1.0 Si5345-44-42-RM Table 32. SMBus Timeout Error Bit Indicators Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 SMBUS_TIMEOUT 0x000C[5] 0x000C[5] 0x000C[5] 1 if there is a SMBus timeout error. Contact Silicon Labs. SMBUS_TIMEOUT_FLG 0x0011[5] 0x0011[5] 0x0011[5] 1 if there is a SMBus timeout error. Contact Silicon Labs. 9.2. SPI Interface When in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit. The 4-wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input (SDI), and serial data output (SDO). The 3-wire interface combines the SDI and SDO signals into a single bidirectional data pin (SDIO). Both 4-wire and 3-wire interface connections are shown in Figure 28. SPI 3-Wire SPI_3WIRE = 1 SPI 4-Wire SPI_3WIRE = 0 I2C_SEL I2C_SEL CS To SPI Host CS SDI To SPI Host SDO SCLK SDIO SCLK Si5345/44/42 Si5345/44/42 Figure 28. SPI Interface Connections Table 33. SPI Command Format Instruction Ist Byte1 2nd Byte 3rd Byte Nth Byte2,3 Set Address 000x xxxx 8-bit Address — — Write Data 010x xxxx 8-bit Data — — Read Data 100x xxxx 8-bit Data — — Write Data + Address Increment 011x xxxx 8-bit Data — — Read Data + Address Increment 101x xxxx 8-bit Data — — Burst Write Data 1110 0000 8-bit Address 8-bit Data 8-bit Data Notes: 1. X = don’t care (1 or 0) 2. The Burst Write Command is terminated by de-asserting /CS (/CS = high) 3. There is no limit to the number of data bytes that follow the Burst Write Command, but the address will wrap around to zero in the byte after address 255 is written. Rev. 1.0 53 Si5345-44-42-RM Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data” command. The 'Write Data + Address Increment' or “Read Data + Address Increment” commands are available for cases where multiple byte operations in sequential address locations is necessary. The “Burst Write Data” instruction provides a compact command format for writing data since it uses a single instruction to define starting address and subsequent data bytes. Figure 29 shows an example of writing three bytes of data using the write commands. This demonstrates that the “Write Burst Data” command is the most efficient method for writing data to sequential address locations. Figure 30 provides a similar comparison for reading data with the read commands. Note that there is no burst read, only read increment. ‘Set Address’ and ‘Write Data’ ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Address’ and ‘Write Data + Address Increment’ ‘Set Addr’ Addr [7:0] ‘Write Data + Addr Inc’ ‘Write Data + Addr Inc’ Data [7:0] ‘Write Data + Addr Inc’ Data [7:0] Data [7:0] ‘Burst Write Data’ ‘Burst Write Data’ Host Addr [7:0] Si5345/44/42 Data [7:0] Host Data [7:0] Data [7:0] Si5345/44/42 Figure 29. Example Writing Three Data Bytes Using the Write Commands 54 Rev. 1.0 Si5345-44-42-RM ‘Set Address’ and ‘Read Data’ ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0] ‘Set Address’ and ‘Read Data + Address Increment’ ‘Set Addr’ Addr [7:0] ‘Read Data + Addr Inc’ ‘Read Data + Addr Inc’ Data [7:0] ‘Read Data + Addr Inc’ Data [7:0] Host Host Si5345/44/42 Data [7:0] Si5345/44/42 Figure 30. Example of Reading Three Data Bytes Using the Read Commands The timing diagrams for the SPI commands are shown in Figures 31, 32, 33, and 34. Previous Command Next Command ‘Set Address’ Command > 2.0 SCLK Periods >2 SCLK Periods Set Address Instruction CS Base Address SCLK 4-Wire SDI 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 SDO 3-Wire SDIO Host Si5345/44/42 Host Si5345/44/42 Don’t Care High Impedance Figure 31. SPI “Set Address” Command Timing Rev. 1.0 55 Si5345-44-42-RM Previous Command ‘Write Data’ or ‘Write Data + Address Increment’ Command Next Command > 2.0 SCLK Periods >2 SCLK Periods Write Data instruction Data byte @ base address + 1 CS SCLK 4-Wire SDI 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 SDO 3-Wire SDIO Host Si5345/44/42 Host Si5345/44/42 Don’t Care High Impedance Figure 32. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing 56 Rev. 1.0 Si5345-44-42-RM Previous Command ‘Read Data’ or ‘Read Data + Address Increment’ Command Next Command > 2.0 SCLK Periods > 2.0 SCLK Periods Read Data instruction Read byte @ base address + 1 CS SCLK 4-Wire SDI 1 0 SDO 1 0 1 0 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 7 6 3-Wire SDIO Host 7 6 5 4 3 Host Si5345/44/42 2 1 0 High Impedance Don’t Care Si5345/44/42 Figure 33. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing Previous Command Next Command ‘Burst Data Write’ Command Burst Write Instruction CS 1st data byte @ base address Base address nth data byte @ base address +n SCLK 4-Wire SDI 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 SDO 3-Wire SDIO Host Si5345/44/42 Host Si5345/44/42 Don’t Care High Impedance Figure 34. SPI “Burst Data Write” Instruction Timing Rev. 1.0 57 Si5345-44-42-RM 10. Field Programming To simplify design and software development of systems using the Si5345/44/42, a field programmer is available. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5345/44/42 sample devices. Refer to www.silabs.com/ CBProgrammer for information about this kit. 58 Rev. 1.0 Si5345-44-42-RM 11. XAXB External References 11.1. Performance of External References An external standard non-pullable crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 35. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accommodated. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of ±200 ppm. The recommended crystal suppliers is provided in Table 30 with PCB layout recommendations for the crystal to ensure optimum jitter performance. 48-54MHz XO 48-54MHz XO 48-54MHz XTAL XA 100 XB 2xCL 48-54MHz XO XA 2xCL OSC 50 XA XB 2xCL 2xCL Si5345/44/42 Crystal Resonator Connection XA 2xCL 2xCL OSC OSC ÷ PXAXB XB 50 XB 2xCL 2xCL OSC ÷ PXAXB ÷ PXAXB Si5345/44/42 Si5345/44/42 Differential XO Connection Single-ended XO Connection ÷ PXAXB Si5345/44/42 Split Differential XO Connection (Highest Performance) Figure 35. Crystal Resonator and External Reference Clock Connection Options The Si5345/44/42 accepts a clipped sine wave, CMOS, or differential reference clock on the XA/XB interface. Most clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 100 or 50 load. For this reason, place the TCXO as close to the Si5345/44/42 as possible to minimize PCB trace length. In addition, ensure that both the Si5345/44/42 and the TCXO are both connected directly to the ground plane. Figure 36 shows the recommended method of connecting a clipped sine wave TCXO to the Si5345/44/42. Because the Si5345/44/42 provides dc bias at the XA and XB pins, the ~800 mV peak-peak swing can be input directly into the XA interface of the Si5345/44/42 once it has been ac-coupled. Because the signal is single-ended, the XB input is ac-coupled to ground. Note that when using a single-ended XO, the XO signal must be driven on XA. If XA is not driven, the device will report an LOSXAXB alarm. Figure 37 illustrates the recommended method of connecting a CMOS railto-rail output to the XA/XB inputs of the Si5345/44/42. The resistor network attenuates the rail-to-rail output swing to ensure that the maximum input voltage swing at the XA pin is less than 1.6 V pk-pk. The signal is ac-coupled before connecting it to the Si5345/44/42 XA input. If an external oscillator is used as the XAXB reference, it is important to use a low jitter source because there is essentially no jitter attenuation from the XAXB pins to the outputs. Rev. 1.0 59 Si5345-44-42-RM V3P3 VDD Si5345/44/42 100 nF TCXO OUT XA XB GND 100 nF Figure 36. Clipped Sine Wave TCXO Output V3P3 VDD Si5345/44/42 TCXO OUT XA 453 100 nF XB GND 453 100 nF 100 nF Figure 37. CMOS TCXO Output The Si5345/44/42 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or REFCLK is controlled by XAXB_EXTCLK_EN, the LSB of register 0x090E. The internal crystal loading capacitors (CL) are disabled when an external clock source is selected. A PXAXB prescale divider is available to accommodate external clock frequencies higher than 125 MHz as shown in Table 34. For best jitter performance, keep the REFCLK frequency above 40 MHz. For applications with loop BW values less than 10 Hz that require low wander output clocks, using a TCXO as the XAXB reference source should be considered to avoid the wander of a crystal. 60 Rev. 1.0 11.2. Recommended Crystals There are two classes of crystals that are recommended: those that are tested over temperature for activity dips and those that are not. There is a cost premium for testing over temperature. An activity dip is defined as when the crystal oscillation frequency changes by more than 2 ppm/C for any temperature between –40 °C and 75 °C. It is estimated that ~0.1% of crystals that are not tested over temperature for activity dips will have an activity dip at some temperature. Customers may contact the vendors to ask that any non-premium crystal be tested over temperature for activity dips. Similarly, any crystal that is tested over temperature can likely be purchased for a lower cost if you prefer to not pay the higher cost for the temperature testing. Table 34 lists the presently recommended crystals. Other vendors can also supply crystals that meet the specs in Figures 38 and 39. Table 34. Recommended Crystals Supplier Part Number Frequency Initial Accuracy over C0, ESR Tolerance –40 °C to +85 °C Max pF Max W in ± ppm in ± ppm Connor Winfield CS-043 48 MHz 15 25 2.0 20 8 No 200 3.2 x 2.5 Connor Winfield CS-044 54 MHz 15 25 2.0 20 8 No 200 3.2 x 2.5 Hosonic E3S48.000F08M22SI 48 MHz 20 20 1.5 25 8 No 200 3.2 x 2.5 Hosonic E2S48.000F08M22SI 48 MHz 20 20 1.5 25 8 No 200 2.5 x 2.0 Hosonic E3S54.000F08M22SI 54 MHz 20 20 2.0 22 8 No 200 3.2 x 2.5 Hosonic E2S54.000F08M22SI 54 MHz 20 20 1.5 25 8 No 200 2.5 x 2.0 Kyocera CX3225SB48000D0FPJC1 48 MHz 10 15 2.0 23 8 No 200 3.2 x 2.5 Kyocera CX3225SB48000D0WPSC1 48 MHz 15 30 2.0 23 8 No 200 3.2 x 2.5 Kyocera CX3225SB48000D0WPTC1 48 MHz 30 60 2.0 23 8 No 200 3.2 x 2.5 Kyocera CX3225SB54000D0FPJC1 54 MHz 10 15 2.0 23 8 No 200 3.2 x 2.5 Kyocera CX3225SB54000D0WPSC1 54 MHz 15 30 2.0 23 8 No 200 3.2 x 2.5 Kyocera CX3225SB54000D0WPTC1 54 MHz 30 60 2.0 23 8 No 200 3.2 x 2.5 Rev. 1.0 CL pF Tested Drive Case Size over Level µW mm x mm Temp for Activity Dips? 61 Table 34. Recommended Crystals (Continued) Supplier Part Number Frequency Initial Accuracy over C0, ESR Tolerance –40 °C to +85 °C Max pF Max W in ± ppm in ± ppm CL pF Tested Drive Case Size over Level µW mm x mm Temp for Activity Dips? Kyocera CX3225SB48000D0FPJC2 48 MHz 10 15 2.0 23 8 Yes 200 3.2 x 2.5 Kyocera CX3225SB48000D0WPSC2 48 MHz 15 30 2.0 23 8 Yes 200 3.2 x 2.5 Kyocera CX3225SB54000D0FPJC2 54 MHz 10 15 2.0 23 8 Yes 200 3.2 x 2.5 Kyocera CX3225SB54000D0WPSC2 54 MHz 15 30 2.0 23 8 Yes 200 3.2 x 2.5 NDK NX3225SA-48.000M-CS07559 48 MHz 20 30 1.8 23 8 No 200 3.2 x 2.5 NDK NX3225SA-54.000M-CS07551 54 MHz 20 30 1.8 23 8 No 200 3.2 x 2.5 Siward XTL571500-S315-006 54 MHz 50 50 2.0 20 8 No 200 3.2 x 2.5 Siward XTL571500-S315-007 54 MHz 50 50 2.0 20 8 No 200 2.5 x 2.0 Taitien S0242-X-001-3 54 MHz 20 20 2.0 23 8 No 200 3.2 x 2.5 Taitien S0242-X-002-3 48 MHz 20 20 2.0 23 8 No 200 3.2 x 2.5 TXC 7M48070012 48 MHz 10 15 2.0 22 8 No 200 3.2 x 2.5 TXC 7M54070010 54 MHz 10 15 2.0 22 8 No 200 3.2 x 2.5 TXC 7M48072001 48 MHz 20 30 2.0 22 8 Yes 200 3.2 x 2.5 TXC 7M54072001 54 MHz 20 30 2.0 22 8 Yes 200 3.2 x 2.5 TXC 7M48072002 48 MHz 10 15 2.0 22 8 Yes 200 3.2 x 2.5 TXC 7M54072002 54 MHz 10 15 2.0 22 8 Yes 200 3.2 x 2.5 In general, a crystal meeting the requirements of Figure 38 or Figure 39 and having a max power rating of at least 200 µW is guaranteed to oscillate. It is preferred that a crystal have a CL rating of 8 pF. Crystals with CL not equal to 8 pF can be used, but the XAXB_FREQ_OFFSET register word may be needed to compensate for oscillation frequency error. 62 Rev. 1.0 Si5345-44-42-RM MaximumESRvsC0for25MHzCrystal 100 90 ESRohms 80 70 60 50 40 30 0 0.5 1 1.5 2 2.5 3 3.5 3 3.5 C0pf Figure 38. Maximum ESR vs. C0 for 25 MHz Crystal MaximumESRvsC0for48Ͳ54MHzCrystal 31 29 ESRohms 27 25 23 21 19 17 15 0 0.5 1 1.5 2 2.5 C0pf Figure 39. Maximum ESR vs. C0 for 48–54 MHz Crystal Rev. 1.0 63 Si5345-44-42-RM 11.3. Recommended Oscillators Table 35 lists recommended TCXO suppliers. Table 35. Recommended Oscillator Suppliers Supplier TCXO/ OCXO Frequency Case Size (mm x mm x mm) 513872 (40MHz RTX7050A HCMOS) TCXO 40.000 5x7 NT7050BB-40.000MENA4199B TCXO 40.000 5x7 Vectron VT-803-EAH-2870-40M0000 TCXO 40.000 5x3.2 Vectron VT-803-EAH-2870-49M1520 TCXO 49.152 5x3.2 Vectron VT-803-EAH-2870-50M0000 TCXO 50.000 5x3.2 Rakon NDK Part Number 11.4. Register Settings to Control External XTAL Reference The following registers can be used to control and make adjustments for the external reference source used. 11.4.1. XAXB_FREQ_OFFSET Frequency Offset Register Table 36. XAXB Frequency Offset Register Register Name XAXB_FREQ_OFFSET Hex Address [Bit Field] Function Si5345 Si5344 Si5342 0202[7:0]0205[7:0] 0202[7:0]0205[7:0] 0202[7:0]0205[7:0] 32-bit number which allows adjustment to the center frequency of the XTAL in the range of ±1000 ppm. The VCO locks to the XO that is formed by the crystal or XO and the XAXB pins. XAXB_FREQ_OFFSET provides a static frequency offset to the VCO frequency. It is a 32-bit 2's complement number. This register can be used to adjust the frequency of the VCO when it is locked to the XAXB frequency. The Default value is 0. 11.4.2. XAXB_EXTCLK_EN Reference Clock Selection Register Table 37. XAXB External Clock Selection Register Register Name XAXB_EXTCLK_EN Hex Address [Bit Field] Si5345 Si5344 Si5342 090E[0] 090E[0] 090E[0] Function This bit selects between the XTAL or external REFCLK on the XA/XB pins. The default is XTAL = 0 This bit selects between XTAL or external REFCLK on the XA/XB pins. Set this bit to use the external REFCLK. 64 Rev. 1.0 Si5345-44-42-RM 11.4.3. PXAXB Pre-scale Divide Ratio for Reference Clock Register Table 38. Pre-Scale Divide Ratio Register Register Name PXAXB Hex Address [Bit Field] Si5345 Si5344 Si5342 0206[1:0] 0206[1:0] 0206[1:0] Function This is a two bit value that sets the divider value. Table 39 lists the input values for the two-bit field and the corresponding divider values. Table 39. Pre-Scale Divide Values Value (Decimal) PXAXB Divider Value 0 1 1 2 2 4 3 8 Rev. 1.0 65 Si5345-44-42-RM 12. Crystal and Device Circuit Layout Recommendations The main layout issues that should be carefully considered include the following: 1. Number and size of the ground vias for the Epad 2. Output clock trace routing 3. Input clock trace routing 4. Control and Status signals to input or output clock trace coupling 5. Xtal signal coupling 6. Xtal layout (See “12.1.2. Si5345 Crystal Guidelines” and “12.2.2. Si5342/44 Crystal Guidelines” for important crystal layout guidelines.) If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to the X1 and X2 pins (4 and 7) to provide the best possible performance. The shield should not be connected to the ground plane and the planes underneath should have as little under the shield as possible. It may be difficult to do this for all the layers, but it is important to do this for the layers that are closest to the shield. 12.1. 64-Pin QFN Si5345 Layout Recommendations This section details the recommended guidelines for the crystal layout of the 64-pin Si5345 device using an example 8-layer PCB. The following are the descriptions of each of the eight layers. Layer 1: device layer, with low speed CMOS control/status signals, ground flooded 2: crystal shield Layer 3: ground plane Layer 4: power distribution, ground flooded Layer 5: power routing layer Layer 6: ground input clocks, ground flooded Layer 7: output clocks layer Layer 8: ground layer Figure 40 is the top layer layout of the Si5345 device mounted on the top PCB layer. This particular layout was designed to implement either a crystal or an external oscillator as the XAXB reference. The crystal/ oscillator area is outlined with the white box around it. In this case, the top layer is flooded with ground. Note that this layout has a resistor in series with each pin of the crystal. In typical applications, these resistors should be removed. Layer 12.1.1. Si5345 Applications without a Crystal For applications that do not use a crystal, leave X1 and X2 pins as “no connect”. Do not tie to ground. There is no need for a crystal shield or the voids underneath the shield. The XAXB connection should be treated as a high speed critical path that is ac-coupled and terminated at the end of the etch run. The layout should minimize the stray capacitance from the XA pin to the XB pin. Jitter is very critical at the XAXB pins and therefore split termination and differential signaling should be used whenever possible. 12.1.2. Si5345 Crystal Guidelines The following are five recommended crystal guidelines: 1. Place the crystal as close as possible to the XA/XB pins. 2. DO NOT connect the crystal's GND pins to PCB gnd. 3. Connect the crystal's GND pins to the DUT's X1 and X2 pins via a local crystal GND shield placed around and under the crystal. See Figure 40 at the bottom left for an illustration of how to create a crystal GND shield by placing vias connecting the top layer traces to the shield layer underneath. Note that a zoom view of the crystal shield layer on the next layer down is shown in Figure 41. 4. Minimize traces adjacent to the crystal/oscillator area especially if they are clocks or frequently toggling digital signals. 66 Rev. 1.0 Si5345-44-42-RM 5. In general do not route GND, power planes/traces, or locate components on the other side, below the crystal GND shield. As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing, then place the next reference plane in the stack-up at least two layers away or at least 0.05 inches away. The Si5345 should have all layers underneath the ground shield removed. Figure 40. 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1) Figure 41. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) Figure 41 shows the layer that implements the shield underneath the crystal. The shield extends underneath the entire crystal and the X1 and X2 pins. This layer also has the clock input pins. The clock input pins go to layer 2 using vias to avoid crosstalk. As soon as the clock inputs are on layer 2, they have a ground shield above, below, and on the sides for protection. Rev. 1.0 67 Si5345-44-42-RM Figure 42 is the ground plane and shows a void underneath the crystal shield. Figure 43 is a power plane and shows the clock output power supply traces. The void underneath the crystal shield is continued. Figure 42. Crystal Ground Plane (Layer 3) Figure 43. Power Plane (Layer 4) 68 Rev. 1.0 Si5345-44-42-RM Figure 44 shows layer 5, which is the power plane with the power routed to the clock output power pins. Figure 44. Layer 5 Power Routing on Power Plane (Layer 5) Figure 45 is another ground plane similar to layer 3. Figure 45. Ground Plane (Layer 6) Rev. 1.0 69 Si5345-44-42-RM 12.1.3. Output Clocks Figure 46 shows the output clocks. Similar to the input clocks the output clocks have vias that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding between the clock output pairs to avoid crosstalk. There should be a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6. Figure 46. Output Clock Layer (Layer 7) Figure 47. Bottom Layer Ground Flooded (Layer 8) 70 Rev. 1.0 Si5345-44-42-RM 12.2. 44-Pin QFN Si5344/42 Layout Recommendations This section details the layout recommendations for the 44-pin Si5344 and Si5342 devices using an example 6layer PCB. The following guidelines details images of a six layer board with the following stack: Layer 1: device layer, with low speed CMOS control/status signals, ground flooded 2: crystal shield, output clocks, ground flooded Layer 3: ground plane Layer 4: power distribution, ground flooded Layer 5: input clocks, ground flooded Layer 6: low-speed CMOS control/status signals, ground flooded This layout was designed to implement either a crystal or an external oscillator as the XAXB reference. The top layer is flooded with ground. The clock output pins go to layer 2 using vias to avoid crosstalk during transit. When the clock output signals are on layer 2 there is a ground shield above, below and on all sides for protection. Output clocks should always be routed on an internal layer with ground reference planes directly above and below. The plane that has the routing for the output clocks should have ground flooded near the clock traces to further isolate the clocks from noise and other signals. Layer 12.2.1. Si5342/44 Applications without a Crystal If the application does not use a crystal, then the X1 and X2 pins should be left as “no connect” and should not be tied to ground. In addition, there is no need for a crystal shield or the voids underneath the shield. If there is a differential external clock input on XAXB there should be a termination circuit near the XA and XB pins. This termination circuit should be two 50 resistors and one 0.1 µF cap connected in the same manner as on the other clock inputs (IN0, IN1 and IN2). The clock input on XAXB must be ac-coupled. Care should be taken to keep all clock inputs well isolated from each other as well as any other dynamic signal. Figure 48. Device Layer (Layer 1) Rev. 1.0 71 Si5345-44-42-RM 12.2.2. Si5342/44 Crystal Guidelines Figure 49 is the second layer. The second layer implements the shield underneath the crystal. The shield extends underneath the entire crystal and the X1 and X2 pins. There should be no less than 12 vias to connect the X1 and X2 planes on layers 1 and 2. These vias are not shown in any other figures. All traces with signals that are not static must be kept well away from the crystal and the X1 and X2 plane. Figure 49. Crystal Shield Layer 2 Figure 50 is the ground plane and shows a void underneath the crystal shield. Figure 50. Ground Plane (Layer 3) 72 Rev. 1.0 Si5345-44-42-RM Figure 51 is a power plane showing the clock output power supply traces. The void underneath the crystal shield is continued. Figure 51. Power Plane and Clock Output Power Supply Traces (Layer 4) Figure 52 shows layer 5 and the clock input traces. Similar to the clock output traces, they are routed to an inner layer and surrounded by ground to avoid crosstalk. Figure 52. Clock Input Traces (Layer 5) Rev. 1.0 73 Si5345-44-42-RM Figure 53 shows the bottom layer, which continues the void underneath the shield. Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue. PCB ground can be placed under the XTAL Ground shield (X1/X2) as long as the PCB ground is at least 0.05 inches below it. Figure 53. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) For any high-speed, low-jitter application, the clock signal runs should be impedance-controlled to 100 differential or 50 single-ended. Differential signaling is preferred because of its increased immunity to commonmode noise. All clock I/O runs should be properly terminated. 74 Rev. 1.0 Si5345-44-42-RM 13. Power Management 13.1. Power Management Features Several unused functions can be powered down to minimize power consumption. The registers listed in Table 40 are used for powering down different features. Table 40. Power-Down Registers Register Name Hex Address [Bit Field] Function Si5345 Si5344 Si5342 PDN 0x001E[0] 0x001E[0] 0x001E[0] This bit allows the device to be powered down. The serial interface remains powered. OUT0_PDN 0x0108[0] 0x0112[0] 0x0112[0] Powers down all unused clock outputs. OUT1_PDN 0x010D[0] 0x0117[0] 0x0117[0] OUT2_PDN 0x0112[0] 0x0126[0] OUT3_PDN 0x0117[0] 0x012B[0] OUT4_PDN 0x011C[0] OUT5_PDN 0x0121[0] OUT6_PDN 0x0126[0] OUT7_PDN 0x012B[0] OUT8_PDN 0x0130[0] OUT9_PDN 0x0135[0] OUT_PDN_ALL 0x0145[0] XAXB_EXTCLK_EN 0x090E[1] 0x0145[0] 0x0145[0] Power down all outputs 0 to use a crystal at the XAXB pins, 1 to use an external clock source at the XAXB pins Rev. 1.0 75 Si5345-44-42-RM 13.2. Power Supply Recommendations The power supply filtering generally is important for optimal timing performance. The Si5345/44/42 devices have multiple stages of on-chip regulation to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will further minimize signal degradation from the power supply. It is recommended to use a 0402 1 µF ceramic capacitor on each power supply pin for optimal performance. If the supply voltage is extremely noisy, it might be necessary to use a ferrite bead in series between the supply voltage and the power supply pin. 13.3. Power Supply Sequencing Four classes of supply voltages exist on the Si5345/44/42: 1. VDD = 1.8 V (Core digital supply) 2. VDDA = 3.3 V (Analog supply) 3. VDDOx = 1.8/2.5/3.3 V ± 5% (Clock output supply) 4. VDDS = 1.8/3.3 V ± 5% (Digital I/O supply) There is no requirement for power supply sequencing unless the output clocks are required to be phase aligned with each other. In this case, the VDDO of each clock which needs to be aligned must be powered up before VDD and VDDA. VDDS has no effect on output clock alignment. If output-to-output alignment is required for applications where it is not possible to properly sequence the power supplies, then the output clocks can be aligned by asserting the SOFT_RST 0x001C[0] or Hard Reset 0x001E[1] register bits or driving the RSTB pin. Note that using a hard reset will reload the register with the contents of the NVM and any unsaved changes will be lost. 13.4. Grounding Vias The pad on the bottom of the device functions as both the sole electrical ground and primary heat transfer path. Hence it is important to minimize the inductance and maximize the heat transfer from this pad to the internal ground plane of the PCB. Use no fewer than 25 vias from the center pad to a ground plane under the device. In general, more vias will perform better. Having the ground plane near the top layer will also help to minimize the via inductance from the device to ground and maximize the heat transfer away from the device. 76 Rev. 1.0 Si5345-44-42-RM 14. Register Map 14.1. Base vs. Factory Preprogrammed Devices The Si5345/44/42 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”) versions. 14.1.1. “Base” Devices (a.k.a. “Blank” Devices) Example “base” orderable part numbers (OPNs) are of the form “Si5345A-A-GM” or “Si5344B-A-GM”. devices are available for applications where volatile reads and writes are used to program and configure the device for a particular application. Base devices do not power up in a usable state (all output clocks are disabled). Base devices are, however, configured by default to use a 48 MHz crystal on the XAXB reference and a 1.8 V compatible I/O voltage setting for the host I2C/SPI interface. Additional programming of a base device is mandatory to achieve a usable configuration. See the on-line lookup utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/ clockbuilder-lookup.aspx to access the default configuration plan and register settings for any base OPN. Base 14.1.2. “Factory Preprogrammed” (Custom OPN) Devices Factory preprogammed devices use a “custom OPN”, such as Si5345A-A-xxxxx-GM, where xxxxx is a sequence of characters assigned by Silicon Labs for each customer-specific configuration. These characters are referred to as the “OPN ID”. Customers must initiate custom OPN creation using the ClockBuilder Pro software. Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the XAXB reference frequency/type, the clock input frequencies, the clock output frequencies, as well as the other options, such as automatic clock selection, loop BW, etc. The ClockBuilder software is required to select among all of these options and to produce a project file which Silicon Labs uses to preprogram all devices with custom orderable part number (“custom OPN”). Custom OPN devices contain all of the initialization information in their non-volatile memory (NVM) so that it powers up fully configured and ready to go. Because preprogrammed device applications are inherently quite different from one another, the default power up values of the register settings can be determined using the custom OPN utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clockbuilder-lookup.aspx. Custom OPN devices include a device top mark which includes the unique OPN ID. Refer to the device data sheet's Ordering Guide and Top Mark sections for more details. Both “base” and “factory preprogrammed” devices can have their operating configurations changed at any time using volatile reads and writes to the registers. Both types of devices can also have their current register configuration written to the NVM by executing an NVM bank burn sequence (see "4.3. NVM Programming" on page 16.) Rev. 1.0 77 Si5345-44-42-RM 14.2. Register Map Overview and Default Settings Values The Si5345/44/42 family has a large register map and is divided into separate pages. Each page contains a total of 256 registers, although all 256 registers are not used. Register 1 on each page is reserved to indicate the page and register 0x00FE is reserved for the device ready status. The following is a summary of the content that can be found on each of the pages. Note any page that is not listed is not used for the device. Do not attempt to write to registers that have not been described in this document, even if they are accessible. Note that the default value will depend on the values loaded into NVM, which is determined by the part number. Where not provided in the register map information below, you can get the default values of the regiister map settings by accessing the part number lookup utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clockbuilder-lookup.aspx Register map settings values are listed in the datasheet addendum, which can also be accessed by using the link above.The register maps are broken out for the Si5345, Si5344, and Si5342 separately. Table 41. Register Map Paging Descriptions Page Start Address (Hex) Start Address (Decimal) Contents Page 0 0000h 0 Page 1 0100h 256 Clock output configuration Page 2 0200h 512 P,R dividers, scratch area Page 3 0300h 768 Output N dividers, N divider Finc/Fdec Page 4 0400h 1024 ZD mode configuration Page 5 0500h 1280 M divider, BW, holdover, input switch, FINC/DEC Page 9 0900h 2304 Control IO configuration Alarms, interrupts, reset, other configuration R = Read Only R/W = Read Write S = Self Clearing Registers that are sticky are cleared by writing “0” to the bits that have been set in hardware. A self-clearing bit will clear on its own when the state has changed. 78 Rev. 1.0 Si5345 Si5345-44-42-RM 14.3. Si5345 Register Map 14.3.1. Page 0 Registers Si5345 Register 0x0000 Die Rev Reg Address Bit Field Type Name 0x0000 3:0 R DIE_REV Reg Address Bit Field Type Name 0x0001 7:0 R/W PAGE Description 4- bit Die Revision Number Register 0x0001 Page Description Selects one of 256 possible pages. There is the “Page Register” which i s located at address 0x01 on every page. When read, it will indicate the current page. When written, it will change the page to the value entered. There is a page register at address 0x0001, 0x0101, 0x0201, 0x0301, … etc. Register 0x0002–0x0003 Base Part Number Reg Address Bit Field Type Name Value Description 0x0002 7:0 R PN_BASE 0x45 0x0003 15:8 R PN_BASE 0x53 Four-digit “base” part number, one nibble per digit Example: Si5345A-A-GM. The base part number (OPN) is 5345, which is stored in this register Refer to the device data sheet Ordering Guide section for more information about device grades. Register 0x0004 Device Grade Reg Address Bit Field Type Name 0x0004 7:0 R GRADE Description One ASCII character indicating the device speed/synthesis mode 0=A 1=B 2=C 3=D Rev. 1.0 79 Si5345 Si5345-44-42-RM Register 0x0005 Device Revision Reg Address Bit Field Type 0x0005 7:0 R Name Description DEVICE_REV One ASCII character indicating the device revision level. 0 = A; 1 = B, etc. Example Si5345C-A12345-GM, the device revision is “A” and stored as 0 Register 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3:0 R/W TOOL_VERSION[3:0] Special 0x0006 7:4 R/W TOOL_VERSION[7:4] Revision 0x0007 7:0 R/W TOOL_VERSION[15:8] Minor[7:0] 0x0008 0 R/W TOOL_VERSION[15:8] Minor[8] 0x0008 4:1 R/W TOOL_VERSION[16] 0x0008 7:5 R/W TOOL_VERSION[13:17] Major Tool. 0 for ClockBuilder Pro The software tool version that created the register values that are downloaded at power up is represented by TOOL_VERSION. Register 0x0009 Temperature Grade Reg Address Bit Field 0x0009 7:0 Type Name TEMP_GRADE Description Device temperature grading 0 = Industrial (-40° C to 85° C) ambient conditions Register 0x000A Package ID 80 Reg Address Bit Field 0x000A 7:0 Type Name PKG_ID Rev. 1.0 Description Package ID 0 = 9x9 mm 64 QFN Si5345 Si5345-44-42-RM Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5345C-A12345-GM. Applies to a “base” or “blank” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5345C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5345 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Register 0x000B I2C Address Reg Address Bit Field Type Setting Name Description 0x000B 6:2 R/W I2C_ADDR The upper 5 bits of the 7 bit I2C address. The lower 2 bits are controlled by the A1 and A0 pins. Register 0x000B I2C Address Reg Address Bit Field Type Setting Name 0x000B 6:2 R/W I2C_ADDR Description The upper 5 bits of the 7 bit I2C address. The lower 2 bits are controlled by the A1 and A0 pins. Register 0x000C Internal Status Bits Reg Address Bit Field Type Name 0x000C 0 R SYSINCAL 1 if the device is calibrating. 0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins. 0x000C 2 R 0x000C 3 R 0x000C 4 R 0x000C 5 R SMBUS_TIMEOUT Description 1 if there is an SMBus timeout error. Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Rev. 1.0 81 Si5345 Si5345-44-42-RM Register 0x000D Out-of-Frequency (OOF) and Loss-of Signal (LOS) Alarms Reg Address Bit Field Type Name Description 0x000D 3:0 R LOS 1 if the clock input is currently LOS 0x000D 7:4 R OOF 1 if the clock input is currently OOF Note that each bit corresponds to the input. The LOS and OOF bits are not sticky. Input 0 (IN0) corresponds to LOS 0x000D [0], OOF 0x000D [4] Input 1 (IN1) corresponds to LOS 0x000D [1], OOF 0x000D [5] Input 2 (IN2) corresponds to LOS 0x000D [2], OOF 0x000D [6] Input 3 (IN3) corresponds to LOS 0x000D [3], OOF 0x000D [7] Register 0x000E Holdover and LOL Status Reg Address Bit Field Type Name 0x000E 1 R LOL 0x000E 5 R HOLD Description 1 if the DSPLL is out of lock 1 if the DSPLL is in holdover (or free run) These status bits indicate if the DSPLL is in holdover and if it is in Loss of Lock. These bits are not sticky. Register 0x000F Calibration Status Reg Address Bit Field Type Name 0x000F 5 R CAL_PLL Description 1 if the DSPLL internal calibration is busy This status bit indicates if a DSPLL is currently busy with calibration. This bit is not sticky. Register 0x0011 Internal Error Flags Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL. Write a 0 to this bit to clear. 0x0011 1 R LOSXAXB_FLG Sticky version of LOSXAXB. Write a 0 to this bit to clear. 0x0011 2 R — 0x0011 3 R — 0x0011 4 R 0x0011 5 R SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT. Write a 0 to this bit to clear. If any of these six bits are high, there is an internal fault. Please contact Silicon Labs. These are sticky flag bits. They are cleared by writing zero to the bit that has been set. 82 Rev. 1.0 Si5345 Si5345-44-42-RM Register 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field Type Name Description 0x0012 3:0 R/W LOS_FLG 1 if the clock input is LOS for the given input 0x0012 7:4 R/W OOF_FLG 1 if the clock input is OOF for the given input These are the sticky flag versions of register 0x000D. These bits are cleared by writing 0 to the bits that have been set. Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012 [4] Input 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012 [5] Input 2 (IN2) corresponds to LOS_FLG 0x0012 [2], OOF_FLG 0x0012 [6] Input 3 (IN3) corresponds to LOS_FLG 0x0012 [3], OOF_FLG 0x0012 [7] Register 0x0013 Sticky Holdover and LOL Flags Reg Address Bit Field Type Name 0x0013 1 R/W LOL_FLG 0x0013 5 R/W HOLD_FLG Description 1 if the DSPLL was unlocked 1 if the DSPLL was in holdover or free run These are the sticky flag versions of register 0x000E. These bits are cleared by writing 0 to the bits that have been set. Register 0x0014 Sticky PLL In Calibration Flag Reg Address Bit Field Type Name 0x0014 5 R/W CAL_PLL_FLG Description 1 if the internal calibration was busy This bit is the sticky flag version of 0x000F. This bit is cleared by writing 0 to bit 5. Register 0x0017 Status Flag Masks Reg Address Bit Field Type Name Description 0x0017 0 R/W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R/W LOSXAXB_FLG_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 2 R/W 0x0017 3 R/W 0x0017 4 R/W 0x0017 5 R/W SMBUS_TIMEOUT_ FLG_MSK Rev. 1.0 1 to mask SMBUS_TIMEOUT_FLG from the interrupt 83 Si5345 Si5345-44-42-RM These are the interrupt mask bits for the fault flags in register 0x0011. If a mask bit is set, the alarm will be blocked from causing an interrupt. Note: Bit 1 corresponds to XAXB LOS from asserting the interrupt (INTR) pin. Register 0x0018 OOF and LOS Masks Reg Address Bit Field Type Name Description 0x0018 3:0 R/W LOS_INTR_MSK 1 to mask the clock input LOS flag 0x0018 7:4 R/W OOF_INTR_MSK 1 to mask the clock input OOF flag These are the interrupt mask bits for the OOF and LOS flags in register 0x0012. Input 0 (IN0) corresponds to LOS_INTR_MSK 0x0018 [0], OOF_INTR_MSK 0x0018 [4] Input 1 (IN1) corresponds to LOS_INTR_MSK 0x0018 [1], OOF_INTR_MSK 0x0018 [5] Input 2 (IN2) corresponds to LOS_INTR_MSK 0x0018 [2], OOF_INTR_MSK 0x0018 [6] Input 3 (IN3) corresponds to LOS_INTR_MSK 0x0018 [3], OOF_INTR_MSK 0x0018 [7] Register 0x0019 Holdover and LOL Masks Reg Address Bit Field Type Name Description 0x0019 1 R/W LOL_INTR_MSK 0x0019 5 R/W HOLD_INTR_MSK 1 to mask the clock input LOL flag 1 to mask the holdover flag These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set the alarm will be blocked from causing an interrupt. Register 0x001A PLL In Calibration Interrupt Mask Reg Address Bit Field Type Name 0x001A 5 R/W CAL_INTR_MSK Description 1 to mask the DSPLL internal calibration busy flag The interrupt mask for this bit flag bit corresponds to register 0x0014. Register 0x001C Soft Reset and Calibration Reg Address Bit Field Type Name 0x001C 0 S SOFT_RST These bits are of type “S”, which is self-clearing. 84 Rev. 1.0 Description 1 Initialize and calibrates the entire device 0 No effect Si5345 Si5345-44-42-RM Register 0x001D FINC, FDEC Reg Address Bit Field Type Name Description 0x001D 0 S FINC 1 a rising edge will cause the selected MultiSynth to increment the output frequency by the FSTEPW parameter. See registers 0x0339–0x0358 0x001D 1 S FDEC 1 a rising edge will cause the selected MultiSynth to decrement the output frequency by the FSTEPW parameter. See registers 0x0339–0x0358 Figure 54 shows the logic for the FINC, FDEC bits. FINC, 1Dh[0] (self clear) FDEC is the same as FINC FINC pin, pos edge trig NxFINC N_FSTEP_MSKx, 339h[4:0] Figure 54. FINC, FDEC Logic Diagram Register 0x001E Sync, Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 0 R/W PDN 0x001E 1 S HARD_RST 0x001E 2 S SYNC 1 to put the device into low power mode 1 causes hard reset. The same as power up except that the serial port access is not held at reset. This does not self-clear, so after setting the bit it must be cleared. 0 No reset Logically equivalent to asserting the SYNC pin. Resets all R dividers to the same state. Register 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Name 0x002B 3 R/W SPI_3WIRE Rev. 1.0 Description 0 for 4-wire SPI, 1 for 3-wire SPI 85 Si5345 Si5345-44-42-RM Register 0x002C LOS Enable Reg Address Bit Field Type Name 0x002C 3:0 R/W LOS_EN Description 1 to enable LOS for a clock input; 0 for disable Input 0 (IN0): LOS_EN[0] Input 1 (IN1): LOS_EN[1] Input 2 (IN2): LOS_EN[2] Input 3 (IN3): LOS_EN[3] Register 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Name Description 0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above 0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above 0x002D 7:6 R/W LOS3_VAL_TIME Clock Input 3, same as above When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME. Register 0x002E-0x002F LOS0 Trigger Threshold Reg Address Bit Field Type Name 0x002E 7:0 R/W LOS0_TRG_THR 0x002F 15:8 R/W LOS0_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan. Register 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name 0x0030 7:0 R/W LOS1_TRG_THR 0x0031 15:8 R/W LOS1_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan. 86 Rev. 1.0 Si5345 Si5345-44-42-RM Register 0x0032-0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type Name 0x0032 7:0 R/W LOS2_TRG_THR 0x0033 15:8 R/W LOS2_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency plan. Register 0x0034-0x0035 LOS3 Trigger Threshold Reg Address Bit Field Type Name 0x0034 7:0 R/W LOS3_TRG_THR 0x0035 15:8 R/W LOS3_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3, given a particular frequency plan. Register 0x0036-0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Name 0x0036 7:0 R/W LOS0_CLR_THR 0x0037 15:8 R/W LOS0_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan. Register 0x0038-0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name 0x0038 7:0 R/W LOS1_CLR_THR 0x0039 15:8 R/W LOS1_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan. Register 0x003A-0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name 0x003A 7:0 R/W LOS2_CLR_THR 0x003B 15:8 R/W LOS2_CLR_THR Rev. 1.0 Description 16-bit Threshold Value 87 Si5345 Si5345-44-42-RM ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan. Register 0x003C-0x003D LOS3 Clear Threshold Reg Address Bit Field Type Name 0x003C 7:0 R/W LOS3_CLR_THR 0x003D 15:8 R/W LOS3_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan. Register 0x003F OOF Enable Reg Address Bit Field Type Name Description 0x003F 3:0 R/W OOF_EN 1 to enable, 0 to disable 0x003F 7:4 R/W FAST_OOF_EN 1 to enable, 0 to disable Input 0 corresponds to OOF_EN [0], FAST_OOF_EN [4] 1 corresponds to OOF_EN [1], FAST_OOF_EN [5] Input 2 corresponds to OOF_EN [2], FAST_OOF_EN [6] Input 3 corresponds to OOF_EN [3], FAST_OOF_EN [7] Input Register 0x0040 OOF Reference Select 88 Reg Address Bit Field Type Name 0x0040 2:0 R/W OOF_REF_SEL Rev. 1.0 Description 0 for CLKIN0 1 for CLKIN1 2 for CLKIN2 3 for CLKIN3 4 for XAXB Si5345 Si5345-44-42-RM Register 0x0046-0x0049 Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0046 7:0 R/W OOF0_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0047 7:0 R/W OOF1_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0048 7:0 R/W OOF2_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0049 7:0 R/W OOF3_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. Register 0x004A-0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x004A 7:0 R/W OOF0_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004B 7:0 R/W OOF1_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004C 7:0 R/W OOF2_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004D 7:0 R/W OOF3_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. ClockBuilder Pro is used to determine the values for these registers. Rev. 1.0 89 Si5345 Si5345-44-42-RM Register 0x0051-0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 7:0 R/W FAST_OOF0_SET_THR (1+ value) x 1000 ppm 0x0052 7:0 R/W FAST_OOF1_SET_THR (1+ value) x 1000 ppm 0x0053 7:0 R/W FAST_OOF2_SET_THR (1+ value) x 1000 ppm 0x0054 7:0 R/W FAST_OOF3_SET_THR (1+ value) x 1000 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers. Register 0x0055-0x0058 Fast Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x0055 7:0 R/W FAST_OOF0_CLR_THR (1+ value) x 1000 ppm 0x0056 7:0 R/W FAST_OOF1_CLR_THR (1+ value) x 1000 ppm 0x0057 7:0 R/W FAST_OOF2_CLR_THR (1+ value) x 1000 ppm 0x0058 7:0 R/W FAST_OOF3_CLR_THR (1+ value) x 1000 ppm These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers. OOF needs a frequency reference. ClockBuilder Pro provides the OOF register values for a particular frequency plan. Register 0x009A LOL Enable Reg Address Bit Field Type 0x009A 1 R/W Name Description LOL_SLW_EN_PLL 1 to enable LOL; 0 to disable LOL. ClockBuilder Pro provides the LOL register values for a particular frequency plan. Register 0x009E LOL Set Threshold 90 Reg Address Bit Field Type Name Description 0x009E 7:4 R/W LOL_SET_THR Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,20000. Values are in ppm. Rev. 1.0 Si5345 Si5345-44-42-RM The following are the thresholds for the value that is placed in the top four bits of register 0x009E. 0 = 0.2 ppm = 0.6 ppm 2 = 2 ppm 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm 1 Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name 0x00A0 7:4 R/W LOL_CLR_THR Description Configures the loss of lock clear thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values in ppm. The following are the thresholds for the value that is placed in the top four bits of register 0x00A0. ClockBuilder Pro™ sets these values. 0 = 0.2 ppm = 0.6 ppm 2 = 2 ppm 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm 1 Register 0x00A2 LOL Timer Enable Reg Address Bit Field Type Name 0x00A2 1 R/W LOL_TIMER_EN Description 0 to disable 1 to enable LOL_TIMER_EN extends the time after LOL negates that the clock outputs can be disabled by LOL_CLR_DELAY (see below). Rev. 1.0 91 Si5345 Si5345-44-42-RM Register 0x00A8-0x00AC LOL Clear Delay Reg Address Bit Field Type Name 0x00A8 7:0 R/W LOL_CLR_DELAY 0x00A9 15:8 R/W LOL_CLR_DELAY 0x00AA 23:16 R/W LOL_CLR_DELAY 0x00AB 31:24 R/W LOL_CLR_DELAY 0x00AC 34:32 R/W LOL_CLR_DELAY Description 35-bit value The LOL Clear Delay value is set by ClockBuilder Pro. Register 0x00E2 Reg Address Bit Field Type Name Description 0x00E2 7:0 R Reg Address Bit Field Type Name Description 0x00E3 7:0 R/W NVM_WRITE Write 0xC7 to initiate an NVM bank burn. Description ACTIVE_NVM_BANK Read-only field indicating number of user bank writes carried out so far. Value Description 0 zero 3 one 15 two 63 three Register 0x00E3 See "4.3. NVM Programming" on page 16. Register 0x00E4 Reg Address Bit Field Type Name 0x00E4 0 S NVM_READ_BANK When set, this bit will read the NVM down into the volatile memory. 92 Rev. 1.0 1 to download NVM. Si5345 Si5345-44-42-RM Register 0x00FE Device Ready Reg Address Bit Field Type Name 0x00FE 7:0 R DEVICE_READY Description 0x0F when device is ready 0xF3 when device is not ready Read-only byte to indicate when the device is ready to accept serial bus writes. The user can poll this byte starting at power-on; when DEVICE_READY is 0x0F the user can safely read or write to any other register. This is only needed after power up after a hard reset using register bit 0x001E[1] or during a bank burn (register 0x0E3). The “Device Ready” register is available on every page in the device at the second last register, 0xFE. There is a device ready register at 0x00FE, 0x01FE, 0x02FE, … etc. Rev. 1.0 93 Si5345 Si5345-44-42-RM 14.3.2. Page 1 Registers Si5345 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 0 R/W OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0108 Clock Output Driver 0 and R-Divider 0 Configuration Reg Address Bit Field Type Name Description 0x0108 0 R/W OUT0_PDN Output driver 0: 0 to power up the regulator, 1 to power down the regulator. Clock outputs will be weakly pulled-low. 0x0108 1 R/W OUT0_OE Output driver 0: 0 to disable the output, 1 to enable the output 0x0108 2 R/W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0109 Output 0 Format Reg Address Bit Field Type Name 0x0109 2:0 R/W OUT0_FORMAT 0 Reserved 1 swing mode (normal swing) differential 2 swing mode (high swing) differential 3 rail to rail swing mode differential 4 LVCMOS single ended 5–7 reserved 0x0109 3 R/W OUT0_SYNC_EN 0 disable 1 enable enable/disable synchronized (glitchless) operation. When enabled, the power down and output enables are synchronized to the output clock. 0x0109 5:4 R/W OUT0_DIS_STATE Determines the state of an output driver when disabled, selectable as Disable low (0), Disable high (1), High impedance. (2) In high-impedance mode the output common mode voltage will be the same when the output is disabled as when the output is enabled. 0x0109 7:6 R/W OUT0_CMOS_DRV LVCMOS output impedance. Selectable as CMOS1,CMOS2, CMOS3. See "6.2. Performance Guidelines for Outputs" on page 32. 94 Rev. 1.0 Description Si5345 Si5345-44-42-RM Register 0x010A Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x010A 3:0 R/W OUT0_CM This field only applies when OUT0_FORMAT=1 or 2. See Table 24, “Settings for LVDS, LVPECL, and HCSL,” on page 39 and " Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes" on page 180 for details of the settings. 0x010A 6:4 R/W OUT0_AMPL This field only applies when OUT0_FORMAT=1, 2, or 3. See Table 11, “Hitless Switching Enable Bit,” on page 22 and Appendix A for details of the settings. See the settings and values from Table 24 for details of the settings. ClockBuilder Pro is used to select the correct settings for this register. Register 0x010B R-Divider 0 Mux Selection Reg Address Bit Field Type Name 0x010B 2:0 R/W OUT0_MUX_SEL 0x010B 7:6 R/W OUT0_INV Description Output driver 0 input mux select.This selects the source of the multisynth. 0: N0 1: N1 2: N2 3: N3 4: N4 5: reserved 6: reserved 7: reserved CLK and CLK not inverted CLK inverted CLK and CLK inverted CLK inverted Each output can be configured to use Multisynth N0-N4 divider. The frequency for each N-divider is set in registers 0x0302–0x0337 for N0 to N4. Five different frequencies can be set in the N-dividers (N0–N4) and each of the 10 outputs can be configured to any of the five different frequencies. The 10 output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other 9 output drivers. Table 42. Registers that Follow the Same Definitions Above Register Address Description (Same as) Address 0x010D Clock Output Driver 1 Config 0x0108 0x010E Clock Output Driver 1 Format, Sync 0x0109 0x010F Clock Output Driver 1 Ampl, CM 0x010A 0x0110 OUT1_MUX_SEL, OUT1_INV 0x010B Rev. 1.0 95 Si5345 Si5345-44-42-RM Table 42. Registers that Follow the Same Definitions Above (Continued) 0x0112 Clock Output Driver 2 Config 0x0108 0x0113 Clock Output Driver 2 Format, Sync 0x0109 0x0114 Clock Output Driver 2 Ampl, CM 0x010A 0x0115 OUT2_MUX_SEL, OUT2_INV 0x010B 0x0117 Clock Output Driver 3 Config 0x0108 0x0118 Clock Output Driver 3 Format, Sync 0x0109 0x0119 Clock Output Driver 3 Ampl, CM 0x010A 0x011A OUT3_MUX_SEL, OUT3_INV 0x010B 0x011C Clock Output Driver 4 Config 0x0108 0x011D Clock Output Driver 4 Format, Sync 0x010A 0x011E Clock Output Driver 4 Ampl, CM 0x0105 0x011F OUT4_MUX_SEL, OUT4_INV 0x010B 0x0121 Clock Output Driver 5 Config 0x0108 0x0122 Clock Output Driver 5 Format, Sync 0x0109 0x0123 Clock Output Driver 5 Ampl, CM 0x010A 0x0124 OUT5_MUX_SEL, OUT5_INV 0x010B 0x0126 Clock Output Driver 6 Config 0x0108 0x0127 Clock Output Driver 6 Format, Sync 0x0109 0x0128 Clock Output Driver 6 Ampl, CM 0x010A 0x0129 OUT6_MUX_SEL, OUT6_INV 0x010B 0x012B Clock Output Driver 7 Config 0x0108 0x012C Clock Output Driver 7 Format, Sync 0x0109 0x012D Clock Output Driver 7 Ampl, CM 0x010A 0x012E OUT7_MUX_SEL, OUT7_INV 0x010B 0x0130 Clock Output Driver 8 Config 0x0108 0x0131 Clock Output Driver 8 Format, Sync 0x0109 0x0132 Clock Output Driver 8 Ampl, CM 0x010A 0x0133 OUT8_MUX_SEL, OUT8_INV 0x010B 0x013A Clock Output Driver 9 Config 0x0108 0x013B Clock Output Driver 9 Format, Sync 0x0109 0x013C Clock Output Driver 9 Ampl, CM 0x010A 0x013D OUT9_MUX_SEL, OUT9_INV 0x010B Register 0x0145 Power Down All 96 Reg Address Bit Field Type Name 0x0145 0 R/W OUT_PDN_ALL Rev. 1.0 Description 0- no effect 1- all drivers powered down Si5345 Si5345-44-42-RM 14.3.3. Page 2 Registers Si5345 Register 0x0202-0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name 0x0202 7:0 R/W XAXB_FREQ_OFFSET 0x0203 15:8 R/W XAXB_FREQ_OFFSET 0x0204 23:16 R/W XAXB_FREQ_OFFSET 0x0205 31:24 R/W XAXB_FREQ_OFFSET Description 32 bit offset adjustment The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The XAXB_FREQ_OFFSET word is used to adjust this frequency reference with high resolution. XAXB_FREQ_OFFSET can be used to compensate for the XTAL frequency error. This will cause the free run frequency to be more accurate. It is programmed as a two’s complement number. This register can be used to adjust the frequency of the VCO when it is locked to the XAXB frequency. ClockBuilder Pro calculates the correct values for these registers. Register 0x0206 Pre-scale Reference Divide Ratio Reg Address Bit Field Type Name 0x0206 1:0 R/W PXAXB Description Sets the prescale divider for the input clock on XAXB. 0 = pre-scale value 1 = pre-scale value 2 2 = pre-scale value 4 3 = pre-scale value 8 This can only be used with external clock sources, not crystals. 1 Register 0x0208-0x020D P0 Divider Numerator Reg Address 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D Bit Field 7:0 15:8 23:16 31:24 39:32 47:40 Type R/W R/W R/W R/W R/W R/W Name P0_NUM P0_NUM P0_NUM P0_NUM P0_NUM P0_NUM Description 48-bit Integer Number This set of registers configures the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers. Rev. 1.0 97 Si5345 Si5345-44-42-RM Register 0x020E-0x0211 P0 Divider Denominator Reg Address Bit Field Type Name 0x020E 7:0 R/W P0_DEN 0x020F 15:8 R/W P0_DEN 0x0210 23:16 R/W P0_DEN 0x0211 31:24 R/W P0_DEN Description 32-bit Integer Number The P1, P2 and P3 divider numerator and denominator follow the same format as P0 described above. ClockBuilder Pro calculates the correct values for the P-dividers. Table 43. Registers that Follow the P0_NUM and P0_DEN Above Register Address Description Size Same as Address 0x0212-0x0217 P1 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0218-0x021B P1 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x021C-0x0221 P2 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0222-0x0225 P2 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x0226-0x022B P3 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3 Divider Denominator 32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers. The Px_Update bit (register 0x0230) for the appropriate channel must be updated for the new P value to take affect. Register 0x0230 Px_UPDATE Reg Address Bit Field Type Name 0x0230 0 S, R/W P0_UPDATE 0x0230 1 S, R/W P1_UPDATE 0x0230 2 S, R/W P2_UPDATE 0x0230 3 S, R/W P3_UPDATE Description 0 - No update for P-divider value 1 - Update P-divider value The Px_Update bit must be asserted to update the P-Divider. The update bits are provided so that all of the divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. 98 Rev. 1.0 Si5345 Si5345-44-42-RM Register 0x024A-0x024C R0 Divider Reg Address Bit Field Type Name 0x024A 7:0 R/W R0_REG 0x024B 15:8 R/W R0_REG 0x024C 23:16 R/W R0_REG Description A 24 bit integer output divider divide value = (R0_REG+1) x 2 To set R0 = 2, set OUT0_RDIV_FORCE2 = 1 and then the R0_REG value is irrelevant. The R dividers are at the output clocks and are purely integer division. The R1–R9 dividers follow the same format as the R0 divider described above. Table 44. Registers that Follow the R0_REG Register Address Description Size Same as Address 0x024D-0x024F R1_REG 24-bit Integer Number 0x024A-0x024C 0x0250-0x0252 R2_REG 24-bit Integer Number 0x024A-0x024C 0x0253-0x0255 R3_REG 24-bit Integer Number 0x024A-0x024C 0x0256-0x0258 R4_REG 24-bit Integer Number 0x024A-0x024C 0x0259-0x025B R5_REG 24-bit Integer Number 0x024A-0x024C 0x025C-0x025E R6_REG 24-bit Integer Number 0x024A-0x024C 0x025F-0x0261 R7_REG 24-bit Integer Number 0x024A-0x024C 0x0262-0x0264 R8_REG 24-bit Integer Number 0x024A-0x024C 0x0268-0x026A R9_REG 24-bit Integer Number 0x024A-0x024C Register 0x026B–0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B 7:0 R/W DESIGN_ID0 0x026C 15:8 R/W DESIGN_ID1 0x026D 23:16 R/W DESIGN_ID2 0x026E 31:24 R/W DESIGN_ID3 0x026F 39:32 R/W DESIGN_ID4 0x0270 47:40 R/W DESIGN_ID5 0x0271 55:48 R/W DESIGN_ID6 0x0272 63:56 R/W DESIGN_ID7 ASCII encoded string defined by CBPro user, with user defined space or null padding of unused characters. A user will normally include a configuration ID + revision ID. For example, “ULT.1A” with null character padding sets: DESIGN_ID0: 0x55 DESIGN_ID1: 0x4C DESIGN_ID2: 0x54 DESIGN_ID3: 0x2E DESIGN_ID4: 0x31 DESIGN_ID5: 0x41 DESIGN_ID6:0x 00 DESIGN_ID7: 0x00 Rev. 1.0 99 Si5345 Si5345-44-42-RM Register 0x0278–0x027C OPN Identifier Reg Address Bit Field Type Name 0x0278 7:0 R/W OPN_ID0 0x0279 15:8 R/W OPN_ID1 0x027A 23:16 R/W OPN_ID2 0x027B 31:24 R/W OPN_ID3 0x027C 39:32 R/W OPN_ID4 Description OPN unique identifier. ASCII encoded. For example, with OPN: 5380C-A12345-GM, 12345 is the OPN unique identifier, which sets: OPN_ID0: 0x31 OPN_ID1: 0x32 OPN_ID2: 0x33 OPN_ID3: 0x34 OPN_ID4: 0x35 Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5345C-A12345-GM. Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5345C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5345 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. 100 Rev. 1.0 Si5345 Si5345-44-42-RM 14.3.4. Page 3 Registers Si5345 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name 0x0302 7:0 R/W N0_NUM 0x0303 15:8 R/W N0_NUM 0x0304 23:16 R/W N0_NUM 0x0305 31:24 R/W N0_NUM 0x0306 39:32 R/W N0_NUM 0x0307 43:40 R/W N0_NUM Description 48-bit Integer Number The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder Pro calculates the correct values for the N-dividers. Register 0x0308-0x030B N0 Denominator Reg Address Bit Field Type Name 0x0308 7:0 R/W N0_DEN 0x0309 15:8 R/W N0_DEN 0x030A 23:16 R/W N0_DEN 0x030B 31:24 R/W N0_DEN 0x030C 0 R/W N0_UPDATE Description 32-bit Integer Number Set this bit to update the N0 divider. This bit is provided so that all of the N0 divider bits can be changed at the same time. First, write all of the new values to the divider; then, set the update bit. Rev. 1.0 101 Si5345 Si5345-44-42-RM Table 45. Registers that Follow the N0_NUM and N0_DEN Definitions Register Address Description Size Same as Address 0x030D-0x0312 N1 Numerator 44-bit Integer Number 0x0302-0x0307 0x0313-0x0316 N1 Denominator 32-bit Integer Number 0x0308-0x030B 0x0317 N1_UPDATE one bit 0x030C 0x0318-0x031D N2 Numerator 44-bit Integer Number 0x0302-0x0307 0x031E-0x0321 N2 Denominator 32-bit Integer Number 0x0308-0x030B 0x0322 N2_UPDATE one bit 0x030C 0x0323-0x0328 N3 Numerator 44-bit Integer Number 0x0302-0x0307 0x0329-0x032C N3 Denominator 32-bit Integer Number 0x0308-0x030B 0x032D N3_UPDATE one bit 0x030C 0x032E-0x0333 N4 Numerator 44-bit Integer Number 0x0302-0x0307 0x0334-0x0337 N4 Denominator 32-bit Integer Number 0x0308-0x030B Register 0x0338 N4 and Global N Divider Update Reg Address Bit Field Type Name 0x0338 1 R/W N_UPDATE_ALL 0x0338 0 R/W N4_UPDATE Description Set this bit to update all five N dividers. Set this bit to update N4 divider. This bit is provided so that all of the divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Register 0x0339 FINC/FDEC Masks Reg Address Bit Field Type Name 0x0339 4:0 R/W N_FSTEP_MSK Bit Description 0 to enable FINC/FDEC updates 1 to disable FINC/FDEC updates 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0] 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1] Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339[2] Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339[3] Bit 4 corresponds to MultiSynth N4 N_FSTEP_MSK 0x0339[4] There is one mask bit for each of the five N dividers. Figure 55, “Logic Diagram of the FINC/FDEC Masks,” on page 103 shows the logic diagram of the FINC/FDEC masks. Bit 102 Rev. 1.0 Si5345 Si5345-44-42-RM FINC, 1Dh[0] (self clear) FDEC is the same as FINC FINC pin, pos edge trig NxFINC N_FSTEP_MSKx, 339h[4:0] Figure 55. Logic Diagram of the FINC/FDEC Masks Register 0x033B-0x0340 N0 Frequency Step Word Reg Address 0x033B 0x033C 0x033D 0x033E 0x033F 0x0340 Bit Field 7:0 15:8 23:16 31:24 39:32 43:40 Type R/W R/W R/W R/W R/W R/W Name N0_FSTEPW N0_FSTEPW N0_FSTEPW N0_ FSTEPW N0_ FSTEPW N0_ FSTEPW Description 44-bit Integer Number This is a 44-bit integer value which is directly added or subtracted from the N-divider when FINC or FDEC is set to a 1. ClockBuilder Pro calculates the correct values for the N0 Frequency Step Word. Each N divider has the ability to add or subtract up to a 44-bit value. Table 46. Registers that Follow the N0_FSTEPW Definitions Register Address Description Size Same as Address 0x0341-0x0346 N1 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 0x0347-0x034C N2 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 0x034D-0x0352 N3 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 0x0353-0x0358 N4 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 Register 0x0359–0x35A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 7:0 R/W N0_DELAY[7:0] Lower byte of N0_DELAY[15:0] 0x035A 15:8 R/W N0_DELAY[15:8] Upper byte of N0_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(215–1)/(256 x Fvco). ClockBuilder Pro calculates the correct value for this register. Changing any of the Nx_DELAY values requires a SOFT_RST, a HARD_RST, or a power up sequence. Rev. 1.0 103 Si5345 Si5345-44-42-RM Register 0x035B–0x035C Divider N1 Delay Control Reg Address Bit Field Type Name Description 0x035B 7:0 R/W N1_DELAY[7:0] Lower byte of N1_DELAY[15:0] 0x035C 15:8 R/W N1_DELAY[15:8] Upper byte of N1_DELAY[15:0] N1_DELAY behaves in the same manner as N0_DELAY Register 0x035D–0x035E Divider N2 Delay Control Reg Address Bit Field Type Name Description 0x035D 7:0 R/W N2_DELAY[7:0] Lower byte of N2_DELAY[15:0] 0x035E 15:8 R/W N2_DELAY[15:8] Upper byte of N2_DELAY[15:0] N2_DELAY behaves in the same manner as N0_DELAY Register 0x035F–0x0360 Divider N3 Delay Control Reg Address Bit Field Type Name Description 0x035F 7:0 R/W N3_DELAY[7:0] Lower byte of N3_DELAY[15:0] 0x0360 15:8 R/W N3_DELAY[15:8] Upper byte of N3_DELAY[15:0] N3_DELAY behaves in the same manner as N0_DELAY Register 0x0361–0x0362 Divider N4 Delay Control Reg Address Bit Field Type Name 0x0361 7:0 R/W N4_DELAY[7:0] Lower byte of N4_DELAY[15:0] 0x0362 15:8 R/W N4_DELAY[15:8] Upper byte of N4_DELAY[15:0] N4_DELAY behaves in the same manner as N0_DELAY 104 Rev. 1.0 Description Si5345 Si5345-44-42-RM 14.3.5. Page 4 Registers Si5345 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name 0x0487 0 R/W ZDM_EN 0x0487 2:1 R/W ZDM_IN_SEL Description 0 to disable ZD mode 1 to enable ZD mode Clock input select when in ZD. 0 for IN0, 1 for IN1,2 for IN2, 3 reserved This register is used for enabling the zero delay mode (ZDM) and selecting the source. The phase difference between the output, which is connected to the selected input below will be nulled to zero. When in zero delay mode, the DSPLL cannot have either hitless or automatic switching. In addition, the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins. Pin controlled clock selection is available in ZD mode (see register 0x052A). Rev. 1.0 105 Si5345 Si5345-44-42-RM 14.3.6. Page 5 Registers Si5345 Register 0x0507 Reg Address Bit Field Type Name 0x0507 7,6 R IN_ACTV Description Current input clock. These bits indicate which input clock is currently selected. 0 for IN0, 1 for IN1, etc. Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 7:0 R/W BW0_PLL PLL bandwidth parameter 0x0509 15:8 R/W BW1_PLL PLL bandwidth parameter 0x050A 23:16 R/W BW2_PLL PLL bandwidth parameter 0x050B 31:24 R/W BW3_PLL PLL bandwidth parameter 0x050C 39:32 R/W BW4_PLL PLL bandwidth parameter 0x050D 47:40 R/W BW5_PLL PLL bandwidth parameter This group of registers determine the loop bandwidth for the DSPLL. It is selectable as 0.1 Hz, 1 Hz, 4 Hz, 10 Hz, 40 Hz, 100 Hz, 400 Hz, 1 kHz, and 4 kHz. The loop BW values are calculated by ClockBuilder Pro and are written into these registers. The BW_UPDATE_PLL bit (reg 0x0514[0]) must be set to cause the BWx_PLL parameters to take effect. Register 0x050E-0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Description 0x050E 7:0 R/W FAST_BW0_PLL PLL fast bandwidth parameter 0x050F 15:8 R/W FAST_BW1_PLL PLL fast bandwidth parameter 0x0510 23:16 R/W FAST_BW2_PLL PLL fast bandwidth parameter 0x0511 31:24 R/W FAST_BW3_PLL PLL fast bandwidth parameter 0x0512 39:32 R/W FAST_BW4_PLL PLL fast bandwidth parameter 0x0513 47:40 R/W FAST_BW5_PLL PLL fast bandwidth parameter 0x0514 0 S BW_UPDATE_PLL Must be set to 1 to update the BWx_PLL and FAST_BWx_PLL parameters The fast lock loop BW values are calculated by ClockBuilder Pro and used when fast lock is enabled. 106 Rev. 1.0 Si5345 Si5345-44-42-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address 0x0515 0x0516 0x0517 0x0518 0x0519 0x051A 0x051B Bit Field 7:0 15:8 23:16 31:24 39:32 47:40 55:48 Type R/W R/W R/W R/W R/W R/W R/W Name M_NUM M_NUM M_NUM M_NUM M_NUM M_NUM M_NUM Description 56-bit Number Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address 0x051C 0x051E 0x051E 0x051F Bit Field 7:0 15:8 23:16 31:24 Type R/W R/W R/W R/W Name M_DEN M_DEN M_DEN M_DEN Description 32-bit Number The loop M divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers. Note that there is a /5 prescaler before the M divider (e.g., if the M_NUM/M_DEN divide ratio is 100, the effective feedback divide ratio will be 500). Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name 0x0520 0 R/W M_UPDATE Description Set this bit to update the M divider. Register 0x052A Input Clock Select Reg Address Bit Field Type Name 0x052A 0 R/W IN_SEL_REGCTRL 0x052A 2:1 R/W IN_SEL Description 0 for pin controlled clock selection 1 for register controlled clock selection 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection. Note: when ZDM_EN (0x0487, bit 0) and IN_SEL_REGCTRL are both high, IN_SEL does not do anything and the clock selection is pin controlled. When IN_SEL_REGCTRL is low, IN_SEL does not do anything and the clock selection is pin controlled. Rev. 1.0 107 Si5345 Si5345-44-42-RM Register 0x052B Fast Lock Control Reg Address Bit Field Type Name Description 0x052B 0 R/W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN = 0 (see below): 0 to enable auto fast lock when the DSPLL is out of lock. 1 to disable auto fast lock. 0x052B 1 R/W FASTLOCK_MAN 0 for normal operation (see above) 1 to force fast lock When in fast lock, the fast lock loop BW can be automatically used. Register 0x052C Holdover Exit Control Reg Address Bit Field Type Name 0x052C 3 R/W HOLD_RAMP_BYP 0x052C 4 R/W HOLD_EXIT_BW_SEL 108 Rev. 1.0 Description Must be set to 1 for normal operation. 0 to use the fastlock loop BW when exiting from holdover 1 to use the normal loop BW when exiting from holdover Si5345 Si5345-44-42-RM Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E 4:0 R/W HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x052F Holdover History Delay Reg Address Bit Field Type Name 0x052F 4:0 R/W HOLD_HIST_DELAY Description The most recent input frequency perturbations can be ignored during entry into holdover. The holdover logic pushes back into the past, above the averaging window. The amount that the average window is delayed is the holdover history delay. Register 0x0535 Force Holdover Reg Address Bit Field Type Name 0x0535 0 R/W FORCE_HOLD Description 0 for normal operation 1 for force holdover Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name 0x0536 1:0 R/W CLK_SWTCH_MODE 0x0536 2 R/W HSW_EN Rev. 1.0 Description 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase buildout turned on) 109 Si5345 Si5345-44-42-RM Register 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3:0 R/W IN_LOS_MSK For each clock input LOS alarm: 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7:4 R/W IN_OOF_MSK For each clock input OOF alarm: 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic This register is for the input clock switch alarm masks. For each of the four clock inputs, the OOF and/or the LOS alarms can be used for the clock selection logic or they can be masked from it. Note that the clock selection logic can affect entry into holdover. Register 0x0538 Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Name Description 0x0538 2:0 R/W IN0_PRIORITY The priority for clock input 0 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0538 6:4 R/W IN1_PRIORITY The priority for clock input 1 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3. 110 Rev. 1.0 Si5345 Si5345-44-42-RM Register 0x0539 Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Name Description 0x0539 2:0 R/W IN2_PRIORITY The priority for clock input 2 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6:4 R/W IN3_PRIORITY The priority for clock input 3 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3. Rev. 1.0 111 Si5345 Si5345-44-42-RM 14.3.7. Page 9 Registers Si5345 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name 0x090E 0 R/W XAXB_EXTCLK_EN Description 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select Reg Address Bit Field Type Name 0x0943 0 R/W IO_VDD_SEL Description 0 for 1.8 V external connections 1 for 3.3 V external connections The IO_VDD_SEL configuration bit selects the option of operating the serial interface voltage thresholds from the VDD or the VDDA pin. The serial interface pins are always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is operating at 3.3 V and the Si5345/44/42 at VDD = 1.8 V, the host must write the IO_VDD_SEL configuration bit to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds. Register 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Name Description 0x0949 3:0 R/W IN_EN 0: Disable and Powerdown Input Buffer 1: Enable Input Buffer for IN3–IN0. 0x0949 7:4 R/W IN_PULSED_CMOS_EN 0: Standard Input Format 1: Pulsed CMOS Input Format for IN3– IN0. See "5. Clock Inputs" on page 19 for more information. When a clock input is disabled, it is powered down. Input 0 corresponds to IN_SEL 0x0949 [0], IN_PULSED_CMOS_EN 0x0949 [4] Input 1 corresponds to IN_SEL 0x0949 [1], IN_PULSED_CMOS_EN 0x0949 [5] Input 2 corresponds to IN_SEL 0x0949 [2], IN_PULSED_CMOS_EN 0x0949 [6] Input 3 corresponds to IN_SEL 0x0949 [3], IN_PULSED_CMOS_EN 0x0949 [7] 112 Rev. 1.0 Si5345 Si5345-44-42-RM 14.3.8. Page A Registers Si5345 Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type 0x0A03 4:0 R/W Name Description N_CLK_TO_OUTX_EN Routes Multisynth outputs to output driver muxes. Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 4:0 R/W N_PIBYP Output Multisynth integer divide mode. Bit 0 for ID0, Bit 1 for ID1, etc. 0: Nx divider is fractional. 1: Nx divider is integer. Register 0x0A05 Output Multisynth Divider Power Down Reg Address Bit Field Type Name 0x0A05 4:0 R/W N_PDNB Rev. 1.0 Description Powers down the N dividers. Set to 0 to power down unused N dividers. Must set to 1 for all active N dividers. See also related registers 0x0A03 and 0x0B4A. 113 Si5345 Si5345-44-42-RM 14.3.9. Page B Registers Si5345 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 3:0 R/W PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) fractional dividers. 0x0B44 5 R/W FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider. Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type 0x0B4A 4:0 R/W 114 Name Description N_CLK_DIS Disable digital clocks to N dividers. Must be set to 0 to use each N divider. See also related registers 0x0A03 and 0x0A05. Rev. 1.0 Si5344 Si5345-44-42-RM 14.4. Si5344 Register Definitions 14.4.1. Page 0 Registers Si5344 Register 0x0000 Die Rev Reg Address Bit Field Type Name 0x0000 3:0 R DIE_REV Reg Address Bit Field Type Name 0x0001 7:0 R/W PAGE Description 4- bit Die Revision Number Register 0x0001 Page Description Selects one of 256 possible pages. There is the “Page Register” which i s located at address 0x01 on every page. When read, it will indicate the current page. When written, it will change the page to the value entered. There is a page register at address 0x0001, 0x0101, 0x0201, 0x0301, … etc. Register 0x0002–0x0003 Base Part Number Reg Address Bit Field Type Name Value Description 0x0002 7:0 R PN_BASE 0x44 0x0003 15:8 R PN_BASE 0x53 Four-digit “base” part number, one nibble per digit Example: Si5344A-A-GM. The base part number (OPN) is 5344, which is stored in this register Register 0x0004 Device Grade Reg Address Bit Field Type Name 0x0004 7:0 R GRADE Description One ASCII character indicating the device speed/synthesis mode 0=A 1=B 2=C 3=D Refer to the device data sheet Ordering Guide section for more information about device grades. Register 0x0005 Device Revision Reg Address Bit Field Type 0x0005 7:0 R Name Description DEVICE_REV One ASCII character indicating the device revision level. 0 = A; 1 = B, etc. Example Si5344C-A12345-GM, the device revision is “A” and stored as 0 Rev. 1.0 115 Si5344 Si5345-44-42-RM Register 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3:0 R/W TOOL_VERSION[3:0] Special 0x0006 7:4 R/W TOOL_VERSION[7:4] Revision 0x0007 7:0 R/W TOOL_VERSION[15:8] Minor[7:0] 0x0008 0 R/W TOOL_VERSION[15:8] Minor[8] 0x0008 4:1 R/W TOOL_VERSION[16] 0x0008 7:5 R/W TOOL_VERSION[13:17] Major Tool. 0 for ClockBuilder Pro The software tool version that created the register values that are downloaded at power up is represented by TOOL_VERSION. Register 0x0009 Temperature Grade Reg Address Bit Field 0x0009 7:0 Type Name Description TEMP_GRADE Device temperature grading 0 = Industrial (-40° C to 85° C) ambient conditions Register 0x000A Package ID Reg Address Bit Field 0x000A 7:0 Type Name PKG_ID Description Package ID 1 = 7x7 mm 44 QFN Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5344C-A12345-GM. Applies to a “base” or “blank” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5344C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5344 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Register 0x000B I2C Address Reg Address Bit Field Type Setting Name 0x000B 6:2 R/W I2C_ADDR 116 Description The upper 5 bits of the 7 bit I2C address. The lower 2 bits are controlled by the A1 and A0 pins. Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x000C Internal Status Bits Reg Address Bit Field Type Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating. 0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins. 0x000C 2 R 0x000C 3 R 0x000C 4 R 0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout error. Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Register 0x000D Out-of-Frequency (OOF) and Loss-of Signal (LOS) Alarms Reg Address Bit Field Type Name Description 0x000D 3:0 R LOS 1 if the clock input is currently LOS 0x000D 7:4 R OOF 1 if the clock input is currently OOF Note that each bit corresponds to the input. The LOS and OOF bits are not sticky. Input 0 (IN0) corresponds to LOS 0x000D [0], OOF 0x000D [4] 1 (IN1) corresponds to LOS 0x000D [1], OOF 0x000D [5] Input 2 (IN2) corresponds to LOS 0x000D [2], OOF 0x000D [6] Input 3 (IN3) corresponds to LOS 0x000D [3], OOF 0x000D [7] Input Register 0x000E Holdover and LOL Status Reg Address Bit Field Type Name 0x000E 1 R LOL 0x000E 5 R HOLD Description 1 if the DSPLL is out of lock 1 if the DSPLL is in holdover (or free run) These status bits indicate if the DSPLL is in holdover and if it is in Loss of Lock. These bits are not sticky. Register 0x000F Calibration Status Reg Address Bit Field Type Name 0x000F 5 R CAL_PLL Description 1 if the DSPLL internal calibration is busy This status bit indicates if a DSPLL is currently busy with calibration. This bit is not sticky. Rev. 1.0 117 Si5344 Si5345-44-42-RM Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL 0x0011 1 R LOSXAXB_FLG Sticky version of LOSXAXB 0x0011 2 R 0x0011 3 R 0x0011 4 R 0x0011 5 R SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT These are sticky flag bits. They are cleared by writing zero to the bit that has been set. Register 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field Type Name Description 0x0012 3:0 R/W LOS_FLG 1 if the clock input is LOS for the given input 0x0012 7:4 R/W OOF_FLG 1 if the clock input is OOF for the given input These are the sticky flag versions of register 0x000D. These bits are cleared by writing 0 to the bits that have been set. Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012 [4] 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012 [5] Input 2 (IN2) corresponds to LOS_FLG 0x0012 [2], OOF_FLG 0x0012 [6] Input 3 (IN3) corresponds to LOS_FLG 0x0012 [3], OOF_FLG 0x0012 [7] Input Register 0x0013 Sticky Holdover and LOL Flags Reg Address 0x0013 0x0013 Bit Field 1 5 Type R/W R/W Name LOL_FLG HOLD_FLG Description 1 if the DSPLL was unlocked 1 if the DSPLL was in holdover or free run These are the sticky flag versions of register 0x000E. These bits are cleared by writing 0 to the bits that have been set. Register 0x0014 Sticky PLL Calibration Flag Reg Address 0x0014 Bit Field 5 Type R/W Name CAL_FLG_PLL Description 1 if the internal calibration is busy This bit is the sticky flag version of 0x000F. This bit is cleared by writing 0 to bit 5. 118 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0017 Status Flag Masks Reg Address 0x0017 Bit Field 0 Type R/W Name SYSINCAL_INTR_MSK 0x0017 1 R/W LOSXAXB_FLG_MSK 0x0017 0x0017 0x0017 0x0017 2 3 4 5 R/W R/W R/W R/W SMBUS_TIMEOUT_FLG_MSK Description 1 to mask SYSINCAL_FLG from causing an interrupt 1 to mask the LOSXAXB_FLG from causing an interrupt 1 to mask SMBUS_TIMEOUT_FLG from the interrupt These are the interrupt mask bits for the fault flags in register 0x0011. If a mask bit is set, the alarm will be blocked from causing an interrupt. Note: Bit 1 corresponds to XAXB LOS from asserting the interrupt (INTR) pin. Register 0x0018 OOF and LOS Masks Reg Address Bit Field Type Name Description 0x0018 3:0 R/W LOS_INTR_MSK 1 to mask the clock input LOS flag 0x0018 7:4 R/W OOF_INTR_MSK 1 to mask the clock input OOF flag These are the interrupt mask bits for the OOF and LOS flags in register 0x0012. Input 0 (IN0) corresponds to LOS_INTR_MSK 0x0018 [0], OOF_INTR_MSK 0x0018 [4] Input 1 (IN1) corresponds to LOS_INTR_MSK 0x0018 [1], OOF_INTR_MSK 0x0018 [5] Input 2 (IN2) corresponds to LOS_INTR_MSK 0x0018 [2], OOF_INTR_MSK 0x0018 [6] Input 3 (IN3) corresponds to LOS_INTR_MSK 0x0018 [3], OOF_INTR_MSK 0x0018 [7] Register 0x0019 Holdover and LOL Masks Reg Address Bit Field Type Name 0x0019 1 R/W LOL_INTR_MSK 0x0019 5 R/W HOLD_INTR_MSK Description 1 to mask the clock input LOL flag 1 to mask the holdover flag These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set the alarm will be blocked from causing an interrupt. Rev. 1.0 119 Si5344 Si5345-44-42-RM Register 0x001A PLL Calibration Interrupt Mask Reg Address Bit Field Type Name Description 0x001A 5 R/W CAL_INTR_MSK 1 to mask the DSPLL internal calibration busy flag The interrupt mask for this bit flag bit corresponds to register 0x0014. the error flags in register 0x0017. If a mask bit is set, the alarm will be blocked from causing an interrupt. Register 0x001C Soft Reset and Calibration Reg Address Bit Field Type Name Description 0x001C 0 S SOFT_RST 1 Initialize and calibrates the entire device 0 No effect These bits are of type “S”, which is self-clearing. Register 0x001D FINC, FDEC Reg Address Bit Field Type Name Description 0x001D 0 S FINC 1 a rising edge will cause the selected MultiSynth to increment the output frequency by the FstepW parameter. See registers 0x0339-0x0353 0x001D 1 S FDEC 1 a rising edge will cause the selected MultiSynth to decrement the output frequency by the FstepW parameter. See registers 0x0339-0x0353 FINC, 1Dh[0] (self clear) FDEC is the same as FINC FINC pin, pos edge trig NxFINC N_FSTEP_MSKx, 339h[4:0] Figure 56. Logic Diagram of the FINC/FDEC Masks 120 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x001E Sync, Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 0 R/W PDN 0x001E 1 S HARD_RST 0x001E 2 S SYNC 1 to put the device into low power mode 1 causes hard reset. The same as power up except that the serial port access is not held at reset. This does not self-clear, so after setting the bit it must be cleared. 0 No reset Logically equivalent to asserting the SYNC pin. Resets all R dividers to the same state. Register 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Name 0x002B 3 R/W SPI_3WIRE Description 0 for 4-wire SPI, 1 for 3-wire SPI Register 0x002C LOS Enable Reg Address Bit Field Type Name 0x002C 3:0 R/W LOS_EN Description 1 to enable LOS for a clock input; 0 for disable Input 0 (IN0): LOS_EN[0] Input 1 (IN1): LOS_EN[1] Input 2 (IN2): LOS_EN[2] Input 3 (IN3): LOS_EN[3] Register 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Name Description 0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above 0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above 0x002D 7:6 R/W LOS3_VAL_TIME Clock Input 3, same as above When an input clock disappears (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME. Rev. 1.0 121 Si5344 Si5345-44-42-RM Register 0x002E-0x002F LOS0 Trigger Threshold Reg Address Bit Field Type Name 0x002E 7:0 R/W LOS0_TRG_THR 0x002F 15:8 R/W LOS0_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan. Register 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name 0x0030 7:0 R/W LOS1_TRG_THR 0x0031 15:8 R/W LOS1_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan. Register 0x0032-0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type Name 0x0032 7:0 R/W LOS2_TRG_THR 0x0033 15:8 R/W LOS2_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency plan. Register 0x0034-0x0035 LOS3 Trigger Threshold Reg Address Bit Field Type Name 0x0034 7:0 R/W LOS3_TRG_THR 0x0035 15:8 R/W LOS3_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3, given a particular frequency plan. Register 0x0036-0x0037 LOS0 Clear Threshold 122 Reg Address Bit Field Type Name 0x0036 7:0 R/W LOS0_CLR_THR 0x0037 15:8 R/W LOS0_CLR_THR Rev. 1.0 Description 16-bit Threshold Value Si5344 Si5345-44-42-RM ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan. Register 0x0038-0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name 0x0038 7:0 R/W LOS1_CLR_THR 0x0039 15:8 R/W LOS1_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan. Register 0x003A-0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name 0x003A 7:0 R/W LOS2_CLR_THR 0x003B 15:8 R/W LOS2_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan. Register 0x003C-0x003D LOS3 Clear Threshold Reg Address Bit Field Type Name 0x003C 7:0 R/W LOS3_CLR_THR 0x003D 15:8 R/W LOS3_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan. Register 0x003F OOF Enable Reg Address Bit Field Type Name Description 0x003F 3:0 R/W OOF_EN 1 to enable, 0 to disable 0x003F 7:4 R/W FAST_OOF_EN 1 to enable, 0 to disable Input 0 corresponds to OOF_EN [0], FAST_OOF_EN [4] Input 1 corresponds to OOF_EN [1], FAST_OOF_EN [5] Input 2 corresponds to OOF_EN [2], FAST_OOF_EN [6] Input 3 corresponds to OOF_EN [3], FAST_OOF_EN [7] Rev. 1.0 123 Si5344 Si5345-44-42-RM Register 0x0040 OOF Reference Select Reg Address Bit Field Type Name 0x0040 2:0 R/W OOF_REF_SEL Description 0 for CLKIN0 1 for CLKIN1 2 for CLKIN2 3 for CLKIN3 4 for XAXB Register 0x0046-0x0049 Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0046 7:0 R/W OOF0_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0047 7:0 R/W OOF1_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0048 7:0 R/W OOF2_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0049 7:0 R/W OOF3_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. 124 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x004A-0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x004A 7:0 R/W OOF0_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004B 7:0 R/W OOF1_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004C 7:0 R/W OOF2_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004D 7:0 R/W OOF3_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. ClockBuilder Pro is used to determine the values for these registers. Register 0x0051-0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 7:0 R/W FAST_OOF0_SET_THR (1+ value) x 1000 ppm 0x0052 7:0 R/W FAST_OOF1_SET_THR (1+ value) x 1000 ppm 0x0053 7:0 R/W FAST_OOF2_SET_THR (1+ value) x 1000 ppm 0x0054 7:0 R/W FAST_OOF3_SET_THR (1+ value) x 1000 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers. Register 0x0055-0x0058 Fast Out of Frequency Clear Threshold Reg Address Bit Field Type Name 0x0055 7:0 R/W FAST_OOF0_CLR_THR (1+ value) x 1000 ppm 0x0056 7:0 R/W FAST_OOF1_CLR_THR (1+ value) x 1000 ppm 0x0057 7:0 R/W FAST_OOF2_CLR_THR (1+ value) x 1000 ppm 0x0058 7:0 R/W FAST_OOF3_CLR_THR (1+ value) x 1000 ppm Rev. 1.0 Description 125 Si5344 Si5345-44-42-RM These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value)*1000 ppm. ClockBuilder Pro is used to determine the values for these registers. OOF needs a frequency reference. ClockBuilder Pro provides the OOF register values for a particular frequency plan. Register 0x009A LOL Enable Reg Address Bit Field Type 0x009A 1 R/W Name Description LOL_SLW_EN_PLL 1 to enable LOL; 0 to disable LOL. ClockBuilder Pro provides the LOL register values for a particular frequency plan. Register 0x009E LOL Set Threshold Reg Address Bit Field Type Name Description 0x009E 7:4 R/W LOL_SET_THR Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values are in ppm. Default is 0.2 ppm. The following are the thresholds for the value that is placed in the top four bits of register 0x009E. 0 = 0.2 ppm (default) 1 = 0.6 ppm 2 = 2 ppm 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name 0x00A0 7:4 R/W LOL_CLR_THR 126 Rev. 1.0 Description Configures the loss of lock clear thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values in ppm. Si5344 Si5345-44-42-RM The following are the thresholds for the value that is placed in the top four bits of register 0x00A0. ClockBuilder Pro sets these values. 0 = 0.2 ppm = 0.6 ppm 2 = 2 ppm (default) 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm 1 Register 0x00A2 LOL Timer Enable Reg Address Bit Field Type Name 0x00A2 1 R/W LOL_TIMER_EN Description 0 to disable 1 to enable LOL_TIMER_EN extends the time after LOL negates that the clock outputs can be disabled by LOL_CLR_DELAY (see below). Register 0x00A8-0x00AC LOL Clear Delay Reg Address Bit Field Type Name 0x00A8 7:0 R/W LOL_CLR_DELAY 0x00A9 15:8 R/W LOL_CLR_DELAY 0x00AA 23:16 R/W LOL_CLR_DELAY 0x00AB 31:24 R/W LOL_CLR_DELAY 0x00AC 34:32 R/W LOL_CLR_DELAY Description 35-bit value The LOL Clear Delay value is set by ClockBuilder Pro. Register 0x00E2 Reg Address Bit Field Type 0x00E2 7:0 R Name Description ACTIVE_NVM_BANK Read-only field indicating number of user bank writes caried out so far. Value Description 0 zero 3 one 15 two 63 three Rev. 1.0 127 Si5344 Si5345-44-42-RM Register 0x00E3 Reg Address Bit Field Type Name Description 0x00E3 7:0 R/W NVM_WRITE Write 0xC7 to initiate an NVM bank burn. Description See "4.3. NVM Programming" on page 16. Register 0x00E34 Reg Address Bit Field Type Name 0x00E34 0 S NVM_READ_BANK 1 to download NVM. When set, this bit will read the NVM down into the volatile memory. Register 0x00FE Device Ready Reg Address Bit Field Type Name 0x00FE 7:0 R DEVICE_READY Description 0x0F when device is ready 0xF3 when device is not ready Read-only byte to indicate when the device is ready to accept serial bus writes. The user can poll this byte starting at power-on; when DEVICE_READY is 0x0F the user can safely read or write to any other register. This is only needed after power up after a hard reset using register bit 0x001E[1] or during a bank burn (register 0x0E3). The “Device Ready” register is available on every page in the device at the second last register, 0xFE. There is a device ready register at 0x00FE, 0x01FE, 0x02FE, … etc. 128 Rev. 1.0 Si5344 Si5345-44-42-RM 14.4.2. Page 1 Registers Si5344 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 0 R/W OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0112 Clock Output Driver 0 and R-Divider 0 Configuration Reg Address Bit Field Type Name Description 0x0112 0 R/W OUT0_PDN Output driver 0: 0 to power up the regulator, 1 to power down the regulator. Clock outputs will be weakly pulled-low. 0x0112 1 R/W OUT0_OE Output driver 0: 0 to disable the output, 1 to enable the output 0x0112 2 R/W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0113 Output 0 Format Reg Address Bit Field Type Name Description 0x0113 2:0 R/W OUT0_FORMAT 0 Reserved 1 swing mode (normal swing) differential 2 swing mode (high swing) differential 3 rail to rail swing mode differential 4 LVCMOS single ended 5–7 reserved 0x0113 3 R/W OUT0_SYNC_EN 0 disable 1 enable 0x0113 5:4 R/W OUT0_DIS_STATE Determines the state of an output driver when disabled, selectable as Disable low (0), Disable high (1), High impedance. (2) In high impedance mode the output common mode voltage will be the same when the output is disabled as when the output is enabled. 0x0113 7:6 R/W OUT0_CMOS_DRV LVCMOS output impedance. Selectable as CMOS1,CMOS2, CMOS3. See "6.2. Performance Guidelines for Outputs" on page 32. Rev. 1.0 129 Si5344 Si5345-44-42-RM Register 0x0114 Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x0114 3:0 R/W OUT0_CM Output common mode voltage adjustment Programmable swing mode with normal swing configuration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5V if VDDO = 2.5 V Range=0.5 V to 0.9 V if VDDO = 1.8 V Programmable swing mode with high0 swing configuration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5 V if VDDO = 2.5 V Range = 0.5 V to 0.9 V if VDDO = 1.8 V Rail-to-rail swing Mode configuration: No flexibility DRV0_CM = 6 if VDDO = 3.3 V (Vcm = 1.5 V) DRV0_CM = 10 if VDDO = 2.5 V (Vcm = 1.1 V) DRV0_CM = 13 if VDDO = 1.8 V (Vcm = 0.8 V) LVCMOS mode: Not supported/No effect 0x0114 6:4 R/W OUT0_AMPL Output swing adjustment Programmable swing mode with normal swing configuration: Step size = 100 mV Range = 100 mVpp-se to 800 mVpp-se Programmable swing mode with high swing configuration: Step size = 200 mV Range = 200 mVpp-se to 1600 mVpp-se Rail-to-rail swing mode: Not supported/No effect LVCMOS mode: Not supported/No effect See the settings and values from Table 24 for details of the settings. ClockBuilder Pro is used to select the correct settings for this register. 130 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0115 R-Divider 0 Mux Selection Reg Address 0x0115 Bit Field 2:0 Type R/W Name OUT0_MUX_SEL 0x0115 7:6 R/W OUT0_INV Description Output driver 0 input mux select.This selects the source of the multisynth. 0: MS0 1: MS1 2: MS2 3: MS3 4: MS4 5: reserved 6: reserved 7: reserved CLK and CLK not inverted CLK inverted CLK and CLK inverted CLK inverted Each output can be configured to use Multisynth N0-N3 divider. The frequency for each N-divider is set in registers 0x0302-0x032C for N0 to N3. Four different frequencies can be set in the N-dividers (N0–N3) and each of the 4 outputs can be configured to any of the 4 different frequencies. The 4 output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other 3 output drivers. Table 47. Registers that Follow the Same Definitions Above Register Address 0x0117 0x0118 0x0119 0x011A 0x0126 0x0127 0x0128 0x0129 0x012B 0x012C 0x012D 0x012E Description Clock Output Driver 1 Config Clock Output Driver 1 Format, Sync Clock Output Driver 1 Ampl, CM OUT1_MUX_SEL, OUT1_INV Clock Output Driver 2 Config Clock Output Driver 2 Format, Sync Clock Output Driver 2 Ampl, CM OUT2_MUX_SEL, OUT2_INV Clock Output Driver 3 Config Clock Output Driver 3 Format, Sync Clock Output Driver 3 Ampl, CM OUT3_MUX_SEL, OUT3_INV (Same as) Address 0x0112 0x0113 0x0114 0x0115 0x0112 0x0113 0x0114 0x0115 0x0112 0x0113 0x0114 0x0115 Register 0x0145 Power Down All Reg Address Bit Field Type Name 0x0145 0 R/W OUT_PDN_ALL Rev. 1.0 Description 0- no effect 1- all drivers powered down 131 Si5344 Si5345-44-42-RM 14.4.3. Page 2 Registers Si5344 Register 0x0202–0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name Description 0x0202 7:0 R/W XAXB_FREQ_OFFSET 0x0203 15:8 R/W XAXB_FREQ_OFFSET 0x0204 23:16 R/W XAXB_FREQ_OFFSET 0x0205 31:24 R/W XAXB_FREQ_OFFSET 32 bit offset adjustment The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The XAXB_FREQ_OFFSET word is used to adjust this frequency reference with high resolution. ClockBuilder Pro calculates the correct values for these registers. Register 0x0206 Pre-scale Reference Divide Ratio Reg Address Bit Field Type Name 0x0206 1:0 R/W PXAXB Description Sets the divider for the input on XAXB 0 = pre-scale value 1 1 = pre-scale value 2 2 = pre-scale value 4 3 = pre-scale value 8 This can only be used with external clock sources, not crystals. Register 0x0208-0x020D P0 Divider Numerator Reg Address Bit Field Type Name 0x0208 7:0 R/W P0_NUM 0x0209 15:8 R/W P0_NUM 0x020A 23:16 R/W P0_NUM 0x020B 31:24 R/W P0_NUM 0x020C 39:32 R/W P0_NUM 0x020D 47:40 R/W P0_NUM Description 48-bit Integer Number This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers. 132 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x020E-0x0211 P0 Divider Denominator Reg Address Bit Field Type Name 0x020E 7:0 R/W P0_DEN 0x020F 15:8 R/W P0_DEN 0x0210 23:16 R/W P0_DEN 0x0211 31:24 R/W P0_DEN Description 32-bit Integer Number The P1, P2 and P3 divider numerator and denominator follow the same format as P0 described above. ClockBuilder Pro calculates the correct values for the P-dividers. Table 48. Registers that Follow the P0_NUM and P0_DEN Register Address Description Size Same as Address 0x0212-0x0217 P1 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0218-0x021B P1 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x021C-0x0221 P2 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0222-0x0225 P2 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x0226-0x022B P3 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3 Divider Denominator 32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers. Register 0x024A-0x024C R0 Divider Reg Address Bit Field Type Name 0x024A 7:0 R/W R0_REG 0x024B 15:8 R/W R0_REG 0x024C 23:16 R/W R0_REG Description A 24 bit integer divide value divide value = (R0_REG+1) x 2 To set R0 = 2, set OUT0_RDIV_FORCE2 = 1 and then the R0_REG value is irrelevant. The R dividers are at the output clocks and are purely integer division. The R1–R3 dividers follow the same format as the R0 divider described above. Rev. 1.0 133 Si5344 Si5345-44-42-RM Register 0x0230 Px_UPDATE Reg Address Bit Field Type Name 0x0230 0 S, R/W P0_UPDATE 0x0230 1 S, R/W P1_UPDATE 0x0230 2 S, R/W P2_UPDATE 0x0230 3 S, R/W P3_UPDATE Description 0 - No update for P-divider value 1 - Update P-divider value The Px_Update bit must be asserted to update the P-Divider. The update bits are provided so that all of the divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Table 49. Registers that Follow the R0_REG Register Address Description Size Same as Address 0x024D-0x024F R1_REG 24-bit Integer Number 0x024A-0x024C 0x0250-0x0252 R2_REG 24-bit Integer Number 0x024A-0x024C 0x0253-0x0255 R3_REG 24-bit Integer Number 0x024A-0x024C Register 0x026B-0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B 7:0 R/W DESIGN_ID0 0x026C 15:8 R/W DESIGN_ID1 0x026D 23:16 R/W DESIGN_ID2 0x026E 31:24 R/W DESIGN_ID3 0x026F 39:32 R/W DESIGN_ID4 0x0270 47:40 R/W DESIGN_ID5 0x0271 55:48 R/W DESIGN_ID6 0x0272 63:56 R/W DESIGN_ID7 ASCII encoded string defined by CBPro user, with user defined space or null padding of unused characters. A user will normally include a configuration ID + revision ID. For example, “ULT.1A” with null character padding sets: DESIGN_ID0: 0x55 DESIGN_ID1: 0x4C DESIGN_ID2: 0x54 DESIGN_ID3: 0x2E DESIGN_ID4: 0x31 DESIGN_ID5: 0x41 DESIGN_ID6:0x 00 DESIGN_ID7: 0x00 134 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0278-0x027C OPN Identifier Reg Address Bit Field Type Name 0x0278 7:0 R/W OPN_ID0 0x0279 15:8 R/W OPN_ID1 0x027A 23:16 R/W OPN_ID2 0x027B 31:24 R/W OPN_ID3 0x027C 39:32 R/W OPN_ID4 Description OPN unique identifier. ASCII encoded. For example, with OPN: 5344C-A12345-GM, 12345 is the OPN unique identifier, which sets: OPN_ID0: 0x31 OPN_ID1: 0x32 OPN_ID2: 0x33 OPN_ID3: 0x34 OPN_ID4: 0x35 Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5344C-A12345-GM. Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5344C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5344 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Rev. 1.0 135 Si5344 Si5345-44-42-RM 14.4.4. Page 3 Registers Si5344 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 7:0 R/W N0_NUM 0x0303 15:8 R/W N0_NUM 0x0304 23:16 R/W N0_NUM 0x0305 31:24 R/W N0_NUM 0x0306 39:32 R/W N0_NUM 0x0307 43:40 R/W N0_NUM 44-bit Integer Number The N0 value is N0_NUM/N0_DEN The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder Pro calculates the correct values for the N-dividers. Register 0x0308-0x030B N0 Denominator Reg Address Bit Field Type Name Description 0x0308 7:0 R/W N0_DEN 0x0309 15:8 R/W N0_DEN 0x030A 23:16 R/W N0_DEN 0x030B 31:24 R/W N0_DEN 0x030C 0 R/W N0_UPDATE 32-bit Integer Number The N0 value is N0_NUM/N0_DEN Set this bit to update the N0 divider. This bit is provided so that all of the N0 divider bits can be changed at the same time. First, write all of the new values to the divider; then, set the update bit. Table 50. Registers that Follow the N0_NUM and N0_DEN Definitions 136 Register Address Description Size Same as Address 0x030D-0x0312 N1 Numerator 44-bit Integer Number 0x0302-0x0307 0x0313-0x0316 N1 Denominator 32-bit Integer Number 0x0308-0x030B 0x0317 N1_UPDATE one bit 0x030C 0x0318-0x031D N2 Numerator 44-bit Integer Number 0x0302-0x0307 0x031E-0x0321 N2 Denominator 32-bit Integer Number 0x0308-0x030B 0x0322 N2_UPDATE one bit 0x030C 0x0323-0x0328 N3 Numerator 44-bit Integer Number 0x0302-0x0307 0x0329-0x032C N3 Denominator 32-bit Integer Number 0x0308-0x030B 0x032D N3_UPDATE one bit 0x030C Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338 1 R/W N_UPDATE_ALL Set this bit to update all five N dividers. This bit is provided so that all of the divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Register 0x0339 FINC/FDEC Masks Reg Address Bit Field Type Name Description 0x0339 3:0 R/W N_FSTEP_MSK 0 to enable FINC/FDEC updates 1 to disable FINC/FDEC updates Bit 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0] 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1] Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339[2] Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339[3] Bit Register 0x033B-0x0340 N0 Frequency Step Word Reg Address Bit Field Type Name Description 0x033B 7:0 R/W N0_FSTEPW 0x033C 15:8 R/W N0_FSTEPW 0x033D 23:16 R/W N0_FSTEPW 0x033E 31:24 R/W N0_ FSTEPW 0x033F 39:32 R/W N0_ FSTEPW 0x0340 43:40 R/W N0_ FSTEPW 44-bit Integer Number This is a 44-bit integer value which is directly added or subtracted from the N-divider. When FINC or FDEC is set to a 1, ClockBuilder Pro calculates the correct values for the N0 Frequency Step Word. Each N divider has the ability to add or subtract up to a 44-bit value. Table 51. Registers that Follow the N0_FSTEPW Definition Register Address Description Size Same as Address 0x0341-0x0346 N1 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 0x0347-0x034C N2 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 0x034D-0x0352 N3 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 Rev. 1.0 137 Si5344 Si5345-44-42-RM Register 0x0359–0x35A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 7:0 R/W N0_DELAY[7:0] Lower byte of N0_DELAY[15:0] 0x035A 7:0 R/W N0_DELAY[15:8] Upper byte of N0_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(215–1)/(256 x Fvco). ClockBuilder Pro calculates the correct value for this register. Changing any of the Nx_DELAY values requires a SOFT_RST, a HARD_RST, or a power up sequence. Register 0x035B-0x035C Divider N1 Delay Control Reg Address Bit Field Type Name Description 0x35B 7:0 R/W N1_DELAY[7:0] Lower byte of N1_DELAY[15:0] 0x35C 7:0 R/W N1_DELAY[15:8] Upper byte of N1_DELAY[15:0] Register 0x035D-0x035E Divider N2 Delay Control Reg Address Bit Field Type Name Description 0x35D 7:0 R/W N2_DELAY[7:0] Lower byte of N2_DELAY[15:0] 0x35E 7:0 R/W N2_DELAY[15:8] Upper byte of N2_DELAY[15:0] Register 0x035F-0x0360 Divider N3 Delay Control Reg Address Bit Field Type Name Description 0x35F 7:0 R/W N3_DELAY[7:0] Lower byte of N3_DELAY[15:0] 0x360 7:0 R/W N3_DELAY[15:8] Upper byte of N3_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(215–1)/(256 x Fvco). ClockBuilder Pro calculates the correct value for this register. 138 Rev. 1.0 Si5344 Si5345-44-42-RM 14.4.5. Page 4 Registers Si5344 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name 0x0487 0 R/W ZDM_EN 0x0487 2:1 R/W ZDM_IN_SEL Description 0 to disable ZD mode 1 to enable ZD mode Clock input select when in ZD. 0 for IN0, 1 for IN1,2 for IN2, 3 reserved This register is used for enabling the zero delay mode (ZDM) and selecting the source. The phase difference between the output, which is connected to the selected input below will be nulled to zero. When in zero delay mode, the DSPLL cannot have either hitless or automatic switching. In addition, the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins. Pin controlled clock selection is available in ZD mode (see register 0x052A). Rev. 1.0 139 Si5344 Si5345-44-42-RM 14.4.6. Page 5 Registers Si5344 Register 0x0507 Reg Address Bit Field Type Name 0x0507 7,6 R IN_ACTV Description Current input clock. These bits indicate which input clock is currently selected. 0 for IN0, 1 for IN1, etc. Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 7:0 R/W BW0_PLL PLL bandwidth parameter 0x0509 15:8 R/W BW1_PLL PLL bandwidth parameter 0x050A 23:16 R/W BW2_PLL PLL bandwidth parameter 0x050B 31:24 R/W BW3_PLL PLL bandwidth parameter 0x050C 39:32 R/W BW4_PLL PLL bandwidth parameter 0x050D 47:40 R/W BW5_PLL PLL bandwidth parameter This group of registers determine the loop bandwidth for the DSPLL. It is selectable as 0.1 Hz, 1 Hz, 4 Hz, 10 Hz, 40 Hz, 100 Hz, 400 Hz, 1 kHz, and 4 kHz. The loop BW values are calculated by ClockBuilder Pro and are written into these registers. The BW_UPDATE_PLL bit (reg 0x0514[0]) must be set to cause the BWx_PLL parameters to take effect. Register 0x050E-0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Description 0x050E 7:0 R/W FAST_BW0_PLL PLL fast bandwidth parameter 0x050F 15:8 R/W FAST_BW1_PLL PLL fast bandwidth parameter 0x0510 23:16 R/W FAST_BW2_PLL PLL fast bandwidth parameter 0x0511 31:24 R/W FAST_BW3_PLL PLL fast bandwidth parameter 0x0512 39:32 R/W FAST_BW4_PLL PLL fast bandwidth parameter 0x0513 47:40 R/W FAST_BW5_PLL PLL fast bandwidth parameter 0x0514 0 S BW_UPDATE_PLL Must be set to 1 to update the BWx_PLL and FAST_BWx_PLL parameters The fast lock loop BW values are calculated by ClockBuilder Pro and used when fast lock is enabled. 140 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address Bit Field Type Name 0x0515 7:0 R/W M_NUM 0x0516 15:8 R/W M_NUM 0x0517 23:16 R/W M_NUM 0x0518 31:24 R/W M_NUM 0x0519 39:32 R/W M_NUM 0x051A 47:40 R/W M_NUM 0x051B 55:48 R/W M_NUM Description 56-bit Number Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address Bit Field Type Name 0x051C 7:0 R/W M_DEN 0x051E 15:8 R/W M_DEN 0x051E 23:16 R/W M_DEN 0x051F 31:24 R/W M_DEN Description 32-bit Number The loop M divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers. Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name 0x0520 0 R/W M_UPDATE Description Set this bit to update the M divider. Register 0x052A Input Clock Select Reg Address Bit Field Type Name 0x052A 0 R/W IN_SEL_REGCTRL 0x052A 2:1 R/W IN_SEL Description 0 for pin controlled clock selection 1 for register controlled clock selection 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection. Note: when ZDM_EN (0x0487, bit 0) and IN_SEL_REGCTRL are both high, IN_SEL does not do anything and the clock selection is pin controlled. When IN_SEL_REGCTRL is low, IN_SEL does not do anything and the clock selection is pin controlled. Rev. 1.0 141 Si5344 Si5345-44-42-RM Register 0x052B Fast Lock Control Reg Address Bit Field Type Name Description 0x052B 0 R/W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN = 0 (see below): 0 to enable auto fast lock when the DSPLL is out of lock 1 to disable auto fast lock 0x052B 1 R/W FASTLOCK_MAN 0 for normal operation (see above) 1 to force fast lock When in fast lock, the fast lock loop BW can be automatically used. Register 0x052C Holdover Exit Control Reg Address Bit Field Type Name 0x052C 3 R/W HOLD_RAMP_BYP 0x052C 4 R/W HOLD_EXIT_BW_SEL Description Must be set to 1 for normal operation. 0 to use the fastlock loop BW when exiting from holdover 1 to use the normal loop BW when exiting from holdover Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E 4:0 R/W HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x052F Holdover History Delay Reg Address Bit Field Type Name 0x052F 4:0 R/W HOLD_HIST_DELAY Description The most recent input frequency perturbations can be ignored during entry into holdover. The holdover logic pushes back into the past, above the averaging window. The amount that the average window is delayed is the holdover history delay. 142 Rev. 1.0 Si5344 Si5345-44-42-RM Register 0x0535 Force Holdover Reg Address Bit Field Type Name 0x0535 0 R/W FORCE_HOLD Description 0 for normal operation 1 for force holdover Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name Description 0x0536 1:0 R/W CLK_SWTCH_MODE 0x0536 2 R/W HSW_EN 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase buildout turned on) Register 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3:0 R/W IN_LOS_MSK For each clock input LOS alarm: 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7:4 R/W IN_OOF_MSK For each clock input OOF alarm: 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic This register is for the input clock switch alarm masks. For each of the four clock inputs, the OOF and/or the LOS alarms can be used for the clock selection logic or they can be masked from it. Note that the clock selection logic can affect entry into holdover. Rev. 1.0 143 Si5344 Si5345-44-42-RM Register 0x0538 Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Name Description 0x0538 2:0 R/W IN0_PRIORITY The priority for clock input 0 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0538 6:4 R/W IN1_PRIORITY The priority for clock input 1 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3. Register 0x0539 Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Name Description 0x0539 2:0 R/W IN2_PRIORITY The priority for clock input 2 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6:4 R/W IN3_PRIORITY The priority for clock input 3 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following priority list: 0, 1, 2, 3. 144 Rev. 1.0 Si5344 Si5345-44-42-RM 14.4.7. Page 9 Registers Si5344 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name 0x090E 0 R/W XAXB_EXTCLK_EN Description 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select Reg Address Bit Field Type Name 0x0943 0 R/W IO_VDD_SEL Description 0 for 1.8 V external connections 1 for 3.3 V external connections The IO_VDD_SEL configuration bit selects the option of operating the serial interface voltage thresholds from the VDD or the VDDA pin. The serial interface pins are always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is operating at 3.3 V and the Si5345/44/42 at VDD = 1.8 V, the host must write the IO_VDD_SEL configuration bit to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds. Register 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Name Description 0x0949 3:0 R/W IN_EN 0: Disable and Powerdown Input Buffer. 1: Enable Input Buffer for IN3–IN0. 0x0949 7:4 R/W IN_PULSED_CMOS_EN 0: Standard Input Format. 1: Pulsed CMOS Input Format for IN3– IN0. See "5. Clock Inputs" on page 19 for more information. When a clock input is disabled, it is powered down. Input 0 corresponds to IN_SEL 0x0949 [0], IN_PULSED_CMOS_EN 0x0949 [4] Input 1 corresponds to IN_SEL 0x0949 [1], IN_PULSED_CMOS_EN 0x0949 [5] Input 2 corresponds to IN_SEL 0x0949 [2], IN_PULSED_CMOS_EN 0x0949 [6] Input 3 corresponds to IN_SEL 0x0949 [3], IN_PULSED_CMOS_EN 0x0949 [7] Rev. 1.0 145 Si5344 Si5345-44-42-RM 14.4.8. Page A Registers Si5344 Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type 0x0A03 3:0 R/W Name Description N_CLK_TO_OUTX_EN Routes Multisynth outputs to output driver muxes. Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 3:0 R/W N_PIBYP Output Multisynth integer divide mode. Bit 0 for ID0; Bit 1 for ID1, etc. 0: Nx divider is fractional. 1: Nx divider is integer. Register 0x0A05 Output Multisynth Divider Power Down 146 Reg Address Bit Field Type Name Description 0x0A05 3:0 R/W N_PDNB Powers down the N dividers. Set to 0 to power down unused N dividers. Must set to 1 for all active N dividers. See also related registers 0x0A03 and 0x0B4A. Rev. 1.0 Si5344 Si5345-44-42-RM 14.4.9. Page B Registers Si5344 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 3:0 R/W PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) fractional dividers. 0x0B44 5 R/W FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider. Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B4A 3:0 R/W N_CLK_DIS Disable digital clocks to N dividers. Must be set to 0 to use each N divider. See also related registers 0x0A03 and 0x0A05. Rev. 1.0 147 Si5342 Si5345-44-42-RM 14.5. Si5342 Register Definitions 14.5.1. Page 0 Registers Si5342 Register 0x0000 Die Rev Reg Address Bit Field Type Name Description 0x0000 3:0 R DIE_REV Reg Address Bit Field Type Name 0x0001 7:0 R/W PAGE 4- bit Die Revision Number Register 0x0001 Page Description Selects one of 256 possible pages. There is the “Page Register” which i s located at address 0x01 on every page. When read, it will indicate the current page. When written, it will change the page to the value entered. There is a page register at address 0x0001, 0x0101, 0x0201, 0x0301, … etc. Register 0x0002–0x0003 Base Part Number Reg Address Bit Field Type Name Value 0x0002 7:0 R PN_BASE 0x42 0x0003 15:8 R PN_BASE 0x53 Description Four-digit “base” part number, one nibble per digit Example: Si5342A-A-GM. The base part number (OPN) is 5342, which is stored in this register. Register 0x0004 Device Grade Reg Address Bit Field Type Name 0x0004 7:0 R GRADE Description One ASCII character indicating the device speed/synthesis mode 0=A 1=B 2=C 3=D Refer to the device data sheet Ordering Guide section for more information about device grades. Register 0x0005 Device Revision Reg Address Bit Field Type 0x0005 7:0 R 148 Name Description DEVICE_REV One ASCII character indicating the device revision level. 0 = A; 1 = B, etc. Example Si5342C-A12345-GM, the device revision is “A” and stored as 0. Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x0006–0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3:0 R/W TOOL_VERSION[3:0] Special 0x0006 7:4 R/W TOOL_VERSION[7:4] Revision 0x0007 7:0 R/W TOOL_VERSION[15:8] Minor[7:0] 0x0008 0 R/W TOOL_VERSION[15:8] Minor[8] 0x0008 4:1 R/W TOOL_VERSION[16] 0x0008 7:5 R/W TOOL_VERSION[13:17] Major Tool. 0 for ClockBuilder Pro The software tool version that created the register values that are downloaded at power up is represented by TOOL_VERSION. Register 0x0009 TEMPERATURE GRADE Reg Address Bit Field 0x0009 7:0 Type Name TEMP_GRADE Description Device temperature grading 0 = Industrial (-40° C to 85° C) ambient conditions Register 0x000A PACKAGE ID Reg Address Bit Field 0x000A 7:0 Type Name PKG_ID Description Package ID 1 = 7x7 mm 44 QFN Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5342C-A12345-GM. Applies to a “base” or “blank” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5342C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5342 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Rev. 1.0 149 Si5342 Si5345-44-42-RM Register 0x000B I2C Address Reg Address Bit Field Type Setting Name 0x000B 6:2 R/W I2C_ADDR Description The upper 5 bits of the 7 bit I2C address. The lower 2 bits are controlled by the A1 and A0 pins. Register 0x000C Internal Status Bits Reg Address Bit Field Type Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating. 0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins. 0x000C 2 R 0x000C 3 R 0x000C 4 R 0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout error. Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins. Register 0x000D Out-of-Frequency (OOF) and Loss-of Signal (LOS) Alarms Reg Address Bit Field Type Name Description 0x000D 3:0 R LOS 1 if the clock input is currently LOS 0x000D 7:4 R OOF 1 if the clock input is currently OOF Note that each bit corresponds to the input. The LOS and OOF bits are not sticky. Input 0 (IN0) corresponds to LOS 0x000D [0], OOF 0x000D [4] Input 1 (IN1) corresponds to LOS 0x000D [1], OOF 0x000D [5] Input 2 (IN2) corresponds to LOS 0x000D [2], OOF 0x000D [6] Input 3 (IN3) corresponds to LOS 0x000D [3], OOF 0x000D [7] Register 0x000E Holdover and LOL Status Reg Address Bit Field Type Name 0x000E 1 R LOL 0x000E 5 R HOLD Description 1 if the DSPLL is out of lock 1 if the DSPLL is in holdover (or free run) These status bits indicate if the DSPLL is in holdover and if it is in Loss of Lock. These bits are not sticky. 150 Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x000F Calibration Status Reg Address Bit Field Type Name 0x000F 5 R CAL_PLL Description 1 if the DSPLL internal calibration is busy This status bit indicates if a DSPLL is currently busy with calibration. This bit is not sticky. Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL 0x0011 1 R LOSXAXB_FLG Sticky version of LOSXAXB 0x0011 2 R 0x0011 3 R 0x0011 4 R 0x0011 5 R SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT If any of these six bits are high, there is an internal fault. Please contact Silicon Labs. These are sticky flag bits. They are cleared by writing zero to the bit that has been set. Register 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field Type Name Description 0x0012 3:0 R/W LOS_FLG 1 if the clock input is LOS for the given input 0x0012 7:4 R/W OOF_FLG 1 if the clock input is OOF for the given input These are the sticky flag versions of register 0x000D. These bits are cleared by writing 0 to the bits that have been set. Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012 [4] Input 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012 [5] Input 2 (IN2) corresponds to LOS_FLG 0x0012 [2], OOF_FLG 0x0012 [6] Input 3 (IN3) corresponds to LOS_FLG 0x0012 [3], OOF_FLG 0x0012 [7] Register 0x0013 Sticky Holdover and LOL Flags Reg Address Bit Field Type Name 0x0013 1 R/W LOL_FLG 0x0013 5 R/W HOLD_FLG Description 1 if the DSPLL was unlocked 1 if the DSPLL was in holdover or free run These are the sticky flag versions of register 0x000E. These bits are cleared by writing 0 to the bits that have been set. Rev. 1.0 151 Si5342 Si5345-44-42-RM Register 0x0014 Sticky INCAL Flag Reg Address Bit Field Type Name 0x0014 5 R/W CAL_FLG_PLL Description 1 if the internal calibration was busy This bit is the sticky flag version of 0x000F. This bit is cleared by writing 0 to bit 5. Register 0x0017 Status Flag Masks Reg Address Bit Field Type Name Description 0x0017 0 R/W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R/W LOSXAXB_FLG_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 2 R/W 0x0017 3 R/W 0x0017 4 R/W 0x0017 5 R/W FAULT5_FLG_MSK 1 to mask SMBUS_TIMEOUT_FLG from the interrupt These are the interrupt mask bits for the fault flags in register 0x0011. If a mask bit is set, the alarm will be blocked from causing an interrupt. Note: Bit 1 corresponds to XAXB LOS from asserting the interrupt (INTR) pin. Register 0x0018 OOF and LOS Masks Reg Address Bit Field Type Name Description 0x0018 3:0 R/W LOS_INTR_MSK 1 to mask the clock input LOS flag 0x0018 7:4 R/W OOF_INTR_MSK 1 to mask the clock input OOF flag These are the interrupt mask bits for the OOF and LOS flags in register 0x0012. Input 0 (IN0) corresponds to LOS_INTR_MSK 0x0018 [0], OOF_INTR_MSK 0x0018 [4] Input 1 (IN1) corresponds to LOS_INTR_MSK 0x0018 [1], OOF_INTR_MSK 0x0018 [5] Input 2 (IN2) corresponds to LOS_INTR_MSK 0x0018 [2], OOF_INTR_MSK 0x0018 [6] Input 3 (IN3) corresponds to LOS_INTR_MSK 0x0018 [3], OOF_INTR_MSK 0x0018 [7] Register 0x0019 Holdover and LOL Masks 152 Reg Address Bit Field Type Name 0x0019 1 R/W LOL_INTR_MSK 0x0019 5 R/W HOLD_INTR_MSK Rev. 1.0 Description 1 to mask the clock input LOL flag 1 to mask the holdover flag Si5342 Si5345-44-42-RM These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set the alarm will be blocked from causing an interrupt. Register 0x001A INCAL Mask Reg Address Bit Field Type Name Description 0x001A 5 R/W CAL_INTR_MSK 1 to mask the DSPLL internal calibration busy flag The interrupt mask for this bit flag bit corresponds to register 0x0014. Register 0x001C Soft Reset and Calibration Reg Address Bit Field Type Name Description 0x001C 0 S SOFT_RST 1 Initialize and calibrates the entire device 0 No effect These bits are of type “S”, which is self-clearing. Register 0x001D FINC, FDEC Reg Address Bit Field Type Name Description 0x001D 0 S FINC 1 a rising edge will cause the selected MultiSynth to increment the output frequency by the FstepW parameter. See registers 0x0339-0x0353 0 No effect 0x001D 1 S FDEC 1 a rising edge will cause the selected MultiSynth to decrement the output frequency by the FstepW parameter. See registers 0x0339-0x03530 No effect Figure 57 shows the logic for the FINC, FDEC bits. FINC, 1Dh[0] (self clear) FDEC is the same as FINC FINC pin, pos edge trig NxFINC N_FSTEP_MSKx, 339h[4:0] Figure 57. FINC, FDEC Logic Diagram Rev. 1.0 153 Si5342 Si5345-44-42-RM Register 0x001E Sync, Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 0 R/W PDN 0x001E 1 S HARD_RST 0x001E 2 S SYNC 1 to put the device into low power mode 1 causes hard reset. The same as power up except that the serial port access is not held at reset. This does not self-clear, so after setting the bit it must be cleared. 0 No reset Logically equivalent to asserting the SYNC pin. Resets all R dividers to the same state. Register 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Name 0x002B 3 R/W SPI_3WIRE Description 0 for 4-wire SPI, 1 for 3-wire SPI Register 0x002C LOS Enable Reg Address Bit Field Type Name 0x002C 3:0 R/W LOS_EN Description 1 to enable LOS for a clock input; 0 for disable Input 0 (IN0): LOS_EN[0] 1 (IN1): LOS_EN[1] Input 2 (IN2): LOS_EN[2] Input 3 (IN3): LOS_EN[3] Input Register 0x002D Loss of Signal Re-Qualification Value Reg Address Bit Field Type Name Description 0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above 0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above 0x002D 7:6 R/W LOS3_VAL_TIME Clock Input 3, same as above When an input clock disappears (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME. 154 Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x002E-0x002F LOS0 Trigger Threshold Reg Address Bit Field Type Name 0x002E 7:0 R/W LOS0_TRG_THR 0x002F 15:8 R/W LOS0_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan. Register 0x0030-0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name 0x0030 7:0 R/W LOS1_TRG_THR 0x0031 15:8 R/W LOS1_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan. Register 0x0032-0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type Name 0x0032 7:0 R/W LOS2_TRG_THR 0x0033 15:8 R/W LOS2_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency plan. Register 0x0034-0x0035 LOS3 Trigger Threshold Reg Address Bit Field Type Name 0x0034 7:0 R/W LOS3_TRG_THR 0x0035 15:8 R/W LOS3_TRG_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3, given a particular frequency plan. Register 0x0036-0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Name 0x0036 7:0 R/W LOS0_CLR_THR 0x0037 15:8 R/W LOS0_CLR_THR Rev. 1.0 Description 16-bit Threshold Value 155 Si5342 Si5345-44-42-RM ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan. Register 0x0038-0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name 0x0038 7:0 R/W LOS1_CLR_THR 0x0039 15:8 R/W LOS1_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan. Register 0x003A-0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name 0x003A 7:0 R/W LOS2_CLR_THR 0x003B 15:8 R/W LOS2_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan. Register 0x003C-0x003D LOS3 Clear Threshold Reg Address Bit Field Type Name 0x003C 7:0 R/W LOS3_CLR_THR 0x003D 15:8 R/W LOS3_CLR_THR Description 16-bit Threshold Value ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan. Register 0x003F OOF Enable Reg Address Bit Field Type Name 0x003F 3:0 R/W OOF_ENI 1 to enable, 0 to disable 0x003F 7:4 R/W FAST_OOF_ENI 1 to enable, 0 to disable Input 0 corresponds to OOF_ENI [0], FAST_OOF_ENI [4] Input 1 corresponds to OOF_ENI [1], FAST_OOF_ENI [5] Input 2 corresponds to OOF_ENI [2], FAST_OOF_ENI [6] Input 3 corresponds to OOF_ENI [3], FAST_OOF_ENI [7] 156 Rev. 1.0 Description Si5342 Si5345-44-42-RM Register 0x0040 OOF Reference Select Reg Address Bit Field Type Name 0x0040 2:0 R/W OOF_REF_SEL Description 0 for CLKIN0 1 for CLKIN1 2 for CLKIN2 3 for CLKIN3 4 for XAXB Register 0x0046-0x0049 Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0046 7:0 R/W OOF0_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0047 7:0 R/W OOF1_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0048 7:0 R/W OOF2_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x0049 7:0 R/W OOF3_SET_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. Rev. 1.0 157 Si5342 Si5345-44-42-RM Register 0x004A-0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x004A 7:0 R/W OOF0_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004B 7:0 R/W OOF1_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004C 7:0 R/W OOF2_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm 0x004D 7:0 R/W OOF3_CLR_THR 1 = 2 ppm 2 = 4 ppm 3 = 6 ppm 255 = 510 ppm These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0. The range is from ±2 ppm up to ±510 ppm in steps of 2 ppm. ClockBuilder Pro is used to determine the values for these registers. Register 0x0051-0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 7:0 R/W FAST_OOF0_SET_THR (1+ value) x 1000 ppm 0x0052 7:0 R/W FAST_OOF1_SET_THR (1+ value) x 1000 ppm 0x0053 7:0 R/W FAST_OOF2_SET_THR (1+ value) x 1000 ppm 0x0054 7:0 R/W FAST_OOF3_SET_THR (1+ value) x 1000 ppm These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers. Register 0x0055-0x0058 Fast Out of Frequency Clear Threshold Reg Address Bit Field Type Name 0x0055 7:0 R/W FAST_OOF0_CLR_THR (1+ value) x 1000 ppm 0x0056 7:0 R/W FAST_OOF1_CLR_THR (1+ value) x 1000 ppm 0x0057 7:0 R/W FAST_OOF2_CLR_THR (1+ value) x 1000 ppm 0x0058 7:0 R/W FAST_OOF3_CLR_THR (1+ value) x 1000 ppm 158 Rev. 1.0 Description Si5342 Si5345-44-42-RM These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value)*1000 ppm. ClockBuilder Pro is used to determine the values for these registers. OOF needs a frequency reference. ClockBuilder Pro provides the OOF register values for a particular frequency plan. Register 0x009A LOL Enable Reg Address Bit Field Type 0x009A 1 R/W Name Description LOL_SLW_EN_PLL 1 to enable LOL; 0 to disable LOL. ClockBuilder Pro provides the LOL register values for a particular frequency plan. Register 0x009E LOL Set Threshold Reg Address Bit Field Type Name Description 0x009E 7:4 R/W LOL_SET_THR Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values are in ppm. Default is 0.2 ppm. The following are the thresholds for the value that is placed in the top four bits of register 0x009E. 0 = 0.2 ppm (default) = 0.6 ppm 2 = 2 ppm 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm 1 Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name 0x00A0 7:4 R/W LOL_CLR_THR Rev. 1.0 Description Configures the loss of lock clear thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values in ppm. Default value is 2 ppm. 159 Si5342 Si5345-44-42-RM The following are the thresholds for the value that is placed in the top four bits of register 0x00A0. ClockBuilder Pro sets these values. 0 = 0.2 ppm = 0.6 ppm 2 = 2 ppm 3 = 6 ppm 4 = 20 ppm 5 = 60 ppm 6 = 200 ppm 7 = 600 ppm 8 = 2000 ppm 9 = 6000 ppm 10 = 20000 ppm 1 Register 0x00A2 LOL Timer Enable Reg Address Bit Field Type Name 0x00A2 1 R/W LOL_TIMER_EN Description 0 to disable 1 to enable LOL_TIMER_EN extends the time after LOL negates that the clock outputs can be disabled by LOL_CLR_DELAY (see below). Register 0x00A8-0x00AC LOL Clear Delay Reg Address Bit Field Type Name 0x00A8 7:0 R/W LOL_CLR_DELAY 0x00A9 15:8 R/W LOL_CLR_DELAY 0x00AA 23:16 R/W LOL_CLR_DELAY 0x00AB 31:24 R/W LOL_CLR_DELAY 0x00AC 34:32 R/W LOL_CLR_DELAY Description 35-bit value The LOL Clear Delay value is set by ClockBuilder Pro. Register 0x00E2 160 Reg Address Bit Field Type 0x00E2 7:0 R Name Description ACTIVE_NVM_BANK Read-only field indicating number of user bank writes carried out so far. Value Description 0 zero 3 one 15 two 63 three Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x00E3 Reg Address Bit Field Type Name Description 0x00E3 7:0 R/W NVM_WRITE Write 0xC7 to initiate an NVM bank burn. Description See "4.3. NVM Programming" on page 16. Register 0x00E34 Reg Address Bit Field Type Name 0x00E4 0 S NVM_READ_BANK 1 to download NVM. When set, this bit will read the NVM down into the volatile memory. Register 0x00FE Device Ready Reg Address Bit Field Type Name 0x00FE 7:0 R DEVICE_READY Description 0x0F when device is ready 0xF3 when device is not ready Read-only byte to indicate when the device is ready to accept serial bus writes. The user can poll this byte starting at power-on; when DEVICE_READY is 0x0F the user can safely read or write to any other register. This is only needed after power up or after a hard reset using register bit 0x001E[1] or during a bank burn (register 0x0-E3). The “Device Ready” register is available on every page in the device at the second last register, 0xFE. There is a device ready register at 0x00FE, 0x01FE, 0x02FE, … etc. Rev. 1.0 161 Si5342 Si5345-44-42-RM 14.5.2. Page 1 Registers Si5342 Register 0x0102 Global OE Gating for all Clock Output Drivers Reg Address Bit Field Type Name Description 0x0102 0 R/W OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables all output drivers Register 0x0112 Clock Output Driver 0 and R-Divider 0 Configuration Reg Address Bit Field Type Name Description 0x0112 0 R/W OUT0_PDN Output driver 0: 0 to power up the regulator, 1 to power down the regulator. Clock outputs will be weakly pulled-low. 0x0112 1 R/W OUT0_OE Output driver 0: 0 to disable the output, 1 to enable the output 0x0112 2 R/W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0113 Output 0 Format Reg Address 0x0113 Bit Field 2:0 Type R/W Name OUT0_FORMAT 0x0113 3 R/W OUT0_SYNC_EN 0x0113 5:4 R/W OUT0_DIS_STATE 0x0113 7:6 R/W OUT0_CMOS_DRV See "6.2. Performance Guidelines for Outputs" on page 32. 162 Rev. 1.0 Description 0 Reserved 1 swing mode (normal swing) differential 2 swing mode (high swing) differential 3 rail to rail swing mode differential 4 LVCMOS single ended 5–7 reserved 0 disable 1 enable Enable/disable synchronized (glitchless) operation. When enabled, the power down and output enables are synchronized to the output clock. Determines the state of an output driver when disabled, selectable as Disable low (0), Disable high (1), High impedance. (2) In high-impedance mode the differential driver will output the common mode voltage and no signal. LVCMOS output impedance. Selectable as CMOS1,CMOS2, CMOS3. Si5342 Si5345-44-42-RM Register 0x0114 Output 0 Swing and Amplitude Reg Address Bit Field Type Name Description 0x0114 3:0 R/W OUT0_CM Output common mode voltage adjustment Programmable swing mode with normal swing configuration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5V if VDDO=2.5 V Range = 0.5 V to 0.9V if VDDO=1.8 V Programmable swing mode with high0 swing configuration: Step size = 100 mV Range = 0.9 V to 2.3 V if VDDO = 3.3 V Range = 0.6 V to 1.5 V if VDDO = 2.5 V Range = 0.5 V to 0.9 V if VDDO = 1.8 V Rail-to-rail swing Mode configuration: No flexibility DRV0_CM = 6 if VDDO = 3.3 V (Vcm = 1.5 V) DRV0_CM = 10 if VDDO = 2.5 V (Vcm = 1.1 V) DRV0_CM = 13 if VDDO = 1.8 V (Vcm = 0.8 V) LVCMOS mode: Not supported/No effect 0x0114 6:4 R/W OUT0_AMPL Output swing adjustment Programmable swing mode with normal swing configuration: Step size = 100 mV Range = 100 mVpp-se to 800 mVpp-se Programmable swing mode with high swing configuration: Step size = 200 mV Range = 200 mVpp-se to 1600 mVpp-se Rail-to-rail swing mode: Not supported/No effect LVCMOS mode: Not supported/No effect See the settings and values from Table 24 for details of the settings. ClockBuilder Pro is used to select the correct settings for this register. Rev. 1.0 163 Si5342 Si5345-44-42-RM Register 0x0115 R-Divider 0 Mux Selection Reg Address Bit Field Type Name 0x0115 1:0 R/W OUT0_MUX_SEL 0x0115 7:6 R/W OUT0_INV Description Output driver 0 input mux select.This selects the source of the multisynth. 0: N0 1: N1 2: reserved 3: reserved 4: reserved 5: reserved 6: reserved 7: reserved CLK and CLK not inverted CLK inverted CLK and CLK inverted CLK inverted Each output can be configured to use Multisynth N0-N1 divider. The frequency for each N-divider is set in registers 0x0302–0x0316 for N0 to N1. Two different frequencies can be set in the N-dividers (N0–N1) and each of the 2 outputs can be configured to any of the 2 different frequencies. The 2 output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other output driver. Table 52. Registers that Follow the Same Definition as Above Register Address Description (Same as) Address 0x0117 Clock Output Driver 1 Config 0x0112 0x0118 Clock Output Driver 1 Format, Sync 0x0113 0x0119 Clock Output Driver 1 Ampl, CM 0x0114 0x011A OUT1_MUX_SEL, OUT1_INV 0x0115 Register 0x0145 Power Down All Reg Address Bit Field Type Name 0x0145 0 R/W OUT_PDN_ALL 164 Rev. 1.0 Description 0- no effect 1- all drivers powered down Si5342 Si5345-44-42-RM 14.5.3. Page 2 Registers Si5342 Register 0x0202-0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name 0x0202 7:0 R/W XAXB_FREQ_OFFSET 0x0203 15:8 R/W XAXB_FREQ_OFFSET 0x0204 23:16 R/W XAXB_FREQ_OFFSET 0x0205 31:24 R/W XAXB_FREQ_OFFSET Description 32 bit offset adjustment The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The XAXB_FREQ_OFFSET word is used to adjust this frequency reference with high resolution. ClockBuilder Pro calculates the correct values for these registers. Register 0x0206 Pre-scale Reference Divide Ratio Reg Address Bit Field Type Name 0x0206 1:0 R/W PXAXB Description Sets the prescale divider for the input clock on XAXB. This can only be used with an external clock source, not with crystals. 0 = pre-scale value 1 1 = pre-scale value 2 2 = pre-scale value 4 3 = pre-scale value 8 Register 0x0208-0x020D P0 Divider Numerator Reg Address Bit Field Type Name 0x0208 7:0 R/W P0_NUM 0x0209 15:8 R/W P0_NUM 0x020A 23:16 R/W P0_NUM 0x020B 31:24 R/W P0_NUM 0x020C 39:32 R/W P0_NUM 0x020D 47:40 R/W P0_NUM Description 48-bit Integer Number This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2. ClockBuilder Pro calculates the correct values for the P-dividers. Rev. 1.0 165 Si5342 Si5345-44-42-RM Register 0x020E-0x0211 P0 Divider Denominator Reg Address Bit Field Type Name 0x020E 7:0 R/W P0_DEN 0x020F 15:8 R/W P0_DEN 0x0210 23:16 R/W P0_DEN 0x0211 31:24 R/W P0_DEN Description 32-bit Integer Number The P1-P3 divider numerator and denominator follow the same format as P0 described above. ClockBuilder Pro calculates the correct values for the P-dividers. Table 53. Registers that Follow the P0_NUM and P0_DEN Definitions Register Address Description Size Same as Address 0x0212-0x0217 P1 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0218-0x021B P1 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x021C-0x0221 P2 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x0222-0x0225 P2 Divider Denominator 32-bit Integer Number 0x020E-0x0211 0x0226-0x022B P3 Divider Numerator 48-bit Integer Number 0x0208-0x020D 0x022C-0x022F P3 Divider Denominator 32-bit Integer Number 0x020E-0x0211 This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2, “Si5342 DSPLL and Multisynth System Flow Diagram,” on page 11. ClockBuilder Pro calculates the correct values for the P-dividers. Register 0x024A-0x024C R0 Divider Reg Address Bit Field Type Name 0x024A 7:0 R/W R0_REG 0x024B 15:8 R/W R0_REG 0x024C 23:16 R/W R0_REG Description A 24 bit integer divider. Divide value = (R0_REG+1) x 2 To set R0 = 2, set OUT0_RDIV_FORCE2 = 1, and then the R0_REG value is irrelevant. The R dividers are at the output clocks and are purely integer division. The R1divider follow the same format as the R0 divider described above. Table 54. Registers that Follow the R0_REG 166 Register Address Description Size Same as Address 0x024D-0x024F R1 Divider 24-bit Integer Number 0x024A-0x024C Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x026B-0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B 7:0 R/W DESIGN_ID0 0x026C 15:8 R/W DESIGN_ID1 0x026D 23:16 R/W DESIGN_ID2 0x026E 31:24 R/W DESIGN_ID3 0x026F 39:32 R/W DESIGN_ID4 0x0270 47:40 R/W DESIGN_ID5 0x0271 55:48 R/W DESIGN_ID6 0x0272 63:56 R/W DESIGN_ID7 ASCII encoded string defined by CBPro user, with user defined space or null padding of unused characters. A user will normally include a configuration ID + revision ID. For example, “ULT.1A” with null character padding sets: DESIGN_ID0: 0x55 DESIGN_ID1: 0x4C DESIGN_ID2: 0x54 DESIGN_ID3: 0x2E DESIGN_ID4: 0x31 DESIGN_ID5: 0x41 DESIGN_ID6:0x 00 DESIGN_ID7: 0x00 Register 0x0278-0x027C OPN Identifier Reg Address Bit Field Type Name 0x0278 7:0 R/W OPN_ID0 0x0279 15:8 R/W OPN_ID1 0x027A 23:16 R/W OPN_ID2 0x027B 31:24 R/W OPN_ID3 0x027C 39:32 R/W OPN_ID4 Description OPN unique identifier. ASCII encoded. For example, with OPN: 5342C-A12345-GM, 12345 is the OPN unique identifier, which sets: OPN_ID0: 0x31 OPN_ID1: 0x32 OPN_ID2: 0x33 OPN_ID3: 0x34 OPN_ID4: 0x35 Part numbers are of the form: Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID> Examples: Si5342C-A12345-GM. Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file. Si5342C-A-GM. Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5342 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro. Rev. 1.0 167 Si5342 Si5345-44-42-RM 14.5.4. Page 3 Registers Si5342 Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 7:0 R/W N0_NUM 0x0303 15:8 R/W N0_NUM 0x0304 23:16 R/W N0_NUM 0x0305 31:24 R/W N0_NUM 0x0306 39:32 R/W N0_NUM 0x0307 43:40 R/W N0_NUM 44-bit Integer Number The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder Pro calculates the correct values for the N-dividers. Register 0x0308-0x030B N0 Denominator Reg Address Bit Field Type Name Description 0x0308 7:0 R/W N0_DEN 0x0309 15:8 R/W N0_DEN 0x030A 23:16 R/W N0_DEN 0x030B 31:24 R/W N0_DEN Reg Address Bit Field Type Name 0x030C 0 R/W N0_UPDATE 32-bit Integer Number Register 0x0338 Description Set this bit to update the N0 divider This bit is provided so that all of the N0 divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Table 55. Register that Follows the N0_NUM and N0_DEN Definitions 168 Register Address Description Size Same as Address 0x030D-0x0312 N1 Numerator 44-bit Integer Number 0x0302-0x0307 0x0313-0x0316 N1 Denominator 32-bit Integer Number 0x0308-0x030B Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x03017 Reg Address Bit Field Type Name Description 0x03017 0 R/W N1_UPDATE Set this bit to update the N1 divider This bit is provided so that all of the N1 divider bits can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Register 0x0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338 1 R/W N_UPDATE_ALL Set this bit to update both N dividers This bit is provided so that both of the N dividers can be changed at the same time. First, write all of the new values to the divider, then set the update bit. Register 0x0339 FINC/FDEC Masks Reg Address Bit Field Type Name 0x0339 1:0 R/W N_FSTEP_MSK Bit Bit Description 0 to enable FINC/FDEC updates 1 to disable FINC/FDEC updates 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0] 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1] Register 0x033B-0x0340 N0 Frequency Step Word Reg Address Bit Field Type Name Description 0x033B 7:0 R/W N0_FSTEPW 0x033C 15:8 R/W N0_FSTEPW 0x033D 23:16 R/W N0_FSTEPW 0x033E 31:24 R/W N0_ FSTEPW 0x033F 39:32 R/W N0_ FSTEPW 0x0340 43:40 R/W N0_ FSTEPW 44-bit Integer Number This is a 44-bit integer value which is directly added or subtracted from the N-divider. ClockBuilder Pro calculates the correct values for the N0 Frequency Step Word. Each N divider has the ability to add or subtract up to a 44-bit value. Changing any of the Nx_DELAY values requires a SOFT_RST, a HARD_RST, or a power up sequence. Table 56. Registers that Follow the N0_FSTEPW Definition Register Address Description Size Same as Address 0x0341-0x0346 N1 Frequency Step Word 44-bit Integer Number 0x033B-0x0340 Rev. 1.0 169 Si5342 Si5345-44-42-RM Register 0x0359–0x035A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 7:0 R/W N0_DELAY[7:0] 8-bit Integer delay portion 0x035A 7:0 R/W N0_DELAY[7:0] Upper byte of N0_DELAY[15:0] Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynthx. The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive and negative delay is ±(215– 1)/(256 x Fvco). ClockBuilder Pro calculates the correct value for this register. Changing any of the Nx_DELAY values requires a SOFT_RST, a HARD_RST, or a power up sequence. Table 57. Registers that Follow the N0_DELAY Definition 170 Register Address Description Size Same as Address 0x035B N1 Delay Integer 8-bit Integer Number 0x0359 0x035C N1 Delay Fractional 8-bit Integer Number 0x035A Rev. 1.0 Si5342 Si5345-44-42-RM 14.5.5. Page 4 Registers Si5342 Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name 0x0487 0 R/W ZDM_EN 0x0487 2:1 R/W ZDM_IN_SEL Description 0 to disable ZD mode 1 to enable ZD mode Clock input select when in ZD. 0 for IN0, 1 for IN1,2 for IN2, 3 reserved This register is used for enabling the zero delay mode (ZDM) and selecting the source. The phase difference between the output, which is connected to the selected input below will be nulled to zero. When in zero delay mode, the DSPLL cannot have either hitless or automatic switching. In addition, the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins. Pin controlled clock selection is available in ZD mode (see register 0x052A). Rev. 1.0 171 Si5342 Si5345-44-42-RM 14.5.6. Page 5 Registers Si5342 Register 0x0507 Reg Address Bit Field Type Name 0x0507 7,6 R IN_ACTV Description Current input clock. These bits indicate which input clock is currently selected. 0 for IN0, 1 for IN1, etc. Register 0x0508-0x050D Loop Bandwidth Reg Address Bit Field Type Name Description 0x0508 7:0 R/W BW0_PLL PLL bandwidth parameter 0x0509 15:8 R/W BW1_PLL PLL bandwidth parameter 0x050A 23:16 R/W BW2_PLL PLL bandwidth parameter 0x050B 31:24 R/W BW3_PLL PLL bandwidth parameter 0x050C 39:32 R/W BW4_PLL PLL bandwidth parameter 0x050D 47:40 R/W BW5_PLL PLL bandwidth parameter This group of registers determine the loop bandwidth for the DSPLL. It is selectable as 0.1 Hz, 1 Hz, 4 Hz, 10 Hz, 40 Hz, 100 Hz, 400 Hz, 1 kHz, and 4 kHz. The loop BW values are calculated by ClockBuilder Pro and are written into these registers. The BW_UPDATE_PLL bit (reg 0x0514[0]) must be set to cause the BWx_PLL parameters to take effect. Register 0x050E-0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Description 0x050E 7:0 R/W FAST_BW0_PLL PLL fast bandwidth parameter 0x050F 15:8 R/W FAST_BW1_PLL PLL fast bandwidth parameter 0x0510 23:16 R/W FAST_BW2_PLL PLL fast bandwidth parameter 0x0511 31:24 R/W FAST_BW3_PLL PLL fast bandwidth parameter 0x0512 39:32 R/W FAST_BW4_PLL PLL fast bandwidth parameter 0x0513 47:40 R/W FAST_BW5_PLL PLL fast bandwidth parameter 0x0514 0 S BW_UPDATE_PLL Must be set to 1 to update the BWx_PLL and FAST_BWx_PLL parameters The fast lock loop BW values are calculated by ClockBuilder Pro and used when fast lock is enabled. 172 Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x0515-0x051B M Divider Numerator, 56-bits Reg Address Bit Field Type Name 0x0515 7:0 R/W M_NUM 0x0516 15:8 R/W M_NUM 0x0517 23:16 R/W M_NUM 0x0518 31:24 R/W M_NUM 0x0519 39:32 R/W M_NUM 0x051A 47:40 R/W M_NUM 0x051B 55:48 R/W M_NUM Description 56-bit Number Register 0x051C-0x051F M Divider Denominator, 32-bits Reg Address Bit Field Type Name 0x051C 7:0 R/W M_DEN 0x051E 15:8 R/W M_DEN 0x051E 23:16 R/W M_DEN 0x051F 31:24 R/W M_DEN Description 32-bit Number The loop M divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers. Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name 0x0520 0 R/W M_UPDATE Description Set this bit to update the M divider. Register 0x052A Input Clock Select Reg Address Bit Field Type Name 0x052A 0 R/W IN_SEL_REGCTRL 0x052A 2:1 R/W IN_SEL Description 0 for pin controlled clock selection 1 for register controlled clock selection 0 for IN0, 1 for IN1, 2 for IN2, 3 for IN3 (or FB_IN) Input clock selection for manual register based and pin controlled clock selection. Note: when ZDM_EN (0x0487, bit 0) and IN_SEL_REGCTRL are both high, IN_SEL does not do anything and the clock selection is pin controlled. When IN_SEL_REGCTRL is low, IN_SEL does not do anything and the clock selection is pin controlled. Rev. 1.0 173 Si5342 Si5345-44-42-RM Register 0x052B Fast Lock Control Reg Address Bit Field Type Name Description 0x052B 0 R/W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN = 0 (see below): 0 to enable auto fast lock when the DSPLL is out of lock 1 to disable auto fast lock 0x052B 1 R/W FASTLOCK_MAN 0 for normal operation (see above) 1 to force fast lock When in fast lock, the fast lock loop BW can be automatically used. Register 0x052C Holdover Exit Control Reg Address Bit Field Type Name 0x052C 3 R/W HOLD_RAMP_BYP 0x052C 4 R/W HOLD_EXIT_BW_SEL Description Must be set to 1 for normal operation. 0 to use the fastlock loop BW when exiting from holdover 1 to use the normal loop BW when exiting from holdover Register 0x052E Holdover History Average Length Reg Address Bit Field Type Name Description 0x052E 4:0 R/W HOLD_HIST_LEN 5-bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The average frequency is then used as the holdover frequency. Register 0x052F Holdover History Delay Reg Address Bit Field Type Name 0x052F 4:0 R/W HOLD_HIST_DELAY Description The most recent input frequency perturbations can be ignored during entry into holdover. The holdover logic pushes back into the past, above the averaging window. The amount that the average window is delayed is the holdover history delay. 174 Rev. 1.0 Si5342 Si5345-44-42-RM Register 0x0535 Force Holdover Reg Address Bit Field Type Name 0x0535 0 R/W FORCE_HOLD Description 0 for normal operation 1 for force holdover Register 0x0536 Input Clock Switching Control Reg Address Bit Field Type Name Description 0x0536 1:0 R/W CLK_SWTCH_MODE 0x0536 2 R/W HSW_EN 0 = manual 1 = automatic/non-revertive 2 = automatic/revertive 3 = reserved 0 glitchless switching mode (phase buildout turned off) 1 hitless switching mode (phase buildout turned on) Register 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3:0 R/W IN_LOS_MSK For each clock input LOS alarm: 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7:4 R/W IN_OOF_MSK For each clock input OOF alarm: 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic This register is for the input clock switch alarm masks. For each of the four clock inputs, the OOF and/or the LOS alarms can be used for the clock selection logic or they can be masked from it. Note that the clock selection logic can affect entry into holdover. Rev. 1.0 175 Si5342 Si5345-44-42-RM Register 0x0538 Clock Inputs 0 and 1 Priority Reg Address Bit Field Type Name Description 0x0538 2:0 R/W IN0_PRIORITY The priority for clock input 0 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0538 6:4 R/W IN1_PRIORITY The priority for clock input 1 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3. Register 0x0539 Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Name Description 0x0539 2:0 R/W IN2_PRIORITY The priority for clock input 2 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6:4 R/W IN3_PRIORITY The priority for clock input 3 is: 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved This register is used to assign a priority to an input clock for automatic clock input switching. The available clock with the lowest priority level will be selected. When input clocks are assigned the same priority, they will use the following default priority list: 0, 1, 2, 3. 176 Rev. 1.0 Si5342 Si5345-44-42-RM 14.5.7. Page 9 Registers Si5342 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name 0x090E 0 R/W XAXB_EXTCLK_EN Description 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I/O Voltage Select Reg Address Bit Field Type Name 0x0943 0 R/W IO_VDD_SEL Description 0 for 1.8 V external connections 1 for 3.3 V external connections The IO_VDD_SEL configuration bit selects the option of operating the serial interface voltage thresholds from the VDD or the VDDA pin. The serial interface pins are always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is operating at 3.3 V and the Si5345/44/42 at VDD = 1.8 V, the host must write the IO_VDD_SEL configuration bit to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds. Register 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Name Description 0x0949 3:0 R/W IN_EN 0: Disable and Powerdown Input Buffer. 1: Enable Input Buffer for IN3–IN0. 0x0949 7:4 R/W IN_PULSED_CMOS_EN 0: Standard Input Format. 1: Pulsed CMOS Input Format for IN3– IN0. See "5. Clock Inputs" on page 19 for more information. When a clock input is disabled, it is powered down. Input 0 corresponds to IN_SEL 0x0949 [0], IN_PULSED_CMOS_EN 0x0949 [4] Input 1 corresponds to IN_SEL 0x0949 [1], IN_PULSED_CMOS_EN 0x0949 [5] Input 2 corresponds to IN_SEL 0x0949 [2], IN_PULSED_CMOS_EN 0x0949 [6] Input 3 corresponds to IN_SEL 0x0949 [3], IN_PULSED_CMOS_EN 0x0949 [7] Rev. 1.0 177 Si5342 Si5345-44-42-RM 14.5.8. Page A Registers Si5342 Register 0x0A03 Output Multisynth Clock to Output Driver Reg Address Bit Field Type 0x0A03 1:0 R/W Name Description N_CLK_TO_OUTX_EN Routes Multisynth outputs to output driver muxes. Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 1:0 R/W N_PIBYP Output Multisynth integer divide mode. Bit 0 for ID0, Bit 1 for ID1, etc. 0: Nx divider is fractional. 1: Nx divider is integer. Register 0x0A05 Output Multisynth Divider Power Down Reg Address Bit Field Type Name 0x0A05 1:0 R/W N_PDNB 178 Rev. 1.0 Description Powers down the N dividers. Set to 0 to power down unused N dividers. Must set to 1 for all active N dividers. See also related registers 0x0A03 and 0x0B4A. Si5342 Si5345-44-42-RM 14.5.9. Page B Registers Si5342 Register 0x0B44 Output Multisynth Clock to Output Driver Reg Address Bit Field Type Name Description 0x0B44 3:0 R/W PDIV_FRACN_CLK_DIS Disable digital clocks to input P (IN0–3) fractional dividers. 0x0B44 5 R/W FRACN_CLK_DIS_PLL Disable digital clock to M fractional divider. Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type 0x0B4A 1:0 R/W Name Description N_CLK_DIS Disable digital clocks to N dividers. Must be set to 0 to use each N divider. See also related registers 0x0A03 and 0x0A05. Rev. 1.0 179 Si5345-44-42-RM APPENDIX A—SETTING THE DIFFERENTIAL OUTPUT DRIVER TO NON-STANDARD AMPLITUDES In some applications it may be desirable to have larger or smaller differential amplitudes than produced by the standard LVPECL and LVDS settings, as selected by CBPro. In these cases, the following information describes how to implement these amplitudes by writing to the OUTx_CM and OUTx_AMPL setting names. Contact Silicon Labs for assistance if you want your custom configured device to be programmed for any of the settings in this appendix. The differential output driver has a variable output amplitude capability and 2 basic formats, normal and low power format. The difference between these two formats is that the normal format has an output impedance of ~100 ohms differential and the low power format has an output impedance of > 500 ohms differential. Note that the rise/fall time is slower when using the Low Power Differential Format. See the Si5345/44/42 data sheet for the rise/fall time specifications. If the standard LVDS or LVPECL compatible output amplitudes will not work for a particular application, the variable amplitude capability can be used to achieve higher or lower amplitudes. For example, a “CML” format is sometimes desired for an application. However, CML is not a defined standard and hence the amplitude of a CML signal for one receiver may be different than that of another receiver. When the output amplitude needs to be different than standard LVDS or LVPECL, the Common Mode Voltage settings must be set as shown in Table 58. No settings other than the ones in Table 58 are supported as the signal integrity could be compromised. In addition the output driver should be AC coupled to the load so that the common mode voltage of the driver is not affected by the load. Table 58. Output Differential Common Mode Voltage Settings 180 VDDOx (Volts) Differential Format OUTx_FORMAT Common Mode Voltage (Volts) OUTx_CM 3.3 Normal 0x1 2.0 0xB 3.3 Low Power 0x2 1.6 0x7 2.5 Normal 0x1 1.3 0xC 2.5 Low Power 0x2 1.1 0xA 1.8 Normal 0x1 0.8 0xD 1.8 Low Power 0x2 0.8 0xD Rev. 1.0 Si5345-44-42-RM The differential amplitude can be set as shown in Table 59. Table 59. Typical Differential Amplitudes OUTx_AMPL Normal Differential Format (Vpp SE mV–Typical) Low Power Differential Format (Vpp SE mV – Typical) 0 130 200 1 230 400 2 350 620 3 450 820 4 575 1010 5 700 1200 6 810 13501 7 920 16001 Notes: 1. In low power mode and VDDOx=1.8V, OUTx_AMPL may not be set to 6 or 7. 2. These amplitudes are based upon a 100 ohm differential termination. See the register map portion of this document for additional information about OUTx_FORMAT, OUTx_CM and OUTx_AMPL. Contact Silicon Labs for assistance at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx if you require a factory-programmed device to be configured for any of the output driver settings in this appendix. Rev. 1.0 181 Si5345-44-42-RM DOCUMENT CHANGE LIST Revision 0.95 to Revision 1.0 Revision 0.1 to Revision 0.2 Updated “11.2. Recommended Crystals”. Updated Table 34. Revision 0.2 to Revision 0.95 Added “3.1. Dividers”. Added “4.2. Dynamic PLL Changes”. Update “5.2. Types of Inputs”. Updated Figure 7, “Input Termination for Standard and Pulsed CMOS Inputs,” on page 21. Updated minimum input frequency for hitless switching when using fractional input P divider. Updated “6.3. Output Signal Format”. Updated “6.3.8. Recommended Differential Format Settings”. Corrected Updated section on dynamic PLL changes. Added page mode addressing information to “9. Serial interface”. Updated Figures 31, 32, 33, and 34 so that CSb high is properly shown as >2.0 SCLK periods in all places. Added description for register 0x000B I2C Address. Updated Figure 17. Updated Table 24. Updated “6.3.8. Output Driver Settings for LVPECL, LVDS, HCSL, and CML”. Fixed OUTx discrepancies for Si5344 and Si5342 registers. Clarified that LOS_XAXB only works on XA input, not XB input. Updated BW_UPDATE_PLL bit type to self-clearing (S) Updated HARD_RST bit type to self-clearing (S) Updated Register 0x0004 Device Grade description differential CM/Amplitude settings. Updated “9. Serial interface”. Added information on I2C_SEL, A1/SDO, and A0/CS pin connection when serial interface is not used. Updated “10. Field Programming”. Updated “13.3. Power Supply Sequencing”. Added “13.4. Grounding Vias”. Updated “14.1. Base vs. Factory Preprogrammed Devices”. Incremented device revision from 0 to 1 for Rev. B in Register 0x0005, “DEVICE_REV”. Added descriptions of registers 0x0520, 0x052C, 0x0A03, 0x0A04, 0x0A05, 0x0B44, and 0x0B4A. Added “ Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes”. See also the ClockBuilder Pro release notes for more information: www.silabs.com/Support%20Documents/Software/ ClockBuilder-Pro-README.pdf 182 Rev. 1.0 Si5345-44-42-RM CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: http://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. Rev. 1.0 183