Si5340/41 Reference Manual

U L T R A L O W J I T T E R, A NY - F R E QUE N C Y, A NY - O UTPUT
C LOCK G ENERATOR
Si5341, Si5340
F AMILY R EFERENCE M ANUAL
Rev. 1.1 9/15
Copyright © 2015 by Silicon Laboratories
Si5341-40-RM
Si5341-40-RM
TABLE O F C ONTENTS
Section
Page
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1. Work Flow Expectations with ClockBuilder Pro and the Register Map . . . . . . . . . . . .6
1.2. Family Product Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3. Available Software Tools and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1. Power Supply Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. NVM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. Inputs on XA/XB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1.1. Crystal on XA/XB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2. Clock Input on XA/XB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2. Clock Inputs on IN2, IN1, IN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3. Reference Input Selection (IN0, IN1, IN2, XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.4.1. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.2. Interrupt Pin (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2. Performance Guidelines for Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3. Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3.1. Differential Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2. Differential Amplitude Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3. Output Driver Settings for LVPECL, LVDS, HCSL, and CML . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5. LVCMOS Output Impedance And Drive Strength Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6. LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7. LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8. Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9. Output Driver State When Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10. Synchronous/Asynchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.11. Output Delay Control (Dt0 – Dt4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.12. Sync Pin (Synchronizing R Dividers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
23
24
25
26
26
26
27
28
29
30
6.4. Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Digitally Controlled Oscillator (DCO) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Using the N Dividers for DCO Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.1. DCO with Frequency Increment/Decrement Pins/Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.2. DCO with Direct Register Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2. Using the M Divider for DCO Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. Dynamic PLL Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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9. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2. SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. Field Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11. Recommended Crystals and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.1. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
11.2. Recommended Oscillator Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12. Crystal and Device Circuit Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.1. 64-Pin QFN Si5341 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.1.1. Si5341 Applications without a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.1.2. Si5341 Crystal Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.1.3. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.2. 44-Pin QFN Si5340 Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2.1. Si5340 Applications without a Crystal as the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2.2. Si5340 Crystal Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
13.1. Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.2. Power Supply Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.3. Grounding Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. Base vs. Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.1. “Base” Devices (also known as “Blank” devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.2. Factory Preprogrammed (Custom OPN) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15.1. Register Map Overview and Default Settings Values . . . . . . . . . . . . . . . . . . . . . . . 58
15.2. Si5341 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.2.1. Page 0 Registers Si5341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2. Page 1 Registers Si5341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.3. Page 2 Registers Si5341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.4. Page 3 Registers Si5341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.5. Page 9 Registers Si5341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.6. Page A Registers Si5341. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.7. Page B Registers Si5341. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
69
73
78
82
83
84
15.3. Si5340 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.3.1. Page 0 Registers Si5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.3.2. Page 1 Registers Si5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
15.3.3. Page 2 Registers Si5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15.3.4. Page 3 Registers Si5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.3.5. Page 9 Registers Si5340 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.3.6. Page A Registers Si5340. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
15.3.7. Page B Registers Si5340. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes . . . . 109
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
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Si5341-40-RM
L I S T OF F IGURES
Figure 1. Block Diagram Si5341/40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Si5341 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Si5340 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Crystal Resonator and External Reference Clock Connection Options . . . . . . . . . . 14
Figure 6. Terminations for Differential and Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. LOS and LOL Fault Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Interrupt Flags and Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Supported Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Example of Independently Configurable Path Delays . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. I2C/SPI Device Connectivity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. 7-bit I2C Slave Address Bit-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. I2C Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SPI Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Example Writing Three Data Bytes using the Write Commands . . . . . . . . . . . . . . 38
Figure 20. Example of Reading Three Data Bytes Using the Read Commands. . . . . . . . . . . 38
Figure 21. SPI “Set Address” Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing . . . . . . 39
Figure 23. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing . . . . . 40
Figure 24. SPI “Burst Data Write” Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. R1 (ESR) vs. C0 for 48 to 54 MHz Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. R1 (ESR) vs. C0 for 25 MHz Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. 64-pin Si5341 Crystal Layout Recommendations Top Layer (Layer 1) . . . . . . . . . 47
Figure 28. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) . . . . . . . . . . . . . 47
Figure 29. Crystal Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 30. Power Plane (Layer 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. Layer 5 Power Routing on Power Plane (Layer 5). . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 32. Ground Plane (Layer 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 33. Output Clock Layer (Layer 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 34. Bottom Layer Ground Flooded (Layer 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 35. Device Layer (Layer 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 36. Crystal Shield Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 37. Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 38. Power Plane and Clock Output Power Supply Traces (Layer 4) . . . . . . . . . . . . . . 53
Figure 39. Clock Input Traces (Layer 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 40. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) . . . . . . . . . 54
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L I S T OF TABLES
Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Reset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. NVM Programming Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Manual Input Selection Using IN_SEL[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Input Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Monitor Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Interrupt Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Example of Output Clock Frequency Sequencing Choice . . . . . . . . . . . . . . . . . . . . 20
Table 9. Output Signal Format Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Differential Output Voltage Swing (Amplitude) Control Registers . . . . . . . . . . . . . . 23
Table 11. Settings for LVDS, LVPECL, and HCSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Output Impedance and Drive Strength Selections . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. LVCMOS Drive Strength Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. LVCMOS Output Polarity Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Output Enable/Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Output Driver Disable State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Synchronous Disable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Output Crosspoint Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20. I2C/SPI Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. SPI Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. Recommended Oscillator Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. Register Map Paging Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 26. Registers for OUT1,2,3,4,5,6,7,8,9 as per above for OUT0 . . . . . . . . . . . . . . . . . . 70
Table 27. R Dividers for Outputs 1,2,3,4,5,6,7,8,9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 28. N1, N2, N3 Numerator and Denominators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 29. Frequency Step Word for N1, N2, N3, N4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 30. Registers for OUT1,2,3 as per OUT0 Above. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 31. R Dividers for Output 1,2,3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 32. N Dividers for N1, N2, N3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 33. Frequency Step Word for N1, N2, N3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 34. Output Differential Common Mode Voltage Settings. . . . . . . . . . . . . . . . . . . . . . . 109
Table 35. Typical Differential Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Rev. 1.1
5
Si5341-40-RM
1. Overview
The Si5341/40 Clock Generators combine MultiSynth™ technologies to enable any-frequency clock generation for
applications that require the highest level of jitter performance. These devices are programmable via a serial
interface with in-circuit programmable non-volatile memory (NVM) ensuring power up with a known frequency
configuration. Using patented MultiSynth™ technology, the Si5341/40 generates up to 10 unique clock
frequencies, each with 0 ppm frequency synthesis error. Each output clock has an independent VDDO reference
and selectable signal format, simplifying format/level translation. The loop filter is fully integrated on-chip
eliminating the risk of potential noise coupling associated with discrete solutions.The Si5341/40 is ideally suited for
simplifying clock tree design by minimizing the number of timing components required. The Si5341/40 supports
factory or in-circuit programmable non-volatile memory, enabling the device to power up in a user-specified
configuration. The default configuration may be overwritten at any time by reprogramming the device via I2C/SPI.
1.1. Work Flow Expectations with ClockBuilder Pro and the Register Map
This reference manual is to be used to describe all the functions and features of the parts in the product family with
register map details on how to implement them. It is important to understand that the intent is for customers to use
the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is
documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond
the scope of this document. Real-time changes to the frequency plan and other operating settings are supported
by the devices. However, describing all the possible changes are not a primary purpose of this document. Refer to
Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to
implement the most common, real-time frequency plan changes.
The primary purpose of the software is that it saves having to understand all the complexities of the device. The
software abstracts the details from the user to allow focus on the high level input and output configuration, making
it intuitive to understand and configure for the end application. The software walks the user through each step, with
explanations about each configuration step in the process to explain the different options available. The software
will restrict the user from entering an invalid combination of selections. The final configuration settings can be
saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory
preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by
viewing the settings in the register map described in this document.
1.2. Family Product Comparison
Table 1 lists a comparison of the different family members.
Table 1. Product Selection Guide
6
Part Number
Number of Inputs
Number of
Fractional Dividers
Number of Outputs
Package Type
Si5341
4
5
10
64-pin QFN
Si5340
4
4
4
44-pin QFN
Rev. 1.1
Si5341-40-RM
Si5341/40
IN_SEL[1:0]
IN0
IN1
PLL
XTAL
IN2
XA
OSC
XB
FB_IN
OUT0
Multi
Synth
OUT1
Multi
Synth
OUT2
Multi
Synth
OUT3
Multi
Synth
OUT4
Si5340
Multi
Synth
OUT5
OUT6
I2 C/ SPI
OUT7
Control/
Status
OUT8
OUT9
Si5341
NVM
Figure 1. Block Diagram Si5341/40
1.3. Available Software Tools and Support
ClockBuilder Pro is a software tool that is used for the Si5341/40 family and other product families, capable of
configuring the timing chip in an intuitive friendly step by step process. The software abstracts the details from the
user to allow focus on the high level input and output configuration, making it intuitive to understand and configure
for the end application. The software walks the user through each step, with explanations about each configuration
step in the process to explain the different options available. The software will restrict the user from entering an
invalid combination of selections. The final configuration settings can be saved, written to a device or written to the
EVB and a custom part number can be created. ClockBuilder Pro integrates all the datasheets, application notes
and information that might be helpful in one environment. It is intended that customers will use the software tool for
the proper configuration of the device. Register map descriptions are given in the document should not be the only
source of information for programming the device. The complexity of the algorithms is embedded in the software
tool.
Rev. 1.1
7
Si5341-40-RM
2. Functional Description
The Si5341/40 uses next generation MultiSynth™ technology to offer the industry’s most frequency-flexible, high
performance clock generator. The PLL locks to either an external crystal (XA/XB) or to an external input on XAXB,
IN0, IN1 or IN2. The input frequency (crystal or external input) is multiplied by the DSPLL and divided by the
MultiSynth™ stage (N divider) and R divider to any frequency in the range of 100 Hz to 712.5 MHz per output. The
phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is
to phase lock to the selected input and provide a common reference to all the output MultiSynth high-performance
fractional dividers (N). The high-resolution fractional MultiSynth™ dividers enables true any-frequency input to anyfrequency on any of the outputs. A crosspoint mux connects any of the MultiSynth divided frequencies to any of the
outputs drivers. Additional output integer dividers (R) provide further frequency division if required. The frequency
configuration of the device is programmed by setting the input dividers (P), the DSPLL feedback fractional divider
(M_NUM/M_DEN), the MultiSynth fractional dividers (N_NUM/N_DEN), and the output integer dividers (R). Silicon
Labs’ Clockbuilder Pro configuration utility determines the optimum divider values for any desired input and output
frequency plan.
The output drivers offer flexible output formats which are independently configurable on each of the outputs. This
clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable nonvolatile memory. The block diagram for the Si5341 is shown in Figure 2, and the block diagram for the Si5340 is
shown in Figure 3.
2.1. Dividers
There are five divider classes within the Si5341/40. See Figure 3 for a block diagram that shows all of these
dividers.

Wide range input dividers Pfb, P2, P1, P0
Only
integer divider values
is from 1 to 2^16-1
Since the input to the phase detector needs to be >= 10 MHz, the practical range is limited to ~75 on the high side.
Each divider has an update bit that must be written to cause a newly written divider value to take effect.
Range

Narrow range input divider Pxaxb
Only

divides by 1, 2, 4, 8
Feedback M divider
Ultra
low jitter in fractional and integer modes
divider
Integer or fractional divide values
44 bit numerator, 32 bit denominator
Practical range limited by phase detector range of 10-120 MHz and VCO range of 13500-14256 MHz
This divider has an update bit that must be written to cause a newly written divider value to take effect.
MultiSynth

Output N dividers
Ultra
low jitter in fractional and integer modes
divider
Integer or fractional divide values
44 bit numerator, 32 bit denominator
Min value is 10
Maximum value is 2^12-1
Each N divider has an update bit that must be written to cause a newly written divider value to take effect. In addition there
is a global update bit that when written updates all N dividers.
MultiSynth

Output R divider
Only
even integer divide values
value is 2
Maximum value is 2^25-2
Min
8
Rev. 1.1
VDDA
VDD
Si5341-40-RM
3
IN_SEL[1:0]
Si5341
Clock
Generator
IN0
÷P0
IN0
÷P1
÷P2
IN2
VDDO1
OUT1
OUT1
÷R2
VDDO2
OUT2
OUT2
÷R3
VDDO3
OUT3
OUT3
÷R4
VDDO4
OUT4
OUT4
÷R5
VDDO5
OUT5
OUT5
÷R6
VDDO6
OUT6
OUT6
÷R7
VDDO7
OUT7
OUT7
÷R8
VDDO8
OUT8
OUT8
÷R9
VDDO9
OUT9
OUT9
LPF
÷
Mn
Md
÷Pxaxb
XB
MultiSynth
N0n
N0d
t0
N1n
N1d
t1
N2n
N2d
t2
N
÷ 3n
N3d
t3
N4n
N4d
t4
÷
Zero Delay
Mode
FB_IN
÷
÷
÷Pfb
FB_IN
I2C_SEL
÷
NVM
RST
A0/CS
LOL
Status
Monitors
INTR
SPI/
I2C
Frequency
Control
FINC
XA
25MHz,
48-54MHz
XTAL
FDEC
OSC
SCLK
÷R1
OE
IN2
PD
SYNC
IN1
A1/SDO
÷R0
VDDO0
OUT0
OUT0
PLL
IN1
SDA/SDIO
Dividers/
Drivers
Figure 2. Si5341 Detailed Block Diagram
Rev. 1.1
9
Si5341-40-RM
Si5340
Clock
Generator
XA
OSC
XB
25MHz,
48-54MHz
XTAL
÷Pxaxb
PLL
IN0
LPF
÷P0
IN0
IN1
PD
÷P1
IN1
IN2
t0
÷R0
VDDO0
OUT0
OUT0
N1n
N1d
t1
÷R1
VDDO1
OUT1
OUT1
÷
N2n
N2d
t2
÷R2
VDDO2
OUT2
OUT2
÷
N3n
N3d
t3
÷R3
VDDO3
OUT3
OUT3
÷
N0n
N0d
÷
Md
÷
Mn
÷P2
IN2
Dividers/
Drivers
MultiSynth
IN_SEL[1:0]
Zero Delay
Mode
FB_IN
FB_IN
÷Pfb
SPI/
I2 C
Status
Monitors
NVM
Figure 3. Si5340 Detailed Block Diagram
10
Rev. 1.1
OE
SCLK
A0/CS
A1/SDO
I2C_SEL
SDA/SDIO
INTR
LOSXAB
LOL
VDDA
VDD
RST
3
Si5341-40-RM
3. Power-Up and Initialization
Figure 4 shows the power-up and initialization sequence Figure 4.
Hard Reset
bit asserted
Power-Up
RST
pin asserted
NVM download
Soft Reset
bit asserted
Initialization
Serial interface
ready
Figure 4. Power-Up and Initialization
3.1. Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and
configuration data from NVM and performs other initialization tasks. Communicating with the device through the
serial interface is possible once this initialization period is complete. No clocks will be generated until the
initialization is done. There are two types of resets available. A hard reset is functionally similar to a device powerup. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state
including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft
reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Table 2. Reset Registers
Register Name
Hex Address [Bit Field]
Function
Si5341
Si5340
HARD_RST
001E[1]
001E[1]
Performs the same function as power cycling the device. All
registers will be restored to their default values.
SOFT_RST
001C[0]
001C[0]
Performs a soft reset. Resets the device while it does not redownload the register configuration from NVM.
The Si541/40 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its
default register values from internal non-volatile memory (NVM). Application specific default configurations can be
written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to
NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8V) and VDDA
(3.3 V) pins.
Rev. 1.1
11
Si5341-40-RM
3.1.1. Power Supply Sequencing
If the output clocks do not need to have a specific phase/delay relationship between them the timing of the power
supplies coming up to full voltage is irrelevant. However, if the phase/delay of any output clock to any other output
clock is important, then the VDDO of the relevant clock output must come up to full voltage before VDD and VDDA
voltages are applied. See Section 4. Voltage can always be applied to the VDDS pin regardless of any output clock
alignment.
3.2. NVM Programming
Because the NVM can be written two times, it is important to configure the registers correctly before beginning the
NVM programming process. Once a new configuration has been written to NVM, the old configuration is no longer
accessible. Note: In-circuit programming is only supported over a temperature range of 0 to 80 °C.
The procedure for writing registers into NVM is as follows:
1. Ensure the part is configured correctly before proceeding.
2. Write 0xC7 to NVM_WRITE register.
3. Wait until DEVICE_READY = 0x0F
4. Set NVM_READ_BANK 0x00E4[0] ='1'.
5. Wait until DEVICE_READY = 0x0F.
6. Steps 4 and 5 can be replaced by simply powering down and then powering up the device.
Table 3. NVM Programming Registers
Register Name
Hex Address [Bit Field]
Function
Si5340
Si5341
ACTIVE_NVM_BANK
0x00E2[5:0]
0x00E2[5:0]
Identifies the active NVM bank.
NVM_WRITE
0x00E3[7:0]
0x00E3[7:0]
Initiates an NVM write when written with 0xC7.
NVM_READ_BANK
0x00E4[0]
0x00E4[0]
DEVICE_READY
0x00FE[7:0]
0x00FE[7:0]
12
Download register values with content stored in NVM.
Indicates that the device serial interface is ready to
accept commands.
Rev. 1.1
Si5341-40-RM
4. Supply Voltage
Three classes of supply voltages exist:
1. VDD=1.8V + –5%
2. VDDA=3.3V+ –5%
3. VDDO=1.8/2.5/3.3V + –5%
4. VDDS. A 1.0 uF cap is recommended for voltage bypass.
There is no requirement for power supply sequencing unless the output clocks are required to be aligned with each
other or if the outputs must have a specific delay relationship between them as defined by the Nx_DELAY bits. In
this case, the VDDO of each clock that needs to be aligned must be powered up before VDD and VDDA. If output
to output alignment is wanted but it is not possible to properly sequence the power supplies then the output clocks
can be aligned by asserting the SOFT_RST bit (register 0x001C[5]) or performing a hard reset (also downloads the
NVM again) by momentarily setting the RST pin low. VDDS has no effect upon the output clock alignment as it is
only used to power the LOSXAXBB and LOLB status outputs.
Rev. 1.1
13
Si5341-40-RM
5. Clock Inputs
The PLL in the Si5341/40 requires a clock at the XAXB or IN2, 1, 0 input pins or a clock from a crystal connected
across the XAXB pins.
5.1. Inputs on XA/XB
5.1.1. Crystal on XA/XB
An external standard crystal (XTAL) is connected to XA/XB when this input is configured as a crystal oscillator. A
crystal frequency of 25 MHz can be used although crystals in the frequency range of 48 MHz to 54 MHz are
recommended for the best jitter performance. Recommended crystals are listed below. The Si5341/40 includes a
built-in XTAL load capacitance (CL) of 8 pF, but crystals with CL specifications as high as 18 pF can also be used.
When using crystals with CL specs higher than 8 pf it is not generally recommended to use external capacitors
from XA/XB to ground to increase the crystal load capacitance. Rather the frequency offset due to CL mismatch
can be adjusted using the XAXB_FREQ_OFFSET word which allows frequency adjustments of up to ±1000 ppm.
See section “12. Crystal and Device Circuit Layout Recommendations” for the PCB layout guidelines.
5.1.2. Clock Input on XA/XB
An external clock can also be input on the XA/XB pins. Selection between the external crystal or clock is controlled
by register configuration. The internal crystal load capacitors (CL) are disabled in external clock mode. Because the
input buffer at XA/XB is a lower noise buffer than the buffers on IN2,1,0, a very clean input clock at XA/XB, such as
a very high quality TCXO or XO, will, in some cases, produce lower output clock jitter than the same input at
IN2,1,0. If the XAXB input is unused and powered down then the XA and XB inputs can be left floating. Note that
ClockBuilder Pro will power down the XAXB input if it is selected as “unused.” If XAXB is powered up but no input
is applied then the XA input should be left floating and the XB input must be connected directly to ground. Both a
single-ended or a differential clock can be connected to the XA/XB pins as shown in Figure 5.
Differential Connection
Single‐ended XO Connection
nc X1
nc X2
nc X1
nc X2
Note: 2.0 Vpp_se max
0.1 uf
50
2xCL
0.1 µf
XA
2xCL
XA
50
OSC
OSC
XB
XO with Clipped Sine Wave 0.1 µf XB
Output
2xCL
Si5341/40
0.1 uf
2xCL
Si5341/40
Note: 2.5 Vpp diff max
Crystal Connection
Single‐ended Connection
nc X1
nc X2
Note: 2.0 Vpp_se max
CMOS/XO Output
R1
X1
2xCL
0.1 µf
XA
OSC
XO VDD
3.3 V
2.5 V
1.8 V
R1
523 
475 
158 
R2
442 
649 
866 
R2
0.1 µf
2xCL
XA
0.1 µf
XTAL
OSC
XB
XB
2xCL
Si5341/40
X2
2xCL
Si5341/40
Figure 5. Crystal Resonator and External Reference Clock Connection Options
14
Rev. 1.1
Si5341-40-RM
5.2. Clock Inputs on IN2, IN1, IN0
A single ended or differential clock may be input to the IN2,1,0 inputs as shown below. All input signals must be accoupled. When INx (x=0,1,2) is unused and powered down the plus and minus input can be left floating.
ClockBuilder Pro will power down any INx input that is selected as “unused.” If any INx is powered up but does not
have any input signal then the plus input should be left floating and the minus input should be directly connected to
ground. If the plus input is left floating and the minus input is connected to ground with a 4.7K or smaller resistor,
then the INx can be powered up or down when it does not have an input. The recommended input termination
schemes are shown in Figure 6. Unused inputs can be disabled by register configuration.
AC Coupled Differential
0.1 uf
50
Si5341/40
INx
50
0.1 uf
50
Differential
Driver LVDS,
LVPECL, CML
INx
50
0.1 uf
AC Coupled LVCMOS or Single Ended
50
3.3V, 2.5V, 1.8V
LVCMOS or Single
Ended Signal
0.1 uf
Si5341/40
INx
0.1 uf
INx
Figure 6. Terminations for Differential and Single-Ended Inputs
Rev. 1.1
15
Si5341-40-RM
5.3. Reference Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL1,0 pins or by register control. The register bit
IN_SEL_REGCTRL determines input selection as pin or register selectable. If the selected input does not have a
clock, all output clocks will be shut off.
Table 4. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
Selected Input
0
0
IN0
0
1
IN1
1
0
IN2
1
1
XA/XB
Table 5. Input Control Registers
Register Name
Hex Address [Bit Field]
Si5341
16
Function
Si5340
XAXB_FREQ_OFFSET
0202[7:0]–0205[7:0]
Adjusts for crystal load capacitance mismatch causing
oscillation frequency errors up to ±1000 ppm. This word
is in 2’s complement format.
The XAXB_FREQ_OFFSET word is added to the M
divider numerator.
XAXB_EXTCLK_EN
090E[0]
Selects between the XTAL or external REFCLK on the
XA/XB pins
IN_SEL_REGCTRL
0021[0]
Determines pin or register clock input selection.
IN_SEL
0021[2:1]
Selects the input when in register input selection mode.
IN_EN
0949[3:0]
Allows enabling/disabling IN0, IN1, IN2 and FB_IN
when not in use.
Rev. 1.1
Si5341-40-RM
5.4. Fault Monitoring
The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB,
FB_IN) and loss of lock (LOL) for the PLL. This is shown in Figure 7.
IN0
÷P0
IN0
Si5341/40
LOS0
LOL
IN1
÷P1
IN1
LOS1
PLL
PD
IN2
÷P2
IN2
LPF
LOS2
÷
÷Pxaxb
÷Pfb
INTR
LOL
LOS0
LOSFB
LOSXAB
FB_IN
FB_IN
OSC
LOS2
XB
LOSXAXB
LOS1
XA
Mn
Md
Figure 7. LOS and LOL Fault Monitors
5.4.1. Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated
pin (LOL). Each of the status indicator register bits has a corresponding sticky bit (_FLG) in a separate register
location. Once a status bit is asserted its corresponding _FLG bit will remain asserted until cleared. Writing a logic
zero to a _FLG register bit clears its state.
Table 6. Status Monitor Bits
Setting Name
Status Register Bits
Hex Address [Bit Field]
Function
Si5341 and Si5340
SYSINCAL
0x000C[0]
Asserted when in calibration.
LOSXAXB
0x000C[1]
Loss of Signal at the XA input.
The Xb input does not have an LOS
detector.
LOSREF
0x000C[2]
Loss of Signal for the input that has
been selected.
LOL
0x000C[3]
Loss of Lock for the PLL.
SMBUS_TIMEOUT
0x000C[5]
The SMB bus has a timeout.
LOSIN[3:0]
0x000D[3:0]
Loss of Signal for the FB_IN, IN2,
IN1, IN0 inputs.
Rev. 1.1
17
Si5341-40-RM
Table 6. Status Monitor Bits (Continued)
Setting Name
Hex Address [Bit Field]
Function
SYSINCAL_FLG
0x0011[0]
Sticky bit for SYSINCAL
LOSXAXB_FLG
0x0011[1]
Sticky bit for LOSXAXBB
LOSREF_FLG
0x0011[2]
Sticky bit for LOSREF
LOL_FLG
0x0011[3]
Sticky bit for LOL
SMBUS_TIMEOUT_FLG
0x0011[5]
Sticky bit for SMBUS_TIMEOUT
LOSIN_FLG
0x0012[3:0]
Sticky bit for FB_IN, IN2, IN1, IN0
Sticky Status Register Bits
5.4.2. Interrupt Pin (INTR)
An interrupt pin (INTR) is asserted (low) whenever any of the unmasked _FLG bits are asserted. All _FLG bits are
maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by writing zeros to all _FLG
bits that are set or by writing a 1 to mask all _FLG bits that are set.
Table 7. Interrupt Mask Bits
Setting Name
Hex Address [Bit Field]
Function
Si5341 and Si5342
18
SYSINCAL_INTR_MSK
0x0017[0]
1 = SYSINCAL_FLG is prevented from asserting the INTR pin
LOSXAXB_INTR_MSK
0x0017[1]
1 = LOSXAXB_FLG is prevented from asserting the INTR pin
LOSREF_INTR_MSK
0x0017[2]
1 = LOSREF_FLG is prevented from asserting
the INTR pin
LOL_INTR_MSK
0x0017[3]
1 = LOL_FLG is prevented from asserting the
INTR pin
SMB_TMOUT_INTR_MSK
0x0017[5]
1 = SMBUS_TIMEOUT_FLG is prevented from
asserting the INTR pin
LOSIN _INTR_MSK[3:0]
0x0018[3:0]
1 = LOS_FLG is prevented from asserting the
INTR pin
Rev. 1.1
Si5341-40-RM
Figure 8. Interrupt Flags and Masks
Rev. 1.1
19
Si5341-40-RM
6. Output Clocks
6.1. Outputs
The Si5341 supports ten differential output drivers which can be independently configured as differential or
LVCMOS. The Si5340 supports four output drivers independently configurable as differential or LVCMOS.
6.2. Performance Guidelines for Outputs
Whenever a number of high frequency, fast rise time, large amplitude signals are all close to one another, the laws
of physics dictate that there will be some amount of crosstalk. The jitter of the Si5341/40 is so low that crosstalk
can become a significant portion of the final measured output jitter. Some of the source of the crosstalk will be the
Si5341/40 and some will be introduced by the PCB. It is difficult (and possibly irrelevant) to allocate the jitter
portions between these two sources because the jitter can only be measured when a Si5341/40 is mounted on a
PCB.
For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be
minimized by modifying the arrangements of different output clocks. For example, consider the following lineup of
output clocks in Table 8.
Table 8. Example of Output Clock Frequency Sequencing Choice
Output
Not Recommended (Frequency MHz)
Recommended (Frequency MHz)
0
155.52
155.52
1
156.25
155.52
2
155.52
622.08
3
156.25
Not used
4
200
156.25
5
100
156.25
6
622.08
625
7
625
Not used
8
Not used
200
9
Not used
100
Using this example, a few guidelines are illustrated:
1. Avoid adjacent frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock.
If the jitter integration bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart.
2. Adjacent frequency values that are integer multiples of one another are okay and these outputs should be
grouped accordingly. Noting that because 155.52 x 4 = 622.08 and 156.25 x 4 = 625, it is okay to place these
frequency values close to one another.
3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. In this
case, see OUT3 and OUT7.
If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that
the critical outputs are the least susceptible to crosstalk. These guidelines typically only need to be followed by
those applications that wish to achieve the highest possible levels of jitter performance. Because CMOS outputs
have large pk-pk swings and do not present a balanced load to the VDDO supplies, CMOS outputs generate much
more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided whenever possible.
When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines. It is highly
recommended to read “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure
Systems”.
20
Rev. 1.1
Si5341-40-RM
6.3. Output Signal Format
The differential amplitude is fully programmable covering a wide variety of signal formats including LVDS, LVPECL,
HCSL. For CML or non-standard amplitude applications, see "Appendix A—Setting the Differential Output Driver to
Non-Standard Amplitudes" on page 109. The common-mode voltage must be set as required for LVDS or LVPECL
or CML/non-standard amplitude levels. The differential formats can be either normal or low power. Low power
format uses less power for the same amplitude but has the drawback of slower rise/fall times. The source
impedance in low power format is much higher than 100 ohms. See Appendix A for register settings to implement
variable amplitude differential outputs. In addition to supporting differential signals, any of the outputs can be
configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of
differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential
outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not
on nearby pins. See AN862 “Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure
Systems” for additional information.
Table 9. Output Signal Format Control Registers
Setting Name
OUT0_FORMAT
OUT1_FORMAT
OUT2_FORMAT
OUT3_FORMAT
OUT4_FORMAT
OUT5_FORMAT
OUT6_FORMAT
OUT7_FORMAT
OUT8_FORMAT
OUT9_FORMAT
Hex Address [Bit Field]
Si5341
Si5340
0109[2:0]
010E[2:0]
0113[2:0]
0118[2:0]
011D[2:0]
0122[2:0]
0127[2:0]
012C[2:0]
0131[2:0]
013B[2:0]
0113[2:0]
0118[2:0]
0127[2:0]
012C[2:0]
—
—
—
—
—
—
Function
Selects the output signal format as normal differential, low
power differential, in phase CMOS or complementary
CMOS.
Rev. 1.1
21
Si5341-40-RM
6.3.1. Differential Output Terminations
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in Figure 9.
AC Coupled LVDS/LVPECL
DC Coupled LVDS
VDDO = 3.3 V, 2.5 V, 1.8 V
VDDO = 3.3 V, 2.5 V
OUTx
50
50
50
AC Coupled HCSL
AC Coupled LVPECL/CML
VDDRX
VDDO = 3.3 V, 2.5 V, 1.8 V
VDD – 1.3 V
R1
R1
VDDO = 3.3 V, 2.5 V
50
50
Standard
HCSL
Receiver
OUTx
50
R2
R2
OUTx
For VCM = 0.37V
VDDRX
3.3 V
2.5 V
1.8 V
50
OUTx
50
R1
R2
442 
56.2 
332 
59 
243 
63.4 
Si5341/40
Figure 9. Supported Differential Output Terminations
22
Internally
self-biased
Si5341/40
Si5341/40
Si5341/40
100
OUTx
100
OUTx
OUTx
50
OUTx
Rev. 1.1
50
Si5341-40-RM
6.3.2. Differential Amplitude Controls
The differential amplitude of each output can be controlled with the following registers. See Appendix A for register
settings for non-standard amplitudes.
Table 10. Differential Output Voltage Swing (Amplitude) Control Registers
Setting Name
OUT0_AMPL
OUT1_AMPL
OUT2_AMPL
OUT3_AMPL
OUT4_AMPL
OUT5_AMPL
OUT6_AMPL
OUT7_AMPL
OUT8_AMPL
OUT9_AMPL
Hex Address [Bit Field]
Si5341
Si5340
010A[6:4]
010F[6:4]
0114[6:4]
0119[6:4]
011E[6:4]
0123[6:4]
0128[6:4]
012D[6:4]
0132[6:4]
013C[6:4]
0114[6:4]
0119[6:4]
0128[6:4]
012D[6:4]
—
—
—
—
—
—
Function
Sets the voltage swing (amplitude) for the differential output
drivers when in Normal differential format and Low Power differential format (Table 11).
6.3.3. Output Driver Settings for LVPECL, LVDS, HCSL, and CML
Each differential output has four settings for control
1. Normal or Low Power Format
2. Amplitude (sometimes called Swing)
3. Common Mode Voltage
4. Stop High or Stop Low
The normal Format setting has a 100 ohm internal resistor between the plus and minus output pins. The Low
Power Format setting removes this 100 ohm internal resistor and then the differential output resistance will be
> 500 ohms. However as long as the termination impedance matches the differential impedance of the pcb traces
the signal integrity across the termination impedance will be good. For the same output amplitude the Low Power
Format will use less power than the Normal Format. The Low Power Format also has a lower rise/fall time than the
Normal Format. See the Si5341/40 data sheet for the rise/fall time specifications. For LVPECL and LVDS
standards, ClockBuilder Pro does not support the Low Power Differential Format. Stop High means that when the
output driver is disabled the plus output will be high and the minus output will be low. Stop Low means that when
the output driver is disabled the plus output will be low and the minus output will be high.
The Format, Amplitude and Common Mode settings for the various supported standards are shown in Table 11.
Rev. 1.1
23
Si5341-40-RM
Table 11. Settings for LVDS, LVPECL, and HCSL
OUTx_FORMAT
Standard
VDDO Volts
OUTx_CM
(Decimal)
OUTx_AMPL
(Decimal)
001 = Normal Differential
LVPECL
3.3
11
6
001 = Normal Differential
LVPECL
2.5
11
6
002 = Low Power Differential
LVPECL
3.3
11
3
002 = Low Power Differential
LVPECL
2.5
11
3
001 = Normal Differential
LVDS
3.3
3
3
001 = Normal Differential
LVDS
2.5
11
3
001 = Normal Differential
Sub-LVDS1
1.8
13
3
002 = Low Power Differential
LVDS
3.3
3
1
002 = Low Power Differential
LVDS
2.5
11
1
002 = Low Power Differential
Sub-LVDS1
1.8
13
1
002 = Low Power Differential
HCSL2
3.3
11
3
002 = Low Power Differential
HCSL2
2.5
11
3
002 = Low Power Differential
2
1.8
13
3
HCSL
Notes:
1. The common mode voltage produced is not compliant with LVDS standards, therefore AC coupling the driver to an
LVDS receiver is highly recommended.
2. Creates HCSL compatible signal. See Figure 9.
3. The low-power format will cause the rise/fall time to increase by approximately a factor of two. See the Si5341/40 data
sheet for more information.
The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes. See
Appendix A for additional information.
6.3.4. LVCMOS Output Terminations
LVCMOS outputs are dc coupled as shown in Figure 10.
DC Coupled LVCMOS
3.3V, 2.5V, 1.8V
LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
Rs
OUTx
50
Si5341/40
Rs
Figure 10. LVCMOS Output Terminations
24
Rev. 1.1
Si5341-40-RM
6.3.5. LVCMOS Output Impedance And Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive
strengths. A source termination resistor (Rs) is highly recommended to help match the selected output impedance
to the trace impedance (i.e. Rs ~= Trace Impedance - Zs). For the best signal integrity, Silicon Labs strongly
recommends using the setting that produces the lowest source impedance and then choosing the proper external
source resistor to produce the best signal shape at the end of the signal trace.
Table 12. Output Impedance and Drive Strength Selections
VDDO
OUTx_CMOS_DRV
Value Setting
Source Impedance (ZS)
3.3 V
0x01
38 
0x02
30 
0x03*
22 
0x01
43 
0x02
35 
0x03*
24 
0x02
46 
0x03*
31 
2.5 V
1.8 V
Note: This setting is strongly recommended.
Table 13. LVCMOS Drive Strength Control Registers
Setting Name
OUT0_CMOS_DRV
OUT1_CMOS_DRV
OUT2_CMOS_DRV
OUT3_CMOS_DRV
OUT4_CMOS_DRV
OUT5_CMOS_DRV
OUT6_CMOS_DRV
OUT7_CMOS_DRV
OUT8_CMOS_DRV
OUT9_CMOS_DRV
Hex Address [Bit Field]
Si5341
Si5340
0109[7:6]
010E[7:6]
0113[7:6]
0118[7:6]
011D[7:6]
0122[7:6]
0127[7:6]
012C[7:6]
0131[7:6]
013B[7:6]
0113[7:6]
0118[7:6]
0127[7:6]
012C[7:6]
—
—
—
—
—
—
Function
LVCMOS output impedance. See Table 12.
Rev. 1.1
25
Si5341-40-RM
6.3.6. LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output
driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
6.3.7. LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By
default the clock on the OUTx pin is generated with the opposite polarity (complementary) with the clock on the
OUTx pin. The polarity of these clocks is configurable enabling in-phase clock generation and/or inverted polarity
with respect to other output drivers.
Table 14. LVCMOS Output Polarity Control Registers
Setting Name
OUT0_INV
OUT1_INV
OUT2_INV
OUT3_INV
OUT4_INV
OUT5_INV
OUT6_INV
OUT7_INV
OUT8_INV
OUT9_INV
Hex Address [Bit Field]
Si5341
Si5340
010B[7:6]
0110[7:6]
0115[7:6]
011A[7:6]
011F[7:6]
0124[7:6]
0129[7:6]
012E[7:6]
0133[7:6]
0138[7:6]
0115[7:6]
011A[7:6]
0129[7:6]
012E[7:6]
—
—
—
—
—
—
Function
Controls output polarity of the OUTx and OUTx pins when in
LVCMOS mode. Selections are:
OUTx_INV
OUTx
OUTx
Comment
00
CLK
CLK
Complementary (default)
01
CLK
CLK
Both in phase
10
CLK
CLK
Inverted
11
CLK
CLK
Both out of phase
6.3.8. Output Enable/Disable
Clock outputs are disabled by four signals within Si5341/40 and the OEB pin:

OUTALL_DISABLE_LOW
 SYSINCAL
 OUTx_OE
 LOL
 OEB pin
Figure 11 shows the logic of how these disable/enables occur.
1 instance of this is used per output driver
LOL
OUTALL_DISABLE_LOW
Enable to Individual
Output Drivers
OEB Pin
OUTX_OE
SYSINCAL
OUTX_OE are the individual Output Driver enables as shown in the table below
Figure 11. Output Enable
26
Rev. 1.1
Si5341-40-RM
Table 15. Output Enable/Disable Control Registers
Setting Name
Hex Address [Bit
Field]
Si5341
OUTALL_DISABLE_LOW
OUT0_OE
OUT1_OE
OUT2_OE
OUT3_OE
OUT4_OE
OUT5_OE
OUT6_OE
OUT7_OE
OUT8_OE
OUT9_OE
Si5340
0102[0]
0108[1]
010D[1]
0112[1]
0117[1]
011C[1]
0121[1]
0126[1]
012B[1]
0130[1]
013A[1]
Function
0 = Disables all outputs.
1 = All outputs are not disabled by this signal but may be
disabled by other signals or the OEB pin. See Figure 11
above.
0112[1]
0117[1]
0126[1]
012B[1]
—
—
—
—
—
—
0 = Specific output disabled.
1 = Specific output is not disabled. The OEB pin or other
signals within the device may be causing an output disable.
See Figure 11 above.
6.3.9. Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low, disable high, or disable mid. When set for
disable mid, the output common mode voltage will stay nearly the same when disabled as when enabled.
Table 16. Output Driver Disable State Control Registers
Setting Name
OUT0_DIS_STATE
OUT1_DIS_STATE
OUT2_DIS_STATE
OUT3_DIS_STATE
OUT4_DIS_STATE
OUT5_DIS_STATE
OUT6_DIS_STATE
OUT7_DIS_STATE
OUT8_DIS_STATE
OUT9_DIS_STATE
Hex Address [Bit Field]
Si5341
Si5340
0109[5:4]
010E[5:4]
0113[5:4]
0118[5:4]
011D[5:4]
0122[5:4]
0127[5:4]
012C[5:4]
0131[5:4]
013B[5:4]
0113[5:4]
0118[5:4]
0127[5:4]
012C[5:4]
—
—
—
—
—
—
Function
Determines the state of an output driver when disabled. Selectable as:
 Disable logic low.
 Disable logic high
Rev. 1.1
27
Si5341-40-RM
6.3.10. Synchronous/Asynchronous Output Disable Feature
Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output
will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from
occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately
without waiting for the period to complete.
Table 17. Synchronous Disable Control Registers
Setting Name
OUT0_SYNC_EN
OUT1_SYNC_EN
OUT2_SYNC_EN
OUT3_SYNC_EN
OUT4_SYNC_EN
OUT5_SYNC_EN
OUT6_SYNC_EN
OUT7_SYNC_EN
OUT8_SYNC_EN
OUT9_SYNC_EN
28
Hex Address [Bit Field]
Si5341
Si5340
0109[3]
010E[3]
0113[3]
0118[3]
011D[3]
0122[3]
0127[3]
012C[3]
0131[3]
013B[3]
0113[3]
0118[3]
0127[3]
012C[3]
—
—
—
—
—
—
Function
When this bit is high, the output will turn on/off (enable/disable)
without generating runt pulses or glitches. The default for this
bit is high. When this bit is low, the outputs will turn on/off asynchronously. In this case there may be glitches on the output
when it turns on/off.
Rev. 1.1
Si5341-40-RM
6.3.11. Output Delay Control (t0 – t4)
The Si5341/40 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10
outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with
each of these dividers is available for applications that need a specific output skew configuration. This is useful for
PCB trace length mismatch compensation. The resolution of the phase adjustment is 1/(256 * FVCO) seconds
(FVCO in Hz) per step definable in a range of 32768/(256 * FVCO) (FVCO in Hz). The output delay controls (Dt0 –
Dt4) are register configurable. After the delay controls are configured, the soft reset bit SOFT_RST must be set
high.
÷N0
t0
÷R0
VDDO0
OUT0
OUT0
VDDO1
OUT1
OUT1
÷N1
t1
÷R1
÷N2
t2
÷R2
VDDO2
OUT2
OUT2
÷N3
t3
÷R3
VDDO3
OUT3
OUT3
÷N4
t4
÷R4
VDDO4
OUT4
OUT4
÷R5
VDDO5
OUT5
OUT5
÷R6
VDDO6
OUT6
OUT6
÷R7
VDDO7
OUT7
OUT7
÷R8
VDDO8
OUT8
OUT8
÷R9
VDDO9
OUT9
OUT9
Figure 12. Example of Independently Configurable Path Delays
All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default
values can be written to the NVM allowing a custom delay offset configuration at power-up or after a hardware
reset.
Here is an example:
If FVCO = 13.75 GHz and the desired delay is 3 ns and the desired output clock is connected to N0, then the
N0_DELAY would be calculated as the N0_DELAY=3e-9*256*13.75e9=10,560 decimal=2940 hex.
Rev. 1.1
29
Si5341-40-RM
Table 18. Delay Registers
Setting Name
Hex Address [Bit Field]
Si5341
Function
Si5340
N0_DELAY
0359[7:0] - 035A[7:0]
N1_DELAY
035B[7:0] - 035C[7:0]
N2_DELAY
035D[7:0] - 035E[7:0]
N3_DELAY
035F[7:0] - 0360[7:0]
N4_DELAY
0361[7:0] - 0362[7:0]
Configures path delay values for each N divider. For example, N0_DELAY is [0x035A[7:0] 0x0359[7:0]]. Each 16-bit
number is 2s complement. The output delay is Nx_DELAY/
(256 x FVCO) where FVCO is the frequency of the VCO in Hz
and the delay is in seconds. Note that the Si5340 does not
have N4_DELAY.
6.3.12. Sync Pin (Synchronizing R Dividers)
All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures
consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or
asserting the hard reset bit will have the same result. The SYNC pin provides another method of re-aligning the R
dividers without resetting the device. This pin is positive edge triggered. Asserting the sync register bit provides the
same function. Note that using the SYNC bit/pin guarantees that the outputs will align to within 50 ns.
6.4. Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the R dividers and output drivers. Note that
each output driver has a specific R divider that is permanently attached and has the same subscript in the name,
i.e., R3 and OUT3.
Table 19. Output Crosspoint Control Registers
Setting Name
OUT0_MUX_SEL
OUT1_MUX_SEL
OUT2_MUX_SEL
OUT3_MUX_SEL
OUT4_MUX_SEL
OUT5_MUX_SEL
OUT6_MUX_SEL
OUT7_MUX_SEL
OUT8_MUX_SEL
OUT9_MUX_SEL
Hex Address [Bit Field]
Si5341
Si5340
010B[2:0]
0110[2:0]
0115[2:0]
011A[2:0]
011F[2:0]
0124[2:0]
0129[2:0]
012E[2:0]
0133[2:0]
013D[2:0]
0115[2:0]
011A[2:0]
0129[2:0]
012E[2:0]
—
—
—
—
—
—
Function
Connects the output drivers to one of the N dividers. Selections are: N0, N1, N2, N3, N4 for each output divider.
6.5. Zero Delay Mode
Please contact Silicon Labs
contacttechnicalsupport.aspx.
30
for
support
of
this
Rev. 1.1
feature
at
https://www.silabs.com/support/pages/
Si5341-40-RM
7. Digitally Controlled Oscillator (DCO) Modes
An output that is controlled as a DCO is useful for simple tasks such as frequency margining, CPU speed control,
or just changing the output frequency. The output can also be used for more sophisticated tasks such as FIFO
management by adjusting the frequency of the read or write clock to the FIFO or using the output as a variable
Local Oscillator in a radio application.
7.1. Using the N Dividers for DCO Applications
The N dividers can be digitally controlled to so that all outputs connected to the N divider change frequency in real
time without any transition glitches. There are two ways to control the N divider to accomplish this task:
Use
the Frequency Increment/Decrement Pins or register bits.
directly to the numerator or denominator of the N divider.
The output N divider can be changed from its minimum value of 10 to its maximum value of 4095 in very small
fractional increments or a single very large increment. Each N divider has a value of Nx_NUM/Nx_DEN. Nx_NUM
is a 44 bit word and Nx_DEN is a 32 bit word. Clockbuilder Pro left shifts these values as far as possible before
writing them to the actual Nx_NUM and Nx_DEN registers. For example, an integer Nx divider of 30/1, when left
shifted, becomes Nx_NUM=6442509440 (decimal) and Nx_DEN=2147483648 (decimal). By adjusting the size of
the Nx_NUM and Nx_DEN but keeping the ratio the same, the resolution of the LSbit of numerator or denominator
can be controlled.
Write
When changing the N divider(s) to fractional values, the setting name N_PIBYP[4:0] must be a 0 for the N divider
that is being changed. This applies when using FINC/FDEC or when directly writing to the N divider.
7.1.1. DCO with Frequency Increment/Decrement Pins/Bits
The FSTEPW (Frequency STEP Word) is a 44 bit word that is used to change the value of the Nx_NUM word.
Whenever an FINC or FDEC is asserted, the FSTEPW will automatically add or subtract from the Nx_NUM word
so that the output frequency will increment (FINC) or decrement (FDEC) respectively.
Each of the N dividers can be independently stepped up or down in numerical predefined steps with a maximum
resolution that varies from ~ 0.05 ppb to a ~0.004 ppb depending upon the frequency plan. One or more N dividers
can be controlled by FINC/FDEC at the same time by use of the N_FSTEP_MSK bits. Any N divider that is masked
by its corresponding bit in the N_FSTEP_MSK field will not change when FINC or FDEC is asserted. The
magnitude of the frequency change caused by FINC or FDEC is determined by the value of the FSTEPW word and
the magnitude of the word in Nx_NUM. For a specific frequency step size it may be necessary to adjust the
Nx_NUM value while keeping the ratio of Nx_NUM/Nx_DEN the same. When the FINC or FDEC pin or register bit
is asserted the selected N dividers will have their numerator changed by the addition or subtraction of the
Nx_FSTEPW so that an FINC will increase the output frequency and an FDEC will decrease the output frequency.
An FINC or FDEC can be followed by another FINC or FDEC in 1 us minimum.
Because the output frequency=FVCO*Nx_DEN/(Rx*Nx_NUM), subsequent changes to Nx_NUM by the FSTEPW
will not produce exactly the same output frequency change. The amount of error in the frequency step is extremely
small and in a vast number of applications will not cause a problem. When consecutive frequency steps must be
exactly the same, it is possible to set FINC and FDEC to change the Nx_DEN instead of Nx_NUM and then
consecutive FINCs or FDECs will be exactly the same frequency change. However, there are some special setups
that are necessary to achieve this. For more information contact Silicon Labs at https://www.silabs.com/support/
pages/contacttechnicalsupport.aspx.
Rev. 1.1
31
Si5341-40-RM
7.1.2. DCO with Direct Register Writes
When a N divider numerator (Nx_NUM) and its corresponding update bit (Nx_UPDATE) is written, the new
numerator value will take effect and the output frequency will change without any glitches. The N divider numerator
and denominator terms (Nx_NUM and Nx_DEN) can be left and right shifted so that the least significant bit of the
numerator word represents the exact step resolution that is needed for your application. Each N divider has an
update bit (Nx_UPDATE) that must be written to cause the written values to take effect. All N dividers can be
updated at the same time by writing the N_UPDATE_ALL bit. Note that writing this bit will not cause any output
glitching on an N divider that did not have its numerator or denominator changed.
When changing the N divider denominator (Nx_DEN) it is remotely possible that a small phase hit of ~550 fs may
occur at the exact time of the frequency change. However with the proper setup it is possible to change Nx_DEN
and never have a phase hit. If your application requires changing an N divider denominator, contact Silicon Labs at
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx for support.
7.2. Using the M Divider for DCO Applications
The VCO can be treated as a DCO by changing the value of the M feedback divider. By changing the M divider, all
the output frequencies will change by the same amount in ppm. Changing the M divider is only valid for small
changes in the output frequencies. Contact Silicon Labs at https://www.silabs.com/support/pages/
contacttechnicalsupport.aspx for assistance in the implementation of this capability.
32
Rev. 1.1
Si5341-40-RM
8. Dynamic PLL Changes
It is possible for the PLL to become permanently out of lock when it is dynamically re-programmed or changed via
the serial port. Re-programming/changing the N divider does not affect the PLL. Any change that causes the VCO
frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following
special sequence of writes. Each of the following actions can cause the VCO frequency change by more than
250 ppm.
1. Any change to an input P divider
2. Changing the M divider by more than 250 ppm.
3. Changing the XAXB_FREQ_OFFSET word so that the frequency of the VCO changes by more than 250 ppm.
4. Changing both the M divider and XAXB_FREQ_OFFSET so that VCO frequency changes by more than 250
ppm.
1. Pre-amble write sequence:
Address
Data
0x0B24
0xD8
0x0B25
0x00
2. Wait 300 ms.
3. Then execute writes to change the P or M dividers or the XAXB_FREQ_OFFSET word.
4. Write a SOFT_RST
Address
Data
0x001C
0x01
5. Post-amble write sequence
Address
Data
0x0B24
0xDB
0x0B25
0x02
Rev. 1.1
33
Si5341-40-RM
9. Serial Interface
Configuration and operation of the Si5341/40 is controlled by reading and writing registers using the I2C or SPI
interface. Both of these serial interfaces are based upon 8-bit addressing, which means that the page byte must be
written every time you need to access a different page in the register map. See the PGE byte at register 0x0001 for
more information. The I2C_SEL pin selects I2C or SPI operation. The Si5341/40 supports communication with a
3.3 V or 1.8 V host by setting the IO_VDD_SEL (0x0943[0]) configuration bit. The SPI mode supports 4-wire or 3wire by setting the SPI_3WIRE configuration bit.
I2C
SPI 4-Wire
SPI 3-Wire
I2C_SEL pin = High
I2C_SEL pin = Low
SPI_3WIRE = 0
I2C_SEL pin = Low
SPI_3WIRE = 1
IO_VDD_SEL = VDD
(Default)
IO_VDD_SEL = VDD
(Default)
1.8V
1.8V
Host = 1.8V
1.8V
I2C SDA
HOST
SCLK
3.3V
1.8V
VDDA
VDD
SDA
CS
SPI
HOST
SCLK
SDO
3.3V
1.8V
VDDA
VDD
3.3V
3.3V
I2C SDA
HOST
SCLK
SPI
HOST
SDI
SDI
SDO
SCLK
SCLK
1.8V
VDDA
VDD
SDA
SCLK
1.8V
VDDA
VDD
CS
SDIO
SCLK
Si5341/40
IO_VDD_SEL = VDDA
3.3V
CS
SDIO
SCLK
3.3V
Si5341/40
3.3V
Host = 3.3V
1.8V
CS
Si5341/40
IO_VDD_SEL = VDDA
IO_VDD_SEL = VDD
(Default)
CS
SPI
HOST
SDO
3.3V
1.8V
VDDA
VDD
3.3V
CS
SPI
HOST
SDI
SDI
SDO
SCLK
SCLK
Si5341/40
IO_VDD_SEL = VDDA
CS
SDIO
SCLK
3.3V
1.8V
VDDA
VDD
CS
SDIO
SCLK
Si5341/40
Si5341/40
Figure 13. I2C/SPI Device Connectivity Configurations
Table 20 lists register settings of interest for the I2C/SPI.
Table 20. I2C/SPI Register Settings
Register Name
Hex Address [Bit Field]
Function
Si5341
Si5340
IO_VDD_SEL
0x0943[0]
0x0943[0]
The IO_VDD_SEL bit determines whether the VDD or VDDA supply voltage is used for the serial port, control pins, and status pins
voltage references. See the register map description of this bit for
additional details.
SPI_3WIRE
0x002B[3]
0x002B[3]
The SPI_3WIRE configuration bit selects the option of 4-wire or 3wire SPI communication. By default the SPI_3WIRE configuration
bit is set to the 4-wire option. In this mode the Si5341/40 will
accept write commands from a 4-wire or 3- wire SPI host allowing
configuration of device registers. For full bidirectional communication in 3-wire mode, the host must write the SPI_3WIRE configuration bit to “1”.
If neither serial interface is used, leave pins I2C_SEL, A1/SDO and A0/CS disconnected and tie SDA/SDIO and
SCLK low.
34
Rev. 1.1
Si5341-40-RM
9.1. I2C Interface
When in I2C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in StandardMode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I2C
bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 24. Both the
SDA and SCL pins must be connected to a supply via an external pull-up (1k to 4.7k ohm) as recommended by the
I2C specification as shown in Figure 14. Two address select bits (A0, A1) are provided allowing up to four Si5341/
40 devices to communicate on the same bus. This also allows four choices in the I2C address for systems that may
have other overlapping addresses for other I2C devices.
I2C
VDD
VDDI2C
I2C_SEL
SDA
To I2C Bus
or Host
SCLK
A0
LSBs of I2C
Address
A1
Si5341/40
Figure 14. I2C Configuration
The 7-bit slave device address of the Si5341/40 consists of a 5-bit fixed address plus two pins that are selectable
for the last two bits, as shown in Figure 15.
Slave Address
6
5
4
3
2
1
1
1
0
1
1
0
A1 A0
Figure 15. 7-bit I2C Slave Address Bit-Configuration
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 18. A write
burst operation is also shown where subsequent data words are written using to an auto-incremented address.
Write Operation – Single Byte
S
Slv Addr [6:0]
0
A Reg Addr [7:0] A
Data [7:0]
A
P
A
Data [7:0]
Write Operation - Burst (Auto Address Increment)
S
Slv Addr [6:0]
0
A Reg Addr [7:0] A
Data [7:0]
A
P
Reg Addr +1
Host
Si5341/40
Host
Si5341/40
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 16. I2C Write Operation
Rev. 1.1
35
Si5341-40-RM
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 17.
Read Operation – Single Byte
S Slv Addr [6:0]
0 A Reg Addr [7:0] A P
S Slv Addr [6:0]
1
A
Data [7:0]
N P
Read Operation - Burst (Auto Address Increment)
S Slv Addr [6:0]
0
A Reg Addr [7:0] A P
S Slv Addr [6:0]
1
A
Data [7:0]
A
Data [7:0]
N P
Reg Addr +1
Host
Si5341/40
Host
Si5341/40
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 17. I2C Read Operation
36
Rev. 1.1
Si5341-40-RM
9.2. SPI Interface
When in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE
configuration bit. The 4-wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input
(SDI), and serial data output (SDO). The 3-wire interface combines the SDI and SDO signals into a single
bidirectional data pin (SDIO). Both 4-wire and 3-wire interface connections are shown in Figure 18.
SPI 3-Wire
SPI_3WIRE = 1
SPI 4-Wire
SPI_3WIRE = 0
I2C_SEL
I2C_SEL
CS
To SPI
Host
CS
SDI
To SPI
Host
SDO
SCLK
SDIO
SCLK
Si5340/41
Si5340/41
Figure 18. SPI Interface Connections
Table 21. SPI Command Format
Instruction
Ist Byte1
2nd Byte
3rd Byte
Nth Byte2,3
Set Address
000x xxxx
8-bit Address
—
—
Write Data
010x xxxx
8-bit Data
—
—
Read Data
100x xxxx
8-bit Data
—
—
Write Data + Address Increment
011x xxxx
8-bit Data
—
—
Read Data + Address Increment
101x xxxx
8-bit Data
—
—
Burst Write Data
1110 0000
8-bit Address
8-bit Data
8-bit Data
Notes:
1. X = don’t care (1 or 0)
2. The Burst Write Command is terminated by de-asserting /CS (/CS = high)
3. There is no limit to the number of data bytes that may follow the Burst Write Command, but the address will wrap
around to 0 in the byte after address 255 is written.
Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data”
command. The 'Write Data + Address Increment' or “Read Data + Address Increment” commands are available for
cases where multiple byte operations in sequential address locations is necessary. The “Burst Write Data”
instruction provides a compact command format for writing data since it uses a single instruction to define starting
address and subsequent data bytes. Figure 19 shows an example of writing three bytes of data using the write
commands. This demonstrates that the “Write Burst Data” command is the most efficient method for writing data to
sequential address locations. Figure 20 provides a similar comparison for reading data with the read commands.
Note that there is no burst read, only read increment.
Rev. 1.1
37
Si5341-40-RM
‘Set Address’ and ‘Write Data’
‘Set Addr’
Addr [7:0]
‘Write Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Write Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Write Data’ Data [7:0]
‘Set Address’ and ‘Write Data + Address Increment’
‘Set Addr’
Addr [7:0]
‘Write Data + Addr Inc’
‘Write Data + Addr Inc’
Data [7:0]
‘Write Data + Addr Inc’
Data [7:0]
Data [7:0]
‘Burst Write Data’
‘Burst Write Data’
Host
Addr [7:0]
Data [7:0]
Host
Si5341/40
Data [7:0]
Data [7:0]
Si5341/0
Figure 19. Example Writing Three Data Bytes using the Write Commands
‘Set Address’ and ‘Read Data’
‘Set Addr’
Addr [7:0]
‘Read Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Read Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Read Data’ Data [7:0]
‘Set Address’ and ‘Read Data + Address Increment’
‘Set Addr’
Addr [7:0]
‘Read Data + Addr Inc’
‘Read Data + Addr Inc’
Data [7:0]
‘Read Data + Addr Inc’
Data [7:0]
Host
Si5341/40
Host
Data [7:0]
Si5341/40
Figure 20. Example of Reading Three Data Bytes Using the Read Commands
The timing diagrams for the SPI commands are shown in Figures 21, 22, 23, and 24.
38
Rev. 1.1
Si5341-40-RM
Previous
Command
Next
Command
‘Set Address’ Command
> 2.0
SCLK
Periods
>2
SCLK
Periods
Set Address Instruction
CS
Base Address
SCLK
4-Wire
SDI
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
SDO
3-Wire
SDIO
Host
Host
Si5341/40
High Impedance
Don’t Care
Si5341/40
Figure 21. SPI “Set Address” Command Timing
Previous
Command
‘Write Data’ or ‘Write Data + Address Increment’
Command
Next
Command
> 2.0
SCLK
Periods
>2
SCLK
Periods
Write Data instruction
Data byte @ base address + 1
CS
SCLK
4-Wire
SDI
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
SDO
3-Wire
SDIO
Host
Si5341/40
Host
Si5341/40
Don’t Care
High Impedance
Figure 22. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing
Rev. 1.1
39
Si5341-40-RM
Previous
Command
‘Read Data’ or ‘Read Data + Address Increment’
Command
Next
Command
> 2.0
SCLK
Periods
> 2.0
SCLK
Periods
Read Data instruction
Read byte @ base address + 1
CS
SCLK
4-Wire
SDI
1
0
SDO
1
0
1
0
7
6
5
4
3
2
1
0
7
6
7
6
5
4
3
2
1
0
7
6
7
6
5
4
3
2
1
0
7
6
3-Wire
SDIO
7
Host
6
5
4
3
Host
Si5341/40
2
1
0
High Impedance
Don’t Care
Si5341/40
Figure 23. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing
Previous
Command
Next
Command
‘Burst Data Write’ Command
> 2.0
SCLK
Periods
> 2.0
SCLK
Periods
Burst Write Instruction
CS
1st data byte @ base address
Base address
nth data byte @ base address +n
SCLK
4-Wire
SDI
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
SDO
3-Wire
SDIO
Host
Si5341/40
Host
Si5341/40
Don’t Care
High Impedance
Figure 24. SPI “Burst Data Write” Instruction Timing
40
Rev. 1.1
Si5341-40-RM
10. Field Programming
To simplify design and software development of systems using the Si5341/40, a field programmer is available. The
ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a
PCB) as well as “in-socket” programming of Si5341/40 sample devices. Refer to
http://www.silabs.com/CBProgrammer for information about this kit.
Rev. 1.1
41
Si5341-40-RM
11. Recommended Crystals and External Oscillators
11.1. Recommended Crystals
Table 22 lists the presently recommended crystals. Other vendors can also supply crystals that meet the specs in
Figures 25 and 26.
Table 22. Recommended Crystals
Supplier
Part Number
Frequency
C0,
Max
pF
ESR
Max

CL
pF
Tested
over
Temp
for
Activity
Dips?
Drive
Level µW
Case Size
mm x mm
Connor
Winfield
CS-043
48 MHz
15
25
2.0
20
8
No
200
3.2 x 2.5
Connor
Winfield
CS-044
54 MHz
15
25
2.0
20
8
No
200
3.2 x 2.5
Hosonic
E3S48.000F08M22SI
48 MHz
20
20
1.5
25
8
No
200
3.2 x 2.5
Hosonic
E2S48.000F08M22SI
48 MHz
20
20
1.5
25
8
No
200
2.5 x 2.0
Hosonic
E3S54.000F08M22SI
54 MHz
20
20
2.0
22
8
No
200
3.2 x 2.5
Hosonic
E2S54.000F08M22SI
54 MHz
20
20
1.5
25
8
No
200
2.5 x 2.0
Kyocera CX3225SB48000D0FPJC1
48 MHz
10
15
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB48000D0W
PSC1
48 MHz
15
30
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB48000D0W
PTC1
48 MHz
30
60
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB54000D0FPJC1
54 MHz
10
15
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB54000D0W
PSC1
54 MHz
15
30
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB54000D0WP
TC1
54 MHz
30
60
2.0
23
8
No
200
3.2 x 2.5
Kyocera CX3225SB48000D0FPJC2
48 MHz
10
15
2.0
23
8
Yes
200
3.2 x 2.5
Kyocera CX3225SB48000D0W
PSC2
48 MHz
15
30
2.0
23
8
Yes
200
3.2 x 2.5
Kyocera CX3225SB54000D0FPJC2
54 MHz
10
15
2.0
23
8
Yes
200
3.2 x 2.5
Kyocera CX3225SB54000D0W
PSC2
54 MHz
15
30
2.0
23
8
Yes
200
3.2 x 2.5
42
Initial
Accuracy
Tolerance over –40 °C
in ± ppm to +85 °C in
± ppm
Rev. 1.1
Si5341-40-RM
Table 22. Recommended Crystals (Continued)
Supplier
Part Number
Frequency
Initial
Accuracy
Tolerance over –40 °C
in ± ppm to +85 °C in
± ppm
C0,
Max
pF
ESR
Max

CL
pF
Tested
over
Temp
for
Activity
Dips?
Drive
Level µW
Case Size
mm x mm
NDK
NX3225SA-48.000MCS07559
48 MHz
20
30
1.8
23
8
No
200
3.2 x 2.5
NDK
NX3225SA-54.000MCS07551
54 MHz
20
30
1.8
23
8
No
200
3.2 x 2.5
Siward
XTL571500-S315-006
54 MHz
50
50
2.0
20
8
No
200
3.2 x 2.5
Siward
XTL571500-S315-007
54 MHz
50
50
2.0
20
8
No
200
2.5 x 2.0
Taitien
S0242-X-001-3
54 MHz
20
20
2.0
23
8
No
200
3.2 x 2.5
Taitien
S0242-X-002-3
48 MHz
20
20
2.0
23
8
No
200
3.2 x 2.5
TXC
7M48070012
48 MHz
10
15
2.0
22
8
No
200
3.2 x 2.5
TXC
7M54070010
54 MHz
10
15
2.0
22
8
No
200
3.2 x 2.5
TXC
7M48072001
48 MHz
20
30
2.0
22
8
Yes
200
3.2 x 2.5
TXC
7M54072001
54 MHz
20
30
2.0
22
8
Yes
200
3.2 x 2.5
TXC
7M48072002
48 MHz
10
15
2.0
22
8
Yes
200
3.2 x 2.5
TXC
7M54072002
54 MHz
10
15
2.0
22
8
Yes
200
3.2 x 2.5
In general, a crystal meeting the requirements of Figure 25 or Figure 26 and having a max power rating of at least
200 µW is guaranteed to oscillate. It is preferred that a crystal have a CL rating of 8 pF. Crystals with CL not equal
to 8 pF can be used, but the XAXB_FREQ_OFFSET register word may be needed to compensate for oscillation
frequency error. 25 MHz crystals also need to meet the 200 W maximum power rating. 25 MHz crystals typically
causes the output jitter to increase by 10-40%.
Some applications may require crystals that have been tested incrementally over the entire temperature range so
that the crystal resonant frequency change over any 2 degree C temperature change is bounded. This testing is to
detect activity dips. This additional testing adds an additional cost to the crystal. The Si534x products are designed
to work with normally tested crystals as well as activity dip-tested crystals.
Rev. 1.1
43
Si5341-40-RM
MaximumESRvsC0for48Ͳ54MHzCrystal
31
29
ESRohms
27
25
23
21
19
17
15
0
0.5
1
1.5
2
2.5
3
3.5
C0pf
Figure 25. R1 (ESR) vs. C0 for 48 to 54 MHz Crystals
MaximumESRvsC0for25MHzCrystal
100
90
ESRohms
80
70
60
50
40
30
0
0.5
1
1.5
2
2.5
C0pf
Figure 26. R1 (ESR) vs. C0 for 25 MHz Crystals
44
Rev. 1.1
3
3.5
Si5341-40-RM
11.2. Recommended Oscillator Suppliers
Table 23 lists the recommended TCXO/OCXO suppliers.
Table 23. Recommended Oscillator Suppliers
Supplier
Part Number
TCXO
OCXO
Kyocera
KT7050A40000KAW33TAG
TCX0
Rakon
509768
TCXO
Rakon
E6213LF
Kyocera
Model
Frequency
Case
Size
40 MHz
5 x 7 x 1.7
RTX7050A
40 MHz
5x7x1.87
TCXO
RPT7050A
40 MHz
5x7x2
0010.000000M13133AT
OCXO
OCXO-1409A
10 MHz
14.8 x 9.1 x 6.2
Rakon
RFP050
OCXO
5–50 MHz
14.6 x 9.7 x 6.2
Rakon
M5686LF
OCXO
25 MHz
9x7x4
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12. Crystal and Device Circuit Layout Recommendations
The main layout issues that should be carefully considered include the following:

Number and size of the ground vias for the Epad (see Section 13.3 for details)
Output clock trace routing
 Input clock trace routing
 Control and Status signals to input or output clock trace coupling
 XTAL signal coupling
 XTAL layout
If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to
the X1 and X2 pins (4 and 7) to provide the best possible performance. The shield should not be connected to the
ground plane and the planes underneath should have as little under the shield as possible. It may be difficult to do
this for all the layers, but it is important to do this for the layers that are closest to the shield.

Refer to http://www.silabs.com/Si538x-4x-EVB to obtain Si5341-EVB and Si5340-EVB schematics, layout and
BOM files.
12.1. 64-Pin QFN Si5341 Layout Recommendations
This section details the recommended guidelines for the crystal layout of the 64-pin Si5341 device using an
example 8-layer PCB. The following are the descriptions of each of the eight layers.

Layer 1: device layer, with low speed CMOS control/status signals, ground flooded
 Layer 2: crystal shield
 Layer 3: ground plane
 Layer 4: power distribution
 Layer 5: power routing layer
 Layer 6: input clocks
 Layer 7: output clocks layer
 Layer 8: ground layer
Figure 27 is the top layer layout of the Si5341 device mounted on the top PCB layer. This particular layout was
designed to implement either a crystal or an external oscillator as the XAXB reference. The crystal/ oscillator area
is outlined with the white box around it. In this case, the top layer is flooded with ground. Note that this layout has a
resistor in series with each pin of the crystal. In typical applications, these resistors should be removed.
12.1.1. Si5341 Applications without a Crystal
If the application does not use a crystal, then the X1 and X2 pins should be left as “no connect” and should not be
tied to ground. In addition, there is no need for a crystal shield or the voids underneath the shield. If there is a
differential external clock input on XAXB there should be a termination circuit near the XA and XB pins. This
termination circuit should be two 50  resistors and one 0.1 µF cap connected in the same manner as on the other
clock inputs (IN0, IN1 and IN2). See Figure 5. The clock input on XAXB must be ac-coupled. Care should be taken
to keep all clock inputs well isolated from each other as well as any other dynamic signal. For LVCMOS or clipped
sine wave inputs on XAXB, see Figure 5.
12.1.2. Si5341 Crystal Layout Guidelines
The following are five recommended crystal layout guidelines:
1. Place the crystal as close as possible to the XA/XB pins.
2. Do not connect the crystal's GND pins to PCB gnd.
3. Connect the crystal's GND pins to the DUT's X1 and X2 pins via a local crystal shield placed around and under
the crystal. Make sure that X1, X2, and both crystal ground pins do NOT connect to the pcb ground. See
Figure 27 for an illustration of how to create a crystal shield by placing vias connecting the top layer traces to
the shield layer underneath. Note that a zoom view of the crystal shield layer on the next layer down is shown in
Figure 28.
4. Keep transitioning signal traces as distant as practical from the crystal/oscillator area especially if they are
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clocks or frequently toggling digital signals.
5. In general do not route GND, power planes/traces, or locate components on the other side, below the crystal
shield. If necessary a ground layer may be placed under the crystal shield plane as long as it is at least 0.05”
below the crystal shield layer.
Figure 27. 64-pin Si5341 Crystal Layout Recommendations Top Layer (Layer 1)
Note the vias that are shown for the center ground pad so that there is a low-impedance path to ground and a good
thermal path to ground. See Section 13.3 for details on these vias.
Figure 28. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2)
Figure 28 shows the layer that implements the shield underneath the crystal. The shield extends underneath the
entire crystal and the X1 and X2 pins. This layer also has the clock input pins. The clock input pins go to layer 2
using vias to avoid crosstalk. As soon as the clock inputs are on layer 2 they have a ground shield above below
and on the sides for protection.
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Figure 29 is the ground plane and shows a void underneath the crystal shield. Figure 30 is a power plane and
shows the clock output power supply traces. The void underneath the crystal shield is continued.
Figure 29. Crystal Ground Plane (Layer 3)
Figure 30. Power Plane (Layer 4)
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Figure 31 shows layer 5, which is the power plane with the power routed to the clock output power pins.
Figure 31. Layer 5 Power Routing on Power Plane (Layer 5)
Figure 32 is another ground plane similar to layer 3.
Figure 32. Ground Plane (Layer 6)
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12.1.3. Output Clocks
Figure 33 shows the output clocks. Similar to the input clocks the output clocks have vias that immediately go to a
buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding
between the clock output pairs to avoid crosstalk. There should be a line of vias through the ground flood on either
side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low
inductance path to the ground plane on layers 3 and 6.
Figure 33. Output Clock Layer (Layer 7)
Figure 34. Bottom Layer Ground Flooded (Layer 8)
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12.2. 44-Pin QFN Si5340 Layout Recommendations
This section details the layout recommendations for the 44-pin Si5340 device using an example 6-layer PCB.
The following guidelines details images of a six layer board with the following stack:

Layer 1: device layer, with low speed CMOS control/status signals, ground flooded
 Layer 2: crystal shield, output clocks, ground flooded
 Layer 3: ground plane
 Layer 4: power distribution, ground flooded
 Layer 5: input clocks, ground flooded
 Layer 6: low-speed CMOS control/status signals, ground flooded
This layout was designed to implement either a crystal or an external clock as the XAXB reference. The top layer is
flooded with ground. The clock output pins go to layer 2 using vias to avoid crosstalk during transit. When the clock
output signals are on layer 2 there is a ground shield above, below and on all sides for protection. Output clocks
should always be routed on an internal layer with ground reference planes directly above and below. The plane that
has the routing for the output clocks should have ground flooded near the clock traces to further isolate the clocks
from noise and other signals.
12.2.1. Si5340 Applications without a Crystal as the Reference Clock
If the application does not use a crystal, then the X1 and X2 pins should be left as “no connect” and should not be
tied to ground. In addition, there is no need for a crystal shield or the voids underneath the shield. If there is a
differential external clock input on XAXB there should be a termination circuit near the XA and XB pins. This
termination circuit should be two 50  resistors and one 0.1 µF cap connected in the same manner as on the other
clock inputs (IN0, IN1 and IN2). The clock input on XAXB must be ac-coupled. Care should be taken to keep all
clock inputs well isolated from each other as well as any other dynamic signal.
Figure 35. Device Layer (Layer 1)
Note the vias to ground from the center ground pad. These are needed to create a low-impedance path to ground
and a good thermal path to ground. See Section 13.3 for additional information on these vias.
Rev. 1.1
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12.2.2. Si5340 Crystal Guidelines
Figure 36 is the second layer. The second layer implements the shield underneath the crystal. The shield extends
underneath the entire crystal and the X1 and X2 pins. There should be no less than 12 vias to connect the X1X2
planes on layers 1 and 2. These vias are not shown in any other figures. All traces with signals that are not static
must be kept well away from the crystal and the X1X2 plane.
Figure 36. Crystal Shield Layer 2
Figure 37 is the ground plane and shows a void underneath the crystal shield.
Figure 37. Ground Plane (Layer 3)
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Figure 38 is a power plane showing the clock output power supply traces. The void underneath the crystal shield is
continued.
Figure 38. Power Plane and Clock Output Power Supply Traces (Layer 4)
Figure 39 shows layer 5 and the clock input traces. Similar to the clock output traces, they are routed to an inner
layer and surrounded by ground to avoid crosstalk.
Figure 39. Clock Input Traces (Layer 5)
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Figure 40 shows the bottom layer, which continues the void underneath the shield. Layer 6 and layer 1 are mainly
used for low speed CMOS control and status signals for which crosstalk is not a significant issue. PCB ground can
be placed under the X1X2 shield as long as the PCB ground is at least 0.05 inches below it.
Figure 40. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer)
For any high-speed, low-jitter application, the clock signal runs should be impedance-controlled to 100 
differential or 50  single-ended. Differential signaling is preferred because of its increased immunity to commonmode noise. All clock I/O runs should be properly terminated.
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13. Power Management
13.1. Power Management Features
Several unused functions can be powered down to minimize power consumption. The registers listed in Table 24
are used for powering down different features.
Table 24. Power Management Registers
Register Name
Hex Address [Bit Field]
Si5341
PDN
OUT0_PDN
OUT1_PDN
OUT2_PDN
OUT3_PDN
OUT4_PDN
OUT5_PDN
OUT6_PDN
OUT7_PDN
OUT8_PDN
OUT9_PDN
Si5340
0x001E[0]
0x0108[0]
0x010D[0]
0x0112[0]
0x0117[0]
0x011C[0]
0x0121[0]
0x0126[0]
0x012B[0]
0x0130[0]
0x013A[0]
Function
0x0112[0]
0x011C[0]
0x0126[0]
0x012B[0]
—
—
—
—
—
—
This bit allows powering down the device. The serial interface remains powered during power down mode.
Powers down unused clock outputs.
OUT_PDN_ALL
0x0145[0]
Power down all output drivers
XAXB_PDNB
0x090E[1]
0-Power down the oscillator and buffer circuitry at the XA/XB
pins
1- No power down
13.2. Power Supply Recommendations
The power supply filtering generally is important for optimal timing performance. The Si5341/0 devices have
multiple stages of on-chip regulation to minimize the impact of board level noise on clock jitter.
It is recommended to use a 0402, 1.0 µF ceramic capacitor on each VDD for optimal performance. Because of the
extensive internal voltage regulation this will be sufficient unless the power supply has very high noise. If the power
supply might have very high noise, then it is suggested to include an optional, single 0603 (resistor/ferrite) bead in
series with each supply to enable additional filtering. This resistor/ferrite should initially be a 0 ohm resistor. If
additional supply filtering is needed then a ferrite component can replace the 0 ohm resistor.
13.3. Grounding Vias
The pad on the bottom of the device functions as both the sole electrical ground and primary heat transfer path.
Hence it is important to minimize the inductance and maximize the heat transfer from this pad to the internal
ground plane of the pcb. Use no less than 25 vias from the center pad to a ground plane under the device. In
general more vias will perform better. Having the ground plane near the top layer will also help to minimize the via
inductance from the device to ground and maximize the heat transfer away from the device.
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13.4. Power Supply Sequencing
Four classes of supply voltages exist:
1. VDD=1.8V  5%
2. VDDA=3.3V  5%
3. VDDO=1.8/2.5/3.3V5%
4. VDDS=1.8/3.3V5%
There is no requirement for power supply sequencing unless the output clocks are required to be aligned. In this
case the VDDO of each clock that needs to be aligned (low skew) must be powered up before VDD and VDDA. If
this is not possible, then the output-output skew can be achieved by performing a SOFT_RST after the device is
powered up.
On the Si5340, a VDDS pin exists but this pin only powers the driver for the status output pins LOLb and
LOSXAXBB. There is no power sequencing requirement for VDDS.
The internal POR (power on reset) will not happen until both VDD and VDDA have been applied.
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14. Base vs. Factory Preprogrammed Devices
The Si5341/40 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”)
versions.
14.1. “Base” Devices (also known as “Blank” devices)






Example “base” orderable part numbers (OPNs) are of the form “Si5341A-A-GM” or “Si5340B-A-GM”.
Base devices are available for applications where volatile reads and writes are used to program and configure
the device for a particular application.
Base devices do not power up in a usable state (all output clocks are disabled).
Base devices are, however, configured by default to use a 48 MHz crystal on the XAXB reference and a 1.8V
compatible I/O voltage setting for the host I2C/SPI interface.
Additional programming of a base device is mandatory to achieve a usable configuration.
See the on-line lookup utility at:
http://www.silabs.com/products/clocksoscillators/pages/clockbuilderlookup.aspx to access the default
configuration plan and register settings for any base OPN.
14.2. Factory Preprogrammed (Custom OPN) Devices

Factory preprogammed devices use a “custom OPN”, such as Si5341A-A-xxxxx-GM, where xxxxx is a
sequence of characters assigned by Silicon Labs for each customer-specific configuration. These characters
are referred to as the “OPN ID”. Customers must initiate custom OPN creation using the ClockBuilder Pro
software.
 Many customers prefer to order devices which are factory preprogrammed for a particular application that
includes specifying the XAXB reference frequency/type, the clock input frequencies, the clock output
frequencies, as well as the other options, such as automatic clock selection, loop BW, etc. The ClockBuilder
software is required to select among all of these options and to produce a project file which Silicon Labs uses to
preprogram all devices with custom orderable part number (“custom OPN”).
 Custom OPN devices contain all of the initiialization information in their non-volatile memory (NVM) so that it
powers up fully configured and ready to go.
 Because preprogrammed device applications are inherently quite different from one another, the default power
up values of the register settings can be determined using the custom OPN utility at:
http://www.silabs.com/products/clocksoscillators/pages/clockbuilderlookup.aspx.
 Custom OPN devices include a device top mark which includes the unique OPN ID. Refer to the device
datasheet’s Ordering Guide and Top Mark sections for more details.
Both “base” and “factory preprogrammed” devices can have their operating configurations changed at any time
using volatile reads and writes to the registers. Both types of devices can also have their current register
configuration written to the NVM by executing an NVM bank burn sequence (see "3.2. NVM Programming" on page
14).
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15. Register Map
15.1. Register Map Overview and Default Settings Values
The Si5341/40 family has a large register map and is divided into separate pages. Each page contains a total of
256 registers, although all 256 registers are not used. Register 1 on each page is reserved to indicate the page and
register 255 is reserved for the device ready status. The following is a summary of the content that can be found on
each of the pages. Note any page that is not listed is not used for the device. Do not attempt to write to registers
that have not been described in this document, even if they are accessible. Note that the default value will depend
on the values loaded into NVM, which is determined by the part number.
Where not provided in the register map information below, you can get the default values of the register map
settings, by accessing the part number lookup utility at: http://www.silabs.com/products/clocksoscillators/pages/
clockbuilderlookup.aspx Register map settings values are listed in the datasheet addendum, which can be
accessed by using the link above. The register maps are broken out for the Si5341 and Si5340 separately.
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15.2. Si5341 Register Map
Because preprogrammed devices are inherently quite different from one another, the default power up values of
the registers can be determined using the custom OPN utility at: http://www.silabs.com/products/clocksoscillators/
pages/clockbuilderlookup.aspx.
Table 25. Register Map Paging Descriptions
Page
Start Address
(Hex)
Start Address
(Decimal)
Contents
Page 0
0000h
0
Page 1
0100h
256
Clock output configuration
Page 2
0200h
512
P,R dividers, scratch area
Page 3
0300h
768
Output N dividers, N divider FINC/FDEC
Page 9
0900h
2304
Control IO configuration
Alarms, interrupts, reset, device ID, revision ID
R = Read Only
R/W = Read Write
S = Self Clearing
Registers that are sticky are cleared by writing “0” to the bits that have been set in hardware. A self-clearing bit will
clear on its own when the state has changed.
Some registers that are listed in the Data Sheet Addendum are not documented in the Register Map below
because they are set and maintained by Clock Builder Pro. In almost all circumstances, these registers should not
be modified by the user. For more details, please contact Silicon Labs.
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15.2.1. Page 0 Registers Si5341
Register 0x0000 Die Rev
Reg Address
Bit Field
Type
Setting Name
0x0000
3:0
R
DIE_REV
Reg Address
Bit Field
Type
Setting Name
0x0001
7:0
R/W
PAGE
Description
4- bit Die Revision Number
0 = Silicon Revision A0
1 = Silicon Revision A1
Register 0x0001 Page
Description
Selects one of 256 possible pages.
There is the “Page Register” which i s located at address 0x01 on every page. When read, it will indicate the
current page. When written, it will change the page to the value entered. There is a page register at address
0x0001, 0x0101, 0x0201, 0x0301, … etc.
Register 0x0002–0x0003 Base Part Number
Reg Address
Bit Field
Type
Setting
Name
0x0002
7:0
R
PN_BASE
0x0003
15:8
R
PN_BASE
Description
Four-digit “base” part number, one nibble per digit
Example: Si5341A-A-GM. The base part number
(OPN) is 5341, which is stored in this register
Register 0x0004 Device Speed/Synthesis Mode Grade
Reg Address
Bit Field
Type
Setting Name
0x0004
7:0
R
GRADE
Setting Name
DEVICE_REV
Description
One ASCII character indicating the device
speed grade
0=A
1=B
2=C
3=D
Register 0x0005 Device Revision
60
Reg Address
Bit Field
Type
0x0005
7:0
R
Rev. 1.1
Description
One ASCII character indicating the device
revision level.
0 = A; 1=B
Example Si5341C-A12345-GM, the device
revision is “A” and stored as 0
Register 0x0006–0x0008 Tool Version
Reg Address
Bit Field
Type
Setting Name
0x0006
3:0
R
TOOL_VERSION[3:0]
Special
0x0006
7:4
R
TOOL_VERSION[7:4]
Revision
0x0007
7:0
R
TOOL_VERSION[15:8]
Minor[7:0]
0x0008
0
R
TOOL_VERSION[15:8]
Minor[8]
0x0008
4:1
R
TOOL_VERSION[16]
0x0008
7:5
R
Description
Major
TOOL_VERSION[13:17] Tool. 0 for Clockbuilder Pro
Register 0x0009 Temperature Grade
Reg Address
Bit Field
Type
Setting Name
Description
0x0009
7:0
R
TEMP_GRADE
Device temperature grading
0 = Industrial (–40 ° C to 85 ° C) ambient
conditions
Description
Register 0x000A Package ID
Reg Address
Bit Field
Type
Setting Name
0x000A
7:0
R
PKG_ID
Package ID
0 = 9x9 mm 64 QFN
1 = 7x7 mm 44 QFN
Part numbers are of the form:
Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>
Examples:
Si5341C-A12345-GM.
Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the
frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file.
Si5341C-A-GM.
Applies to a “base” or “blank” OPN device. Base devices are factory pre-programmed to a specific base part type
(e.g., Si5341 but exclude any user-defined frequency plan or other user-defined operating characteristics selected
in ClockBuilder Pro.
Register 0x000B I2C Address
Reg Address
Bit Field
Type
Setting Name
0x000B
6:2
R/W
I2C_ADDR
Rev. 1.1
Description
The upper 5 bits of the 7 bit I2C address.
The lower 2 bits are controlled by the A1
and A0 pins.
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Register 0x000C Status Bits
Reg Address
Bit Field
Type
Setting Name
0x000C
0
R
SYSINCAL
1 if the device is calibrating.
0x000C
1
R
LOSXAXB
1 if there is no signal at the XA pin as the LOS
detector is only connected to the XA pin.
0x000C
2
R
LOSREF
0x000C
3
R
LOL
0x000C
5
R
SMBUS_TIMEOUT
Description
1 if the Phase Frequency detector does not have
a signal from XAXB, IN2, IN1, or IN0.
1 if the DSPLL is out of lock.
1 if there is an SMBus timeout error.
Register 0x000D INx Loss of Signal (LOS) Alarms
Reg Address
Bit Field
Type
Setting Name
0x000D
3:0
R
LOS
Description
1 if no clock is present at [FB_IN, IN2,
IN1, IN0]
Note that each bit corresponds to the input. The LOS bits are not sticky.

Input 0 (IN0) corresponds to LOS at 0x000D [0]
Input 1 (IN1) corresponds to LOS at 0x000D [1]
 Input 2 (IN2) corresponds to LOS at 0x000D [2]
 FB_IN corresponds to LOS at 0x000D[3]
 See also LOSXAXB for LOS at the XAXB input

Register 0x0011 Sticky versions of Status Bits
62
Reg Address
Bit Field
Type
Setting Name
Description
0x0011
0
R
SYSINCAL_FLG
Sticky version of SYSINCAL. Write a 0 to
clear the flag.
0x0011
1
R
LOSXAXB_FLG
Sticky version of LOSXAXB. Write a 0 to
clear the flag.
0x0011
2
R
LOSREF_FLG
Sticky version of LOSREF. Write a 0 to
clear the flag.
0x0011
3
R
LOL_FLG
Sticky version of LOL. Write a 0 to clear
the flag.
0x0011
5
R
SMBUS_TIMEOUT_FLG
Rev. 1.1
Sticky version of SMBUS_TIMEOUT.
Write a 0 to clear the flag.
Register 0x0012 INx LOS Flags
Reg Address
Bit Field
Type
Setting Name
Description
0x0012
3:0
R/W
LOS_FLG
Sticky version of LOS. Write a 0 to clear each individual flag.
Register 0x0017 Status Flag Interrupt Masks
Reg Address
Bit Field
Type
0x0017
0
R/W
Setting Name
SYSINCAL_INTR_MSK
0x0017
1
R/W
LOSXAXB_INTR_MSK
0x0017
2
R/W
LOSREF_INTR_MSK
0x0017
0x0017
3
5
R/W
R/W
LOL_INTR_MSK
SMB_TMOUT_
INTR_MSK
Description
1 to mask SYSINCAL_FLG from causing an
interrupt
1 to mask the LOSXAXB_FLG from causing
an interrupt
1 to mask LOSREF_FLG from causing an
interrupt
1 to mask LOL_FLG from causing an interrupt
1 to mask SMBUS_TIMEOUT_FLG from
causing an interrupt
These are the interrupt mask bits for the fault flags in register 0x0011. If a mask bit is set, the alarm will be blocked
from causing an interrupt.
Register 0x0018 Interrupt Masks
Reg Address
Bit Field
Type
0x0018
3:0
R/W
Setting Name
LOS_INTR_MSK
Description
1 to mask the interrupt from LOS_FLG[3:0]

Input 0 (IN0) corresponds to LOSIN_INTR_MSK 0x0018 [0]
 Input 1 (IN1) corresponds to LOSIN_INTR_MSK 0x0018 [1]
 Input 2 (IN2) corresponds to LOSIN_INTR_MSK 0x0018 [2]
 FB_IN corresponds to LOSIN_INTR_MSK 0x0018[3]
Register 0x001C Soft Reset
Reg Address
Bit Field
Type
Setting Name
Description
0x001C
0
S
SOFT_RST
1 Performs a soft rest. Resets the device while
not re-downloading the register configuration
from NVM. If minimal output skew is needed
and VDDOX does not come up before VDD and
VDDA then a soft reset will align the output
clocks.
0 No effect.
This bits are of type “S”, which is self-clearing.
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Register 0x001D FINC, FDEC
Reg Address
Bit Field
Type
Setting Name
0x001D
0
S
FINC
1 A rising edge will cause a frequency increment.
See also N_FSTEP_MSK and Nx_FSTEPW
0 No effect
0x001D
1
S
FDEC
1 A rising edge will cause a frequency decrement.
See also N_FSTEP_MSK and Nx_FSTEPW
0 No effect
Description
Register 0x001E Sync, Power Down and Hard Reset
Reg Address
Bit Field
Type
Setting Name
0x001E
0
R/W
PDN
0x001E
1
S
HARD_RST
1 causes hard reset. The same as power up
except that the serial port access is not held at
reset. NVM is re-downloaded. This does not selfclear, so after setting the bit it must be cleared.
0 No reset
0x001E
2
S
SYNC
Logically equivalent to asserting the SYNC pin.
Resets all R dividers so that synchronous output
frequencies will be aligned.
Description
1 to put the device into low power mode
Register 0x0021 Input Clock Selection
Reg Address
Bit Field
Type
Setting Name
Description
0x0021
0
R/W
IN_SEL_REGCTRL
Selects between register controlled reference clock
selection and pin controlled clock selection using
IN_SEL1 and IN_SEL0 pins: 0 for pin controlled
clock selection; 1 for register clock selection via IN_SEL bits
0x0021
2:1
R/W
IN_SEL
64
Selects the reference clock input to the PLL when
IN_SEL_REGCTRL=1.
0 IN0
1 IN1
2 IN2
3 XA/XB
Rev. 1.1
Register 0x002B SPI 3 vs 4 Wire
Reg Address
Bit Field
Type
Setting Name
0x002B
3
R/W
SPI_3WIRE
Description
0 for 4-wire SPI, 1 for 3-wire SPI
Register 0x002C LOS Enable
Reg Address
Bit Field
Type
Setting Name
Description
0x002C
3:0
R/W
LOS_EN
1 to enable LOS for the inputs other than
XAXB;
0 for disable
0x002C
4
R/W
LOSXAXB_DIS
1 to disable LOS for the XAXB input

Input 0 (IN0): LOS_EN[0]
 Input 1 (IN1): LOS_EN[1]
 Input 2 (IN2): LOS_EN[2]
 FB_IN: LOS_EN[3]
Register 0x002D Loss of Signal Requalification Time
Reg Address
Bit Field
Type
Setting Name
0x002D
1:0
R/W
LOS0_VAL_TIME
Clock Input 0
0 for 2 msec
1 for 100 msec
2 for 200 msec
3 for one second
0x002D
3:2
R/W
LOS1_VAL_TIME
Clock Input 1, same as above
0x002D
5:4
R/W
LOS2_VAL_TIME
Clock Input 2, same as above
Description
When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time
that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME.
Register 0x002E-0x002F LOS0 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x002E
7:0
R/W
LOS0_TRG_THR
0x002F
15:8
R/W
LOS0_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency
plan.
Rev. 1.1
65
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Si5341
Si5341-40-RM
Register 0x0030-0x0031 LOS1 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x0030
7:0
R/W
LOS1_TRG_THR
0x0031
15:8
R/W
LOS1_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency
plan.
Register 0x0032-0x0033 LOS2 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x0032
7:0
R/W
LOS2_TRG_THR
0x0033
15:8
R/W
LOS2_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency
plan.
Register 0x0041-0x0044 LOS Pre-Divider for IN0, IN1, IN3, FB_IN
Reg Address
Bit Field
Type
Setting Name
Description
0x0041
7:0
R/W
LOS0_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
0x0042
7:0
R/W
LOS1_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
0x0043
7:0
R/W
LOS2_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
0x0044
7:0
R/W
LOSFB_IN_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
The following are the predivider values for the above register values.
66
Register Value (Decimal)
Divider Value
0
1 (bypass)
1
2
2
4
3
8
4
16
5
32
6
64
Rev. 1.1
Register Value (Decimal)
Divider Value
7
128
8
256
9
512
10
1024
11
2048
12
4096
13
8192
14
16384
15
32768
16
65536
Register 0x00E2 Active NVM Bank
Reg Address
Bit Field
Type
Description
Setting Name
ACTIVE_NVM_BANK 0x033 when no NVM burn by customer
0x0F when 1 NVM bank has been burned
by customer
0x3F when 2 NVM banks have been
burned by customer
When ACTIVE_NVM_BANK=0x3F, the
last bank has already been burned. See
section 3.2 for a detailed description of
how to program the NVM.
0x00E2
5:0
R
Reg Address
Bit Field
Type
Setting Name
Description
0x00E3
7:0
R/W
NVM_WRITE
Write 0xC7 to initiate an NVM bank burn.
Reg Address
Bit Field
Type
Setting Name
Description
0x00E4
0
S
NVM_READ_BANK
When set, this bit will read the NVM down
into the volatile memory.
Register 0x00E3
Register 0x00E4
Rev. 1.1
67
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Si5341-40-RM
Register 0x00FE Device Ready
Reg Address
Bit Field
Type
0x00FE
7:0
R
Setting Name
DEVICE_READY
Description
0x0F when device is ready
0xF3 when device is not ready
Read-only byte to indicate when the device is ready to accept serial bus transactions. NVM; when
DEVICE_READY is 0x0F the user can safely read or write to any other register. This is only needed after power up
or a hard reset using register bit 0x001E[1]. The “Device Ready” register is available on every page in the device at
the second last register, 0xFE.
68
Rev. 1.1
15.2.2. Page 1 Registers Si5341
Register 0x0102 All Output Clock Driver Disable
Reg Address
Bit Field
Type
Setting Name
Description
0x0102
0
R/W
OUTALL_DISABLE_LOW
0 disables all output drivers.
1 no output drivers are disabled by
this bit but other signals may disable
the outputs.
Register 0x0108 Clock Output 0 Configs and DIV2 Mode
Reg Address
Bit Field
Type
Setting Name
Description
0x0108
0
R/W
OUT0_PDN
Output driver 0: 0 to power up the driver, 1
to power down the driver. Clock outputs
will be weakly pulled-low.
0x0108
1
R/W
OUT0_OE
Output driver 0: 0 to disable the output, 1
to enable the output
0x0108
2
R/W
OUT0_RDIV_FORCE2
0 R0 divider value is set by R0_REG
1 R0 divider value is forced into divide by 2
Register 0x0109 Clock Output 0 Format
Reg Address
Bit Field
Type
Setting Name
0x0109
2:0
R/W
OUT0_FORMAT
0 Reserved
1 normal differential
2 low power differential
3 reserved
4 LVCMOS
5–7 reserved
0x0109
3
R/W
OUT0_SYNC_EN
0 disable
1 enable
enable/disable synchronized (glitchless) operation. When enabled, the power down and output
enables are synchronized to the output clock.
0x0109
5:4
R/W
OUT0_DIS_STATE
Determines the state of an output driver when disabled, selectable as
0 disable in low state
1 disable in high state
2 reserved
3 reserved
0x0109
7:6
R/W
OUT0_CMOS_DRV
LVCMOS output impedance. See Table 11.
Description
See "6.2. Performance Guidelines for Outputs" on page 20.
Rev. 1.1
69
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Si5341-40-RM
Si5341
Si5341-40-RM
Register 0x010A Clock Output 0 Amplitude and Common Mode Voltage
Reg Address
Bit Field
Type
Setting Name
Description
0x010A
3:0
R/W
OUT0_CM
This field only applies when OUT0_FORMAT=1 or 2.
See Table 11 and Appendix A for details of the settings.
0x010A
6:4
R/W
OUT0_AMPL
This field only applies when OUT0_FORMAT=1, 2, or
3. See Table 11 and Appendix A for details of the settings.
ClockBuilder Pro sets the correct common mode voltage and amplitude for LVDS, LVPECL, and HCSL outputs.
Register 0x010B Clock Output 0 Mux and Inversion
Reg Address
Bit Field
Type
Setting Name
0x010B
2:0
R/W
OUT0_MUX_SEL
0x010B
7:6
R/W
OUT0_INV
Description
Output driver 0 input mux select.This
selects the multisynth (N divider) that is
connected to the output driver.
0: N0
1: N1
2: N2
3: N3
4: N4
5: reserved
6: reserved
7: reserved
0: CLK and CLK not inverted
1: CLK inverted
2: CLK and CLK inverted
3: CLK inverted
Each of the 10 output drivers can be connected to any of the five N dividers. More than 1 output driver can connect
to the same N divider.
The 10 output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other 9
output drivers.
Table 26. Registers for OUT1,2,3,4,5,6,7,8,9 as per above for OUT0
70
Register Address
Description
(Same as) Address
0x010D
OUT1_PDN, OUT1_OE, OUT1_RDIV_FORCE2
0x0108
0x010E
OUT1_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x010F
OUT1_CM, OUT1_AMPL
0x010A
0x0110
OUT1_MUX_SEL, OUT1_INV
0x010B
0x0112
OUT2_PDN, OUT2_OE, OUT2_RDIV_FORCE2
0x0108
0x0113
OUT2_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0114
OUT2_CM, OUT2_AMPL
0x010A
Rev. 1.1
Table 26. Registers for OUT1,2,3,4,5,6,7,8,9 as per above for OUT0 (Continued)
Register Address
Description
(Same as) Address
0x0115
OUT2_MUX_SEL, OUT2_INV
0x010B
0x0117
OUT3_PDN, OUT3_OE, OUT3_RDIV_FORCE2
0x0108
0x0118
OUT3_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0119
OUT3_CM, OUT3_AMPL
0x010A
0x011A
OUT3_MUX_SEL, OUT3_INV
0x010B
0x011C
OUT4_PDN, OUT4_OE, OUT4_RDIV_FORCE2
0x0108
0x011D
OUT4_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x010A
0x011E
OUT4_CM, OUT4_AMPL
0x0105
0x011F
OUT4_MUX_SEL, OUT4_INV
0x010B
0x0121
OUT5_PDN, OUT5_OE, OUT5_RDIV_FORCE2
0x0108
0x0122
OUT5_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0123
OUT5_CM, OUT5_AMPL
0x010A
0x0124
OUT5_MUX_SEL, OUT5_INV
0x010B
0x0126
OUT6_PDN, OUT6_OE, OUT6_RDIV_FORCE2
0x0108
0x0127
OUT6_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x010A
0x0128
OUT6_CM, OUT6_AMPL
0x0109
0x0129
OUT6_MUX_SEL, OUT6_INV
0x010B
0x012B
OUT7_PDN, OUT7_OE, OUT7_RDIV_FORCE2
0x0108
0x012C
OUT7_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x012D
OUT7_CM, OUT7_AMPL
0x010A
0x012E
OUT7_MUX_SEL, OUT7_INV
0x010B
0x0130
OUT8_PDN, OUT8_OE, OUT8_RDIV_FORCE2
0x0108
0x0131
OUT8_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0132
OUT8_CM, OUT8_AMPL
0x010A
0x0133
OUT8_MUX_SEL, OUT8_INV
0x010B
0x013A
OUT9_PDN, OUT9_OE, OUT9_RDIV_FORCE2
0x0108
0x013B
OUT9_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x013C
OUT9_CM, OUT9_AMPL
0x010A
0x013D
OUT9_MUX_SEL, OUT9_INV
0x010B
Rev. 1.1
71
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Si5341
Si5341-40-RM
Register 0x0135 to 0x0139 User Scratch
Reg Address
Bit Field
Type
Setting Name
Description
0x0135
7:0
R/W
User Scratch
User R/W byte
0x0136
7:0
R/W
User Scratch
User R/W byte
0x0137
7:0
R/W
User Scratch
User R/W byte
0x0138
7:0
R/W
User Scratch
User R/W byte
0x0139
7:0
R/W
User Scratch
User R/W byte
Register 0x0145 Power Down All Outputs
72
Reg Address
Bit Field
Type
Setting Name
0x0145
0
R/W
OUT_PDN_ALL
Rev. 1.1
Description
0- no effect
1- all drivers powered down
15.2.3. Page 2 Registers Si5341
Register 0x0202-0x0205 XAXB Frequency Adjust
Reg Address
Bit Field
Type
Setting Name
0x0202
7:0
R/W
XAXB_FREQ_OFFSET
0x0203
15:8
R/W
XAXB_FREQ_OFFSET
0x0204
23:16
R/W
XAXB_FREQ_OFFSET
0x0205
31:24
R/W
XAXB_FREQ_OFFSET
Description
32 bit 2’s complement offset
adjustment
The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The
XAXB_FREQ_OFFSET word is added to the M_NUM to shift the VCO frequency to compensate for a crystal that
does not have an 8 pf CL specification.
Register 0x0206 PXAXB Divider
Reg Address
Bit Field
Type
Setting Name
Description
0x0206
1:0
R/W
PXAXB
Sets the value for the divider on the
XAXB input.

0 = divider value 1
 1 = divider value 2
 2 = divider value 4
 3 = divider value 8
Register 0x0208, 0x0212, 0x021C, 0x0226 P Dividers
Reg Address
Bit Field
Type
Setting Name
0x0208
7:0
R/W
P0
0x0212
7:0
R/W
P1
0x021C
7:0
R/W
P2
0x0226
7:0
R/W
PFB
Description
8-bit Integer Number
This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 2.
ClockBuilder Pro calculates the correct values for the P-dividers.
Register 0x020E P0 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
Description
0x020E
7:0
R/W
P0_SET
Do not write to this bit. This byte must
always be 0x01 for the P0 divider to
work.
Rev. 1.1
73
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Si5341
Si5341-40-RM
Register 0x0218 P1 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
Description
0x0218
7:0
R/W
P1_SET
Do not write to this bit. This byte must
always be 0x01 for the P1 divider to
work.
Register 0x0222 P2 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
Description
0x0222
7:0
R/W
P2_SET
Do not write to this bit. This byte must
always be 0x01 for the P2 divider to
work.
Register 0x022C PFB Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
Description
0x022C
7:0
R/W
PFB_SET
Do not write to this bit. This byte must
always be 0x01 for the PFB divider to
work.
Description
Register 0x0230 P Divider Update Bits
Reg Address
Bit Field
Type
Setting Name
0x0230
0
S
P0_UPDATE
Must write a 1 to this bit to cause a
change to the P0 divider to take
effect.
0x0230
1
S
P1_UPDATE
Must write a 1 to this bit to cause a
change to the P1 divider to take
effect.
0x0230
2
S
P2_UPDATE
Must write a 1 to this bit to cause a
change to the P2 divider to take
effect.
0x0230
3
S
PFB_UPDATE
Must write a 1 to this bit to cause a
change to the PFB divider to take
effect.
Bits 7:4 of this register have no function and can be written to any value
74
Rev. 1.1
Register 0x023F M Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x023F
0
S
M_UPDATE
Description
Must write a 1 to this bit to cause M
divider changes to take effect.
Bits 7:1 of this register have no function and can be written to any value
Register 0x0235-0x023A M Divider Numerator
Reg Address
Bit Field
Type
Setting Name
0x0235
7:0
R/W
M_NUM
0x0236
15:8
R/W
M_NUM
0x0237
23:16
R/W
M_NUM
0x0238
31:24
R/W
M_NUM
0x0239
39:32
R/W
M_NUM
0x023A
43:40
R/W
M_NUM
Description
44-bit Integer Number
Register 0x023B-0x023E M Divider Denominator
Reg Address
Bit Field
Type
Setting Name
0x023B
7:0
R/W
M_DEN
0x023C
15:8
R/W
M_DEN
0x023D
23:16
R/W
M_DEN
0x023E
31:24
R/W
M_DEN
Description
32-bit Integer Number
The M-divider numerator and denominator are set by ClockBuilder Pro for a given frequency plan.
Register 0x024A-0x024C R0 Divider
Reg Address
Bit Field
Type
Setting Name
Description
0x024A
7:0
R/W
R0_REG
0x024B
15:8
R/W
R0_REG
0x024C
23:16
R/W
R0_REG
24-bit Integer Number. Divide
value = (R0_REG+1) x 2
To set R0 = 2, set
OUT0_RDIV_FORCE2 = 1, and then
the R0_REG value is irrelevant.
Setting R0_REG=0 will disable the
divider.
The R dividers are with the output drivers and are even integer dividers. The R1–R9 dividers follow the same
format as the R0 divider described above.
Rev. 1.1
75
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Si5341
Si5341-40-RM
Table 27. R Dividers for Outputs 1,2,3,4,5,6,7,8,9
Register Address
Setting Name
Size
Same as Address
0x024D-0x024F
R1_REG
24-bit Integer Number
0x024A-0x024C
0x0250-0x0252
R2_REG
24-bit Integer Number
0x024A-0x024C
0x0253-0x0255
R3_REG
24-bit Integer Number
0x024A-0x024C
0x0256-0x0258
R4_REG
24-bit Integer Number
0x024A-0x024C
0x0259-0x025B
R5_REG
24-bit Integer Number
0x024A-0x024C
0x025C-0x025E
R6_REG
24-bit Integer Number
0x024A-0x024C
0x025F-0x0261
R7_REG
24-bit Integer Number
0x024A-0x024C
0x0262-0x0264
R8_REG
24-bit Integer Number
0x024A-0x024C
0x0268-0x026A
R9_REG
24-bit Integer Number
0x024A-0x024C
Register 0x026B–0x0272 Design ID
76
Reg Address
Bit Field
Type
Setting Name
Description
0x026B
7:0
R/W
DESIGN_ID0
0x026C
15:8
R/W
DESIGN_ID1
0x026D
23:16
R/W
DESIGN_ID2
0x026E
31:24
R/W
DESIGN_ID3
0x026F
39:32
R/W
DESIGN_ID4
0x0270
47:40
R/W
DESIGN_ID5
0x0271
55:48
R/W
DESIGN_ID6
0x0272
63:56
R/W
DESIGN_ID7
ASCII encoded string defined by
CBPro user, with user defined space
or null padding of unused characters.
A user will normally include a configuration ID + revision ID. For example,
“ULT.1A” with null character padding
sets:
DESIGN_ID0: 0x55
DESIGN_ID1: 0x4C
DESIGN_ID2: 0x54
DESIGN_ID3: 0x2E
DESIGN_ID4: 0x31
DESIGN_ID5: 0x41
DESIGN_ID6:0x 00
DESIGN_ID7: 0x00
Rev. 1.1
Register 0x0278-0x027C OPN Identifier
Reg Address
Bit Field
Type
Setting Name
0x0278
7:0
R/W
OPN_ID0
0x0279
15:8
R/W
OPN_ID1
0x027A
23:16
R/W
OPN_ID2
0x027B
31:24
R/W
OPN_ID3
0x027C
39:32
R/W
OPN_ID4
Description
OPN unique identifier. ASCII
encoded. For example, with OPN:
5341C-A12345-GM, 12345 is the
OPN unique identifier, which sets:
OPN_ID0: 0x31
OPN_ID1: 0x32
OPN_ID2: 0x33
OPN_ID3: 0x34
OPN_ID4: 0x35
Part numbers are of the form:
Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>
Examples:
Si5341C-A12345-GM.
Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the
frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file.
Si5341C-A-GM.
Applies to a “base” or “blank” OPN device. Base devices are factory pre-programmed to a specific base part type
(e.g., Si5341 but exclude any user-defined frequency plan or other user-defined operating characteristics selected
in ClockBuilder Pro.
Register 0x027D OPN Revision
Reg Address
Bit Field
Type
Setting Name
0x027D
7:0
R/W
OPN_Revision
Description
ClockBuilder Pro sets this value based
upon changes to the NVM for a given
OPN.
Register 0x027E Baseline ID
Reg Address
Bit Field
Type
Setting Name
0x027E
7:0
R/W
BaseLine ID
Rev. 1.1
Description
An identifier for the device NVM without
the frequency plan programmed into
NVM.
77
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Si5341
Si5341-40-RM
15.2.4. Page 3 Registers Si5341
Register 0x0302-0x0307 N0 Numerator
Reg Address
Bit Field
Type
Setting Name
0x0302
7:0
R/W
N0_NUM
0x0303
15:8
R/W
N0_NUM
0x0304
23:16
R/W
N0_NUM
0x0305
31:24
R/W
N0_NUM
0x0306
39:32
R/W
N0_NUM
0x0307
43:40
R/W
N0_NUM
Description
44-bit Integer Number
The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder
Pro calculates the correct values for the N-dividers.
Register 0x0308-0x030B N0 Denominator
Reg Address
Bit Field
Type
Setting Name
0x0308
7:0
R/W
N0_DEN
0x0309
15:8
R/W
N0_DEN
0x030A
23:16
R/W
N0_DEN
0x030B
31:24
R/W
N0_DEN
Description
32-bit Integer Number
Register 0x030C N0 Divider Update Bit
78
Reg Address
Bit Field
Type
Setting Name
0x030C
0
S
N0_UPDATE
Rev. 1.1
Description
Must write a 1 to this bit to cause N0
divider changes to take effect,
Table 28. N1, N2, N3 Numerator and Denominators
Register Address
Setting Name
Size
Same as Address
0x030D-0x0312
N1_NUM
44-bit Integer Number
0x0302-0x0307
0x0313-0x0316
N1_DEN
32-bit Integer Number
0x0308-0x030B
0x0318-0x031D
N2_NUM
44-bit Integer Number
0x0302-0x0307
0x031E-0x0321
N2_DEN
32-bit Integer Number
0x0308-0x030B
0x0323-0x0328
N3_NUM
44-bit Integer Number
0x0302-0x0307
0x0329-0x032C
N3_DEN
32-bit Integer Number
0x0308-0x030B
0x032E-0x0333
N4_NUM
44-bit Integer Number
0x0302-0x0307
0x0334-0x0337
N4_DEN
32-bit Integer Number
0x0308-0x030B
Register 0x0317 N1 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0317
0
S
N1_UPDATE
Description
Must write a 1 to this bit to cause N1
divider changes to take effect.
Register 0x0322 N2 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0322
0
S
N2_UPDATE
Description
Must write a 1 to this bit to cause N2
divider changes to take effect.
Register 0x032D N3 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x032D
0
S
N3_UPDATE
Description
Must write a 1 to this bit to cause N3
divider changes to take effect.
Register 0x0338 N4 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0338
0
S
N4_UPDATE
Rev. 1.1
Description
Must write a 1 to this bit to cause N4
divider changes to take effect.
79
Si5341
Si5341-40-RM
Si5341
Si5341-40-RM
Register 0x0338 All N Dividers Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0338
1
S
N_UPDATE
Description
Writing a 1 to this bit will update all N
dividers to the latest value written to
them. A specific N divider that has not
been changed will not be affected by
writing a 1 to this bit. When this bit is
written to a 1, all other bits in this byte
should only be written to a 0.
Register 0x0339 FINC/FDEC Masks
Reg Address
Bit Field
Type
Setting Name
0x0339
4:0
R/W
N_FSTEP_MSK
Description
0 to enable FINC/FDEC updates
1 to disable FINC/FDEC updates

Bit 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0]
Bit 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1]
 Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339[2]
 Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339[3]
 Bit 4 corresponds to MultiSynth N4 N_FSTEP_MSK 0x0339[4]
There is one mask bit for each of the five N dividers.

Register 0x033B-0x0340 N0 Frequency Step Word
Reg Address
Bit Field
Type
Setting Name
0x033B
7:0
R/W
N0_FSTEPW
0x033C
15:8
R/W
N0_FSTEPW
0x033D
23:16
R/W
N0_FSTEPW
0x033E
31:24
R/W
N0_ FSTEPW
0x033F
39:32
R/W
N0_ FSTEPW
0x0340
43:40
R/W
N0_ FSTEPW
Description
44-bit Integer Number
This is a 44-bit integer value which is directly added (FDEC) or subtracted (FINC) from the Nx_NUM parameter
when FINC or FDEC is asserted. ClockBuilder Pro calculates the correct values for the N0 Frequency Step Word.
Each N divider has the ability to add or subtract up to a 44-bit value. The Nx_NUM register value does not change
when an FINC or FDEC is performed so that the starting point of Nx_NUM is in the Nx_NUM register.
80
Rev. 1.1
Table 29. Frequency Step Word for N1, N2, N3, N4
Register Address
Setting Name
Size
Same as Address
0x0341-0x0346
N1_FSTEPW
44-bit Integer Number
0x033B-0x0340
0x0347-0x034C
N2_FSTEPW
44-bit Integer Number
0x033B-0x0340
0x034D-0x0352
N3_FSTEPW
44-bit Integer Number
0x033B-0x0340
0x0353-0x0358
N4_FSTEPW
44-bit Integer Number
0x033B-0x0340
Register 0x0359–0x35A N0 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x0359
7:0
R/W
N0_DELAY[7:0]
Lower byte of N0_DELAY[15:0]
0x035A
7:0
R/W
N0_DELAY[15:8]
Upper byte of N0_DELAY[15:0]
Description
Register 0x035B-0x035C Divider N1 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035B
7:0
R/W
N1_DELAY[7:0]
Lower byte of N1_DELAY[15:0]
0x035C
7:0
R/W
N1_DELAY[15:8]
Upper byte of N1_DELAY[15:0]
Description
Register 0x035D-0x035E Divider N2 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035D
7:0
R/W
N2_DELAY[7:0]
Lower byte of N2_DELAY[15:0]
0x035E
7:0
R/W
N2_DELAY[15:8]
Upper byte of N2_DELAY[15:0]
Description
Register 0x035F-0x0360 Divider N3 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035F
7:0
R/W
N3_DELAY[7:0]
Lower byte of N3_DELAY[15:0]
0x0360
7:0
R/W
N3_DELAY[15:8]
Upper byte of N3_DELAY[15:0]
Rev. 1.1
Description
81
Si5341
Si5341-40-RM
Si5341
Si5341-40-RM
Register 0x0361–0x0362 Divider N4 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x0361
7:0
R/W
N4_DELAY[7:0]
Lower byte of N4_DELAY[15:0]
0x0362
15:8
R/W
N4_DELAY[15:8]
Upper byte of N4_DELAY[15:0]
Description
The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive
and negative delay is ±(215–1)/(256 x Fvco). Nx_DELAY values are only applied at power up or during a reset.
ClockBuilder Pro calculates the correct value for this register. It is expected that only the upper byte of Nx_DELAY
is necessary as the step sizes in the lower byte are so small as to be essentially irrelevant. At power up or when
the RSTb pin is asserted, the Nx_DELAY values are downloaded from NVM. If Nx_DELAY is written via the serial
port, the SOFT_RST reset bit must be written to cause the delay to take effect.
15.2.5. Page 9 Registers Si5341
Register 0x090E XAXB Configuration
Reg Address
Bit Field
Type
Setting Name
0x090E
0
R/W
XAXB_EXTCLK_EN
0x090E
1
R/W
XAXB_PDNB
Description
0 to use a crystal at the XAXB pins
1 to use an external clock source at the
XAXB pins. A singled ended clock must
be applied at the XA input.
0-Power down the oscillator and buffer circuitry at the XA/XB pins
1- No power down
Register 0x091C Enable Zero Delay Mode
Reg Address
Bit Field
Type
Setting Name
0x091C
2:0
R/W
ZDM_EN
Description
3 = Zero delay mode
4 = Normal mode
All other values must not be written.
Register 0x0943 Status and Control I/O Voltage Select
Reg Address
Bit Field
Type
Setting Name
0x0943
0
R/W
IO_VDD_SEL
Description
0 for 1.8 V external connections
1 for 3.3 V external connections
The IO_VDD_SEL configuration bit selects the option of operating the serial interface voltage thresholds from the
VDD or the VDDA pin. By default the IO_VDD_SEL bit is set to the VDD option. The serial interface pins are
always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is
operating at 3.3 V and the Si5341/40 IO_VDD_SEL = 1.8 V, the host should write the IO_VDD_SEL configuration
bit to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum
82
Rev. 1.1
voltage thresholds. The IO_VDD_SEL bit also affects the status pin levels and control pin thresholds. When
IO_VDD_SEL = 0, the status outputs will have a VOH of ~1.8 V. When IO_VDD_SEL = 1 the status outputs will
have a VOH of ~3.3 V. When IO_VDD_SEL=0, the control input pins will have an input threshold based upon the
VDD supply voltage of 1.8 V. When IO_VDD_SEL=1, the control input pins will have an input threshold based upon
the VDDA supply voltage of 3.3 V. See Table 4 and Table 6 of the Si5341/40 data sheet for details.
Register 0x0949 Clock Input Control
Reg Address
0x0949
Bit Field
3:0
Type
R/W
Setting Name
IN_EN
Description
Enables for the four inputs clocks, IN0 through
FB_IN.
1 to enable, 0 to disable

Input 0 corresponds to IN_EN 0x0949 [0]
 Input 1 corresponds to IN_EN 0x0949 [1]
 Input 2 corresponds to IN_EN 0x0949 [2]
 FB_IN corresponds to IN_EN 0x0949 [3]
Register 0x094A Input Clock Routing Enable
Reg Address
0x094A
Bit Field
6:4
Type
R/W
Setting Name
INx_TO_PFD_EN
Description
When = 1, enables the routing of the 3 input
clocks IN0,1,2 to the Phase Detector. Each bit corresponds to the inputs as follows [6:4] = [IN2 IN1
IN0]. IN_SEL is used to select the input clock that
is applied to the phase detector.
15.2.6. Page A Registers Si5341
Register 0x0A03 N Divider Clocks
Reg Address
0x0A03
Bit Field
4:0
Type
R/W
Setting Name
N_CLK_TO_OUTX_EN
Description
BIts in this field correspond to the N dividers as [N4 N3 N2 N1 N0]. If an N divider is
used, the corresponding bit must be 1. See
also registers 0x0A05 and 0x0B4A[4:0].
Register 0x0A04 N Divider Phase Interpolator Bypass
Reg Address
0x0A04
Bit Field
4:0
Type
R/W
Setting Name
N_PIBYP
Description
Bypasses the Phase Interpolator of the N Multisynth
divider. Set to a 1 when the value of N divider is integer and will not be used as a DCO. Set to a 0 when
the value of N is fractional (used as a DCO). Slightly
lower output jitter may occur when the Phase Interpolator is bypassed (=1). Bits in this field correspond to
the N dividers as [N4 N3 N2 N1 N0].
Rev. 1.1
83
Si5341
Si5341-40-RM
Si5341
Si5341-40-RM
Register 0x0A05 N Divider Power Down
Reg Address
Bit Field
Type
Setting Name
Description
0x0A05
4:0
R/W
N_PDNB
Powers down the N divider. If an N
divider is not used, set the respective bit to 0 to power it down. Bits in
this field correspond to the N dividers as [N4 N3 N2 N1 N0]. See also
registers 0x0A03 and 0x0B4A[4;0].
Description
15.2.7. Page B Registers Si5341
Register 0x0B46 Loss of Signal Clock Disable
Reg Address
Bit Field
Type
Setting Name
0x0B46
3:0
R/W
LOS_CLK_DIS
Controls the clock to the digital
LOS circuitry. Must be set to 0 to
enable the LOS function of the
respective Inputs [FB_IN IN2 IN1
IN0].
Register 0x0B49 Calibration Bits
Reg Address
Bit Field
Type
Setting Name
Description
0x0B49
1:0
R/W
CAL_DIS
All bits must be low for proper operation.
0x0B49
3:2
R/W
CAL_FORCE
All bits must be low for proper operation.
Register 0x0B4A Divider Clock Disables
84
Reg Address
Bit Field
Type
Setting Name
Description
0x0B4A
4:0
R/W
N_CLK_DIS
Controls the clock to the N divider. If an N
divider is used the corresponding bit must be 0.
[N3 N2 N1 N0]. See also registers 0x0A03 and
0x0A05.
0x0B4A
5
R/W
M_CLK_DIS
Controls the clock to the M divider. Must be set
to 0 to enable the M divider.
0x0B4A
6
R/W
M_DIV_CAL_DIS
Controls the clock to the calibration circuitry in
the M divider. Must be set to 0 as calibration is
required on every power up or Reset.
Rev. 1.1
15.3. Si5340 Registers
Because preprogrammed devices are inherently quite different from one another, the default power up values of
the registers can be determined using the custom OPN utility at: http://www.silabs.com/products/clocksoscillators/
pages/clockbuilderlookup.aspx. Some registers that are listed in the Data Sheet Addendum are not documented in
the Register Map below because they are set and maintained by Clock Builder Pro. In almost all circumstances,
these registers should not be modified by the user. For more details, please contact Silicon Labs.
15.3.1. Page 0 Registers Si5340
Register 0x0000 Die Rev
Reg Address
Bit Field
Type
Setting Name
0x0000
3:0
R
DIE_REV
Reg Address
Bit Field
Type
Setting Name
0x0001
7:0
R/W
PAGE
Description
4- bit Die Revision Number
Register 0x0001 Page
Description
Selects one of 256 possible pages.
There is the “Page Register” which i s located at address 0x01 on every page. When read, it will indicate the
current page. When written, it will change the page to the value entered. There is a page register at address
0x0001, 0x0101, 0x0201, 0x0301, … etc.
Register 0x0002–0x0003 Base Part Number
Reg Address
Bit Field
Type
Setting
Name
0x0002
7:0
R
PN_BASE
0x0003
15:8
R
PN_BASE
Description
Four-digit “base” part number, one nibble per digit
Example: Si5340A-A-GM. The base part number
(OPN) is 5340, which is stored in this register
Register 0x0004 Device Speed/Synthesis Mode Grade
Reg Address
Bit Field
Type
Setting Name
0x0004
7:0
R
GRADE
Rev. 1.1
Description
One ASCII character indicating the device
speed grade
0=A
1=B
2=C
3=D
85
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x0005 Device Revision
Reg Address
Bit Field
Type
0x0005
7:0
R
Setting Name
DEVICE_REV
Description
One ASCII character indicating the device
revision level.
0=A
Example Si5340C-A12345-GM, the device
revision is “A” and stored as 0
Register 0x0006–0x0008 NVM Identifier
Setting Name
Reg Address
Bit Field
Type
Description
0x0006
3:0
R
TOOL_VERSION[3:0] Special
0x0006
7:4
R
TOOL_VERSION[7:4] Revision
0x0007
7:0
R
TOOL_VERSION[15:8] Minor[7:0]
0x0008
0
R
TOOL_VERSION[15:8] Minor[8]
0x0008
4:1
R
TOOL_VERSION[16]
0x0008
7:5
R
TOOL_VERSION[13:17]
Type
Setting Name
Major
Tool. 0 for Clockbuilder Pro
Register 0x0009 Temperature Grade
Reg Address
Bit Field
0x0009
7:0
TEMP_GRADE
Description
Device temperature grading
0 = Industrial (-40° C to 85° C) ambient
conditions
Register 0x000A Package ID
Reg Address
Bit Field
0x000A
7:0
Type
Setting Name
PKG_ID
Description
Package ID
0 = 9x9 mm 64 QFN
1 = 7x7 mm 44 QFN
Part numbers are of the form:
Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>
Examples:
Si5341C-A-12345-GM.
Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the
frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file.
Si5341C-A-GM.
86
Rev. 1.1
Applies to a “base” or “blank” OPN device. Base devices are factory pre-programmed to a specific base part type
(e.g., Si5341 but exclude any user-defined frequency plan or other user-defined operating characteristics selected
in ClockBuilder Pro.
Register 0x000B I2C Address
Reg Address
Bit Field
Type
Setting Name
0x000B
6:0
R/W
I2C_ADDR
Description
7 bit I2C Address
Register 0x000C Status Bits
Reg Address
Bit Field
Type
Setting Name
0x000C
0
R
SYSINCAL
1 if the device is calibrating.
0x000C
1
R
LOSXAXB
1 if there is no signal at the XA pin as the LOS
detector is only connected to the XA pin.
0x000C
2
R
LOSREF
1 if the Phase Detector does not have an input
from FB_IN, IN2, IN1, or IN0.
0x000C
3
R
LOL
0x000C
4
R
0x000C
5
R
Description
1 if the DSPLL is out of lock.
SMB_TMOUT
1 if there is an SMBus timeout error.
Register 0x000D INx Loss of Signal (LOS) Alarms
Reg Address
Bit Field
Type
Setting Name
0x000D
3:0
R
LOS
Description
1 if no clock is present at [FB_IN, IN2,
IN1, IN0]
Note that each bit corresponds to the input. The LOS bits are not sticky.





Input 0 (IN0) corresponds to LOS at 0x000D [0]
Input 1 (IN1) corresponds to LOS at 0x000D [1]
Input 2 (IN2) corresponds to LOS at 0x000D [2]
FB_IN corresponds to LOS at 0x000D [3]
See also LOSXAXB for LOS at the XAXB input
Rev. 1.1
87
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x0011 Sticky versions of Status Bits
Reg Address
Bit Field
Type
Setting Name
Description
0x0011
0
R
SYSINCAL_FLG
Sticky version of SYSINCAL. Write a 0 to
clear the flag.
0x0011
1
R
LOSXAXB_FLG
Sticky version of LOSXAXB. Write a 0 to
clear the flag.
0x0011
2
R
LOSREF_FLG
Sticky version of LOSREF. Write a 0 to
clear the flag.
0x0011
3
R
LOL_FLG
Sticky version of LOL. Write a 0 to clear
the flag.
0x0011
4
R
0x0011
5
R
SMB_TMOUT_FLG
Sticky version of SMBUS_TIMEOUT.
Write a 0 to clear the flag.
Register 0x0012 INx LOS Flags
Reg Address
Bit Field
Type
Setting Name
Description
0x0012
3:0
R/W
LOS_FLG
Sticky version of LOS. Write a 0 to clear each individual flag.
Register 0x0017 Status Flag Interrupt Masks
Reg Address
Bit Field
Type
0x0017
0
R/W
Setting Name
SYSINCAL_INTR_MSK
0x0017
1
R/W
LOSXAXB_INTR_MSK
0x0017
2
R/W
LOSREF_INTR_MSK
0x0017
3
R/W
LOL_INTR_MSK
0x0017
0x0017
4
5
R/W
R/W
Description
1 to mask SYSINCAL_FLG from causing an
interrupt
1 to mask the LOSXAXB_FLG from causing
an interrupt
1 to mask the LOSREF_FLG from causing an
interrupt
1 to mask the LOL_FLG from causing an
interrupt
SMB_TMOUT_INTR_MSK 1 to mask SMBUS_TIMEOUT_FLG from
causing an interrupt
These are the interrupt mask bits for the flags in register 0x0011. If a mask bit is set, the alarm will be blocked from
causing an interrupt.
88
Rev. 1.1
Register 0x0018 Interrupt Masks
Reg Address
Bit Field
Type
0x0018
3:0
R/W
Setting Name
Description
LOS_INTR_MSK
1 to mask the interrupt from LOS_FLG[3:0].
Write a 0 to clear each individual FLAG.
Register 0x001C Soft Reset
Reg Address
Bit Field
Type
Setting Name
Description
0x001C
0
S
SOFT_RST
1 Performs a soft rest. Resets the device while
not re-downloading the register configuration
from NVM. If output-output skew is needed and
VDDOx does not come up before VDD/VDDA
then a soft reset will align the output clocks.
0 No effect
This bits are of type “S”, which is self-clearing.
Register 0x001D FINC, FDEC
Reg Address
Bit Field
Type
Setting Name
0x001D
0
S
FINC
1 A rising edge will cause a frequency increment.
See also N_FSTEP_MSK and Nx_FSTEPW
0 No effect
0x001D
1
S
FDEC
1 A rising edge will cause a frequency decrement.
See also N_FSTEP_MSK and Nx_FSTEPW
0 No effect
Description
Register 0x001E Sync, Power Down and Hard Reset
Reg Address
Bit Field
Type
Setting Name
0x001E
0
R/W
PDN
0x001E
1
R/W
HARD_RST
0x001E
2
S
SYNC
Rev. 1.1
Description
1 to put the device into low power mode
1 causes hard reset. The same as power up
except that the serial port access is not held at
reset. NVM is re-downloaded. This does not selfclear, so after setting the bit it must be cleared.
0 No reset
Logically equivalent to asserting the SYNC pin.
Resets all R dividers to the same state.
89
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x0021 Input Clock Selection
Reg Address
Bit Field
Type
Setting Name
Description
0x0021
0
R/W
IN_SEL_REGCTRL
Selects between register controlled reference clock selection and pin controlled
clock selection using IN_SEL1 and IN_SEL0 pins:
0 for pin controlled clock selection
1 for register clock selection
0x0021
2:1
R/W
IN_SEL
Selects the reference clock input to the
PLL when IN_SEL_REGCTRL=1.
0 IN0
1 IN1
2 IN2
3 XA/XB
Register 0x002B SPI 3 vs 4 Wire
Reg Address
Bit Field
Type
Setting Name
0x002B
3
R/W
SPI_3WIRE
Description
0 for 4-wire SPI, 1 for 3-wire SPI
Register 0x002C LOS Enable
Reg Address
Bit Field
Type
Setting Name
0x002C
3:0
R/W
LOS_EN
0x002C
4
R/W
LOSXAXB_DIS
Description
1 to enable LOS for a clock input;
0 for disable
0 to enable LOS for the XAXB input
1 to disable the LOS for the XAXB input

Input 0 (IN0): LOS_EN[0]
Input 1 (IN1): LOS_EN[1]
 Input 2 (IN2): LOS_EN[2]
 FB_IN: LOS_EN[3]

Register 0x002D Loss of Signal Time Value
90
Reg Address
Bit Field
Type
Setting Name
0x002D
1:0
R/W
LOS0_VAL_TIME
Rev. 1.1
Description
Clock Input 0
0 for 2 msec
1 for 100 msec
2 for 200 msec
3 for one second
Register 0x002D Loss of Signal Time Value
0x002D
3:2
R/W
LOS1_VAL_TIME
Clock Input 1, same as above
0x002D
5:4
R/W
LOS2_VAL_TIME
Clock Input 2, same as above
When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time
that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME.
Register 0x002E-0x002F LOS0 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x002E
7:0
R/W
LOS0_TRG_THR
0x002F
15:8
R/W
LOS0_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency
plan.
Register 0x0030-0x0031 LOS1 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x0030
7:0
R/W
LOS1_TRG_THR
0x0031
15:8
R/W
LOS1_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency
plan.
Register 0x0032-0x0033 LOS2 Trigger Threshold
Reg Address
Bit Field
Type
Setting Name
0x0032
7:0
R/W
LOS2_TRG_THR
0x0033
15:8
R/W
LOS2_TRG_THR
Description
16-bit Threshold Value
ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency
plan.
Register 0x0041-0x0044 LOS Pre-Divider for IN0, IN1, IN3, FB_IN
Reg Address Bit Field
Type
Setting Name
Description
0x0041
7:0
R/W
LOS0_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
0x0042
7:0
R/W
LOS1_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
Rev. 1.1
91
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x0041-0x0044 LOS Pre-Divider for IN0, IN1, IN3, FB_IN
0x0043
7:0
R/W
0x0044
7:0
R/W
LOS2_DIV_SEL
A pre-divider that is configured by ClockBuilder Pro
LOSFB_IN_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
The following are the predivider values for the above register values.
Register Value (Decimal)
Divider Value
0
1 (bypass)
1
2
2
4
3
8
4
16
5
32
6
64
7
128
8
256
9
512
10
1024
11
2048
12
4096
13
8192
14
16384
15
32768
16
65536
Register 0x00E2 Active NVM Bank
92
Reg Address
Bit Field
Type
0x00E2
5:0
R
Description
Setting Name
ACTIVE_NVM_BANK 0x033 when no NVM burn by customer
0x0F when 1 NVM bank has been burned
by customer
0x3F when 2 NVM banks have been
burned by customer
When ACTIVE_NVM_BANK=0x3F, the
last bank has already been burned. See
section 3.2 for a detailed description of
how to program the NVM.
Rev. 1.1
Register 0x00E3
Reg Address
Bit Field
Type
Setting Name
Description
0x00E3
7:0
R/W
NVM_WRITE
Write 0xC7 to initiate an NVM bank burn.
Reg Address
Bit Field
Type
Setting Name
Description
0x00E4
0
S
NVM_READ_BANK
When set, this bit will read the NVM down
into the volatile memory.
Description
Register 0x00E4
Register 0x00FE Device Ready
Reg Address
Bit Field
Type
Setting Name
0x00FE
7:0
R
DEVICE_READY
0x0F when device is ready
0xF3 when device is not ready
Read-only byte to indicate when the device is ready to accept serial bus transactions. The user can poll this byte
starting at power-on; when DEVICE_READY is 0x0F the user can safely read or write to any other register. This is
only needed after power up or a hard reset using register bit 0x001E[1]. The “Device Ready” register is available on
every page in the device at the second last register, 0xFE.
Rev. 1.1
93
Si5340
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Si5340
Si5341-40-RM
15.3.2. Page 1 Registers Si5340
Register 0x0102 All Output Clock Driver Disable
Reg Address
Bit Field
Type
Setting Name
Description
0x0102
0
R/W
OUTALL_DISABLE_LOW
0 disables all output drivers
1 no output drivers are disabled by
this bit but other signals may disable
the outputs.
Register 0x0112 Clock Output Driver 0 Configs and Div2 Mode
Reg Address
Bit Field
Type
Setting Name
Description
0x0112
0
R/W
OUT0_PDN
Output driver 0: 0 to power up the driver, 1
to power down the driver. Clock outputs
will be weakly pulled-low.
0x0112
1
R/W
OUT0_OE
Output driver 0: 0 to disable the output, 1
to enable the output
0x0112
2
R/W
OUT0_RDIV_FORCE2
0 R0 divider value is set by R0_REG
1 R0 divider value is forced into divide by 2
Register 0x0113 Clock Output Driver 0 Format
94
Reg Address
Bit Field
Type
Setting Name
0x0113
2:0
R/W
OUT0_FORMAT
0 Reserved
1 normal differential
2 Low Power differential
3 reserved
4 LVCMOS
5–7 reserved
0x0113
3
R/W
OUT0_SYNC_EN
0 disable
1 enable
0x0113
5:4
R/W
OUT0_DIS_STATE
Determines the state of an output driver when
disabled, selectable as
0 disable in low state
1 disable in high state
2 reserved
3 reserved
0x0113
7:6
R/W
OUT0_CMOS_DRV
LVCMOS output impedance.
Rev. 1.1
Description
Register 0x0114 Output 0 Amplitude and Common Mode Voltage
Reg Address
Bit Field
Type
Setting Name
Description
0x0114
3:0
R/W
OUT0_CM
This field only applies when OUT0_FORMAT=1 or 2.
See Table 11 and Appendix A for details of the settings.
0x0114
6:4
R/W
OUT0_AMPL
This field only applies when OUT0_FORMAT=1, 2, or
3. See Table 11 and Appendix A for details of the settings when the OUT0_FORMAT=1 or 2.
Register 0x0115 Clock Output 0 Mux and Inversion
Reg Address
Bit Field
Type
0x0115
2:0
R/W
Setting Name
OUT0_MUX_SEL
0x0115
7:6
R/W
OUT0_INV
Description
Output driver 0 input mux select.This
selects the source of the multisynth.
0: N0
1: N1
2: N2
3: N3
4: reserved
5: reserved
6: reserved
7: reserved
CLK and CLK not inverted
CLK inverted
CLK and CLK inverted
CLK inverted
Each of the 10 output drivers can be connected to any of the five N dividers. More than 1 output driver can connect
to the same N divider.
The four output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other
three output drivers.
Table 30. Registers for OUT1,2,3 as per OUT0 Above
Register Address
Description
(Same as) Address
0x0117
OUT1_PDN, OUT1_OE, OUT1_RDIV_FORCE2
0x0108
0x0118
OUT1_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0119
OUT1_AMPL, OUT1_CM
0x010A
0x011A
OUT1_MUX_SEL, OUT1_INV
0x010B
0x011B
OUT2_PDN, OUT2_OE, OUT2_RDIV_FORCE2
0x0108
0x0126
OUT2_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x0127
OUT2_AMPL, OUT2_CM
0x010A
0x0128
OUT2_MUX_SEL, OUT2_INV
0x010B
0x0129
OUT3_PDN, OUT3_OE, OUT3_RDIV_FORCE2
0x0108
Rev. 1.1
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Si5341-40-RM
Table 30. Registers for OUT1,2,3 as per OUT0 Above (Continued)
Register Address
Description
(Same as) Address
0x012A
OUT3_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x0109
0x012B
OUT3_AMPL, OUT3_CM
0x010A
0x012C
OUT3_MUX_SEL, OUT3_INV
0x010B
0x012D
OUT4_PDN, OUT4_OE, OUT4_RDIV_FORCE2
0x0108
0x012E
OUT4_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV
0x010A
0x012F
OUT4_AMPL, OUT4_CM
0x0105
Register 0x0135–0x0139 User Scratch
Reg Address
Bit Field
Type
Setting Name
Description
0x0135
7:0
R/W
User Scratch
User R/W byte
0x0136
7:0
R/W
User Scratch
User R/W byte
0x0137
7:0
R/W
User Scratch
User R/W byte
0x0138
7:0
R/W
User Scratch
User R/W byte
0x0139
7:0
R/W
User Scratch
User R/W byte
Register 0x0145 Power Down All Outputs
96
Reg Address
Bit Field
Type
Setting Name
0x0145
0
R/W
OUT_PDN_ALL
Rev. 1.1
Description
0- no effect
1- all drivers powered down
15.3.3. Page 2 Registers Si5340
Register 0x0202-0x0205 XAXB Frequency Adjust
Reg Address
Bit Field
Type
Setting Name
0x0202
7:0
R/W
XAXB_FREQ_OFFSET
0x0203
15:8
R/W
XAXB_FREQ_OFFSET
0x0204
23:16
R/W
XAXB_FREQ_OFFSET
0x0205
31:24
R/W
XAXB_FREQ_OFFSET
Description
32 bit 2’s complement offset
adjustment
The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The
XAXB_FREQ_OFFSET word is added to the M_NUM to shift the VCO frequency to compensate for a crystal that
does not have an 8 pf CL specification. The adjustment range is up to ±1000 ppm.
Register 0x0206 PXAXB Divider Value
Reg Address
Bit Field
Type
Setting Name
Description
0x0206
1:0
R/W
PXAXB
Sets the value for the divider on the
XAXB input.

0 = divider value 1
1 = divider value 2
 2 = divider value 4
 3 = divider value 8

Register 0x0208, 0x0212, 0x021C, 0x0226 P Dividers
Reg Address
Bit Field
Type
Setting Name
0x0208
7:0
R/W
P0
0x0212
7:0
R/W
P1
0x021C
7:0
R/W
P2
0x0226
7:0
R/W
PFB
Description
8-bit Integer Number
This set of registers configure the P-dividers which are located at the four input clocks seen in Figure 3 on page 10.
ClockBuilder Pro calculates the correct values for the P-dividers.
Register 0x020E P0 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
0x020E
7:0
R/W
P0_SET
Rev. 1.1
Description
Do not write to this byte. This byte
must always be 0x01 for the P0
divider to work.
97
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x0218 P1 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
0x0218
7:0
R/W
P1_SET
Description
Do not write to this byte. This byte
must always be 0x01 for the P1
divider to work.
Register 0x0222 P2 Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
0x0222
7:0
R/W
P2_SET
Description
Do not write to this byte. This byte
must always be 0x01 for the P2
divider to work.
Register 0x022C PFB Divider Enable/Set
Reg Address
Bit Field
Type
Setting Name
0x022C
7:0
R/W
PFB_SET
Description
Do not write to this byte. This byte
must always be 0x01 for the PFB
divider to work.
Register 0x0230 P Divider Update Bits
Reg Address
Bit Field
Type
Setting Name
0x0230
0
S
P0_UPDATE
Must write a 1 to this bit to cause a
change to the P0 divider to take
effect.
0x0230
1
S
P1_UPDATE
Must write a 1 to this bit to cause a
change to the P1 divider to take
effect.
0x0230
2
S
P2_UPDATE
Must write a 1 to this bit to cause a
change to the P2 divider to take
effect.
0x0230
3
S
PFB_UPDATE
Must write a 1 to this bit to cause a
change to the PFB divider to take
effect.
Bits 7:4 of this register have no function and can be written to any value
98
Rev. 1.1
Description
Register 0x023F M Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x023F
0
S
M_UPDATE
Description
Must write a 1 to this bit to cause M
divider changes to take effect.
Bits 7:1 of this register have no function and can be written to any value
Register 0x023B-0x023E M Divider Denominator
Reg Address
Bit Field
Type
Setting Name
0x023B
7:0
R/W
M_DEN
0x023C
15:8
R/W
M_DEN
0x023D
23:16
R/W
M_DEN
0x023E
31:24
R/W
M_DEN
Description
32-bit Integer Number
The M-divider numerator and denominator is determined by ClockBuilder Pro for a given frequency plan.
Register 0x0253-0x0255 R0 Divider
Reg Address
Bit Field
Type
Setting Name
Description
0x0253
7:0
R/W
R0_REG
0x0254
15:8
R/W
R0_REG
0x0255
23:16
R/W
R0_REG
24-bit Integer Number. Divide
value = (R0_REG+1) x 2
To set R0 = 2, set
OUT0_RDIV_FORCE2 = 1, and then
the R0_REG value is irrelevant. Setting R0_REG=0 will disable the
divider.
The R dividers are with the output drivers and are even integer dividers. The R1–R3 dividers follow the same
format as the R0 divider described above.
Table 31. R Dividers for Output 1,2,3
Register Address
Setting Name
Size
Same as Address
0x0256-0x0258
R1_REG
24-bit Integer Number
0x0253-0x0255
0x025F-0x0261
R2_REG
24-bit Integer Number
0x0253-0x0255
0x0262-0x0264
R3_REG
24-bit Integer Number
0x0253-0x0255
Rev. 1.1
99
Si5340
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Si5340
Si5341-40-RM
Register 0x026B–0x0272 Design ID
Reg Address
Bit Field
Type
Setting Name
Description
0x026B
7:0
R/W
DESIGN_ID0
0x026C
15:8
R/W
DESIGN_ID1
0x026D
23:16
R/W
DESIGN_ID2
0x026E
31:24
R/W
DESIGN_ID3
0x026F
39:32
R/W
DESIGN_ID4
0x0270
47:40
R/W
DESIGN_ID5
0x0271
55:48
R/W
DESIGN_ID6
0x0272
63:56
R/W
DESIGN_ID7
ASCII encoded string defined by
CBPro user, with user defined space
or null padding of unused characters.
A user will normally include a configuration ID + revision ID. For example,
“ULT.1A” with null character padding
sets:
DESIGN_ID0: 0x55
DESIGN_ID1: 0x4C
DESIGN_ID2: 0x54
DESIGN_ID3: 0x2E
DESIGN_ID4: 0x31
DESIGN_ID5: 0x41
DESIGN_ID6:0x 00
DESIGN_ID7: 0x00
Register 0x0278-0x027C OPN Identifier
Reg Address
Bit Field
Type
Setting Name
0x0278
7:0
R/W
OPN_ID0
0x0279
15:8
R/W
OPN_ID1
0x027A
23:16
R/W
OPN_ID2
0x027B
31:24
R/W
OPN_ID3
0x027C
39:32
R/W
OPN_ID4
Description
OPN unique identifier. ASCII
encoded. For example, with OPN:
5340C-A12345-GM, 12345 is the
OPN unique identifier, which sets:
OPN_ID0: 0x31
OPN_ID1: 0x32
OPN_ID2: 0x33
OPN_ID3: 0x34
OPN_ID4: 0x35
Part numbers are of the form:
Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>
Examples:
Si5340C-A12345-GM.
Applies to a “custom” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the
frequency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file.
Si5340C-A-GM.
Applies to a “base” or “blank” OPN device. Base devices are factory pre-programmed to a specific base part type
(e.g., Si5340 but exclude any user-defined frequency plan or other user-defined operating characteristics selected
in ClockBuilder Pro.
100
Rev. 1.1
Register 0x027D OPN Revision
Reg Address
Bit Field
Type
Setting Name
0x27D
7:0
R/W
OPN_Revision
Description
ClockBuilder Pro sets this value based
upon changes to the NVM for a given
OPN.
Register 0x027E Baseline ID
Reg Address
Bit Field
Type
Setting Name
0x27E
7:0
R/W
BaseLine ID
Description
An identifier for the device NVM without
the frequency plan programmed into
NVM.
15.3.4. Page 3 Registers Si5340
Register 0x0302-0x0307 N0 Numerator
Reg Address
Bit Field
Type
Setting Name
0x0302
7:0
R/W
N0_NUM
0x0303
15:8
R/W
N0_NUM
0x0304
23:16
R/W
N0_NUM
0x0305
31:24
R/W
N0_NUM
0x0306
39:32
R/W
N0_NUM
0x0307
43:40
R/W
N0_NUM
Description
44-bit Integer Number
The N dividers are interpolative dividers that are used as output dividers that feed into the R dividers. ClockBuilder
Pro calculates the correct values for the N-dividers.
Register 0x0308-0x030B N0 Denominator
Reg Address
Bit Field
Type
Setting Name
0x0308
7:0
R/W
N0_DEN
0x0309
15:8
R/W
N0_DEN
0x030A
23:16
R/W
N0_DEN
0x030B
31:24
R/W
N0_DEN
Rev. 1.1
Description
32-bit Integer Number
101
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
Register 0x030C N0 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x030C
0
S
N0_UPDATE
Description
Must write a 1 to this bit to cause N0
divider changes to take effect.
Table 32. N Dividers for N1, N2, N3
Register Address
Setting Name
Size
Same as Address
0x030D-0x0312
N1_NUM
48-bit Integer Number
0x0302-0x0307
0x0313-0x0316
N1_DEN
32-bit Integer Number
0x0308-0x030B
0x0318-0x031D
N2_NUM
48-bit Integer Number
0x0302-0x0307
0x031E-0x0321
N2_DEN
32-bit Integer Number
0x0308-0x030B
0x0323-0x0328
N3_NUM
48-bit Integer Number
0x0302-0x0307
0x0329-0x032C
N3_DEN
32-bit Integer Number
0x0308-0x030B
Register 0x0317 N1 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0317
0
S
N1_UPDATE
Description
Must write a 1 to this bit to cause N1
divider changes to take effect.
Register 0x0322 N2 Divider Update Bit
Reg Address
Bit Field
Type
Setting Name
0x0322
0
S
N2_UPDATE
Description
Must write a 1 to this bit to cause N2
divider changes to take effect.
Register 0x032D N3 Divider Update Bit
102
Reg Address
Bit Field
Type
Setting Name
0x032D
0
S
N3_UPDATE
Rev. 1.1
Description
Must write a 1 to this bit to cause N3
divider changes to take effect.
Register 0x0338 All N Dividers Update Bit
Reg Address
Bit Field
Type
Setting Name
Description
0x0338
1
S
N_UPDATE
Writing a 1 to this bit will update all N
dividers to the latest value written to them.
A specific N divider that has not been
changed will not be affected by writing a 1
to this bit. When this bit is written to a 1, all
other bits in this byte should only be written to a 0.
Register 0x0339 FINC/FDEC Masks
Reg Address
Bit Field
Type
Setting Name
0x0339
3:0
R/W
N_FSTEP_MSK
Description
0 to enable FINC/FDEC updates
1 to disable FINC/FDEC updates

Bit 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0]
Bit 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1]
 Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339[2]
 Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339[3]
There is one mask bit for each of the four N dividers.

Register 0x033B-0x0340 N0 Frequency Step Word
Reg Address
Bit Field
Type
Setting Name
0x033B
7:0
R/W
N0_FSTEPW
0x033C
15:8
R/W
N0_FSTEPW
0x033D
23:16
R/W
N0_FSTEPW
0x033E
31:24
R/W
N0_ FSTEPW
0x033F
39:32
R/W
N0_ FSTEPW
0x0340
43:40
R/W
N0_ FSTEPW
Description
44-bit Integer Number
This is a 44-bit integer value which is directly added (FDEC) or subtracted (FINC) from the Nx_NUM parameter
when FINC or FDEC is asserted. ClockBuilder Pro calculates the correct values for the N0 Frequency Step Word.
Each N divider has the ability to add or subtract up to a 44-bit value. The Nx_NUM register value does not change
when an FINC or FDEC is performed so that the starting point of Nx_NUM is in the Nx_NUM register.
Rev. 1.1
103
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Table 33. Frequency Step Word for N1, N2, N3
Register Address
Setting Name
Size
Same as Address
0x0341-0x0346
N1_FSTEPW
44-bit Integer Number
0x033B-0x0340
0x0347-0x034C
N2_FSTEPW
44-bit Integer Number
0x033B-0x0340
0x034D-0x0352
N3_FSTEPW
44-bit Integer Number
0x033B-0x0340
Register 0x0359–0x35A N0 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x0359
7:0
R/W
N0_DELAY[7:0]
Lower byte of N0_DELAY[15:0]
0x035A
7:0
R/W
N0_DELAY[15:8]
Upper byte of N0_DELAY[15:0]
Description
Register 0x035B-0x035C Divider N1 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035B
7:0
R/W
N1_DELAY[7:0]
Lower byte of N1_DELAY[15:0]
0x035C
7:0
R/W
N1_DELAY[15:8]
Upper byte of N1_DELAY[15:0]
Description
Register 0x035D-0x035E Divider N2 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035D
7:0
R/W
N2_DELAY[7:0]
Lower byte of N2_DELAY[15:0]
0x035E
7:0
R/W
N2_DELAY[15:8]
Upper byte of N2_DELAY[15:0]
Description
Register 0x035F-0x0360 Divider N3 Delay Control
Reg Address
Bit Field
Type
Setting Name
0x035F
7:0
R/W
N3_DELAY[7:0]
Lower byte of N3_DELAY[15:0]
0x0360
7:0
R/W
N3_DELAY[15:8]
Upper byte of N3_DELAY[15:0]
Description
Nx_DELAY[15:0] is a 2s complement number that sets the output delay of MultiSynths.
The delay in seconds is Nx_DELAY/(256 x Fvco) where Fvco is the VCO frequency in Hz. The maximum positive
and negative delay is ±(215–1)/(256 x Fvco). Nx_DELAY values are only applied at power up or during a reset.
ClockBuilder Pro calculates the correct value for this register.
104
Rev. 1.1
15.3.5. Page 9 Registers Si5340
Register 0x090E XAXB Configuration
Reg Address
Bit Field
Type
0x090E
0
R/W
Setting Name
XAXB_EXTCLK_EN
0x090E
1
R/W
XAXB_PDNB
Description
0 to use a crystal at the XAXB pins
1 to use an external clock source at the
XAXB pins
A single ended clock must be applied at
the XA input.
0-Power down the oscillator and buffer circuitry at the XA/XB pins
1- No power down
Register 0x091C Enable Zero Delay Mode
Reg Address
Bit Field
Type
Setting Name
0x091C
2:0
R/W
ZDM_EN
Description
3 = Zero delay mode
4 = Normal mode
All other values must not be written.
Register 0x0943 Status and Control I/O Voltage Select
Reg Address
Bit Field
Type
0x0943
0
R/W
Setting Name
IO_VDD_SEL
Description
0 for 1.8 V external connections
1 for 3.3 V external connections
The IO_VDD_SEL configuration bit selects the option of operating the serial interface voltage thresholds from the
VDD or the VDDA pin. By default the IO_VDD_SEL bit is set to the VDD option. The serial interface pins are
always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is
operating at 3.3 V and the Si5341/40 IO_VDD_SEL = 1.8 V, the host must write the IO_VDD_SEL configuration bit
to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum voltage
thresholds. The IO_VDD_SEL bit also affects the status pin levels and control pin thresholds. When
IO_VDD_SEL = 0, the status outputs will have a VOH of ~1.8 V. When IO_VDD_SEL = 1 the status outputs will
have a VOH of ~3.3 V. When IO_VDD_SEL=0, the control input pins will have an input threshold based upon the
VDD supply voltage of 1.8 V. When IO_VDD_SEL=1, the control input pins will have an input threshold based upon
the VDDA supply voltage of 3.3 V. The IO_VDD_SEL bit has no effect on the LOL or LOSXAXB pins VOH or VOL.
See Table 4 and Table 6 of the Si5341/40 data sheet for details.
Rev. 1.1
105
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Register 0x0949 Clock Input Control
Reg Address
Bit Field
Type
0x0949
3:0
R/W
Setting Name
IN_EN
Description
Enables for the four inputs clocks,
IN0 through FB_IN.
1 to enable, 0 to disable

Input 0 corresponds to IN_EN 0x0949 [0]
Input 1 corresponds to IN_EN 0x0949 [1]
 Input 2 corresponds to IN_EN 0x0949 [2]
 FB_IN corresponds to IN_EN 0x0949 [3]

Register 0x094A Input Clock Routing Enable
Reg Address
0x094A
106
Bit Field
6:4
Type
R/W
Setting Name
INx_TO_PFD_EN
Rev. 1.1
Description
When = 1, enables the routing of the 3 input
clocks IN0,1,2 to the Phase Detector. Each bit corresponds to the inputs as follows [6:4] = [IN2 IN1
IN0]. IN_SEL is used to select the input clock that
is applied to the phase detector.
15.3.6. Page A Registers Si5340
Register 0x0A03 N Divider Clocks
Reg Address
Bit Field
Type
0x0A03
3:0
R/W
Setting Name
N_CLK_TO_OUTX_EN
Description
Bits in this field correspond to the N
dividers as [N3 N2 N1 N0]. If an N
divider is used, the corresponding
bit must be 1. See also registers
0x0A05 and 0x0B4A[3:0].
Register 0x0A04 N Divider Phase Interpolator Bypass
Reg Address
Bit Field
Type
0x0A04
3:0
R/W
Setting Name
N_PIBYP
Description
Bypasses the Phase Interpolator of
the N Multisynth divider. Set to a 1
when the value of the N divider is
integer and will not be used as a
DCO. Set to a 0 when the value of
N is fractional (used as a DCO).
Slightly lower output jitter may
occur when the Phase Interpolator
is bypassed (=1). Bits in this field
correspond to the N dividers as [N3
N2 N1 N0].
Register 0x0A05 N Divider Power Down
Reg Address
Bit Field
Type
0x0A05
3:0
R/W
Setting Name
N_PDNB
Rev. 1.1
Description
Powers down the N divider. If an N
divider is not used, set the respective bit to 0 to power it down. Bits in
this field correspond to the N dividers as [N3 N2 N1 N0].
107
Si5340
Si5341-40-RM
Si5340
Si5341-40-RM
15.3.7. Page B Registers Si5340
Register 0x0B46 Loss of Signal Clock Disable
Reg Address
Bit Field
Type
0x0B46
3:0
R/W
Setting Name
LOS_CLK_DIS
Description
Controls the clock to the digital
LOS circuitry. Must be set to 0 to
enable the LOS function of the
respective Inputs [FB_IN IN2 IN1
In0].
Register 0x0B49 Calibration Bits
Reg Address
Bit Field
Type
0x0B49
1:0
R/W
Setting Name
CAL_DIS
0x0B49
3:2
R/W
CAL_FORCE
Description
All bits must be low for proper operation.
All bits must be low for proper operation.
Register 0x0B4A Divider Clock Disables
Reg Address
Bit Field
Type
0x0B4A
3:0
R/W
Setting Name
N_CLK_DIS
0x0B4A
5
R/W
M_CLK_DIS
0x0B4A
6
R/W
M_DIV_CAL_DIS
108
Rev. 1.1
Description
Controls the clock to the N divider.
If an N divider is used the corresponding bit must be 0. [N3 N2 N1
N0]. See also registers 0x0A03 and
0x0A05.
Controls the clock to the M divider.
Must be set to 0 to enable the M
divider.
Controls the clock to the calibration
circuitry in the M divider. Must be
set to 0 as calibration is required on
every power up or Reset.
Si5341-40-RM
A P P E N D I X A — S E T T I N G T H E D I F F E R E N T I A L O U T P U T D R IV ER T O
N O N - S TA N D A R D A M P L I T U D E S
In some applications it may be desirable to have larger or smaller differential amplitudes than produced by the
standard LVPECL and LVDS settings, as selected by CBPro. In these cases, the following information describes
how to implement these amplitudes by writing to the OUTx_CM and OUTx_AMPL setting names. Contact Silicon
Labs for assistance if you want your custom configured device to be programmed for any of the settings in this
appendix.
The differential output driver has a variable output amplitude capability and 2 basic formats, normal and low power
format. The difference between these two formats is that the normal format has an output impedance of ~100 ohms
differential and the low power format has an output impedance of > 500 ohms differential. Note that the rise/fall
time is slower when using the Low Power Differential Format. See the Si5341/40 data sheet for the rise/fall time
specifications.
If the standard LVDS or LVPECL compatible output amplitudes will not work for a particular application, the variable
amplitude capability can be used to achieve higher or lower amplitudes. For example, a “CML” format is sometimes
desired for an application. However, CML is not a defined standard and hence the amplitude of a CML signal for
one receiver may be different than that of another receiver.
When the output amplitude needs to be different than standard LVDS or LVPECL, the Common Mode Voltage
settings must be set as shown in Table 34. No settings other than the ones in Table 34 are supported as the signal
integrity could be compromised. In addition the output driver should be AC coupled to the load so that the common
mode voltage of the driver is not affected by the load.
Table 34. Output Differential Common Mode Voltage Settings
VDDOx
(Volts)
Differential
Format
OUTx_FORMAT
Common
Mode Voltage
(Volts)
OUTx_CM
3.3
Normal
0x1
2.0
0xB
3.3
Low Power
0x2
1.6
0x7
2.5
Normal
0x1
1.3
0xC
2.5
Low Power
0x2
1.1
0xA
1.8
Normal
0x1
0.8
0xD
1.8
Low Power
0x2
0.8
0xD
Rev. 1.1
109
Si5341-40-RM
The differential amplitude can be set as shown in Table 35.
Table 35. Typical Differential Amplitudes
OUTx_AMPL
Normal Differential Format
(Vpp SE mV–Typical)
Low Power Differential Format
(Vpp SE mV – Typical)
0
130
200
1
230
400
2
350
620
3
450
820
4
575
1010
5
700
1200
6
810
13501
7
920
16001
Notes:
1. In low power mode and VDDOx=1.8V, OUTx_AMPL may not be set to 6 or 7.
2. These amplitudes are based upon a 100 ohm differential termination.
See the register map portion of this document for additional information about OUTx_FORMAT, OUTx_CM and
OUTx_AMPL. Contact Silicon Labs for assistance at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
if you require a factory-programmed device to be configured for any of the output driver settings in this appendix.
110
Rev. 1.1
Si5341-40-RM
DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.3

Specified
Corrected Figure 15, “7-bit I2C Slave Address BitConfiguration,” on page 35.
Revision 1.0 to Revision 1.1

Corrected the description of register 0x0004.
 Changed the bit type of HARD_RST from R/W to S.
Updated “11.1. Recommended Crystals”.
Updated
need for many ground vias under the Si5341/
40.
Revision 0.3 to Revision 0.4

Updated “12.2.1. Si5340 Applications without a
Crystal as the Reference Clock”.
Table 22.
Revision 0.4 to Revision 0.95








Removed Zero Delay section as Factory assistance
is needed to implement this feature.
Removed the variable DC coupled common mode
voltage capability of the OUTx driver as the driver
performance can be compromised at non optimal
common mode voltage settings.
Added Appendix A for variable output amplitudes
such as CML.
Added registers that were previously not described.
Added information to the DCO mode sections.
Added pre and post register write sequence
requirements.
Changed the 64 and 44 pin layout pictures to show
the vias used for E-pad grounding.
Clarified the section on Blank and Factory
Programmed devices.
Revision 0.95 to Revision 1.0

Updated Figure 5.
Changed
100  resistors to 50 

Added registers 0x91C and 0x94A.
 Clarified that LOS_XAXB only works on XA input,
not XB input.
 Updated “8. Dynamic PLL Changes”.
Added
information and changed the last write to register
0x0B24 to be 0xDB.

Updated “9. Serial Interface”.
Added

page mode addressing information.
Updated Figures 21 through 24.
To
show that CSb high is properly shown as >2.0 SCLK
periods in all places.

Corrected mistakes regarding register 0x000B I2C
Address.
 Updated Figure 9.
Removed
VDDO = 1.8 V from dc-coupled LVDS
diagram.

Updated Table 11.
Added
a note about the low power format causing a
slower rise/fall time.
Rev. 1.1
111
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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