SCH3221 Silicon Errata and Data Sheet Clarification

SCH3221
SCH3221
Silicon Errata and Data Sheet Clarification
TABLE 1:
SILICON DEV/REV VALUES
Device ID(1)
Part Number
Revision ID for Silicon Revision(2)
A
SCH3221
Note 1:
2:
5Bh
00h
The Device ID is visible as an 8-bit number at Plug and Play Configuration Index 20h.
The HW Revision Number is visible as an 8-bit number at Plug and Play Configuration Index 21h.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item Number
Issue Summary
Affected
Revisions(1)
A
Runtime
Registers
Note 1:
PME
1.
GP50 Generates PME on Negative Edge
Only
X
Only those issues indicated in the last column apply to the current silicon revision.
Silicon Errata Issues
1. Module: Runtime Registers
DESCRIPTION
Only a high-to-low signal on the GP50 pin will set the associated PME status bit and generate a PME event (if enabled).
This operates the same way regardless of how the polarity bit is set (i.e., non-inverted or inverted).
END USER IMPLICATIONS
Cannot use GP50 to generate a PME event on a transition from low-to-high.
Work Around
None.
 2016 Microchip Technology Inc.
DS80000695A-page 1
SCH3221
Data Sheet Clarifications
The following typographic corrections and clarifications apply only to the SCH3221 Data Sheet, which is currently Document #00002120A. Other members of the SCH322x family have separate data sheets, and separate errata sheets.
Note:
Where appropriate, corrections are shown in bold. Where possible, the original bold text formatting has
been removed for clarity.
TABLE 3:
DATA SHEET CLARIFICATION SUMMARY
Module
Item
Number
Issue Summary
Runtime Registers
1.
GP30 Has Two PME Status Bits
Timing Diagrams
2.
Minimum LPC Clock Frequency
1. Module: Runtime Registers
GP30 has two sets of PME status and enable bits associated with it.
1. Bit[0] of the PME_STS3 register at offset 04h is only set on a low-to-high transition of the GP30 pin. If the
corresponding enable bit, located in the PME_EN3 register at offset 07h, is set then the IO_PME# signal will
be asserted.
2. Bit[0] of the PME_STS4 register at offset 1Ah is only set on a high-to-low transition of the GP30 pin. If the
corresponding enable bit, located in the PME_EN4 register at offset1Bh, is set then the IO_PME# signal will
be asserted.
2. Module: Timing Diagrams
The maximum period for the PCI Clock is 55.5nS. This permits an LPC clock of 18MHz.
DS80000695A-page 2
 2016 Microchip Technology Inc.
SCH3221
APPENDIX A:
DOCUMENT REVISION HISTORY
Revision Level and Date
DS80000695A (04-11-16)
Description
Initial Draft Version
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DS80000695A-page 3
SCH3221
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DS80000695A-page 4
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SCH3221
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522404750
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DS80000695A-page 5
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