Low Capacitance ESD Protection Array ACSRS065V0P RoHs Device Features - ESD Protect for 4 high-speed I/O channels. - IEC61000-4-2 Level 4 ESD protection. - IEC61000-4-4 (FET)20A for I/O,80A for Power. - Working voltage: 5V - Low capacitance:1.3pF(Typ.). - High component density. - Comply with AEC-Q101 SOT-23-6 0.119(3.02) 0.111(2.82) 0.067(1.70) 0.059(1.50) Mechanical data 0.037(0.95) BSC. 0.079(2.00) 0.071(1.80) -Case: SOT-23-6 standard package, molded plastic. 0.008(0.20) 0.004(0.10) -Terminals: Solder plated, solderable per MIL-STD-750,method 2026. 0.045(1.15) 0.041(1.05) 0.116(2.95) 0.104(2.65) -Mounting position: Any -Weight: 0.015 gram (approx.). Circuit Diagram 0.024(0.60) 0.012(0.30) 0.004(0.10) 0.000(0.00) 0.020(0.50) 0.012(0.30) 5 Dimensions in inches and (millimeter) 1 3 4 6 2 Pin Configuration 6 5 4 1 2 3 Maximum Ratings (at TA=25°C unless otherwise noted) Symbol Value Unit Peak pulse current ( tp = 8/20 us) IPP 6.5 A ESD per IEC 61000-4-2(Air) ESD per IEC 61000-4-2(Contact) ESD 18 14 kV ESD_VDD 30 kV TSOL 260 ( 10 sec) °C Tj -55 to +85 °C TSTG -55 to +125 °C VIO (GND -0.5) to (VDD +0.5) V Parameter ESD per IEC 61000-4-2(Air)(VDD-GND) ESD per IEC 61000-4-2(Contact)(VDD-GND) Lead soldering temperature Operating temperature Storage temperature DC voltage at any I/O pin Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 1 AQW-BP002 Comchip Technology CO., LTD. Low Capacitance ESD Protection Array Electrical Characteristics (at TA=25°C unless otherwise noted) Parameter Reverse stand-Off voltage Conditions Pin 5 to Pin 2 Symbol Min Typ Max Unit 5 VRWM 5 VRWM = 5 V, Pin 5 to Pin 2 Reverse leakage current uA IR 1 VPIN 5 = 5 V, VPIN 2 =0V ,VIO = 0~5V Diode breakdown voltage IR = 1 mA, Pin 5 to Pin 2 VBD Forward voltage IF = 15 mA, Pin 2 to Pin 5 VF IPP = 5 A, tp=8/20us, Any Channel Pin to Ground Clamping voltage IEC 61000-4-2 +6kV,Contact mode Any Channel Pin to Ground VC IEC 61000-4-2 +6kV,Contact moed VDD Pin to Ground Vpin5 = 5V,Vpin2= 0V, VIO=2.5V f = 1MHz,Between Channel Pins Vpin5 = 5V,Vpin2= 0V, VIN=2.5V f = 1MHz,Channel_x pin to ground channel_y pin to ground 6 9 V 0.8 1 V 8.1 9 V 12.5 9 Vpin5 = 5V,Vpin2= 0V, VIO=2.5V, f = 1MHz,Any Channel Pin to Ground Junction capacitance V Cj 1.3 1.6 0.12 0.14 0.05 0.07 Company reserves the right to improve product design , functions and reliability without notice. pF REV:A Page 2 AQW-BP002 Comchip Technology CO., LTD. Low Capacitance ESD Protection Array RATING AND CHARACTERISTIC CURVES (ACSRS065V0P) Fig. 1 - Power derating curve Fig. 2 - Clamping voltage vs. Peak pulse current 12 110 10 Clamping voltage ( V ) 11 90 % of Rated power or IPP 100 80 70 60 50 40 30 9 8 7 6 5 Waveform Parameters: tr=8us td=20us 4 I/O pin to GND PIN 3 20 2 10 1 0 0 0 25 50 75 100 125 150 4.5 5.0 5.5 6.0 6.5 7.0 7.5 Peak pulse current (A) Ambient temperature (°C) Fig.3 - Forward voltage v.s. forward current Fig.4 - Typical variation of CIN v.s. VIN 2.0 4.0 1.8 3.5 1.6 Input capacitance(pF) Forward voltage (V) 3.0 2.5 2.0 Waveform Parameters: tr=8us td=20us 1.5 I/O pin to GND PIN 1.0 1.4 1.2 1.0 0.8 0.6 0.2 0 0.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD =5V,GND =0V,f =1MHz,TA=25°C 0.4 0.5 7.5 0 1 2 Peak pulse current(A) 1.35 1.30 1.25 1.20 1.15 VDD =5V,GND =0V,VIN =2.5V f=1MHz 1.05 1.00 20 40 60 80 Temperature (°C) 100 120 5 Fig.7 -Transmission line pulsing (TLP) measurement 18 16 14 V_pulse Pulse from a transmission line 12 100ns 10 TLP_I + TLP_V DUT 8 6 I/O to GND 4 2 0 0 1 2 3 4 5 6 7 8 Transmission line pulsing(TLP)voltage(V) Transmission line pulsing(TLP)current(A) Input capacitance(pF) 1.40 1.10 Fig. 6 - Transmission line pulsing (TLP) measurement Transmission line pulsing(TLP)current(A) 1.50 4 Input voltage (V) Fig. 5 - Typical variation of CIN v.s. temperature 1.45 3 18 16 14 V_pulse 12 Pulse from a transmission line 10 100ns TLP_I + TLP_V 8 DUT - 6 4 VDD to GND 2 0 0 1 2 3 4 5 6 7 8 9 Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 3 AQW-BP002 Comchip Technology CO., LTD. 10 Transmission line pulsing(TLP)voltage(V) Low Capacitance ESD Protection Array Reel Taping Specification P1 d T W B F E P0 C A P 12 o 0 D2 D1 D W1 SOT-23-6 SOT-23-6 SYMBOL A B C d D D1 D2 (mm) 3.17 ± 0.10 3.23 ± 0.10 1.37 ± 0.10 1.50 ± 0.05 180.0 + 0.00 /–0.30 60.00 ± 0.50 13.00 ± 0.20 (inch) 0.125 ± 0.004 0.127 ± 0.004 0.054 ± 0.004 0.059 ± 0.002 7.087 + 0.00 /–0.012 2.362 ± 0.020 0.512 ± 0.008 SYMBOL E F P P0 P1 W W1 (mm) 1.75 ± 0.10 3.50 ± 0.05 4.00 ± 0.10 4.00 ± 0.10 2.00 ± 0.05 8.00 + 0.30 /–0.10 12.30 ± 0.20 (inch) 0.069 ± 0.004 0.138 ± 0.002 0.157 ± 0.004 0.157 ± 0.004 0.079 ± 0.002 0.315 + 0.012 /–0.004 0.484 ± 0.008 Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 4 AQW-BP002 Comchip Technology CO., LTD. Low Capacitance ESD Protection Array Marking Code 6 Part Number Marking Code ACSRS065V0P C05 5 4 C05 1 2 3 Suggested PAD Layout C SOT-23-6 SIZE (mm) (inch) A 1.10 0.043 B 0.60 0.024 C 0.95 0.037 D 2.50 0.098 E 3.60 0.142 A D E B Standard Packaging REEL PACK Case Type SOT-23-6 REEL Reel Size ( pcs ) (inch) 3,000 7 Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 5 AQW-BP002 Comchip Technology CO., LTD.