LF PA K 56 PSMN0R9-30YLD N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 14 December 2015 Product data sheet 1. General description 300 Amp Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers high efficiency, low spiking performance usually associated with MOSFETs with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • • • • 300 Amp capability Avalanche rated, 100 % tested at I(as) = 190 Amps Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching frequencies Superfast switching with soft-recovery; s-factor > 1 Low spiking and ringing for low EMI designs Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds, qualified to 150 °C Wave solderable; exposed leads for optimal visual solder inspection 3. Applications • • • • • • • On-board DC-to-DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - - 30 V Scan or click this QR code to view the latest information for this product PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 2 Ptot total power dissipation Tmb = 25 °C; Fig. 1 Tj junction temperature [1] Min Typ Max Unit - - 300 A - - 291 W -55 - 150 °C - 0.79 1.09 mΩ - 0.65 0.87 mΩ - 13.5 - nC - 109 - nC - 0.9 - Static characteristics RDSon drain-source on-state resistance VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 QG(tot) total gate charge VGS = 10 V; ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 Source-drain diode S softness factor IS = 25 A; VGS = 0 V; dIS/dt = -100 A/µs; VDS = 15 V; Fig. 16 [1] 300A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, Thermal design and operating temperature. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D G mbb076 1 2 3 S 4 LFPAK56; PowerSO8 (SOT1023) 6. Ordering information Table 3. Ordering information Type number PSMN0R9-30YLD PSMN0R9-30YLD Product data sheet Package Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56); 4 leads SOT1023 All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 7. Marking Table 4. Marking codes Type number Marking code PSMN0R9-30YLD 0D930L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - 30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 291 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 300 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 284 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 1800 A [1] IDM peak drain current Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage HBM 2000 - V Source-drain diode IS source current Tmb = 25 °C - 242 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1800 A [2] - 190 A [2] - 2987 mJ Avalanche ruggedness IAS EDS(AL)S non-repetitive avalanche current Vsup ≤ 30 V; VGS = 10 V; Tj(init) = 25 °C; non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 25 A; RGS = 50 Ω Vsup ≤ 30 V; RGS = 50 Ω; unclamped; tp = 6.1 ms [1] [2] PSMN0R9-30YLD Product data sheet 300A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, Thermal design and operating temperature. Protected by 100% test All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 03ne36 120 aaa-020460 500 ID (A) Pder (%) 400 80 300 (1) 200 40 100 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 25 50 75 100 125 150 175 Tmb (°C) 200 (1) 300A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, Thermal design and operating temperature Normalized total power dissipation as a function of mounting base temperature Fig. 2. ID (A) 0 Continuous drain current as a function of mounting base temperature aaa-020461 104 Limit RDSon = VDS / ID 103 tp = 10 us 102 100 us 1 ms DC 10 10 ms 100 ms 1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 4 - 0.35 0.43 K/W PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 4 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient Fig. 5 - 50 - K/W Fig. 6 - 125 - K/W 003aag977 1 Z th(j-mb) (K/W) δ = 0.5 10-1 0.2 0.1 0.05 10 -2 P 0.02 single shot 10 tp -3 Fig. 4. 10-6 10-5 10-4 10-3 10-2 t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration aaa-005751 aaa-005750 Fig. 5. tp T δ= PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint; FR4 Board; 2oz copper 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C 1.2 1.5 2.2 V Static characteristics V(BR)DSS VGS(th) PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.5 - mV/K IDSS drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 24 V; VGS = 0 V; Tj = 125 °C - 3.7 - µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; - 0.79 1.09 mΩ - - 1.8 mΩ - 0.65 0.87 mΩ - - 1.44 mΩ f = 1 MHz - 1.4 - Ω ID = 25 A; VDS = 15 V; VGS = 10 V; - 109 - nC - 51 - nC ID = 0 A; VDS = 0 V; VGS = 0 V - 99 - nC IGSS RDSon gate leakage current drain-source on-state resistance Fig. 10 VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 10; Fig. 11 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 10; Fig. 11 RG internal gate resistance (AC) Dynamic characteristics QG(tot) total gate charge Fig. 12; Fig. 13 ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 12; Fig. 13 QGS gate-source charge ID = 25 A; VDS = 15 V; VGS = 4.5 V; - 15.3 - nC QGS(th) pre-threshold gatesource charge Fig. 12; Fig. 13 - 10.5 - nC QGS(th-pl) post-threshold gatesource charge - 4.8 - nC QGD gate-drain charge - 13.5 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 - 2.4 - V Ciss input capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; - 7668 - pF Coss output capacitance Tj = 25 °C; Fig. 14 - 2914 - pF Crss reverse transfer capacitance - 445 - pF td(on) turn-on delay time VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V; - 38.1 - ns tr rise time RG(ext) = 5 Ω - 49.8 - ns td(off) turn-off delay time - 63 - ns tf fall time - 42.6 - ns PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Qoss output charge VGS = 0 V; VDS = 15 V; f = 1 MHz; - 83.11 - nC Tmb = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.76 1.2 V trr reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 52 - ns Qr recovered charge VDS = 15 V; Fig. 16 - 67 - nC ta reverse recovery rise time - 27.4 - ns tb reverse recovery fall time - 24.7 - ns S softness factor - 0.9 - [1] [1] includes capacitive recovery aaa-011698 180 ID (A) 10 V VGS = 3 V 2.8 V RDSon (mΩ) aaa-011700 6 5 135 4 2.6 V 90 3 2 45 2.4 V 1 2.2 V 0 Fig. 7. 0 0.5 1 1.5 2 VDS (V) 0 2.5 Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values PSMN0R9-30YLD Product data sheet 0 2 6 8 10 12 14 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 14 December 2015 4 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-011701 200 ID (A) aaa-011702 12 RDSon (mΩ) 160 2.4 V 2.6 V 2.8 V 9 120 6 80 40 150°C 3 Tj = 25°C 3V 4.5 V 0 Fig. 9. 0 0.5 1 1.5 2 2.5 3 VGS (V) 0 3.5 Transfer characteristics; drain current as a function of gate-source voltage; typical values 50 75 100 125 150 175 ID (A) 200 Fig. 10. Drain-source on-state resistance as a function of drain current; typical values VDS ID 10 V 1.6 VGS(pl) 1.2 VGS(th) VGS = 4.5 V 0.8 VGS QGS2 QGS1 0.4 0 -60 25 003aal037 2 a VGS = 10 V 0 -30 0 30 60 90 120 150 Tj (°C) 180 QGS QGD QG(tot) 003aaa508 Fig. 12. MOSFET transistor: Gate charge waveform definitions Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology VGS (V) aaa-011703 10 aaa-011705 105 C (pF) 8 104 Ciss 6 24 V Coss 15 V 4 103 VDS = 6 V Crss 2 0 0 20 40 60 80 100 QG (nC) 102 10-1 120 Fig. 13. Gate-source voltage as a function of gate charge; typical values IS (A) 1 10 VDS (V) Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aal160 aaa-011706 103 102 ID (A) 102 trr ta 10 0.25 IRM 1 10-1 tb 0 150°C 0 0.2 Tj = 25°C 0.4 0.6 0.8 IRM 1 VSD (V) t (s) 1.2 Fig. 15. Source current as a function of source-drain voltage; typical values PSMN0R9-30YLD Product data sheet Fig. 16. Reverse recovery timing definition All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56); 4 leads A E SOT1023 E1 A b1 b2 (3x) c1 mounting base H D1 D L 1 2 3 4 b e A1 w A X c C θ Lp detail X 0 2.5 mm 5 mm scale Dimensions Unit y C A A1 b b1 b2 c c1 D(1) D1(1) E(1) E1(1) max 1.10 0.15 0.50 4.41 0.25 0.30 4.70 4.45 5.30 nom 0.85 min 0.95 0.00 0.35 3.62 0.19 0.24 4.45 4.95 3.7 3.5 e 1.27 H L Lp 6.2 1.3 0.85 5.9 0.8 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version JEDEC 8° 0° sot1023_po References IEC θ JEITA European projection Issue date 11-12-09 13-03-05 SOT1023 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT1023) PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 13 PSMN0R9-30YLD NXP Semiconductors N-channel 30 V, 0.87 mΩ, 300 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 3 8 Limiting values .......................................................3 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 December 2015 PSMN0R9-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved 13 / 13