PSMN2R0-30YLD N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11 December 2014 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers high efficiency, low spiking performance usually associated with MOSFETs with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • • Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching frequencies Superfast switching with soft-recovery; s-factor > 1 Low spiking and ringing for low EMI designs Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds, qualified to 175 °C Wave solderable; exposed leads for optimal visual solder inspection 3. Applications • • • • • • On-board DC-to-DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 2 - - 100 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 142 W Scan or click this QR code to view the latest information for this product [1] PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Tj junction temperature Min Typ Max Unit -55 - 175 °C - 2.1 2.5 mΩ - 1.61 2 mΩ - 6.3 - nC - 21.8 - nC - 1.02 - Static characteristics RDSon drain-source on-state resistance VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 QG(tot) total gate charge VGS = 4.5 V; ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 Source-drain diode S softness factor IS = 25 A; VGS = 0 V; dIS/dt = -100 A/µs; VDS = 15 V; Fig. 16 [1] Continuous current is limited by package. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number PSMN2R0-30YLD PSMN2R0-30YLD Product data sheet Package Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 2 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 7. Marking Table 4. Marking codes Type number Marking code PSMN2R0-30YLD 2D030L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 142 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 100 A VGS = 10 V; Tmb = 100 °C; Fig. 2 [1] - 100 A - 793 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 1000 - V - 100 A - 793 A - 397 mJ HBM Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C [1] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 25 A; [2] Vsup ≤ 30 V; RGS = 50 Ω; unclamped; tp = 815 µs [1] [2] PSMN2R0-30YLD Product data sheet Continuous current is limited by package. Protected by 100% test All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 3 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 03aa16 120 aaa-008403 200 ID (A) Pder (%) 150 80 (1) 100 40 50 0 Fig. 1. ID (A) 0 50 100 150 Tmb (°C) 0 200 0 25 50 75 100 125 150 175 Tmb (°C) 200 (1) Capped at 100A due to package Normalized total power dissipation as a function of mounting base temperature Fig. 2. Continuous drain current as a function of mounting base temperature aaa-008404 103 Limit RDSon = VDS / ID tp = 10 us 102 100 us 10 DC 1 ms 10 ms 100 ms 1 10-1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 4 - 0.92 1.06 K/W PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 4 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient Fig. 5 - 50 - K/W Fig. 6 - 125 - K/W aaa-008447 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 P δ= 0.05 0.02 single shot 10-2 10-6 Fig. 4. 10-5 tp 10-4 10-3 10-2 T t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration aaa-005751 aaa-005750 Fig. 5. tp PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint; FR4 Board; 2oz copper 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C 1.2 1.7 2.2 V Static characteristics V(BR)DSS VGS(th) PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 5 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.4 - mV/K IDSS drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 24 V; VGS = 0 V; Tj = 125 °C - 1.7 - µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; - 2.1 2.5 mΩ - - 4.2 mΩ - 1.61 2 mΩ - - 3.3 mΩ f = 1 MHz - 0.9 - Ω ID = 25 A; VDS = 15 V; VGS = 10 V; - 46 - nC - 21.8 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 41.5 - nC IGSS RDSon gate leakage current drain-source on-state resistance Fig. 10 VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 11; Fig. 10 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 11; Fig. 10 RG gate resistance Dynamic characteristics QG(tot) total gate charge Fig. 12; Fig. 13 ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 12; Fig. 13 QGS gate-source charge ID = 25 A; VDS = 15 V; VGS = 4.5 V; - 6.8 - nC QGS(th) pre-threshold gatesource charge Fig. 12; Fig. 13 - 4.5 - nC QGS(th-pl) post-threshold gatesource charge - 2.3 - nC QGD gate-drain charge - 6.3 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 - 2.5 - V Ciss input capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; - 2969 - pF Coss output capacitance Tj = 25 °C; Fig. 14 - 1477 - pF Crss reverse transfer capacitance - 206 - pF td(on) turn-on delay time VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V; - 19 - ns tr rise time RG(ext) = 5 Ω - 31 - ns td(off) turn-off delay time - 24 - ns tf fall time - 19 - ns PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 6 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit Qoss output charge VGS = 0 V; VDS = 15 V; f = 1 MHz; - 31.6 - nC Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.8 1.2 V trr reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 37.5 - ns Qr recovered charge VDS = 15 V; Fig. 16 - 32 - nC ta reverse recovery rise time - 18.6 - ns tb reverse recovery fall time - 18.9 - ns S softness factor - 1.02 - [1] 150 10 V ID (A) [1] includes capacitive recovery aaa-008405 4.5 V RDSon (mΩ) 5 VGS = 3 V 120 aaa-008406 6 4 90 2.8 V 3 60 2 2.6 V 30 1 2.4 V 0 Fig. 7. 0 0.5 1 1.5 2 VDS (V) 0 2.5 Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values PSMN2R0-30YLD Product data sheet 0 2 6 8 10 12 14 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 11 December 2014 4 © NXP Semiconductors N.V. 2014. All rights reserved 7 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-008407 200 ID (A) aaa-008408 20 RDSon (mΩ) 2.8 V 3V 16 150 12 100 8 50 0 Fig. 9. 150°C 0 0.8 1.6 Tj = 25°C 2.4 3.2 VGS (V) 0 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values 4.5 V VGS = 10 V 0 30 60 90 120 ID (A) 150 Fig. 10. Drain-source on-state resistance as a function of drain current; typical values 003aal037 2 a 3.5 V 4 VDS 10 V 1.6 ID VGS(pl) 1.2 VGS(th) VGS = 4.5 V 0.8 VGS QGS1 QGS2 QGS 0.4 QGD QG(tot) 003aaa508 0 -60 -30 0 30 60 90 120 150 Tj (°C) 180 Fig. 12. Gate charge waveform definitions Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 8 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology VGS (V) aaa-008409 10 aaa-008410 104 C (pF) Ciss 8 Coss 103 6 24 V 15 V 4 Crss 102 VDS = 6 V 2 0 0 10 20 30 40 50 QG (nC) 10 10-1 60 Fig. 13. Gate-source voltage as a function of gate charge; typical values IS (A) 1 10 VDS (V) Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aal160 aaa-008411 103 102 ID (A) 102 trr ta 10 0.25 IRM 1 10-1 tb 0 150°C 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) IRM t (s) 1.2 Fig. 15. Source current as a function of source-drain voltage; typical values PSMN2R0-30YLD Product data sheet Fig. 16. Reverse recovery timing definition All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 9 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 10 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 11 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. 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The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 12 / 13 PSMN2R0-30YLD NXP Semiconductors N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 3 8 Limiting values .......................................................3 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2014. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 December 2014 PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 11 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved 13 / 13