PSMN1R0-30YLC N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 15 January 2015 Product data sheet 1. General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 2. Features and benefits • • • • High reliability Power SO8 package, qualified to 175°C Optimised for 4.5V Gate drive utilising NextPower Superjunction technology Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads Ultra low Rdson and low parasitic inductance 3. Applications • • • • • • DC-to-DC converters Lithium-ion battery protection Load switching Power OR-ing Server power supplies Sync rectifier 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 2 - - 100 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 272 W Tj junction temperature -55 - 175 °C - 1.1 1.4 mΩ - 0.85 1.15 mΩ [1] Static characteristics RDSon drain-source on-state resistance VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 12 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 12 Scan or click this QR code to view the latest information for this product PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit VGS = 4.5 V; ID = 25 A; VDS = 15 V; - 14.6 26 nC - 50 70 nC Dynamic characteristics QGD gate-drain charge Fig. 14; Fig. 15 QG(tot) total gate charge VGS = 4.5 V; ID = 25 A; VDS = 15 V; Fig. 15; Fig. 14 [1] Continuous current is limited by package. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN1R0-30YLC Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN1R0-30YLC 1C030L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 30 V PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions VGS gate-source voltage Ptot total power dissipation Tmb = 25 °C; Fig. 1 ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 VGS = 10 V; Tmb = 100 °C; Fig. 2 Min Max Unit -20 20 V - 272 W [1] - 100 A [1] - 100 A - 1450 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 960 - V - 100 A MM (JEDEC JESD22-A115) Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1450 A VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; - 259 mJ [1] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Vsup ≤ 30 V; RGS = 50 Ω; unclamped; Fig. 4 [1] Continuous current is limited by package. 03na19 120 003a a e 940 4 00 ID (A) 3 20 Pder (%) 80 2 40 1 60 40 (1) 80 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature PSMN1R0-30YLC Product data sheet 0 200 Fig. 2. 0 10 0 150 200 Tmb ( C) Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 15 January 2015 50 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a e 941 104 ID (A) Limit R DS on = VDS / ID 103 tp =10 ms 102 100 ms 1 ms DC 10 10 ms 100 ms 1 10-1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003a a e 954 103 I AL (A) 102 (1) (2) 10 1 10-1 10-3 Fig. 4. 10-2 10-1 1 tAL (ms ) 10 Single pulse avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - 0.45 0.55 K/W PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 4 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a ae942 1 Z th(j-mb) (K/W) d = 0.5 0.2 10-1 0.1 0.05 0.02 P 10-2 tp T d= s ing le s hot tp 10 -3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 t T 10-1 tp (s ) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.05 1.41 1.95 V 0.5 - - V - - 2.25 V VDS = 30 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; - 1.1 1.4 mΩ - - 2.4 mΩ - 0.85 1.15 mΩ - - 1.85 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 10 ID = 10 mA; VDS = VGS; Tj = 150 °C; Fig. 11 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 11 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 12 VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 12; Fig. 13 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 12 VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 12; Fig. 13 PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit RG gate resistance f = 1 MHz - 1.1 2.2 Ω ID = 25 A; VDS = 15 V; VGS = 10 V; - 103.5 145 nC - 50 70 nC ID = 0 A; VDS = 0 V; VGS = 10 V; Fig. 15 - 96.5 - nC Dynamic characteristics QG(tot) total gate charge Fig. 14; Fig. 15 ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 15; Fig. 14 QGS gate-source charge ID = 25 A; VDS = 15 V; VGS = 4.5 V; - 12.9 - nC QGS(th) pre-threshold gatesource charge Fig. 14; Fig. 15 - 10.1 - nC QGS(th-pl) post-threshold gatesource charge - 2.8 - nC QGD gate-drain charge - 14.6 26 nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 15 V; Fig. 14 - 2.2 - V Ciss input capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; 3322 6645 9968 pF Coss output capacitance Tj = 25 °C; Fig. 16 605 1210 1815 pF Crss reverse transfer capacitance 240 481 842 pF td(on) turn-on delay time VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V; - 44 - ns tr rise time RG(ext) = 4.7 Ω - 77 - ns td(off) turn-off delay time - 108 - ns tf fall time - 60 - ns Qoss output charge - 35.2 - nC VGS = 0 V; VDS = 15 V; f = 1 MHz; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.8 1.1 V trr reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 45 - ns Qr recovered charge VDS = 15 V - 67 - nC ta reverse recovery rise time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 28.5 - ns - 16.5 - ns tb VDS = 15 V; Fig. 18 reverse recovery fall time PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a e 943 100 3 .0 2.8 ID (A) 6 VGS (V) = 2.4 50 25 0 Fig. 6. RDS on (mW) 4.5 10.0 75 4 2 2.2 0 003a a e 944 8 2.6 0.5 VDS (V) 0 1 Fig. 7. Output characteristics: drain current as a function of drain-source voltage; typical values 003a a e 949 300 0 4 8 12 16 Drain-source on-state resistance as a function of gate-source voltage; typical values 003a a e 951 100 gfs (S ) VGS (V) ID (A) 240 75 180 50 Tj = 150 C 120 25 60 0 Fig. 8. Tj = 25 C 0 25 50 75 ID (A) 0 100 Forward transconductance as a function of drain current; typical values PSMN1R0-30YLC Product data sheet Fig. 9. 0 2 3 VGS (V) 4 Transfer characteristics: drain current as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 15 January 2015 1 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a e 948 10-1 ID (A) VGS (th) (V) 10-2 10 Min -3 Typ 003a a e 947 3 Ma x (1 mA) 2 Ma x I D = 5mA 1mA 10-4 1 Min (5mA) 10-5 10-6 0 1 2 0 -60 3 VGS (V) Fig. 10. Sub-threshold drain current as a function of gate-source voltage 120 Tj ( C) 180 003a a e 946 2 2.4 RDS on (mW) 60 Fig. 11. Gate-source threshold voltage as a function of junction temperature 003a a e 945 8 0 a 4 .5V 6 1.5 VGS (V) =2.6 VGS = 10V 1 4 2.8 3 .0 2 0 0.5 3.5 10 4.5 0 25 50 75 ID (A) 0 -60 100 Fig. 12. Drain-source on-state resistance as a function of drain current; typical values PSMN1R0-30YLC Product data sheet 0 60 120 Tj ( C) 180 Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a e 952 10 VDS VGS (V) ID 8 VGS(pl) 6 6V VGS(th) VGS 1 5V 4 QGS1 QGS2 QGS V DS = 24V QGD 2 QG(tot) 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 40 80 Q G (nC) 120 Fig. 15. Gate-source voltage as a function of gate charge; typical values 003a a e 950 104 Cis s 003a a e 953 100 IS (A) C (pF) 75 Cos s 103 50 Tj = 150 C Crs s 25 Tj = 2 5 C 102 10-1 1 10 V DS (V) 0 102 0 0.3 0.6 0.9 VS D (V) 1.2 Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain voltage; typical values as a function of drain-source voltage; typical values PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a f 444 ID (A) trr ta tb 0 0.25 IR M IRM t (s ) Fig. 18. Reverse recovery timing definition PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 14 PSMN1R0-30YLC NXP Semiconductors N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using NextPower technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 19. Package outline LFPAK56; Power-SO8 (SOT669) PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 11 12 12.1 12.2 12.3 12.4 Legal information .................................................12 Data sheet status ............................................... 12 Definitions ...........................................................12 Disclaimers .........................................................12 Trademarks ........................................................ 13 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 January 2015 PSMN1R0-30YLC Product data sheet All information provided in this document is subject to legal disclaimers. 15 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved 14 / 14